sw.c 13 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2010 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/vmalloc.h>
  31. #include "../wifi.h"
  32. #include "../core.h"
  33. #include "../pci.h"
  34. #include "reg.h"
  35. #include "def.h"
  36. #include "phy.h"
  37. #include "dm.h"
  38. #include "fw.h"
  39. #include "hw.h"
  40. #include "sw.h"
  41. #include "trx.h"
  42. #include "led.h"
  43. static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
  44. {
  45. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  46. /*close ASPM for AMD defaultly */
  47. rtlpci->const_amdpci_aspm = 0;
  48. /*
  49. * ASPM PS mode.
  50. * 0 - Disable ASPM,
  51. * 1 - Enable ASPM without Clock Req,
  52. * 2 - Enable ASPM with Clock Req,
  53. * 3 - Alwyas Enable ASPM with Clock Req,
  54. * 4 - Always Enable ASPM without Clock Req.
  55. * set defult to RTL8192CE:3 RTL8192E:2
  56. * */
  57. rtlpci->const_pci_aspm = 2;
  58. /*Setting for PCI-E device */
  59. rtlpci->const_devicepci_aspm_setting = 0x03;
  60. /*Setting for PCI-E bridge */
  61. rtlpci->const_hostpci_aspm_setting = 0x02;
  62. /*
  63. * In Hw/Sw Radio Off situation.
  64. * 0 - Default,
  65. * 1 - From ASPM setting without low Mac Pwr,
  66. * 2 - From ASPM setting with low Mac Pwr,
  67. * 3 - Bus D3
  68. * set default to RTL8192CE:0 RTL8192SE:2
  69. */
  70. rtlpci->const_hwsw_rfoff_d3 = 2;
  71. /*
  72. * This setting works for those device with
  73. * backdoor ASPM setting such as EPHY setting.
  74. * 0 - Not support ASPM,
  75. * 1 - Support ASPM,
  76. * 2 - According to chipset.
  77. */
  78. rtlpci->const_support_pciaspm = 2;
  79. }
  80. static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
  81. {
  82. struct rtl_priv *rtlpriv = rtl_priv(hw);
  83. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  84. const struct firmware *firmware;
  85. struct rt_firmware *pfirmware = NULL;
  86. int err = 0;
  87. u16 earlyrxthreshold = 7;
  88. rtlpriv->dm.dm_initialgain_enable = 1;
  89. rtlpriv->dm.dm_flag = 0;
  90. rtlpriv->dm.disable_framebursting = 0;
  91. rtlpriv->dm.thermalvalue = 0;
  92. rtlpriv->dm.useramask = true;
  93. /* compatible 5G band 91se just 2.4G band & smsp */
  94. rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
  95. rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
  96. rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
  97. rtlpci->transmit_config = 0;
  98. rtlpci->receive_config =
  99. RCR_APPFCS |
  100. RCR_APWRMGT |
  101. /*RCR_ADD3 |*/
  102. RCR_AMF |
  103. RCR_ADF |
  104. RCR_APP_MIC |
  105. RCR_APP_ICV |
  106. RCR_AICV |
  107. /* Accept ICV error, CRC32 Error */
  108. RCR_ACRC32 |
  109. RCR_AB |
  110. /* Accept Broadcast, Multicast */
  111. RCR_AM |
  112. /* Accept Physical match */
  113. RCR_APM |
  114. /* Accept Destination Address packets */
  115. /*RCR_AAP |*/
  116. RCR_APP_PHYST_STAFF |
  117. /* Accept PHY status */
  118. RCR_APP_PHYST_RXFF |
  119. (earlyrxthreshold << RCR_FIFO_OFFSET);
  120. rtlpci->irq_mask[0] = (u32)
  121. (IMR_ROK |
  122. IMR_VODOK |
  123. IMR_VIDOK |
  124. IMR_BEDOK |
  125. IMR_BKDOK |
  126. IMR_HCCADOK |
  127. IMR_MGNTDOK |
  128. IMR_COMDOK |
  129. IMR_HIGHDOK |
  130. IMR_BDOK |
  131. IMR_RXCMDOK |
  132. /*IMR_TIMEOUT0 |*/
  133. IMR_RDU |
  134. IMR_RXFOVW |
  135. IMR_BCNINT
  136. /*| IMR_TXFOVW*/
  137. /*| IMR_TBDOK |
  138. IMR_TBDER*/);
  139. rtlpci->irq_mask[1] = (u32) 0;
  140. rtlpci->shortretry_limit = 0x30;
  141. rtlpci->longretry_limit = 0x30;
  142. rtlpci->first_init = true;
  143. /* for debug level */
  144. rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
  145. /* for LPS & IPS */
  146. rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
  147. rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
  148. rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
  149. if (!rtlpriv->psc.inactiveps)
  150. pr_info("rtl8192ce: Power Save off (module option)\n");
  151. if (!rtlpriv->psc.fwctrl_lps)
  152. pr_info("rtl8192ce: FW Power Save off (module option)\n");
  153. rtlpriv->psc.reg_fwctrl_lps = 3;
  154. rtlpriv->psc.reg_max_lps_awakeintvl = 5;
  155. /* for ASPM, you can close aspm through
  156. * set const_support_pciaspm = 0 */
  157. rtl92s_init_aspm_vars(hw);
  158. if (rtlpriv->psc.reg_fwctrl_lps == 1)
  159. rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
  160. else if (rtlpriv->psc.reg_fwctrl_lps == 2)
  161. rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
  162. else if (rtlpriv->psc.reg_fwctrl_lps == 3)
  163. rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
  164. /* for firmware buf */
  165. rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
  166. if (!rtlpriv->rtlhal.pfirmware) {
  167. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  168. ("Can't alloc buffer for fw.\n"));
  169. return 1;
  170. }
  171. pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
  172. "Loading firmware %s\n", rtlpriv->cfg->fw_name);
  173. /* request fw */
  174. err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
  175. rtlpriv->io.dev);
  176. if (err) {
  177. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  178. ("Failed to request firmware!\n"));
  179. return 1;
  180. }
  181. if (firmware->size > sizeof(struct rt_firmware)) {
  182. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  183. ("Firmware is too big!\n"));
  184. release_firmware(firmware);
  185. return 1;
  186. }
  187. pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
  188. memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
  189. pfirmware->sz_fw_tmpbufferlen = firmware->size;
  190. release_firmware(firmware);
  191. return err;
  192. }
  193. static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
  194. {
  195. struct rtl_priv *rtlpriv = rtl_priv(hw);
  196. if (rtlpriv->rtlhal.pfirmware) {
  197. vfree(rtlpriv->rtlhal.pfirmware);
  198. rtlpriv->rtlhal.pfirmware = NULL;
  199. }
  200. }
  201. static struct rtl_hal_ops rtl8192se_hal_ops = {
  202. .init_sw_vars = rtl92s_init_sw_vars,
  203. .deinit_sw_vars = rtl92s_deinit_sw_vars,
  204. .read_eeprom_info = rtl92se_read_eeprom_info,
  205. .interrupt_recognized = rtl92se_interrupt_recognized,
  206. .hw_init = rtl92se_hw_init,
  207. .hw_disable = rtl92se_card_disable,
  208. .hw_suspend = rtl92se_suspend,
  209. .hw_resume = rtl92se_resume,
  210. .enable_interrupt = rtl92se_enable_interrupt,
  211. .disable_interrupt = rtl92se_disable_interrupt,
  212. .set_network_type = rtl92se_set_network_type,
  213. .set_chk_bssid = rtl92se_set_check_bssid,
  214. .set_qos = rtl92se_set_qos,
  215. .set_bcn_reg = rtl92se_set_beacon_related_registers,
  216. .set_bcn_intv = rtl92se_set_beacon_interval,
  217. .update_interrupt_mask = rtl92se_update_interrupt_mask,
  218. .get_hw_reg = rtl92se_get_hw_reg,
  219. .set_hw_reg = rtl92se_set_hw_reg,
  220. .update_rate_tbl = rtl92se_update_hal_rate_tbl,
  221. .fill_tx_desc = rtl92se_tx_fill_desc,
  222. .fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
  223. .query_rx_desc = rtl92se_rx_query_desc,
  224. .set_channel_access = rtl92se_update_channel_access_setting,
  225. .radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
  226. .set_bw_mode = rtl92s_phy_set_bw_mode,
  227. .switch_channel = rtl92s_phy_sw_chnl,
  228. .dm_watchdog = rtl92s_dm_watchdog,
  229. .scan_operation_backup = rtl92s_phy_scan_operation_backup,
  230. .set_rf_power_state = rtl92s_phy_set_rf_power_state,
  231. .led_control = rtl92se_led_control,
  232. .set_desc = rtl92se_set_desc,
  233. .get_desc = rtl92se_get_desc,
  234. .tx_polling = rtl92se_tx_polling,
  235. .enable_hw_sec = rtl92se_enable_hw_security_config,
  236. .set_key = rtl92se_set_key,
  237. .init_sw_leds = rtl92se_init_sw_leds,
  238. .get_bbreg = rtl92s_phy_query_bb_reg,
  239. .set_bbreg = rtl92s_phy_set_bb_reg,
  240. .get_rfreg = rtl92s_phy_query_rf_reg,
  241. .set_rfreg = rtl92s_phy_set_rf_reg,
  242. };
  243. static struct rtl_mod_params rtl92se_mod_params = {
  244. .sw_crypto = false,
  245. .inactiveps = true,
  246. .swctrl_lps = true,
  247. .fwctrl_lps = false,
  248. .debug = DBG_EMERG,
  249. };
  250. /* Because memory R/W bursting will cause system hang/crash
  251. * for 92se, so we don't read back after every write action */
  252. static struct rtl_hal_cfg rtl92se_hal_cfg = {
  253. .bar_id = 1,
  254. .write_readback = false,
  255. .name = "rtl92s_pci",
  256. .fw_name = "rtlwifi/rtl8192sefw.bin",
  257. .ops = &rtl8192se_hal_ops,
  258. .mod_params = &rtl92se_mod_params,
  259. .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
  260. .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
  261. .maps[SYS_CLK] = SYS_CLKR,
  262. .maps[MAC_RCR_AM] = RCR_AM,
  263. .maps[MAC_RCR_AB] = RCR_AB,
  264. .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
  265. .maps[MAC_RCR_ACF] = RCR_ACF,
  266. .maps[MAC_RCR_AAP] = RCR_AAP,
  267. .maps[EFUSE_TEST] = REG_EFUSE_TEST,
  268. .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
  269. .maps[EFUSE_CLK] = REG_EFUSE_CLK,
  270. .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
  271. .maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
  272. .maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
  273. .maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
  274. .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
  275. .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
  276. .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
  277. .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
  278. .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
  279. .maps[RWCAM] = REG_RWCAM,
  280. .maps[WCAMI] = REG_WCAMI,
  281. .maps[RCAMO] = REG_RCAMO,
  282. .maps[CAMDBG] = REG_CAMDBG,
  283. .maps[SECR] = REG_SECR,
  284. .maps[SEC_CAM_NONE] = CAM_NONE,
  285. .maps[SEC_CAM_WEP40] = CAM_WEP40,
  286. .maps[SEC_CAM_TKIP] = CAM_TKIP,
  287. .maps[SEC_CAM_AES] = CAM_AES,
  288. .maps[SEC_CAM_WEP104] = CAM_WEP104,
  289. .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
  290. .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
  291. .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
  292. .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
  293. .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
  294. .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
  295. .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
  296. .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
  297. .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
  298. .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
  299. .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
  300. .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
  301. .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
  302. .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
  303. .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
  304. .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
  305. .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
  306. .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
  307. .maps[RTL_IMR_BcnInt] = IMR_BCNINT,
  308. .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
  309. .maps[RTL_IMR_RDU] = IMR_RDU,
  310. .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
  311. .maps[RTL_IMR_BDOK] = IMR_BDOK,
  312. .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
  313. .maps[RTL_IMR_TBDER] = IMR_TBDER,
  314. .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
  315. .maps[RTL_IMR_COMDOK] = IMR_COMDOK,
  316. .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
  317. .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
  318. .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
  319. .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
  320. .maps[RTL_IMR_VODOK] = IMR_VODOK,
  321. .maps[RTL_IMR_ROK] = IMR_ROK,
  322. .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
  323. .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
  324. .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
  325. .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
  326. .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
  327. .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
  328. .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
  329. .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
  330. .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
  331. .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
  332. .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
  333. .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
  334. .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
  335. .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
  336. .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
  337. };
  338. static struct pci_device_id rtl92se_pci_ids[] __devinitdata = {
  339. {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
  340. {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
  341. {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
  342. {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
  343. {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
  344. {},
  345. };
  346. MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);
  347. MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
  348. MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
  349. MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
  350. MODULE_LICENSE("GPL");
  351. MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
  352. MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");
  353. module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
  354. module_param_named(debug, rtl92se_mod_params.debug, int, 0444);
  355. module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
  356. module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
  357. module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
  358. MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
  359. MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
  360. MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
  361. MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
  362. MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
  363. static const struct dev_pm_ops rtlwifi_pm_ops = {
  364. .suspend = rtl_pci_suspend,
  365. .resume = rtl_pci_resume,
  366. .freeze = rtl_pci_suspend,
  367. .thaw = rtl_pci_resume,
  368. .poweroff = rtl_pci_suspend,
  369. .restore = rtl_pci_resume,
  370. };
  371. static struct pci_driver rtl92se_driver = {
  372. .name = KBUILD_MODNAME,
  373. .id_table = rtl92se_pci_ids,
  374. .probe = rtl_pci_probe,
  375. .remove = rtl_pci_disconnect,
  376. .driver.pm = &rtlwifi_pm_ops,
  377. };
  378. static int __init rtl92se_module_init(void)
  379. {
  380. int ret = 0;
  381. ret = pci_register_driver(&rtl92se_driver);
  382. if (ret)
  383. RT_ASSERT(false, (": No device found\n"));
  384. return ret;
  385. }
  386. static void __exit rtl92se_module_exit(void)
  387. {
  388. pci_unregister_driver(&rtl92se_driver);
  389. }
  390. module_init(rtl92se_module_init);
  391. module_exit(rtl92se_module_exit);