intel_display.c 252 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/cpufreq.h>
  27. #include <linux/module.h>
  28. #include <linux/input.h>
  29. #include <linux/i2c.h>
  30. #include <linux/kernel.h>
  31. #include <linux/slab.h>
  32. #include <linux/vgaarb.h>
  33. #include <drm/drm_edid.h>
  34. #include "drmP.h"
  35. #include "intel_drv.h"
  36. #include "i915_drm.h"
  37. #include "i915_drv.h"
  38. #include "i915_trace.h"
  39. #include "drm_dp_helper.h"
  40. #include "drm_crtc_helper.h"
  41. #include <linux/dma_remapping.h>
  42. #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43. bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  44. static void intel_update_watermarks(struct drm_device *dev);
  45. static void intel_increase_pllclock(struct drm_crtc *crtc);
  46. static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47. typedef struct {
  48. /* given values */
  49. int n;
  50. int m1, m2;
  51. int p1, p2;
  52. /* derived values */
  53. int dot;
  54. int vco;
  55. int m;
  56. int p;
  57. } intel_clock_t;
  58. typedef struct {
  59. int min, max;
  60. } intel_range_t;
  61. typedef struct {
  62. int dot_limit;
  63. int p2_slow, p2_fast;
  64. } intel_p2_t;
  65. #define INTEL_P2_NUM 2
  66. typedef struct intel_limit intel_limit_t;
  67. struct intel_limit {
  68. intel_range_t dot, vco, n, m, m1, m2, p, p1;
  69. intel_p2_t p2;
  70. bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  71. int, int, intel_clock_t *, intel_clock_t *);
  72. };
  73. /* FDI */
  74. #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
  75. static bool
  76. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  77. int target, int refclk, intel_clock_t *match_clock,
  78. intel_clock_t *best_clock);
  79. static bool
  80. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  81. int target, int refclk, intel_clock_t *match_clock,
  82. intel_clock_t *best_clock);
  83. static bool
  84. intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
  85. int target, int refclk, intel_clock_t *match_clock,
  86. intel_clock_t *best_clock);
  87. static bool
  88. intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
  89. int target, int refclk, intel_clock_t *match_clock,
  90. intel_clock_t *best_clock);
  91. static inline u32 /* units of 100MHz */
  92. intel_fdi_link_freq(struct drm_device *dev)
  93. {
  94. if (IS_GEN5(dev)) {
  95. struct drm_i915_private *dev_priv = dev->dev_private;
  96. return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
  97. } else
  98. return 27;
  99. }
  100. static const intel_limit_t intel_limits_i8xx_dvo = {
  101. .dot = { .min = 25000, .max = 350000 },
  102. .vco = { .min = 930000, .max = 1400000 },
  103. .n = { .min = 3, .max = 16 },
  104. .m = { .min = 96, .max = 140 },
  105. .m1 = { .min = 18, .max = 26 },
  106. .m2 = { .min = 6, .max = 16 },
  107. .p = { .min = 4, .max = 128 },
  108. .p1 = { .min = 2, .max = 33 },
  109. .p2 = { .dot_limit = 165000,
  110. .p2_slow = 4, .p2_fast = 2 },
  111. .find_pll = intel_find_best_PLL,
  112. };
  113. static const intel_limit_t intel_limits_i8xx_lvds = {
  114. .dot = { .min = 25000, .max = 350000 },
  115. .vco = { .min = 930000, .max = 1400000 },
  116. .n = { .min = 3, .max = 16 },
  117. .m = { .min = 96, .max = 140 },
  118. .m1 = { .min = 18, .max = 26 },
  119. .m2 = { .min = 6, .max = 16 },
  120. .p = { .min = 4, .max = 128 },
  121. .p1 = { .min = 1, .max = 6 },
  122. .p2 = { .dot_limit = 165000,
  123. .p2_slow = 14, .p2_fast = 7 },
  124. .find_pll = intel_find_best_PLL,
  125. };
  126. static const intel_limit_t intel_limits_i9xx_sdvo = {
  127. .dot = { .min = 20000, .max = 400000 },
  128. .vco = { .min = 1400000, .max = 2800000 },
  129. .n = { .min = 1, .max = 6 },
  130. .m = { .min = 70, .max = 120 },
  131. .m1 = { .min = 10, .max = 22 },
  132. .m2 = { .min = 5, .max = 9 },
  133. .p = { .min = 5, .max = 80 },
  134. .p1 = { .min = 1, .max = 8 },
  135. .p2 = { .dot_limit = 200000,
  136. .p2_slow = 10, .p2_fast = 5 },
  137. .find_pll = intel_find_best_PLL,
  138. };
  139. static const intel_limit_t intel_limits_i9xx_lvds = {
  140. .dot = { .min = 20000, .max = 400000 },
  141. .vco = { .min = 1400000, .max = 2800000 },
  142. .n = { .min = 1, .max = 6 },
  143. .m = { .min = 70, .max = 120 },
  144. .m1 = { .min = 10, .max = 22 },
  145. .m2 = { .min = 5, .max = 9 },
  146. .p = { .min = 7, .max = 98 },
  147. .p1 = { .min = 1, .max = 8 },
  148. .p2 = { .dot_limit = 112000,
  149. .p2_slow = 14, .p2_fast = 7 },
  150. .find_pll = intel_find_best_PLL,
  151. };
  152. static const intel_limit_t intel_limits_g4x_sdvo = {
  153. .dot = { .min = 25000, .max = 270000 },
  154. .vco = { .min = 1750000, .max = 3500000},
  155. .n = { .min = 1, .max = 4 },
  156. .m = { .min = 104, .max = 138 },
  157. .m1 = { .min = 17, .max = 23 },
  158. .m2 = { .min = 5, .max = 11 },
  159. .p = { .min = 10, .max = 30 },
  160. .p1 = { .min = 1, .max = 3},
  161. .p2 = { .dot_limit = 270000,
  162. .p2_slow = 10,
  163. .p2_fast = 10
  164. },
  165. .find_pll = intel_g4x_find_best_PLL,
  166. };
  167. static const intel_limit_t intel_limits_g4x_hdmi = {
  168. .dot = { .min = 22000, .max = 400000 },
  169. .vco = { .min = 1750000, .max = 3500000},
  170. .n = { .min = 1, .max = 4 },
  171. .m = { .min = 104, .max = 138 },
  172. .m1 = { .min = 16, .max = 23 },
  173. .m2 = { .min = 5, .max = 11 },
  174. .p = { .min = 5, .max = 80 },
  175. .p1 = { .min = 1, .max = 8},
  176. .p2 = { .dot_limit = 165000,
  177. .p2_slow = 10, .p2_fast = 5 },
  178. .find_pll = intel_g4x_find_best_PLL,
  179. };
  180. static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
  181. .dot = { .min = 20000, .max = 115000 },
  182. .vco = { .min = 1750000, .max = 3500000 },
  183. .n = { .min = 1, .max = 3 },
  184. .m = { .min = 104, .max = 138 },
  185. .m1 = { .min = 17, .max = 23 },
  186. .m2 = { .min = 5, .max = 11 },
  187. .p = { .min = 28, .max = 112 },
  188. .p1 = { .min = 2, .max = 8 },
  189. .p2 = { .dot_limit = 0,
  190. .p2_slow = 14, .p2_fast = 14
  191. },
  192. .find_pll = intel_g4x_find_best_PLL,
  193. };
  194. static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
  195. .dot = { .min = 80000, .max = 224000 },
  196. .vco = { .min = 1750000, .max = 3500000 },
  197. .n = { .min = 1, .max = 3 },
  198. .m = { .min = 104, .max = 138 },
  199. .m1 = { .min = 17, .max = 23 },
  200. .m2 = { .min = 5, .max = 11 },
  201. .p = { .min = 14, .max = 42 },
  202. .p1 = { .min = 2, .max = 6 },
  203. .p2 = { .dot_limit = 0,
  204. .p2_slow = 7, .p2_fast = 7
  205. },
  206. .find_pll = intel_g4x_find_best_PLL,
  207. };
  208. static const intel_limit_t intel_limits_g4x_display_port = {
  209. .dot = { .min = 161670, .max = 227000 },
  210. .vco = { .min = 1750000, .max = 3500000},
  211. .n = { .min = 1, .max = 2 },
  212. .m = { .min = 97, .max = 108 },
  213. .m1 = { .min = 0x10, .max = 0x12 },
  214. .m2 = { .min = 0x05, .max = 0x06 },
  215. .p = { .min = 10, .max = 20 },
  216. .p1 = { .min = 1, .max = 2},
  217. .p2 = { .dot_limit = 0,
  218. .p2_slow = 10, .p2_fast = 10 },
  219. .find_pll = intel_find_pll_g4x_dp,
  220. };
  221. static const intel_limit_t intel_limits_pineview_sdvo = {
  222. .dot = { .min = 20000, .max = 400000},
  223. .vco = { .min = 1700000, .max = 3500000 },
  224. /* Pineview's Ncounter is a ring counter */
  225. .n = { .min = 3, .max = 6 },
  226. .m = { .min = 2, .max = 256 },
  227. /* Pineview only has one combined m divider, which we treat as m2. */
  228. .m1 = { .min = 0, .max = 0 },
  229. .m2 = { .min = 0, .max = 254 },
  230. .p = { .min = 5, .max = 80 },
  231. .p1 = { .min = 1, .max = 8 },
  232. .p2 = { .dot_limit = 200000,
  233. .p2_slow = 10, .p2_fast = 5 },
  234. .find_pll = intel_find_best_PLL,
  235. };
  236. static const intel_limit_t intel_limits_pineview_lvds = {
  237. .dot = { .min = 20000, .max = 400000 },
  238. .vco = { .min = 1700000, .max = 3500000 },
  239. .n = { .min = 3, .max = 6 },
  240. .m = { .min = 2, .max = 256 },
  241. .m1 = { .min = 0, .max = 0 },
  242. .m2 = { .min = 0, .max = 254 },
  243. .p = { .min = 7, .max = 112 },
  244. .p1 = { .min = 1, .max = 8 },
  245. .p2 = { .dot_limit = 112000,
  246. .p2_slow = 14, .p2_fast = 14 },
  247. .find_pll = intel_find_best_PLL,
  248. };
  249. /* Ironlake / Sandybridge
  250. *
  251. * We calculate clock using (register_value + 2) for N/M1/M2, so here
  252. * the range value for them is (actual_value - 2).
  253. */
  254. static const intel_limit_t intel_limits_ironlake_dac = {
  255. .dot = { .min = 25000, .max = 350000 },
  256. .vco = { .min = 1760000, .max = 3510000 },
  257. .n = { .min = 1, .max = 5 },
  258. .m = { .min = 79, .max = 127 },
  259. .m1 = { .min = 12, .max = 22 },
  260. .m2 = { .min = 5, .max = 9 },
  261. .p = { .min = 5, .max = 80 },
  262. .p1 = { .min = 1, .max = 8 },
  263. .p2 = { .dot_limit = 225000,
  264. .p2_slow = 10, .p2_fast = 5 },
  265. .find_pll = intel_g4x_find_best_PLL,
  266. };
  267. static const intel_limit_t intel_limits_ironlake_single_lvds = {
  268. .dot = { .min = 25000, .max = 350000 },
  269. .vco = { .min = 1760000, .max = 3510000 },
  270. .n = { .min = 1, .max = 3 },
  271. .m = { .min = 79, .max = 118 },
  272. .m1 = { .min = 12, .max = 22 },
  273. .m2 = { .min = 5, .max = 9 },
  274. .p = { .min = 28, .max = 112 },
  275. .p1 = { .min = 2, .max = 8 },
  276. .p2 = { .dot_limit = 225000,
  277. .p2_slow = 14, .p2_fast = 14 },
  278. .find_pll = intel_g4x_find_best_PLL,
  279. };
  280. static const intel_limit_t intel_limits_ironlake_dual_lvds = {
  281. .dot = { .min = 25000, .max = 350000 },
  282. .vco = { .min = 1760000, .max = 3510000 },
  283. .n = { .min = 1, .max = 3 },
  284. .m = { .min = 79, .max = 127 },
  285. .m1 = { .min = 12, .max = 22 },
  286. .m2 = { .min = 5, .max = 9 },
  287. .p = { .min = 14, .max = 56 },
  288. .p1 = { .min = 2, .max = 8 },
  289. .p2 = { .dot_limit = 225000,
  290. .p2_slow = 7, .p2_fast = 7 },
  291. .find_pll = intel_g4x_find_best_PLL,
  292. };
  293. /* LVDS 100mhz refclk limits. */
  294. static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
  295. .dot = { .min = 25000, .max = 350000 },
  296. .vco = { .min = 1760000, .max = 3510000 },
  297. .n = { .min = 1, .max = 2 },
  298. .m = { .min = 79, .max = 126 },
  299. .m1 = { .min = 12, .max = 22 },
  300. .m2 = { .min = 5, .max = 9 },
  301. .p = { .min = 28, .max = 112 },
  302. .p1 = { .min = 2, .max = 8 },
  303. .p2 = { .dot_limit = 225000,
  304. .p2_slow = 14, .p2_fast = 14 },
  305. .find_pll = intel_g4x_find_best_PLL,
  306. };
  307. static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
  308. .dot = { .min = 25000, .max = 350000 },
  309. .vco = { .min = 1760000, .max = 3510000 },
  310. .n = { .min = 1, .max = 3 },
  311. .m = { .min = 79, .max = 126 },
  312. .m1 = { .min = 12, .max = 22 },
  313. .m2 = { .min = 5, .max = 9 },
  314. .p = { .min = 14, .max = 42 },
  315. .p1 = { .min = 2, .max = 6 },
  316. .p2 = { .dot_limit = 225000,
  317. .p2_slow = 7, .p2_fast = 7 },
  318. .find_pll = intel_g4x_find_best_PLL,
  319. };
  320. static const intel_limit_t intel_limits_ironlake_display_port = {
  321. .dot = { .min = 25000, .max = 350000 },
  322. .vco = { .min = 1760000, .max = 3510000},
  323. .n = { .min = 1, .max = 2 },
  324. .m = { .min = 81, .max = 90 },
  325. .m1 = { .min = 12, .max = 22 },
  326. .m2 = { .min = 5, .max = 9 },
  327. .p = { .min = 10, .max = 20 },
  328. .p1 = { .min = 1, .max = 2},
  329. .p2 = { .dot_limit = 0,
  330. .p2_slow = 10, .p2_fast = 10 },
  331. .find_pll = intel_find_pll_ironlake_dp,
  332. };
  333. static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
  334. int refclk)
  335. {
  336. struct drm_device *dev = crtc->dev;
  337. struct drm_i915_private *dev_priv = dev->dev_private;
  338. const intel_limit_t *limit;
  339. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  340. if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
  341. LVDS_CLKB_POWER_UP) {
  342. /* LVDS dual channel */
  343. if (refclk == 100000)
  344. limit = &intel_limits_ironlake_dual_lvds_100m;
  345. else
  346. limit = &intel_limits_ironlake_dual_lvds;
  347. } else {
  348. if (refclk == 100000)
  349. limit = &intel_limits_ironlake_single_lvds_100m;
  350. else
  351. limit = &intel_limits_ironlake_single_lvds;
  352. }
  353. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  354. HAS_eDP)
  355. limit = &intel_limits_ironlake_display_port;
  356. else
  357. limit = &intel_limits_ironlake_dac;
  358. return limit;
  359. }
  360. static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
  361. {
  362. struct drm_device *dev = crtc->dev;
  363. struct drm_i915_private *dev_priv = dev->dev_private;
  364. const intel_limit_t *limit;
  365. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  366. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  367. LVDS_CLKB_POWER_UP)
  368. /* LVDS with dual channel */
  369. limit = &intel_limits_g4x_dual_channel_lvds;
  370. else
  371. /* LVDS with dual channel */
  372. limit = &intel_limits_g4x_single_channel_lvds;
  373. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
  374. intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
  375. limit = &intel_limits_g4x_hdmi;
  376. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
  377. limit = &intel_limits_g4x_sdvo;
  378. } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  379. limit = &intel_limits_g4x_display_port;
  380. } else /* The option is for other outputs */
  381. limit = &intel_limits_i9xx_sdvo;
  382. return limit;
  383. }
  384. static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
  385. {
  386. struct drm_device *dev = crtc->dev;
  387. const intel_limit_t *limit;
  388. if (HAS_PCH_SPLIT(dev))
  389. limit = intel_ironlake_limit(crtc, refclk);
  390. else if (IS_G4X(dev)) {
  391. limit = intel_g4x_limit(crtc);
  392. } else if (IS_PINEVIEW(dev)) {
  393. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  394. limit = &intel_limits_pineview_lvds;
  395. else
  396. limit = &intel_limits_pineview_sdvo;
  397. } else if (!IS_GEN2(dev)) {
  398. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  399. limit = &intel_limits_i9xx_lvds;
  400. else
  401. limit = &intel_limits_i9xx_sdvo;
  402. } else {
  403. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  404. limit = &intel_limits_i8xx_lvds;
  405. else
  406. limit = &intel_limits_i8xx_dvo;
  407. }
  408. return limit;
  409. }
  410. /* m1 is reserved as 0 in Pineview, n is a ring counter */
  411. static void pineview_clock(int refclk, intel_clock_t *clock)
  412. {
  413. clock->m = clock->m2 + 2;
  414. clock->p = clock->p1 * clock->p2;
  415. clock->vco = refclk * clock->m / clock->n;
  416. clock->dot = clock->vco / clock->p;
  417. }
  418. static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
  419. {
  420. if (IS_PINEVIEW(dev)) {
  421. pineview_clock(refclk, clock);
  422. return;
  423. }
  424. clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  425. clock->p = clock->p1 * clock->p2;
  426. clock->vco = refclk * clock->m / (clock->n + 2);
  427. clock->dot = clock->vco / clock->p;
  428. }
  429. /**
  430. * Returns whether any output on the specified pipe is of the specified type
  431. */
  432. bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
  433. {
  434. struct drm_device *dev = crtc->dev;
  435. struct drm_mode_config *mode_config = &dev->mode_config;
  436. struct intel_encoder *encoder;
  437. list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
  438. if (encoder->base.crtc == crtc && encoder->type == type)
  439. return true;
  440. return false;
  441. }
  442. #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
  443. /**
  444. * Returns whether the given set of divisors are valid for a given refclk with
  445. * the given connectors.
  446. */
  447. static bool intel_PLL_is_valid(struct drm_device *dev,
  448. const intel_limit_t *limit,
  449. const intel_clock_t *clock)
  450. {
  451. if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
  452. INTELPllInvalid("p1 out of range\n");
  453. if (clock->p < limit->p.min || limit->p.max < clock->p)
  454. INTELPllInvalid("p out of range\n");
  455. if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
  456. INTELPllInvalid("m2 out of range\n");
  457. if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
  458. INTELPllInvalid("m1 out of range\n");
  459. if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
  460. INTELPllInvalid("m1 <= m2\n");
  461. if (clock->m < limit->m.min || limit->m.max < clock->m)
  462. INTELPllInvalid("m out of range\n");
  463. if (clock->n < limit->n.min || limit->n.max < clock->n)
  464. INTELPllInvalid("n out of range\n");
  465. if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
  466. INTELPllInvalid("vco out of range\n");
  467. /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
  468. * connector, etc., rather than just a single range.
  469. */
  470. if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
  471. INTELPllInvalid("dot out of range\n");
  472. return true;
  473. }
  474. static bool
  475. intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  476. int target, int refclk, intel_clock_t *match_clock,
  477. intel_clock_t *best_clock)
  478. {
  479. struct drm_device *dev = crtc->dev;
  480. struct drm_i915_private *dev_priv = dev->dev_private;
  481. intel_clock_t clock;
  482. int err = target;
  483. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  484. (I915_READ(LVDS)) != 0) {
  485. /*
  486. * For LVDS, if the panel is on, just rely on its current
  487. * settings for dual-channel. We haven't figured out how to
  488. * reliably set up different single/dual channel state, if we
  489. * even can.
  490. */
  491. if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
  492. LVDS_CLKB_POWER_UP)
  493. clock.p2 = limit->p2.p2_fast;
  494. else
  495. clock.p2 = limit->p2.p2_slow;
  496. } else {
  497. if (target < limit->p2.dot_limit)
  498. clock.p2 = limit->p2.p2_slow;
  499. else
  500. clock.p2 = limit->p2.p2_fast;
  501. }
  502. memset(best_clock, 0, sizeof(*best_clock));
  503. for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
  504. clock.m1++) {
  505. for (clock.m2 = limit->m2.min;
  506. clock.m2 <= limit->m2.max; clock.m2++) {
  507. /* m1 is always 0 in Pineview */
  508. if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
  509. break;
  510. for (clock.n = limit->n.min;
  511. clock.n <= limit->n.max; clock.n++) {
  512. for (clock.p1 = limit->p1.min;
  513. clock.p1 <= limit->p1.max; clock.p1++) {
  514. int this_err;
  515. intel_clock(dev, refclk, &clock);
  516. if (!intel_PLL_is_valid(dev, limit,
  517. &clock))
  518. continue;
  519. if (match_clock &&
  520. clock.p != match_clock->p)
  521. continue;
  522. this_err = abs(clock.dot - target);
  523. if (this_err < err) {
  524. *best_clock = clock;
  525. err = this_err;
  526. }
  527. }
  528. }
  529. }
  530. }
  531. return (err != target);
  532. }
  533. static bool
  534. intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  535. int target, int refclk, intel_clock_t *match_clock,
  536. intel_clock_t *best_clock)
  537. {
  538. struct drm_device *dev = crtc->dev;
  539. struct drm_i915_private *dev_priv = dev->dev_private;
  540. intel_clock_t clock;
  541. int max_n;
  542. bool found;
  543. /* approximately equals target * 0.00585 */
  544. int err_most = (target >> 8) + (target >> 9);
  545. found = false;
  546. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  547. int lvds_reg;
  548. if (HAS_PCH_SPLIT(dev))
  549. lvds_reg = PCH_LVDS;
  550. else
  551. lvds_reg = LVDS;
  552. if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
  553. LVDS_CLKB_POWER_UP)
  554. clock.p2 = limit->p2.p2_fast;
  555. else
  556. clock.p2 = limit->p2.p2_slow;
  557. } else {
  558. if (target < limit->p2.dot_limit)
  559. clock.p2 = limit->p2.p2_slow;
  560. else
  561. clock.p2 = limit->p2.p2_fast;
  562. }
  563. memset(best_clock, 0, sizeof(*best_clock));
  564. max_n = limit->n.max;
  565. /* based on hardware requirement, prefer smaller n to precision */
  566. for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
  567. /* based on hardware requirement, prefere larger m1,m2 */
  568. for (clock.m1 = limit->m1.max;
  569. clock.m1 >= limit->m1.min; clock.m1--) {
  570. for (clock.m2 = limit->m2.max;
  571. clock.m2 >= limit->m2.min; clock.m2--) {
  572. for (clock.p1 = limit->p1.max;
  573. clock.p1 >= limit->p1.min; clock.p1--) {
  574. int this_err;
  575. intel_clock(dev, refclk, &clock);
  576. if (!intel_PLL_is_valid(dev, limit,
  577. &clock))
  578. continue;
  579. if (match_clock &&
  580. clock.p != match_clock->p)
  581. continue;
  582. this_err = abs(clock.dot - target);
  583. if (this_err < err_most) {
  584. *best_clock = clock;
  585. err_most = this_err;
  586. max_n = clock.n;
  587. found = true;
  588. }
  589. }
  590. }
  591. }
  592. }
  593. return found;
  594. }
  595. static bool
  596. intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  597. int target, int refclk, intel_clock_t *match_clock,
  598. intel_clock_t *best_clock)
  599. {
  600. struct drm_device *dev = crtc->dev;
  601. intel_clock_t clock;
  602. if (target < 200000) {
  603. clock.n = 1;
  604. clock.p1 = 2;
  605. clock.p2 = 10;
  606. clock.m1 = 12;
  607. clock.m2 = 9;
  608. } else {
  609. clock.n = 2;
  610. clock.p1 = 1;
  611. clock.p2 = 10;
  612. clock.m1 = 14;
  613. clock.m2 = 8;
  614. }
  615. intel_clock(dev, refclk, &clock);
  616. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  617. return true;
  618. }
  619. /* DisplayPort has only two frequencies, 162MHz and 270MHz */
  620. static bool
  621. intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
  622. int target, int refclk, intel_clock_t *match_clock,
  623. intel_clock_t *best_clock)
  624. {
  625. intel_clock_t clock;
  626. if (target < 200000) {
  627. clock.p1 = 2;
  628. clock.p2 = 10;
  629. clock.n = 2;
  630. clock.m1 = 23;
  631. clock.m2 = 8;
  632. } else {
  633. clock.p1 = 1;
  634. clock.p2 = 10;
  635. clock.n = 1;
  636. clock.m1 = 14;
  637. clock.m2 = 2;
  638. }
  639. clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
  640. clock.p = (clock.p1 * clock.p2);
  641. clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
  642. clock.vco = 0;
  643. memcpy(best_clock, &clock, sizeof(intel_clock_t));
  644. return true;
  645. }
  646. /**
  647. * intel_wait_for_vblank - wait for vblank on a given pipe
  648. * @dev: drm device
  649. * @pipe: pipe to wait for
  650. *
  651. * Wait for vblank to occur on a given pipe. Needed for various bits of
  652. * mode setting code.
  653. */
  654. void intel_wait_for_vblank(struct drm_device *dev, int pipe)
  655. {
  656. struct drm_i915_private *dev_priv = dev->dev_private;
  657. int pipestat_reg = PIPESTAT(pipe);
  658. /* Clear existing vblank status. Note this will clear any other
  659. * sticky status fields as well.
  660. *
  661. * This races with i915_driver_irq_handler() with the result
  662. * that either function could miss a vblank event. Here it is not
  663. * fatal, as we will either wait upon the next vblank interrupt or
  664. * timeout. Generally speaking intel_wait_for_vblank() is only
  665. * called during modeset at which time the GPU should be idle and
  666. * should *not* be performing page flips and thus not waiting on
  667. * vblanks...
  668. * Currently, the result of us stealing a vblank from the irq
  669. * handler is that a single frame will be skipped during swapbuffers.
  670. */
  671. I915_WRITE(pipestat_reg,
  672. I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
  673. /* Wait for vblank interrupt bit to set */
  674. if (wait_for(I915_READ(pipestat_reg) &
  675. PIPE_VBLANK_INTERRUPT_STATUS,
  676. 50))
  677. DRM_DEBUG_KMS("vblank wait timed out\n");
  678. }
  679. /*
  680. * intel_wait_for_pipe_off - wait for pipe to turn off
  681. * @dev: drm device
  682. * @pipe: pipe to wait for
  683. *
  684. * After disabling a pipe, we can't wait for vblank in the usual way,
  685. * spinning on the vblank interrupt status bit, since we won't actually
  686. * see an interrupt when the pipe is disabled.
  687. *
  688. * On Gen4 and above:
  689. * wait for the pipe register state bit to turn off
  690. *
  691. * Otherwise:
  692. * wait for the display line value to settle (it usually
  693. * ends up stopping at the start of the next frame).
  694. *
  695. */
  696. void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
  697. {
  698. struct drm_i915_private *dev_priv = dev->dev_private;
  699. if (INTEL_INFO(dev)->gen >= 4) {
  700. int reg = PIPECONF(pipe);
  701. /* Wait for the Pipe State to go off */
  702. if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
  703. 100))
  704. DRM_DEBUG_KMS("pipe_off wait timed out\n");
  705. } else {
  706. u32 last_line;
  707. int reg = PIPEDSL(pipe);
  708. unsigned long timeout = jiffies + msecs_to_jiffies(100);
  709. /* Wait for the display line to settle */
  710. do {
  711. last_line = I915_READ(reg) & DSL_LINEMASK;
  712. mdelay(5);
  713. } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
  714. time_after(timeout, jiffies));
  715. if (time_after(jiffies, timeout))
  716. DRM_DEBUG_KMS("pipe_off wait timed out\n");
  717. }
  718. }
  719. static const char *state_string(bool enabled)
  720. {
  721. return enabled ? "on" : "off";
  722. }
  723. /* Only for pre-ILK configs */
  724. static void assert_pll(struct drm_i915_private *dev_priv,
  725. enum pipe pipe, bool state)
  726. {
  727. int reg;
  728. u32 val;
  729. bool cur_state;
  730. reg = DPLL(pipe);
  731. val = I915_READ(reg);
  732. cur_state = !!(val & DPLL_VCO_ENABLE);
  733. WARN(cur_state != state,
  734. "PLL state assertion failure (expected %s, current %s)\n",
  735. state_string(state), state_string(cur_state));
  736. }
  737. #define assert_pll_enabled(d, p) assert_pll(d, p, true)
  738. #define assert_pll_disabled(d, p) assert_pll(d, p, false)
  739. /* For ILK+ */
  740. static void assert_pch_pll(struct drm_i915_private *dev_priv,
  741. enum pipe pipe, bool state)
  742. {
  743. int reg;
  744. u32 val;
  745. bool cur_state;
  746. if (HAS_PCH_CPT(dev_priv->dev)) {
  747. u32 pch_dpll;
  748. pch_dpll = I915_READ(PCH_DPLL_SEL);
  749. /* Make sure the selected PLL is enabled to the transcoder */
  750. WARN(!((pch_dpll >> (4 * pipe)) & 8),
  751. "transcoder %d PLL not enabled\n", pipe);
  752. /* Convert the transcoder pipe number to a pll pipe number */
  753. pipe = (pch_dpll >> (4 * pipe)) & 1;
  754. }
  755. reg = PCH_DPLL(pipe);
  756. val = I915_READ(reg);
  757. cur_state = !!(val & DPLL_VCO_ENABLE);
  758. WARN(cur_state != state,
  759. "PCH PLL state assertion failure (expected %s, current %s)\n",
  760. state_string(state), state_string(cur_state));
  761. }
  762. #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
  763. #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
  764. static void assert_fdi_tx(struct drm_i915_private *dev_priv,
  765. enum pipe pipe, bool state)
  766. {
  767. int reg;
  768. u32 val;
  769. bool cur_state;
  770. reg = FDI_TX_CTL(pipe);
  771. val = I915_READ(reg);
  772. cur_state = !!(val & FDI_TX_ENABLE);
  773. WARN(cur_state != state,
  774. "FDI TX state assertion failure (expected %s, current %s)\n",
  775. state_string(state), state_string(cur_state));
  776. }
  777. #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
  778. #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
  779. static void assert_fdi_rx(struct drm_i915_private *dev_priv,
  780. enum pipe pipe, bool state)
  781. {
  782. int reg;
  783. u32 val;
  784. bool cur_state;
  785. reg = FDI_RX_CTL(pipe);
  786. val = I915_READ(reg);
  787. cur_state = !!(val & FDI_RX_ENABLE);
  788. WARN(cur_state != state,
  789. "FDI RX state assertion failure (expected %s, current %s)\n",
  790. state_string(state), state_string(cur_state));
  791. }
  792. #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
  793. #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
  794. static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
  795. enum pipe pipe)
  796. {
  797. int reg;
  798. u32 val;
  799. /* ILK FDI PLL is always enabled */
  800. if (dev_priv->info->gen == 5)
  801. return;
  802. reg = FDI_TX_CTL(pipe);
  803. val = I915_READ(reg);
  804. WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
  805. }
  806. static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
  807. enum pipe pipe)
  808. {
  809. int reg;
  810. u32 val;
  811. reg = FDI_RX_CTL(pipe);
  812. val = I915_READ(reg);
  813. WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
  814. }
  815. static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
  816. enum pipe pipe)
  817. {
  818. int pp_reg, lvds_reg;
  819. u32 val;
  820. enum pipe panel_pipe = PIPE_A;
  821. bool locked = true;
  822. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  823. pp_reg = PCH_PP_CONTROL;
  824. lvds_reg = PCH_LVDS;
  825. } else {
  826. pp_reg = PP_CONTROL;
  827. lvds_reg = LVDS;
  828. }
  829. val = I915_READ(pp_reg);
  830. if (!(val & PANEL_POWER_ON) ||
  831. ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
  832. locked = false;
  833. if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
  834. panel_pipe = PIPE_B;
  835. WARN(panel_pipe == pipe && locked,
  836. "panel assertion failure, pipe %c regs locked\n",
  837. pipe_name(pipe));
  838. }
  839. void assert_pipe(struct drm_i915_private *dev_priv,
  840. enum pipe pipe, bool state)
  841. {
  842. int reg;
  843. u32 val;
  844. bool cur_state;
  845. /* if we need the pipe A quirk it must be always on */
  846. if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
  847. state = true;
  848. reg = PIPECONF(pipe);
  849. val = I915_READ(reg);
  850. cur_state = !!(val & PIPECONF_ENABLE);
  851. WARN(cur_state != state,
  852. "pipe %c assertion failure (expected %s, current %s)\n",
  853. pipe_name(pipe), state_string(state), state_string(cur_state));
  854. }
  855. static void assert_plane(struct drm_i915_private *dev_priv,
  856. enum plane plane, bool state)
  857. {
  858. int reg;
  859. u32 val;
  860. bool cur_state;
  861. reg = DSPCNTR(plane);
  862. val = I915_READ(reg);
  863. cur_state = !!(val & DISPLAY_PLANE_ENABLE);
  864. WARN(cur_state != state,
  865. "plane %c assertion failure (expected %s, current %s)\n",
  866. plane_name(plane), state_string(state), state_string(cur_state));
  867. }
  868. #define assert_plane_enabled(d, p) assert_plane(d, p, true)
  869. #define assert_plane_disabled(d, p) assert_plane(d, p, false)
  870. static void assert_planes_disabled(struct drm_i915_private *dev_priv,
  871. enum pipe pipe)
  872. {
  873. int reg, i;
  874. u32 val;
  875. int cur_pipe;
  876. /* Planes are fixed to pipes on ILK+ */
  877. if (HAS_PCH_SPLIT(dev_priv->dev)) {
  878. reg = DSPCNTR(pipe);
  879. val = I915_READ(reg);
  880. WARN((val & DISPLAY_PLANE_ENABLE),
  881. "plane %c assertion failure, should be disabled but not\n",
  882. plane_name(pipe));
  883. return;
  884. }
  885. /* Need to check both planes against the pipe */
  886. for (i = 0; i < 2; i++) {
  887. reg = DSPCNTR(i);
  888. val = I915_READ(reg);
  889. cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
  890. DISPPLANE_SEL_PIPE_SHIFT;
  891. WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
  892. "plane %c assertion failure, should be off on pipe %c but is still active\n",
  893. plane_name(i), pipe_name(pipe));
  894. }
  895. }
  896. static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
  897. {
  898. u32 val;
  899. bool enabled;
  900. val = I915_READ(PCH_DREF_CONTROL);
  901. enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
  902. DREF_SUPERSPREAD_SOURCE_MASK));
  903. WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
  904. }
  905. static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
  906. enum pipe pipe)
  907. {
  908. int reg;
  909. u32 val;
  910. bool enabled;
  911. reg = TRANSCONF(pipe);
  912. val = I915_READ(reg);
  913. enabled = !!(val & TRANS_ENABLE);
  914. WARN(enabled,
  915. "transcoder assertion failed, should be off on pipe %c but is still active\n",
  916. pipe_name(pipe));
  917. }
  918. static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
  919. enum pipe pipe, u32 port_sel, u32 val)
  920. {
  921. if ((val & DP_PORT_EN) == 0)
  922. return false;
  923. if (HAS_PCH_CPT(dev_priv->dev)) {
  924. u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
  925. u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
  926. if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
  927. return false;
  928. } else {
  929. if ((val & DP_PIPE_MASK) != (pipe << 30))
  930. return false;
  931. }
  932. return true;
  933. }
  934. static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
  935. enum pipe pipe, u32 val)
  936. {
  937. if ((val & PORT_ENABLE) == 0)
  938. return false;
  939. if (HAS_PCH_CPT(dev_priv->dev)) {
  940. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  941. return false;
  942. } else {
  943. if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
  944. return false;
  945. }
  946. return true;
  947. }
  948. static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
  949. enum pipe pipe, u32 val)
  950. {
  951. if ((val & LVDS_PORT_EN) == 0)
  952. return false;
  953. if (HAS_PCH_CPT(dev_priv->dev)) {
  954. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  955. return false;
  956. } else {
  957. if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
  958. return false;
  959. }
  960. return true;
  961. }
  962. static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
  963. enum pipe pipe, u32 val)
  964. {
  965. if ((val & ADPA_DAC_ENABLE) == 0)
  966. return false;
  967. if (HAS_PCH_CPT(dev_priv->dev)) {
  968. if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
  969. return false;
  970. } else {
  971. if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
  972. return false;
  973. }
  974. return true;
  975. }
  976. static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
  977. enum pipe pipe, int reg, u32 port_sel)
  978. {
  979. u32 val = I915_READ(reg);
  980. WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
  981. "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
  982. reg, pipe_name(pipe));
  983. }
  984. static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
  985. enum pipe pipe, int reg)
  986. {
  987. u32 val = I915_READ(reg);
  988. WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
  989. "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
  990. reg, pipe_name(pipe));
  991. }
  992. static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
  993. enum pipe pipe)
  994. {
  995. int reg;
  996. u32 val;
  997. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  998. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  999. assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1000. reg = PCH_ADPA;
  1001. val = I915_READ(reg);
  1002. WARN(adpa_pipe_enabled(dev_priv, val, pipe),
  1003. "PCH VGA enabled on transcoder %c, should be disabled\n",
  1004. pipe_name(pipe));
  1005. reg = PCH_LVDS;
  1006. val = I915_READ(reg);
  1007. WARN(lvds_pipe_enabled(dev_priv, val, pipe),
  1008. "PCH LVDS enabled on transcoder %c, should be disabled\n",
  1009. pipe_name(pipe));
  1010. assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
  1011. assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
  1012. assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
  1013. }
  1014. /**
  1015. * intel_enable_pll - enable a PLL
  1016. * @dev_priv: i915 private structure
  1017. * @pipe: pipe PLL to enable
  1018. *
  1019. * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
  1020. * make sure the PLL reg is writable first though, since the panel write
  1021. * protect mechanism may be enabled.
  1022. *
  1023. * Note! This is for pre-ILK only.
  1024. */
  1025. static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1026. {
  1027. int reg;
  1028. u32 val;
  1029. /* No really, not for ILK+ */
  1030. BUG_ON(dev_priv->info->gen >= 5);
  1031. /* PLL is protected by panel, make sure we can write it */
  1032. if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
  1033. assert_panel_unlocked(dev_priv, pipe);
  1034. reg = DPLL(pipe);
  1035. val = I915_READ(reg);
  1036. val |= DPLL_VCO_ENABLE;
  1037. /* We do this three times for luck */
  1038. I915_WRITE(reg, val);
  1039. POSTING_READ(reg);
  1040. udelay(150); /* wait for warmup */
  1041. I915_WRITE(reg, val);
  1042. POSTING_READ(reg);
  1043. udelay(150); /* wait for warmup */
  1044. I915_WRITE(reg, val);
  1045. POSTING_READ(reg);
  1046. udelay(150); /* wait for warmup */
  1047. }
  1048. /**
  1049. * intel_disable_pll - disable a PLL
  1050. * @dev_priv: i915 private structure
  1051. * @pipe: pipe PLL to disable
  1052. *
  1053. * Disable the PLL for @pipe, making sure the pipe is off first.
  1054. *
  1055. * Note! This is for pre-ILK only.
  1056. */
  1057. static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
  1058. {
  1059. int reg;
  1060. u32 val;
  1061. /* Don't disable pipe A or pipe A PLLs if needed */
  1062. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1063. return;
  1064. /* Make sure the pipe isn't still relying on us */
  1065. assert_pipe_disabled(dev_priv, pipe);
  1066. reg = DPLL(pipe);
  1067. val = I915_READ(reg);
  1068. val &= ~DPLL_VCO_ENABLE;
  1069. I915_WRITE(reg, val);
  1070. POSTING_READ(reg);
  1071. }
  1072. /**
  1073. * intel_enable_pch_pll - enable PCH PLL
  1074. * @dev_priv: i915 private structure
  1075. * @pipe: pipe PLL to enable
  1076. *
  1077. * The PCH PLL needs to be enabled before the PCH transcoder, since it
  1078. * drives the transcoder clock.
  1079. */
  1080. static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
  1081. enum pipe pipe)
  1082. {
  1083. int reg;
  1084. u32 val;
  1085. if (pipe > 1)
  1086. return;
  1087. /* PCH only available on ILK+ */
  1088. BUG_ON(dev_priv->info->gen < 5);
  1089. /* PCH refclock must be enabled first */
  1090. assert_pch_refclk_enabled(dev_priv);
  1091. reg = PCH_DPLL(pipe);
  1092. val = I915_READ(reg);
  1093. val |= DPLL_VCO_ENABLE;
  1094. I915_WRITE(reg, val);
  1095. POSTING_READ(reg);
  1096. udelay(200);
  1097. }
  1098. static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
  1099. enum pipe pipe)
  1100. {
  1101. int reg;
  1102. u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
  1103. pll_sel = TRANSC_DPLL_ENABLE;
  1104. if (pipe > 1)
  1105. return;
  1106. /* PCH only available on ILK+ */
  1107. BUG_ON(dev_priv->info->gen < 5);
  1108. /* Make sure transcoder isn't still depending on us */
  1109. assert_transcoder_disabled(dev_priv, pipe);
  1110. if (pipe == 0)
  1111. pll_sel |= TRANSC_DPLLA_SEL;
  1112. else if (pipe == 1)
  1113. pll_sel |= TRANSC_DPLLB_SEL;
  1114. if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
  1115. return;
  1116. reg = PCH_DPLL(pipe);
  1117. val = I915_READ(reg);
  1118. val &= ~DPLL_VCO_ENABLE;
  1119. I915_WRITE(reg, val);
  1120. POSTING_READ(reg);
  1121. udelay(200);
  1122. }
  1123. static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
  1124. enum pipe pipe)
  1125. {
  1126. int reg;
  1127. u32 val, pipeconf_val;
  1128. /* PCH only available on ILK+ */
  1129. BUG_ON(dev_priv->info->gen < 5);
  1130. /* Make sure PCH DPLL is enabled */
  1131. assert_pch_pll_enabled(dev_priv, pipe);
  1132. /* FDI must be feeding us bits for PCH ports */
  1133. assert_fdi_tx_enabled(dev_priv, pipe);
  1134. assert_fdi_rx_enabled(dev_priv, pipe);
  1135. reg = TRANSCONF(pipe);
  1136. val = I915_READ(reg);
  1137. pipeconf_val = I915_READ(PIPECONF(pipe));
  1138. if (HAS_PCH_IBX(dev_priv->dev)) {
  1139. /*
  1140. * make the BPC in transcoder be consistent with
  1141. * that in pipeconf reg.
  1142. */
  1143. val &= ~PIPE_BPC_MASK;
  1144. val |= pipeconf_val & PIPE_BPC_MASK;
  1145. }
  1146. val &= ~TRANS_INTERLACE_MASK;
  1147. if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
  1148. val |= TRANS_INTERLACED;
  1149. else
  1150. val |= TRANS_PROGRESSIVE;
  1151. I915_WRITE(reg, val | TRANS_ENABLE);
  1152. if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
  1153. DRM_ERROR("failed to enable transcoder %d\n", pipe);
  1154. }
  1155. static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
  1156. enum pipe pipe)
  1157. {
  1158. int reg;
  1159. u32 val;
  1160. /* FDI relies on the transcoder */
  1161. assert_fdi_tx_disabled(dev_priv, pipe);
  1162. assert_fdi_rx_disabled(dev_priv, pipe);
  1163. /* Ports must be off as well */
  1164. assert_pch_ports_disabled(dev_priv, pipe);
  1165. reg = TRANSCONF(pipe);
  1166. val = I915_READ(reg);
  1167. val &= ~TRANS_ENABLE;
  1168. I915_WRITE(reg, val);
  1169. /* wait for PCH transcoder off, transcoder state */
  1170. if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
  1171. DRM_ERROR("failed to disable transcoder %d\n", pipe);
  1172. }
  1173. /**
  1174. * intel_enable_pipe - enable a pipe, asserting requirements
  1175. * @dev_priv: i915 private structure
  1176. * @pipe: pipe to enable
  1177. * @pch_port: on ILK+, is this pipe driving a PCH port or not
  1178. *
  1179. * Enable @pipe, making sure that various hardware specific requirements
  1180. * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
  1181. *
  1182. * @pipe should be %PIPE_A or %PIPE_B.
  1183. *
  1184. * Will wait until the pipe is actually running (i.e. first vblank) before
  1185. * returning.
  1186. */
  1187. static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
  1188. bool pch_port)
  1189. {
  1190. int reg;
  1191. u32 val;
  1192. /*
  1193. * A pipe without a PLL won't actually be able to drive bits from
  1194. * a plane. On ILK+ the pipe PLLs are integrated, so we don't
  1195. * need the check.
  1196. */
  1197. if (!HAS_PCH_SPLIT(dev_priv->dev))
  1198. assert_pll_enabled(dev_priv, pipe);
  1199. else {
  1200. if (pch_port) {
  1201. /* if driving the PCH, we need FDI enabled */
  1202. assert_fdi_rx_pll_enabled(dev_priv, pipe);
  1203. assert_fdi_tx_pll_enabled(dev_priv, pipe);
  1204. }
  1205. /* FIXME: assert CPU port conditions for SNB+ */
  1206. }
  1207. reg = PIPECONF(pipe);
  1208. val = I915_READ(reg);
  1209. if (val & PIPECONF_ENABLE)
  1210. return;
  1211. I915_WRITE(reg, val | PIPECONF_ENABLE);
  1212. intel_wait_for_vblank(dev_priv->dev, pipe);
  1213. }
  1214. /**
  1215. * intel_disable_pipe - disable a pipe, asserting requirements
  1216. * @dev_priv: i915 private structure
  1217. * @pipe: pipe to disable
  1218. *
  1219. * Disable @pipe, making sure that various hardware specific requirements
  1220. * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
  1221. *
  1222. * @pipe should be %PIPE_A or %PIPE_B.
  1223. *
  1224. * Will wait until the pipe has shut down before returning.
  1225. */
  1226. static void intel_disable_pipe(struct drm_i915_private *dev_priv,
  1227. enum pipe pipe)
  1228. {
  1229. int reg;
  1230. u32 val;
  1231. /*
  1232. * Make sure planes won't keep trying to pump pixels to us,
  1233. * or we might hang the display.
  1234. */
  1235. assert_planes_disabled(dev_priv, pipe);
  1236. /* Don't disable pipe A or pipe A PLLs if needed */
  1237. if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
  1238. return;
  1239. reg = PIPECONF(pipe);
  1240. val = I915_READ(reg);
  1241. if ((val & PIPECONF_ENABLE) == 0)
  1242. return;
  1243. I915_WRITE(reg, val & ~PIPECONF_ENABLE);
  1244. intel_wait_for_pipe_off(dev_priv->dev, pipe);
  1245. }
  1246. /*
  1247. * Plane regs are double buffered, going from enabled->disabled needs a
  1248. * trigger in order to latch. The display address reg provides this.
  1249. */
  1250. static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
  1251. enum plane plane)
  1252. {
  1253. I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
  1254. I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
  1255. }
  1256. /**
  1257. * intel_enable_plane - enable a display plane on a given pipe
  1258. * @dev_priv: i915 private structure
  1259. * @plane: plane to enable
  1260. * @pipe: pipe being fed
  1261. *
  1262. * Enable @plane on @pipe, making sure that @pipe is running first.
  1263. */
  1264. static void intel_enable_plane(struct drm_i915_private *dev_priv,
  1265. enum plane plane, enum pipe pipe)
  1266. {
  1267. int reg;
  1268. u32 val;
  1269. /* If the pipe isn't enabled, we can't pump pixels and may hang */
  1270. assert_pipe_enabled(dev_priv, pipe);
  1271. reg = DSPCNTR(plane);
  1272. val = I915_READ(reg);
  1273. if (val & DISPLAY_PLANE_ENABLE)
  1274. return;
  1275. I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
  1276. intel_flush_display_plane(dev_priv, plane);
  1277. intel_wait_for_vblank(dev_priv->dev, pipe);
  1278. }
  1279. /**
  1280. * intel_disable_plane - disable a display plane
  1281. * @dev_priv: i915 private structure
  1282. * @plane: plane to disable
  1283. * @pipe: pipe consuming the data
  1284. *
  1285. * Disable @plane; should be an independent operation.
  1286. */
  1287. static void intel_disable_plane(struct drm_i915_private *dev_priv,
  1288. enum plane plane, enum pipe pipe)
  1289. {
  1290. int reg;
  1291. u32 val;
  1292. reg = DSPCNTR(plane);
  1293. val = I915_READ(reg);
  1294. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  1295. return;
  1296. I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
  1297. intel_flush_display_plane(dev_priv, plane);
  1298. intel_wait_for_vblank(dev_priv->dev, pipe);
  1299. }
  1300. static void disable_pch_dp(struct drm_i915_private *dev_priv,
  1301. enum pipe pipe, int reg, u32 port_sel)
  1302. {
  1303. u32 val = I915_READ(reg);
  1304. if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
  1305. DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
  1306. I915_WRITE(reg, val & ~DP_PORT_EN);
  1307. }
  1308. }
  1309. static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
  1310. enum pipe pipe, int reg)
  1311. {
  1312. u32 val = I915_READ(reg);
  1313. if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
  1314. DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
  1315. reg, pipe);
  1316. I915_WRITE(reg, val & ~PORT_ENABLE);
  1317. }
  1318. }
  1319. /* Disable any ports connected to this transcoder */
  1320. static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
  1321. enum pipe pipe)
  1322. {
  1323. u32 reg, val;
  1324. val = I915_READ(PCH_PP_CONTROL);
  1325. I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
  1326. disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
  1327. disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
  1328. disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
  1329. reg = PCH_ADPA;
  1330. val = I915_READ(reg);
  1331. if (adpa_pipe_enabled(dev_priv, val, pipe))
  1332. I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
  1333. reg = PCH_LVDS;
  1334. val = I915_READ(reg);
  1335. if (lvds_pipe_enabled(dev_priv, val, pipe)) {
  1336. DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
  1337. I915_WRITE(reg, val & ~LVDS_PORT_EN);
  1338. POSTING_READ(reg);
  1339. udelay(100);
  1340. }
  1341. disable_pch_hdmi(dev_priv, pipe, HDMIB);
  1342. disable_pch_hdmi(dev_priv, pipe, HDMIC);
  1343. disable_pch_hdmi(dev_priv, pipe, HDMID);
  1344. }
  1345. static void i8xx_disable_fbc(struct drm_device *dev)
  1346. {
  1347. struct drm_i915_private *dev_priv = dev->dev_private;
  1348. u32 fbc_ctl;
  1349. /* Disable compression */
  1350. fbc_ctl = I915_READ(FBC_CONTROL);
  1351. if ((fbc_ctl & FBC_CTL_EN) == 0)
  1352. return;
  1353. fbc_ctl &= ~FBC_CTL_EN;
  1354. I915_WRITE(FBC_CONTROL, fbc_ctl);
  1355. /* Wait for compressing bit to clear */
  1356. if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  1357. DRM_DEBUG_KMS("FBC idle timed out\n");
  1358. return;
  1359. }
  1360. DRM_DEBUG_KMS("disabled FBC\n");
  1361. }
  1362. static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1363. {
  1364. struct drm_device *dev = crtc->dev;
  1365. struct drm_i915_private *dev_priv = dev->dev_private;
  1366. struct drm_framebuffer *fb = crtc->fb;
  1367. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1368. struct drm_i915_gem_object *obj = intel_fb->obj;
  1369. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1370. int cfb_pitch;
  1371. int plane, i;
  1372. u32 fbc_ctl, fbc_ctl2;
  1373. cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  1374. if (fb->pitches[0] < cfb_pitch)
  1375. cfb_pitch = fb->pitches[0];
  1376. /* FBC_CTL wants 64B units */
  1377. cfb_pitch = (cfb_pitch / 64) - 1;
  1378. plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  1379. /* Clear old tags */
  1380. for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  1381. I915_WRITE(FBC_TAG + (i * 4), 0);
  1382. /* Set it up... */
  1383. fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
  1384. fbc_ctl2 |= plane;
  1385. I915_WRITE(FBC_CONTROL2, fbc_ctl2);
  1386. I915_WRITE(FBC_FENCE_OFF, crtc->y);
  1387. /* enable it... */
  1388. fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
  1389. if (IS_I945GM(dev))
  1390. fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
  1391. fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
  1392. fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
  1393. fbc_ctl |= obj->fence_reg;
  1394. I915_WRITE(FBC_CONTROL, fbc_ctl);
  1395. DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
  1396. cfb_pitch, crtc->y, intel_crtc->plane);
  1397. }
  1398. static bool i8xx_fbc_enabled(struct drm_device *dev)
  1399. {
  1400. struct drm_i915_private *dev_priv = dev->dev_private;
  1401. return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
  1402. }
  1403. static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1404. {
  1405. struct drm_device *dev = crtc->dev;
  1406. struct drm_i915_private *dev_priv = dev->dev_private;
  1407. struct drm_framebuffer *fb = crtc->fb;
  1408. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1409. struct drm_i915_gem_object *obj = intel_fb->obj;
  1410. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1411. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  1412. unsigned long stall_watermark = 200;
  1413. u32 dpfc_ctl;
  1414. dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
  1415. dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
  1416. I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
  1417. I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  1418. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  1419. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  1420. I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
  1421. /* enable it... */
  1422. I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
  1423. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1424. }
  1425. static void g4x_disable_fbc(struct drm_device *dev)
  1426. {
  1427. struct drm_i915_private *dev_priv = dev->dev_private;
  1428. u32 dpfc_ctl;
  1429. /* Disable compression */
  1430. dpfc_ctl = I915_READ(DPFC_CONTROL);
  1431. if (dpfc_ctl & DPFC_CTL_EN) {
  1432. dpfc_ctl &= ~DPFC_CTL_EN;
  1433. I915_WRITE(DPFC_CONTROL, dpfc_ctl);
  1434. DRM_DEBUG_KMS("disabled FBC\n");
  1435. }
  1436. }
  1437. static bool g4x_fbc_enabled(struct drm_device *dev)
  1438. {
  1439. struct drm_i915_private *dev_priv = dev->dev_private;
  1440. return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
  1441. }
  1442. static void sandybridge_blit_fbc_update(struct drm_device *dev)
  1443. {
  1444. struct drm_i915_private *dev_priv = dev->dev_private;
  1445. u32 blt_ecoskpd;
  1446. /* Make sure blitter notifies FBC of writes */
  1447. gen6_gt_force_wake_get(dev_priv);
  1448. blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
  1449. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
  1450. GEN6_BLITTER_LOCK_SHIFT;
  1451. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  1452. blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
  1453. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  1454. blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
  1455. GEN6_BLITTER_LOCK_SHIFT);
  1456. I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
  1457. POSTING_READ(GEN6_BLITTER_ECOSKPD);
  1458. gen6_gt_force_wake_put(dev_priv);
  1459. }
  1460. static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1461. {
  1462. struct drm_device *dev = crtc->dev;
  1463. struct drm_i915_private *dev_priv = dev->dev_private;
  1464. struct drm_framebuffer *fb = crtc->fb;
  1465. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  1466. struct drm_i915_gem_object *obj = intel_fb->obj;
  1467. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1468. int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
  1469. unsigned long stall_watermark = 200;
  1470. u32 dpfc_ctl;
  1471. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  1472. dpfc_ctl &= DPFC_RESERVED;
  1473. dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
  1474. /* Set persistent mode for front-buffer rendering, ala X. */
  1475. dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
  1476. dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
  1477. I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
  1478. I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
  1479. (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
  1480. (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
  1481. I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
  1482. I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
  1483. /* enable it... */
  1484. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
  1485. if (IS_GEN6(dev)) {
  1486. I915_WRITE(SNB_DPFC_CTL_SA,
  1487. SNB_CPU_FENCE_ENABLE | obj->fence_reg);
  1488. I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
  1489. sandybridge_blit_fbc_update(dev);
  1490. }
  1491. DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
  1492. }
  1493. static void ironlake_disable_fbc(struct drm_device *dev)
  1494. {
  1495. struct drm_i915_private *dev_priv = dev->dev_private;
  1496. u32 dpfc_ctl;
  1497. /* Disable compression */
  1498. dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
  1499. if (dpfc_ctl & DPFC_CTL_EN) {
  1500. dpfc_ctl &= ~DPFC_CTL_EN;
  1501. I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
  1502. DRM_DEBUG_KMS("disabled FBC\n");
  1503. }
  1504. }
  1505. static bool ironlake_fbc_enabled(struct drm_device *dev)
  1506. {
  1507. struct drm_i915_private *dev_priv = dev->dev_private;
  1508. return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
  1509. }
  1510. bool intel_fbc_enabled(struct drm_device *dev)
  1511. {
  1512. struct drm_i915_private *dev_priv = dev->dev_private;
  1513. if (!dev_priv->display.fbc_enabled)
  1514. return false;
  1515. return dev_priv->display.fbc_enabled(dev);
  1516. }
  1517. static void intel_fbc_work_fn(struct work_struct *__work)
  1518. {
  1519. struct intel_fbc_work *work =
  1520. container_of(to_delayed_work(__work),
  1521. struct intel_fbc_work, work);
  1522. struct drm_device *dev = work->crtc->dev;
  1523. struct drm_i915_private *dev_priv = dev->dev_private;
  1524. mutex_lock(&dev->struct_mutex);
  1525. if (work == dev_priv->fbc_work) {
  1526. /* Double check that we haven't switched fb without cancelling
  1527. * the prior work.
  1528. */
  1529. if (work->crtc->fb == work->fb) {
  1530. dev_priv->display.enable_fbc(work->crtc,
  1531. work->interval);
  1532. dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
  1533. dev_priv->cfb_fb = work->crtc->fb->base.id;
  1534. dev_priv->cfb_y = work->crtc->y;
  1535. }
  1536. dev_priv->fbc_work = NULL;
  1537. }
  1538. mutex_unlock(&dev->struct_mutex);
  1539. kfree(work);
  1540. }
  1541. static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
  1542. {
  1543. if (dev_priv->fbc_work == NULL)
  1544. return;
  1545. DRM_DEBUG_KMS("cancelling pending FBC enable\n");
  1546. /* Synchronisation is provided by struct_mutex and checking of
  1547. * dev_priv->fbc_work, so we can perform the cancellation
  1548. * entirely asynchronously.
  1549. */
  1550. if (cancel_delayed_work(&dev_priv->fbc_work->work))
  1551. /* tasklet was killed before being run, clean up */
  1552. kfree(dev_priv->fbc_work);
  1553. /* Mark the work as no longer wanted so that if it does
  1554. * wake-up (because the work was already running and waiting
  1555. * for our mutex), it will discover that is no longer
  1556. * necessary to run.
  1557. */
  1558. dev_priv->fbc_work = NULL;
  1559. }
  1560. static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  1561. {
  1562. struct intel_fbc_work *work;
  1563. struct drm_device *dev = crtc->dev;
  1564. struct drm_i915_private *dev_priv = dev->dev_private;
  1565. if (!dev_priv->display.enable_fbc)
  1566. return;
  1567. intel_cancel_fbc_work(dev_priv);
  1568. work = kzalloc(sizeof *work, GFP_KERNEL);
  1569. if (work == NULL) {
  1570. dev_priv->display.enable_fbc(crtc, interval);
  1571. return;
  1572. }
  1573. work->crtc = crtc;
  1574. work->fb = crtc->fb;
  1575. work->interval = interval;
  1576. INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
  1577. dev_priv->fbc_work = work;
  1578. DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
  1579. /* Delay the actual enabling to let pageflipping cease and the
  1580. * display to settle before starting the compression. Note that
  1581. * this delay also serves a second purpose: it allows for a
  1582. * vblank to pass after disabling the FBC before we attempt
  1583. * to modify the control registers.
  1584. *
  1585. * A more complicated solution would involve tracking vblanks
  1586. * following the termination of the page-flipping sequence
  1587. * and indeed performing the enable as a co-routine and not
  1588. * waiting synchronously upon the vblank.
  1589. */
  1590. schedule_delayed_work(&work->work, msecs_to_jiffies(50));
  1591. }
  1592. void intel_disable_fbc(struct drm_device *dev)
  1593. {
  1594. struct drm_i915_private *dev_priv = dev->dev_private;
  1595. intel_cancel_fbc_work(dev_priv);
  1596. if (!dev_priv->display.disable_fbc)
  1597. return;
  1598. dev_priv->display.disable_fbc(dev);
  1599. dev_priv->cfb_plane = -1;
  1600. }
  1601. /**
  1602. * intel_update_fbc - enable/disable FBC as needed
  1603. * @dev: the drm_device
  1604. *
  1605. * Set up the framebuffer compression hardware at mode set time. We
  1606. * enable it if possible:
  1607. * - plane A only (on pre-965)
  1608. * - no pixel mulitply/line duplication
  1609. * - no alpha buffer discard
  1610. * - no dual wide
  1611. * - framebuffer <= 2048 in width, 1536 in height
  1612. *
  1613. * We can't assume that any compression will take place (worst case),
  1614. * so the compressed buffer has to be the same size as the uncompressed
  1615. * one. It also must reside (along with the line length buffer) in
  1616. * stolen memory.
  1617. *
  1618. * We need to enable/disable FBC on a global basis.
  1619. */
  1620. static void intel_update_fbc(struct drm_device *dev)
  1621. {
  1622. struct drm_i915_private *dev_priv = dev->dev_private;
  1623. struct drm_crtc *crtc = NULL, *tmp_crtc;
  1624. struct intel_crtc *intel_crtc;
  1625. struct drm_framebuffer *fb;
  1626. struct intel_framebuffer *intel_fb;
  1627. struct drm_i915_gem_object *obj;
  1628. int enable_fbc;
  1629. DRM_DEBUG_KMS("\n");
  1630. if (!i915_powersave)
  1631. return;
  1632. if (!I915_HAS_FBC(dev))
  1633. return;
  1634. /*
  1635. * If FBC is already on, we just have to verify that we can
  1636. * keep it that way...
  1637. * Need to disable if:
  1638. * - more than one pipe is active
  1639. * - changing FBC params (stride, fence, mode)
  1640. * - new fb is too large to fit in compressed buffer
  1641. * - going to an unsupported config (interlace, pixel multiply, etc.)
  1642. */
  1643. list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
  1644. if (tmp_crtc->enabled && tmp_crtc->fb) {
  1645. if (crtc) {
  1646. DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
  1647. dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
  1648. goto out_disable;
  1649. }
  1650. crtc = tmp_crtc;
  1651. }
  1652. }
  1653. if (!crtc || crtc->fb == NULL) {
  1654. DRM_DEBUG_KMS("no output, disabling\n");
  1655. dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
  1656. goto out_disable;
  1657. }
  1658. intel_crtc = to_intel_crtc(crtc);
  1659. fb = crtc->fb;
  1660. intel_fb = to_intel_framebuffer(fb);
  1661. obj = intel_fb->obj;
  1662. enable_fbc = i915_enable_fbc;
  1663. if (enable_fbc < 0) {
  1664. DRM_DEBUG_KMS("fbc set to per-chip default\n");
  1665. enable_fbc = 1;
  1666. if (INTEL_INFO(dev)->gen <= 6)
  1667. enable_fbc = 0;
  1668. }
  1669. if (!enable_fbc) {
  1670. DRM_DEBUG_KMS("fbc disabled per module param\n");
  1671. dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
  1672. goto out_disable;
  1673. }
  1674. if (intel_fb->obj->base.size > dev_priv->cfb_size) {
  1675. DRM_DEBUG_KMS("framebuffer too large, disabling "
  1676. "compression\n");
  1677. dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
  1678. goto out_disable;
  1679. }
  1680. if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
  1681. (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
  1682. DRM_DEBUG_KMS("mode incompatible with compression, "
  1683. "disabling\n");
  1684. dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
  1685. goto out_disable;
  1686. }
  1687. if ((crtc->mode.hdisplay > 2048) ||
  1688. (crtc->mode.vdisplay > 1536)) {
  1689. DRM_DEBUG_KMS("mode too large for compression, disabling\n");
  1690. dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
  1691. goto out_disable;
  1692. }
  1693. if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
  1694. DRM_DEBUG_KMS("plane not 0, disabling compression\n");
  1695. dev_priv->no_fbc_reason = FBC_BAD_PLANE;
  1696. goto out_disable;
  1697. }
  1698. /* The use of a CPU fence is mandatory in order to detect writes
  1699. * by the CPU to the scanout and trigger updates to the FBC.
  1700. */
  1701. if (obj->tiling_mode != I915_TILING_X ||
  1702. obj->fence_reg == I915_FENCE_REG_NONE) {
  1703. DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
  1704. dev_priv->no_fbc_reason = FBC_NOT_TILED;
  1705. goto out_disable;
  1706. }
  1707. /* If the kernel debugger is active, always disable compression */
  1708. if (in_dbg_master())
  1709. goto out_disable;
  1710. /* If the scanout has not changed, don't modify the FBC settings.
  1711. * Note that we make the fundamental assumption that the fb->obj
  1712. * cannot be unpinned (and have its GTT offset and fence revoked)
  1713. * without first being decoupled from the scanout and FBC disabled.
  1714. */
  1715. if (dev_priv->cfb_plane == intel_crtc->plane &&
  1716. dev_priv->cfb_fb == fb->base.id &&
  1717. dev_priv->cfb_y == crtc->y)
  1718. return;
  1719. if (intel_fbc_enabled(dev)) {
  1720. /* We update FBC along two paths, after changing fb/crtc
  1721. * configuration (modeswitching) and after page-flipping
  1722. * finishes. For the latter, we know that not only did
  1723. * we disable the FBC at the start of the page-flip
  1724. * sequence, but also more than one vblank has passed.
  1725. *
  1726. * For the former case of modeswitching, it is possible
  1727. * to switch between two FBC valid configurations
  1728. * instantaneously so we do need to disable the FBC
  1729. * before we can modify its control registers. We also
  1730. * have to wait for the next vblank for that to take
  1731. * effect. However, since we delay enabling FBC we can
  1732. * assume that a vblank has passed since disabling and
  1733. * that we can safely alter the registers in the deferred
  1734. * callback.
  1735. *
  1736. * In the scenario that we go from a valid to invalid
  1737. * and then back to valid FBC configuration we have
  1738. * no strict enforcement that a vblank occurred since
  1739. * disabling the FBC. However, along all current pipe
  1740. * disabling paths we do need to wait for a vblank at
  1741. * some point. And we wait before enabling FBC anyway.
  1742. */
  1743. DRM_DEBUG_KMS("disabling active FBC for update\n");
  1744. intel_disable_fbc(dev);
  1745. }
  1746. intel_enable_fbc(crtc, 500);
  1747. return;
  1748. out_disable:
  1749. /* Multiple disables should be harmless */
  1750. if (intel_fbc_enabled(dev)) {
  1751. DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
  1752. intel_disable_fbc(dev);
  1753. }
  1754. }
  1755. int
  1756. intel_pin_and_fence_fb_obj(struct drm_device *dev,
  1757. struct drm_i915_gem_object *obj,
  1758. struct intel_ring_buffer *pipelined)
  1759. {
  1760. struct drm_i915_private *dev_priv = dev->dev_private;
  1761. u32 alignment;
  1762. int ret;
  1763. switch (obj->tiling_mode) {
  1764. case I915_TILING_NONE:
  1765. if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
  1766. alignment = 128 * 1024;
  1767. else if (INTEL_INFO(dev)->gen >= 4)
  1768. alignment = 4 * 1024;
  1769. else
  1770. alignment = 64 * 1024;
  1771. break;
  1772. case I915_TILING_X:
  1773. /* pin() will align the object as required by fence */
  1774. alignment = 0;
  1775. break;
  1776. case I915_TILING_Y:
  1777. /* FIXME: Is this true? */
  1778. DRM_ERROR("Y tiled not allowed for scan out buffers\n");
  1779. return -EINVAL;
  1780. default:
  1781. BUG();
  1782. }
  1783. dev_priv->mm.interruptible = false;
  1784. ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
  1785. if (ret)
  1786. goto err_interruptible;
  1787. /* Install a fence for tiled scan-out. Pre-i965 always needs a
  1788. * fence, whereas 965+ only requires a fence if using
  1789. * framebuffer compression. For simplicity, we always install
  1790. * a fence as the cost is not that onerous.
  1791. */
  1792. if (obj->tiling_mode != I915_TILING_NONE) {
  1793. ret = i915_gem_object_get_fence(obj, pipelined);
  1794. if (ret)
  1795. goto err_unpin;
  1796. i915_gem_object_pin_fence(obj);
  1797. }
  1798. dev_priv->mm.interruptible = true;
  1799. return 0;
  1800. err_unpin:
  1801. i915_gem_object_unpin(obj);
  1802. err_interruptible:
  1803. dev_priv->mm.interruptible = true;
  1804. return ret;
  1805. }
  1806. void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
  1807. {
  1808. i915_gem_object_unpin_fence(obj);
  1809. i915_gem_object_unpin(obj);
  1810. }
  1811. static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1812. int x, int y)
  1813. {
  1814. struct drm_device *dev = crtc->dev;
  1815. struct drm_i915_private *dev_priv = dev->dev_private;
  1816. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1817. struct intel_framebuffer *intel_fb;
  1818. struct drm_i915_gem_object *obj;
  1819. int plane = intel_crtc->plane;
  1820. unsigned long Start, Offset;
  1821. u32 dspcntr;
  1822. u32 reg;
  1823. switch (plane) {
  1824. case 0:
  1825. case 1:
  1826. break;
  1827. default:
  1828. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1829. return -EINVAL;
  1830. }
  1831. intel_fb = to_intel_framebuffer(fb);
  1832. obj = intel_fb->obj;
  1833. reg = DSPCNTR(plane);
  1834. dspcntr = I915_READ(reg);
  1835. /* Mask out pixel format bits in case we change it */
  1836. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1837. switch (fb->bits_per_pixel) {
  1838. case 8:
  1839. dspcntr |= DISPPLANE_8BPP;
  1840. break;
  1841. case 16:
  1842. if (fb->depth == 15)
  1843. dspcntr |= DISPPLANE_15_16BPP;
  1844. else
  1845. dspcntr |= DISPPLANE_16BPP;
  1846. break;
  1847. case 24:
  1848. case 32:
  1849. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1850. break;
  1851. default:
  1852. DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
  1853. return -EINVAL;
  1854. }
  1855. if (INTEL_INFO(dev)->gen >= 4) {
  1856. if (obj->tiling_mode != I915_TILING_NONE)
  1857. dspcntr |= DISPPLANE_TILED;
  1858. else
  1859. dspcntr &= ~DISPPLANE_TILED;
  1860. }
  1861. I915_WRITE(reg, dspcntr);
  1862. Start = obj->gtt_offset;
  1863. Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1864. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1865. Start, Offset, x, y, fb->pitches[0]);
  1866. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1867. if (INTEL_INFO(dev)->gen >= 4) {
  1868. I915_WRITE(DSPSURF(plane), Start);
  1869. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1870. I915_WRITE(DSPADDR(plane), Offset);
  1871. } else
  1872. I915_WRITE(DSPADDR(plane), Start + Offset);
  1873. POSTING_READ(reg);
  1874. return 0;
  1875. }
  1876. static int ironlake_update_plane(struct drm_crtc *crtc,
  1877. struct drm_framebuffer *fb, int x, int y)
  1878. {
  1879. struct drm_device *dev = crtc->dev;
  1880. struct drm_i915_private *dev_priv = dev->dev_private;
  1881. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1882. struct intel_framebuffer *intel_fb;
  1883. struct drm_i915_gem_object *obj;
  1884. int plane = intel_crtc->plane;
  1885. unsigned long Start, Offset;
  1886. u32 dspcntr;
  1887. u32 reg;
  1888. switch (plane) {
  1889. case 0:
  1890. case 1:
  1891. case 2:
  1892. break;
  1893. default:
  1894. DRM_ERROR("Can't update plane %d in SAREA\n", plane);
  1895. return -EINVAL;
  1896. }
  1897. intel_fb = to_intel_framebuffer(fb);
  1898. obj = intel_fb->obj;
  1899. reg = DSPCNTR(plane);
  1900. dspcntr = I915_READ(reg);
  1901. /* Mask out pixel format bits in case we change it */
  1902. dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  1903. switch (fb->bits_per_pixel) {
  1904. case 8:
  1905. dspcntr |= DISPPLANE_8BPP;
  1906. break;
  1907. case 16:
  1908. if (fb->depth != 16)
  1909. return -EINVAL;
  1910. dspcntr |= DISPPLANE_16BPP;
  1911. break;
  1912. case 24:
  1913. case 32:
  1914. if (fb->depth == 24)
  1915. dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
  1916. else if (fb->depth == 30)
  1917. dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
  1918. else
  1919. return -EINVAL;
  1920. break;
  1921. default:
  1922. DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
  1923. return -EINVAL;
  1924. }
  1925. if (obj->tiling_mode != I915_TILING_NONE)
  1926. dspcntr |= DISPPLANE_TILED;
  1927. else
  1928. dspcntr &= ~DISPPLANE_TILED;
  1929. /* must disable */
  1930. dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
  1931. I915_WRITE(reg, dspcntr);
  1932. Start = obj->gtt_offset;
  1933. Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
  1934. DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
  1935. Start, Offset, x, y, fb->pitches[0]);
  1936. I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
  1937. I915_WRITE(DSPSURF(plane), Start);
  1938. I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
  1939. I915_WRITE(DSPADDR(plane), Offset);
  1940. POSTING_READ(reg);
  1941. return 0;
  1942. }
  1943. /* Assume fb object is pinned & idle & fenced and just update base pointers */
  1944. static int
  1945. intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
  1946. int x, int y, enum mode_set_atomic state)
  1947. {
  1948. struct drm_device *dev = crtc->dev;
  1949. struct drm_i915_private *dev_priv = dev->dev_private;
  1950. int ret;
  1951. ret = dev_priv->display.update_plane(crtc, fb, x, y);
  1952. if (ret)
  1953. return ret;
  1954. intel_update_fbc(dev);
  1955. intel_increase_pllclock(crtc);
  1956. return 0;
  1957. }
  1958. static int
  1959. intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  1960. struct drm_framebuffer *old_fb)
  1961. {
  1962. struct drm_device *dev = crtc->dev;
  1963. struct drm_i915_master_private *master_priv;
  1964. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1965. int ret;
  1966. /* no fb bound */
  1967. if (!crtc->fb) {
  1968. DRM_ERROR("No FB bound\n");
  1969. return 0;
  1970. }
  1971. switch (intel_crtc->plane) {
  1972. case 0:
  1973. case 1:
  1974. break;
  1975. case 2:
  1976. if (IS_IVYBRIDGE(dev))
  1977. break;
  1978. /* fall through otherwise */
  1979. default:
  1980. DRM_ERROR("no plane for crtc\n");
  1981. return -EINVAL;
  1982. }
  1983. mutex_lock(&dev->struct_mutex);
  1984. ret = intel_pin_and_fence_fb_obj(dev,
  1985. to_intel_framebuffer(crtc->fb)->obj,
  1986. NULL);
  1987. if (ret != 0) {
  1988. mutex_unlock(&dev->struct_mutex);
  1989. DRM_ERROR("pin & fence failed\n");
  1990. return ret;
  1991. }
  1992. if (old_fb) {
  1993. struct drm_i915_private *dev_priv = dev->dev_private;
  1994. struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
  1995. wait_event(dev_priv->pending_flip_queue,
  1996. atomic_read(&dev_priv->mm.wedged) ||
  1997. atomic_read(&obj->pending_flip) == 0);
  1998. /* Big Hammer, we also need to ensure that any pending
  1999. * MI_WAIT_FOR_EVENT inside a user batch buffer on the
  2000. * current scanout is retired before unpinning the old
  2001. * framebuffer.
  2002. *
  2003. * This should only fail upon a hung GPU, in which case we
  2004. * can safely continue.
  2005. */
  2006. ret = i915_gem_object_finish_gpu(obj);
  2007. (void) ret;
  2008. }
  2009. ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
  2010. LEAVE_ATOMIC_MODE_SET);
  2011. if (ret) {
  2012. intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
  2013. mutex_unlock(&dev->struct_mutex);
  2014. DRM_ERROR("failed to update base address\n");
  2015. return ret;
  2016. }
  2017. if (old_fb) {
  2018. intel_wait_for_vblank(dev, intel_crtc->pipe);
  2019. intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
  2020. }
  2021. mutex_unlock(&dev->struct_mutex);
  2022. if (!dev->primary->master)
  2023. return 0;
  2024. master_priv = dev->primary->master->driver_priv;
  2025. if (!master_priv->sarea_priv)
  2026. return 0;
  2027. if (intel_crtc->pipe) {
  2028. master_priv->sarea_priv->pipeB_x = x;
  2029. master_priv->sarea_priv->pipeB_y = y;
  2030. } else {
  2031. master_priv->sarea_priv->pipeA_x = x;
  2032. master_priv->sarea_priv->pipeA_y = y;
  2033. }
  2034. return 0;
  2035. }
  2036. static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
  2037. {
  2038. struct drm_device *dev = crtc->dev;
  2039. struct drm_i915_private *dev_priv = dev->dev_private;
  2040. u32 dpa_ctl;
  2041. DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
  2042. dpa_ctl = I915_READ(DP_A);
  2043. dpa_ctl &= ~DP_PLL_FREQ_MASK;
  2044. if (clock < 200000) {
  2045. u32 temp;
  2046. dpa_ctl |= DP_PLL_FREQ_160MHZ;
  2047. /* workaround for 160Mhz:
  2048. 1) program 0x4600c bits 15:0 = 0x8124
  2049. 2) program 0x46010 bit 0 = 1
  2050. 3) program 0x46034 bit 24 = 1
  2051. 4) program 0x64000 bit 14 = 1
  2052. */
  2053. temp = I915_READ(0x4600c);
  2054. temp &= 0xffff0000;
  2055. I915_WRITE(0x4600c, temp | 0x8124);
  2056. temp = I915_READ(0x46010);
  2057. I915_WRITE(0x46010, temp | 1);
  2058. temp = I915_READ(0x46034);
  2059. I915_WRITE(0x46034, temp | (1 << 24));
  2060. } else {
  2061. dpa_ctl |= DP_PLL_FREQ_270MHZ;
  2062. }
  2063. I915_WRITE(DP_A, dpa_ctl);
  2064. POSTING_READ(DP_A);
  2065. udelay(500);
  2066. }
  2067. static void intel_fdi_normal_train(struct drm_crtc *crtc)
  2068. {
  2069. struct drm_device *dev = crtc->dev;
  2070. struct drm_i915_private *dev_priv = dev->dev_private;
  2071. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2072. int pipe = intel_crtc->pipe;
  2073. u32 reg, temp;
  2074. /* enable normal train */
  2075. reg = FDI_TX_CTL(pipe);
  2076. temp = I915_READ(reg);
  2077. if (IS_IVYBRIDGE(dev)) {
  2078. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2079. temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
  2080. } else {
  2081. temp &= ~FDI_LINK_TRAIN_NONE;
  2082. temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
  2083. }
  2084. I915_WRITE(reg, temp);
  2085. reg = FDI_RX_CTL(pipe);
  2086. temp = I915_READ(reg);
  2087. if (HAS_PCH_CPT(dev)) {
  2088. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2089. temp |= FDI_LINK_TRAIN_NORMAL_CPT;
  2090. } else {
  2091. temp &= ~FDI_LINK_TRAIN_NONE;
  2092. temp |= FDI_LINK_TRAIN_NONE;
  2093. }
  2094. I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
  2095. /* wait one idle pattern time */
  2096. POSTING_READ(reg);
  2097. udelay(1000);
  2098. /* IVB wants error correction enabled */
  2099. if (IS_IVYBRIDGE(dev))
  2100. I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
  2101. FDI_FE_ERRC_ENABLE);
  2102. }
  2103. static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
  2104. {
  2105. struct drm_i915_private *dev_priv = dev->dev_private;
  2106. u32 flags = I915_READ(SOUTH_CHICKEN1);
  2107. flags |= FDI_PHASE_SYNC_OVR(pipe);
  2108. I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
  2109. flags |= FDI_PHASE_SYNC_EN(pipe);
  2110. I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
  2111. POSTING_READ(SOUTH_CHICKEN1);
  2112. }
  2113. /* The FDI link training functions for ILK/Ibexpeak. */
  2114. static void ironlake_fdi_link_train(struct drm_crtc *crtc)
  2115. {
  2116. struct drm_device *dev = crtc->dev;
  2117. struct drm_i915_private *dev_priv = dev->dev_private;
  2118. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2119. int pipe = intel_crtc->pipe;
  2120. int plane = intel_crtc->plane;
  2121. u32 reg, temp, tries;
  2122. /* FDI needs bits from pipe & plane first */
  2123. assert_pipe_enabled(dev_priv, pipe);
  2124. assert_plane_enabled(dev_priv, plane);
  2125. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2126. for train result */
  2127. reg = FDI_RX_IMR(pipe);
  2128. temp = I915_READ(reg);
  2129. temp &= ~FDI_RX_SYMBOL_LOCK;
  2130. temp &= ~FDI_RX_BIT_LOCK;
  2131. I915_WRITE(reg, temp);
  2132. I915_READ(reg);
  2133. udelay(150);
  2134. /* enable CPU FDI TX and PCH FDI RX */
  2135. reg = FDI_TX_CTL(pipe);
  2136. temp = I915_READ(reg);
  2137. temp &= ~(7 << 19);
  2138. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2139. temp &= ~FDI_LINK_TRAIN_NONE;
  2140. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2141. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2142. reg = FDI_RX_CTL(pipe);
  2143. temp = I915_READ(reg);
  2144. temp &= ~FDI_LINK_TRAIN_NONE;
  2145. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2146. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2147. POSTING_READ(reg);
  2148. udelay(150);
  2149. /* Ironlake workaround, enable clock pointer after FDI enable*/
  2150. if (HAS_PCH_IBX(dev)) {
  2151. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2152. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
  2153. FDI_RX_PHASE_SYNC_POINTER_EN);
  2154. }
  2155. reg = FDI_RX_IIR(pipe);
  2156. for (tries = 0; tries < 5; tries++) {
  2157. temp = I915_READ(reg);
  2158. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2159. if ((temp & FDI_RX_BIT_LOCK)) {
  2160. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2161. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2162. break;
  2163. }
  2164. }
  2165. if (tries == 5)
  2166. DRM_ERROR("FDI train 1 fail!\n");
  2167. /* Train 2 */
  2168. reg = FDI_TX_CTL(pipe);
  2169. temp = I915_READ(reg);
  2170. temp &= ~FDI_LINK_TRAIN_NONE;
  2171. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2172. I915_WRITE(reg, temp);
  2173. reg = FDI_RX_CTL(pipe);
  2174. temp = I915_READ(reg);
  2175. temp &= ~FDI_LINK_TRAIN_NONE;
  2176. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2177. I915_WRITE(reg, temp);
  2178. POSTING_READ(reg);
  2179. udelay(150);
  2180. reg = FDI_RX_IIR(pipe);
  2181. for (tries = 0; tries < 5; tries++) {
  2182. temp = I915_READ(reg);
  2183. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2184. if (temp & FDI_RX_SYMBOL_LOCK) {
  2185. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2186. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2187. break;
  2188. }
  2189. }
  2190. if (tries == 5)
  2191. DRM_ERROR("FDI train 2 fail!\n");
  2192. DRM_DEBUG_KMS("FDI train done\n");
  2193. }
  2194. static const int snb_b_fdi_train_param[] = {
  2195. FDI_LINK_TRAIN_400MV_0DB_SNB_B,
  2196. FDI_LINK_TRAIN_400MV_6DB_SNB_B,
  2197. FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
  2198. FDI_LINK_TRAIN_800MV_0DB_SNB_B,
  2199. };
  2200. /* The FDI link training functions for SNB/Cougarpoint. */
  2201. static void gen6_fdi_link_train(struct drm_crtc *crtc)
  2202. {
  2203. struct drm_device *dev = crtc->dev;
  2204. struct drm_i915_private *dev_priv = dev->dev_private;
  2205. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2206. int pipe = intel_crtc->pipe;
  2207. u32 reg, temp, i;
  2208. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2209. for train result */
  2210. reg = FDI_RX_IMR(pipe);
  2211. temp = I915_READ(reg);
  2212. temp &= ~FDI_RX_SYMBOL_LOCK;
  2213. temp &= ~FDI_RX_BIT_LOCK;
  2214. I915_WRITE(reg, temp);
  2215. POSTING_READ(reg);
  2216. udelay(150);
  2217. /* enable CPU FDI TX and PCH FDI RX */
  2218. reg = FDI_TX_CTL(pipe);
  2219. temp = I915_READ(reg);
  2220. temp &= ~(7 << 19);
  2221. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2222. temp &= ~FDI_LINK_TRAIN_NONE;
  2223. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2224. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2225. /* SNB-B */
  2226. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2227. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2228. reg = FDI_RX_CTL(pipe);
  2229. temp = I915_READ(reg);
  2230. if (HAS_PCH_CPT(dev)) {
  2231. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2232. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2233. } else {
  2234. temp &= ~FDI_LINK_TRAIN_NONE;
  2235. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2236. }
  2237. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2238. POSTING_READ(reg);
  2239. udelay(150);
  2240. if (HAS_PCH_CPT(dev))
  2241. cpt_phase_pointer_enable(dev, pipe);
  2242. for (i = 0; i < 4; i++) {
  2243. reg = FDI_TX_CTL(pipe);
  2244. temp = I915_READ(reg);
  2245. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2246. temp |= snb_b_fdi_train_param[i];
  2247. I915_WRITE(reg, temp);
  2248. POSTING_READ(reg);
  2249. udelay(500);
  2250. reg = FDI_RX_IIR(pipe);
  2251. temp = I915_READ(reg);
  2252. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2253. if (temp & FDI_RX_BIT_LOCK) {
  2254. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2255. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2256. break;
  2257. }
  2258. }
  2259. if (i == 4)
  2260. DRM_ERROR("FDI train 1 fail!\n");
  2261. /* Train 2 */
  2262. reg = FDI_TX_CTL(pipe);
  2263. temp = I915_READ(reg);
  2264. temp &= ~FDI_LINK_TRAIN_NONE;
  2265. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2266. if (IS_GEN6(dev)) {
  2267. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2268. /* SNB-B */
  2269. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2270. }
  2271. I915_WRITE(reg, temp);
  2272. reg = FDI_RX_CTL(pipe);
  2273. temp = I915_READ(reg);
  2274. if (HAS_PCH_CPT(dev)) {
  2275. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2276. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2277. } else {
  2278. temp &= ~FDI_LINK_TRAIN_NONE;
  2279. temp |= FDI_LINK_TRAIN_PATTERN_2;
  2280. }
  2281. I915_WRITE(reg, temp);
  2282. POSTING_READ(reg);
  2283. udelay(150);
  2284. for (i = 0; i < 4; i++) {
  2285. reg = FDI_TX_CTL(pipe);
  2286. temp = I915_READ(reg);
  2287. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2288. temp |= snb_b_fdi_train_param[i];
  2289. I915_WRITE(reg, temp);
  2290. POSTING_READ(reg);
  2291. udelay(500);
  2292. reg = FDI_RX_IIR(pipe);
  2293. temp = I915_READ(reg);
  2294. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2295. if (temp & FDI_RX_SYMBOL_LOCK) {
  2296. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2297. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2298. break;
  2299. }
  2300. }
  2301. if (i == 4)
  2302. DRM_ERROR("FDI train 2 fail!\n");
  2303. DRM_DEBUG_KMS("FDI train done.\n");
  2304. }
  2305. /* Manual link training for Ivy Bridge A0 parts */
  2306. static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
  2307. {
  2308. struct drm_device *dev = crtc->dev;
  2309. struct drm_i915_private *dev_priv = dev->dev_private;
  2310. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2311. int pipe = intel_crtc->pipe;
  2312. u32 reg, temp, i;
  2313. /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
  2314. for train result */
  2315. reg = FDI_RX_IMR(pipe);
  2316. temp = I915_READ(reg);
  2317. temp &= ~FDI_RX_SYMBOL_LOCK;
  2318. temp &= ~FDI_RX_BIT_LOCK;
  2319. I915_WRITE(reg, temp);
  2320. POSTING_READ(reg);
  2321. udelay(150);
  2322. /* enable CPU FDI TX and PCH FDI RX */
  2323. reg = FDI_TX_CTL(pipe);
  2324. temp = I915_READ(reg);
  2325. temp &= ~(7 << 19);
  2326. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2327. temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
  2328. temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
  2329. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2330. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2331. temp |= FDI_COMPOSITE_SYNC;
  2332. I915_WRITE(reg, temp | FDI_TX_ENABLE);
  2333. reg = FDI_RX_CTL(pipe);
  2334. temp = I915_READ(reg);
  2335. temp &= ~FDI_LINK_TRAIN_AUTO;
  2336. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2337. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2338. temp |= FDI_COMPOSITE_SYNC;
  2339. I915_WRITE(reg, temp | FDI_RX_ENABLE);
  2340. POSTING_READ(reg);
  2341. udelay(150);
  2342. if (HAS_PCH_CPT(dev))
  2343. cpt_phase_pointer_enable(dev, pipe);
  2344. for (i = 0; i < 4; i++) {
  2345. reg = FDI_TX_CTL(pipe);
  2346. temp = I915_READ(reg);
  2347. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2348. temp |= snb_b_fdi_train_param[i];
  2349. I915_WRITE(reg, temp);
  2350. POSTING_READ(reg);
  2351. udelay(500);
  2352. reg = FDI_RX_IIR(pipe);
  2353. temp = I915_READ(reg);
  2354. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2355. if (temp & FDI_RX_BIT_LOCK ||
  2356. (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
  2357. I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
  2358. DRM_DEBUG_KMS("FDI train 1 done.\n");
  2359. break;
  2360. }
  2361. }
  2362. if (i == 4)
  2363. DRM_ERROR("FDI train 1 fail!\n");
  2364. /* Train 2 */
  2365. reg = FDI_TX_CTL(pipe);
  2366. temp = I915_READ(reg);
  2367. temp &= ~FDI_LINK_TRAIN_NONE_IVB;
  2368. temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
  2369. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2370. temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
  2371. I915_WRITE(reg, temp);
  2372. reg = FDI_RX_CTL(pipe);
  2373. temp = I915_READ(reg);
  2374. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2375. temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
  2376. I915_WRITE(reg, temp);
  2377. POSTING_READ(reg);
  2378. udelay(150);
  2379. for (i = 0; i < 4; i++) {
  2380. reg = FDI_TX_CTL(pipe);
  2381. temp = I915_READ(reg);
  2382. temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
  2383. temp |= snb_b_fdi_train_param[i];
  2384. I915_WRITE(reg, temp);
  2385. POSTING_READ(reg);
  2386. udelay(500);
  2387. reg = FDI_RX_IIR(pipe);
  2388. temp = I915_READ(reg);
  2389. DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
  2390. if (temp & FDI_RX_SYMBOL_LOCK) {
  2391. I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
  2392. DRM_DEBUG_KMS("FDI train 2 done.\n");
  2393. break;
  2394. }
  2395. }
  2396. if (i == 4)
  2397. DRM_ERROR("FDI train 2 fail!\n");
  2398. DRM_DEBUG_KMS("FDI train done.\n");
  2399. }
  2400. static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
  2401. {
  2402. struct drm_device *dev = crtc->dev;
  2403. struct drm_i915_private *dev_priv = dev->dev_private;
  2404. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2405. int pipe = intel_crtc->pipe;
  2406. u32 reg, temp;
  2407. /* Write the TU size bits so error detection works */
  2408. I915_WRITE(FDI_RX_TUSIZE1(pipe),
  2409. I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
  2410. /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
  2411. reg = FDI_RX_CTL(pipe);
  2412. temp = I915_READ(reg);
  2413. temp &= ~((0x7 << 19) | (0x7 << 16));
  2414. temp |= (intel_crtc->fdi_lanes - 1) << 19;
  2415. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2416. I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
  2417. POSTING_READ(reg);
  2418. udelay(200);
  2419. /* Switch from Rawclk to PCDclk */
  2420. temp = I915_READ(reg);
  2421. I915_WRITE(reg, temp | FDI_PCDCLK);
  2422. POSTING_READ(reg);
  2423. udelay(200);
  2424. /* Enable CPU FDI TX PLL, always on for Ironlake */
  2425. reg = FDI_TX_CTL(pipe);
  2426. temp = I915_READ(reg);
  2427. if ((temp & FDI_TX_PLL_ENABLE) == 0) {
  2428. I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
  2429. POSTING_READ(reg);
  2430. udelay(100);
  2431. }
  2432. }
  2433. static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
  2434. {
  2435. struct drm_i915_private *dev_priv = dev->dev_private;
  2436. u32 flags = I915_READ(SOUTH_CHICKEN1);
  2437. flags &= ~(FDI_PHASE_SYNC_EN(pipe));
  2438. I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
  2439. flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
  2440. I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
  2441. POSTING_READ(SOUTH_CHICKEN1);
  2442. }
  2443. static void ironlake_fdi_disable(struct drm_crtc *crtc)
  2444. {
  2445. struct drm_device *dev = crtc->dev;
  2446. struct drm_i915_private *dev_priv = dev->dev_private;
  2447. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2448. int pipe = intel_crtc->pipe;
  2449. u32 reg, temp;
  2450. /* disable CPU FDI tx and PCH FDI rx */
  2451. reg = FDI_TX_CTL(pipe);
  2452. temp = I915_READ(reg);
  2453. I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
  2454. POSTING_READ(reg);
  2455. reg = FDI_RX_CTL(pipe);
  2456. temp = I915_READ(reg);
  2457. temp &= ~(0x7 << 16);
  2458. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2459. I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
  2460. POSTING_READ(reg);
  2461. udelay(100);
  2462. /* Ironlake workaround, disable clock pointer after downing FDI */
  2463. if (HAS_PCH_IBX(dev)) {
  2464. I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
  2465. I915_WRITE(FDI_RX_CHICKEN(pipe),
  2466. I915_READ(FDI_RX_CHICKEN(pipe) &
  2467. ~FDI_RX_PHASE_SYNC_POINTER_EN));
  2468. } else if (HAS_PCH_CPT(dev)) {
  2469. cpt_phase_pointer_disable(dev, pipe);
  2470. }
  2471. /* still set train pattern 1 */
  2472. reg = FDI_TX_CTL(pipe);
  2473. temp = I915_READ(reg);
  2474. temp &= ~FDI_LINK_TRAIN_NONE;
  2475. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2476. I915_WRITE(reg, temp);
  2477. reg = FDI_RX_CTL(pipe);
  2478. temp = I915_READ(reg);
  2479. if (HAS_PCH_CPT(dev)) {
  2480. temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
  2481. temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
  2482. } else {
  2483. temp &= ~FDI_LINK_TRAIN_NONE;
  2484. temp |= FDI_LINK_TRAIN_PATTERN_1;
  2485. }
  2486. /* BPC in FDI rx is consistent with that in PIPECONF */
  2487. temp &= ~(0x07 << 16);
  2488. temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
  2489. I915_WRITE(reg, temp);
  2490. POSTING_READ(reg);
  2491. udelay(100);
  2492. }
  2493. /*
  2494. * When we disable a pipe, we need to clear any pending scanline wait events
  2495. * to avoid hanging the ring, which we assume we are waiting on.
  2496. */
  2497. static void intel_clear_scanline_wait(struct drm_device *dev)
  2498. {
  2499. struct drm_i915_private *dev_priv = dev->dev_private;
  2500. struct intel_ring_buffer *ring;
  2501. u32 tmp;
  2502. if (IS_GEN2(dev))
  2503. /* Can't break the hang on i8xx */
  2504. return;
  2505. ring = LP_RING(dev_priv);
  2506. tmp = I915_READ_CTL(ring);
  2507. if (tmp & RING_WAIT)
  2508. I915_WRITE_CTL(ring, tmp);
  2509. }
  2510. static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
  2511. {
  2512. struct drm_i915_gem_object *obj;
  2513. struct drm_i915_private *dev_priv;
  2514. if (crtc->fb == NULL)
  2515. return;
  2516. obj = to_intel_framebuffer(crtc->fb)->obj;
  2517. dev_priv = crtc->dev->dev_private;
  2518. wait_event(dev_priv->pending_flip_queue,
  2519. atomic_read(&obj->pending_flip) == 0);
  2520. }
  2521. static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
  2522. {
  2523. struct drm_device *dev = crtc->dev;
  2524. struct drm_mode_config *mode_config = &dev->mode_config;
  2525. struct intel_encoder *encoder;
  2526. /*
  2527. * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
  2528. * must be driven by its own crtc; no sharing is possible.
  2529. */
  2530. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  2531. if (encoder->base.crtc != crtc)
  2532. continue;
  2533. switch (encoder->type) {
  2534. case INTEL_OUTPUT_EDP:
  2535. if (!intel_encoder_is_pch_edp(&encoder->base))
  2536. return false;
  2537. continue;
  2538. }
  2539. }
  2540. return true;
  2541. }
  2542. /*
  2543. * Enable PCH resources required for PCH ports:
  2544. * - PCH PLLs
  2545. * - FDI training & RX/TX
  2546. * - update transcoder timings
  2547. * - DP transcoding bits
  2548. * - transcoder
  2549. */
  2550. static void ironlake_pch_enable(struct drm_crtc *crtc)
  2551. {
  2552. struct drm_device *dev = crtc->dev;
  2553. struct drm_i915_private *dev_priv = dev->dev_private;
  2554. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2555. int pipe = intel_crtc->pipe;
  2556. u32 reg, temp, transc_sel;
  2557. /* For PCH output, training FDI link */
  2558. dev_priv->display.fdi_link_train(crtc);
  2559. intel_enable_pch_pll(dev_priv, pipe);
  2560. if (HAS_PCH_CPT(dev)) {
  2561. transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
  2562. TRANSC_DPLLB_SEL;
  2563. /* Be sure PCH DPLL SEL is set */
  2564. temp = I915_READ(PCH_DPLL_SEL);
  2565. if (pipe == 0) {
  2566. temp &= ~(TRANSA_DPLLB_SEL);
  2567. temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
  2568. } else if (pipe == 1) {
  2569. temp &= ~(TRANSB_DPLLB_SEL);
  2570. temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  2571. } else if (pipe == 2) {
  2572. temp &= ~(TRANSC_DPLLB_SEL);
  2573. temp |= (TRANSC_DPLL_ENABLE | transc_sel);
  2574. }
  2575. I915_WRITE(PCH_DPLL_SEL, temp);
  2576. }
  2577. /* set transcoder timing, panel must allow it */
  2578. assert_panel_unlocked(dev_priv, pipe);
  2579. I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
  2580. I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
  2581. I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
  2582. I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
  2583. I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
  2584. I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
  2585. I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
  2586. intel_fdi_normal_train(crtc);
  2587. /* For PCH DP, enable TRANS_DP_CTL */
  2588. if (HAS_PCH_CPT(dev) &&
  2589. (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
  2590. intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
  2591. u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
  2592. reg = TRANS_DP_CTL(pipe);
  2593. temp = I915_READ(reg);
  2594. temp &= ~(TRANS_DP_PORT_SEL_MASK |
  2595. TRANS_DP_SYNC_MASK |
  2596. TRANS_DP_BPC_MASK);
  2597. temp |= (TRANS_DP_OUTPUT_ENABLE |
  2598. TRANS_DP_ENH_FRAMING);
  2599. temp |= bpc << 9; /* same format but at 11:9 */
  2600. if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
  2601. temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
  2602. if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
  2603. temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
  2604. switch (intel_trans_dp_port_sel(crtc)) {
  2605. case PCH_DP_B:
  2606. temp |= TRANS_DP_PORT_SEL_B;
  2607. break;
  2608. case PCH_DP_C:
  2609. temp |= TRANS_DP_PORT_SEL_C;
  2610. break;
  2611. case PCH_DP_D:
  2612. temp |= TRANS_DP_PORT_SEL_D;
  2613. break;
  2614. default:
  2615. DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
  2616. temp |= TRANS_DP_PORT_SEL_B;
  2617. break;
  2618. }
  2619. I915_WRITE(reg, temp);
  2620. }
  2621. intel_enable_transcoder(dev_priv, pipe);
  2622. }
  2623. void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
  2624. {
  2625. struct drm_i915_private *dev_priv = dev->dev_private;
  2626. int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
  2627. u32 temp;
  2628. temp = I915_READ(dslreg);
  2629. udelay(500);
  2630. if (wait_for(I915_READ(dslreg) != temp, 5)) {
  2631. /* Without this, mode sets may fail silently on FDI */
  2632. I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
  2633. udelay(250);
  2634. I915_WRITE(tc2reg, 0);
  2635. if (wait_for(I915_READ(dslreg) != temp, 5))
  2636. DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
  2637. }
  2638. }
  2639. static void ironlake_crtc_enable(struct drm_crtc *crtc)
  2640. {
  2641. struct drm_device *dev = crtc->dev;
  2642. struct drm_i915_private *dev_priv = dev->dev_private;
  2643. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2644. int pipe = intel_crtc->pipe;
  2645. int plane = intel_crtc->plane;
  2646. u32 temp;
  2647. bool is_pch_port;
  2648. if (intel_crtc->active)
  2649. return;
  2650. intel_crtc->active = true;
  2651. intel_update_watermarks(dev);
  2652. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
  2653. temp = I915_READ(PCH_LVDS);
  2654. if ((temp & LVDS_PORT_EN) == 0)
  2655. I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
  2656. }
  2657. is_pch_port = intel_crtc_driving_pch(crtc);
  2658. if (is_pch_port)
  2659. ironlake_fdi_pll_enable(crtc);
  2660. else
  2661. ironlake_fdi_disable(crtc);
  2662. /* Enable panel fitting for LVDS */
  2663. if (dev_priv->pch_pf_size &&
  2664. (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
  2665. /* Force use of hard-coded filter coefficients
  2666. * as some pre-programmed values are broken,
  2667. * e.g. x201.
  2668. */
  2669. I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
  2670. I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
  2671. I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
  2672. }
  2673. /*
  2674. * On ILK+ LUT must be loaded before the pipe is running but with
  2675. * clocks enabled
  2676. */
  2677. intel_crtc_load_lut(crtc);
  2678. intel_enable_pipe(dev_priv, pipe, is_pch_port);
  2679. intel_enable_plane(dev_priv, plane, pipe);
  2680. if (is_pch_port)
  2681. ironlake_pch_enable(crtc);
  2682. mutex_lock(&dev->struct_mutex);
  2683. intel_update_fbc(dev);
  2684. mutex_unlock(&dev->struct_mutex);
  2685. intel_crtc_update_cursor(crtc, true);
  2686. }
  2687. static void ironlake_crtc_disable(struct drm_crtc *crtc)
  2688. {
  2689. struct drm_device *dev = crtc->dev;
  2690. struct drm_i915_private *dev_priv = dev->dev_private;
  2691. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2692. int pipe = intel_crtc->pipe;
  2693. int plane = intel_crtc->plane;
  2694. u32 reg, temp;
  2695. if (!intel_crtc->active)
  2696. return;
  2697. intel_crtc_wait_for_pending_flips(crtc);
  2698. drm_vblank_off(dev, pipe);
  2699. intel_crtc_update_cursor(crtc, false);
  2700. intel_disable_plane(dev_priv, plane, pipe);
  2701. if (dev_priv->cfb_plane == plane)
  2702. intel_disable_fbc(dev);
  2703. intel_disable_pipe(dev_priv, pipe);
  2704. /* Disable PF */
  2705. I915_WRITE(PF_CTL(pipe), 0);
  2706. I915_WRITE(PF_WIN_SZ(pipe), 0);
  2707. ironlake_fdi_disable(crtc);
  2708. /* This is a horrible layering violation; we should be doing this in
  2709. * the connector/encoder ->prepare instead, but we don't always have
  2710. * enough information there about the config to know whether it will
  2711. * actually be necessary or just cause undesired flicker.
  2712. */
  2713. intel_disable_pch_ports(dev_priv, pipe);
  2714. intel_disable_transcoder(dev_priv, pipe);
  2715. if (HAS_PCH_CPT(dev)) {
  2716. /* disable TRANS_DP_CTL */
  2717. reg = TRANS_DP_CTL(pipe);
  2718. temp = I915_READ(reg);
  2719. temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
  2720. temp |= TRANS_DP_PORT_SEL_NONE;
  2721. I915_WRITE(reg, temp);
  2722. /* disable DPLL_SEL */
  2723. temp = I915_READ(PCH_DPLL_SEL);
  2724. switch (pipe) {
  2725. case 0:
  2726. temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
  2727. break;
  2728. case 1:
  2729. temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
  2730. break;
  2731. case 2:
  2732. /* C shares PLL A or B */
  2733. temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
  2734. break;
  2735. default:
  2736. BUG(); /* wtf */
  2737. }
  2738. I915_WRITE(PCH_DPLL_SEL, temp);
  2739. }
  2740. /* disable PCH DPLL */
  2741. if (!intel_crtc->no_pll)
  2742. intel_disable_pch_pll(dev_priv, pipe);
  2743. /* Switch from PCDclk to Rawclk */
  2744. reg = FDI_RX_CTL(pipe);
  2745. temp = I915_READ(reg);
  2746. I915_WRITE(reg, temp & ~FDI_PCDCLK);
  2747. /* Disable CPU FDI TX PLL */
  2748. reg = FDI_TX_CTL(pipe);
  2749. temp = I915_READ(reg);
  2750. I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
  2751. POSTING_READ(reg);
  2752. udelay(100);
  2753. reg = FDI_RX_CTL(pipe);
  2754. temp = I915_READ(reg);
  2755. I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
  2756. /* Wait for the clocks to turn off. */
  2757. POSTING_READ(reg);
  2758. udelay(100);
  2759. intel_crtc->active = false;
  2760. intel_update_watermarks(dev);
  2761. mutex_lock(&dev->struct_mutex);
  2762. intel_update_fbc(dev);
  2763. intel_clear_scanline_wait(dev);
  2764. mutex_unlock(&dev->struct_mutex);
  2765. }
  2766. static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
  2767. {
  2768. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2769. int pipe = intel_crtc->pipe;
  2770. int plane = intel_crtc->plane;
  2771. /* XXX: When our outputs are all unaware of DPMS modes other than off
  2772. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  2773. */
  2774. switch (mode) {
  2775. case DRM_MODE_DPMS_ON:
  2776. case DRM_MODE_DPMS_STANDBY:
  2777. case DRM_MODE_DPMS_SUSPEND:
  2778. DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
  2779. ironlake_crtc_enable(crtc);
  2780. break;
  2781. case DRM_MODE_DPMS_OFF:
  2782. DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
  2783. ironlake_crtc_disable(crtc);
  2784. break;
  2785. }
  2786. }
  2787. static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
  2788. {
  2789. if (!enable && intel_crtc->overlay) {
  2790. struct drm_device *dev = intel_crtc->base.dev;
  2791. struct drm_i915_private *dev_priv = dev->dev_private;
  2792. mutex_lock(&dev->struct_mutex);
  2793. dev_priv->mm.interruptible = false;
  2794. (void) intel_overlay_switch_off(intel_crtc->overlay);
  2795. dev_priv->mm.interruptible = true;
  2796. mutex_unlock(&dev->struct_mutex);
  2797. }
  2798. /* Let userspace switch the overlay on again. In most cases userspace
  2799. * has to recompute where to put it anyway.
  2800. */
  2801. }
  2802. static void i9xx_crtc_enable(struct drm_crtc *crtc)
  2803. {
  2804. struct drm_device *dev = crtc->dev;
  2805. struct drm_i915_private *dev_priv = dev->dev_private;
  2806. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2807. int pipe = intel_crtc->pipe;
  2808. int plane = intel_crtc->plane;
  2809. if (intel_crtc->active)
  2810. return;
  2811. intel_crtc->active = true;
  2812. intel_update_watermarks(dev);
  2813. intel_enable_pll(dev_priv, pipe);
  2814. intel_enable_pipe(dev_priv, pipe, false);
  2815. intel_enable_plane(dev_priv, plane, pipe);
  2816. intel_crtc_load_lut(crtc);
  2817. intel_update_fbc(dev);
  2818. /* Give the overlay scaler a chance to enable if it's on this pipe */
  2819. intel_crtc_dpms_overlay(intel_crtc, true);
  2820. intel_crtc_update_cursor(crtc, true);
  2821. }
  2822. static void i9xx_crtc_disable(struct drm_crtc *crtc)
  2823. {
  2824. struct drm_device *dev = crtc->dev;
  2825. struct drm_i915_private *dev_priv = dev->dev_private;
  2826. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2827. int pipe = intel_crtc->pipe;
  2828. int plane = intel_crtc->plane;
  2829. if (!intel_crtc->active)
  2830. return;
  2831. /* Give the overlay scaler a chance to disable if it's on this pipe */
  2832. intel_crtc_wait_for_pending_flips(crtc);
  2833. drm_vblank_off(dev, pipe);
  2834. intel_crtc_dpms_overlay(intel_crtc, false);
  2835. intel_crtc_update_cursor(crtc, false);
  2836. if (dev_priv->cfb_plane == plane)
  2837. intel_disable_fbc(dev);
  2838. intel_disable_plane(dev_priv, plane, pipe);
  2839. intel_disable_pipe(dev_priv, pipe);
  2840. intel_disable_pll(dev_priv, pipe);
  2841. intel_crtc->active = false;
  2842. intel_update_fbc(dev);
  2843. intel_update_watermarks(dev);
  2844. intel_clear_scanline_wait(dev);
  2845. }
  2846. static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
  2847. {
  2848. /* XXX: When our outputs are all unaware of DPMS modes other than off
  2849. * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
  2850. */
  2851. switch (mode) {
  2852. case DRM_MODE_DPMS_ON:
  2853. case DRM_MODE_DPMS_STANDBY:
  2854. case DRM_MODE_DPMS_SUSPEND:
  2855. i9xx_crtc_enable(crtc);
  2856. break;
  2857. case DRM_MODE_DPMS_OFF:
  2858. i9xx_crtc_disable(crtc);
  2859. break;
  2860. }
  2861. }
  2862. /**
  2863. * Sets the power management mode of the pipe and plane.
  2864. */
  2865. static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
  2866. {
  2867. struct drm_device *dev = crtc->dev;
  2868. struct drm_i915_private *dev_priv = dev->dev_private;
  2869. struct drm_i915_master_private *master_priv;
  2870. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  2871. int pipe = intel_crtc->pipe;
  2872. bool enabled;
  2873. if (intel_crtc->dpms_mode == mode)
  2874. return;
  2875. intel_crtc->dpms_mode = mode;
  2876. dev_priv->display.dpms(crtc, mode);
  2877. if (!dev->primary->master)
  2878. return;
  2879. master_priv = dev->primary->master->driver_priv;
  2880. if (!master_priv->sarea_priv)
  2881. return;
  2882. enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
  2883. switch (pipe) {
  2884. case 0:
  2885. master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
  2886. master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
  2887. break;
  2888. case 1:
  2889. master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
  2890. master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
  2891. break;
  2892. default:
  2893. DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
  2894. break;
  2895. }
  2896. }
  2897. static void intel_crtc_disable(struct drm_crtc *crtc)
  2898. {
  2899. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  2900. struct drm_device *dev = crtc->dev;
  2901. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
  2902. assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
  2903. assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
  2904. if (crtc->fb) {
  2905. mutex_lock(&dev->struct_mutex);
  2906. intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
  2907. mutex_unlock(&dev->struct_mutex);
  2908. }
  2909. }
  2910. /* Prepare for a mode set.
  2911. *
  2912. * Note we could be a lot smarter here. We need to figure out which outputs
  2913. * will be enabled, which disabled (in short, how the config will changes)
  2914. * and perform the minimum necessary steps to accomplish that, e.g. updating
  2915. * watermarks, FBC configuration, making sure PLLs are programmed correctly,
  2916. * panel fitting is in the proper state, etc.
  2917. */
  2918. static void i9xx_crtc_prepare(struct drm_crtc *crtc)
  2919. {
  2920. i9xx_crtc_disable(crtc);
  2921. }
  2922. static void i9xx_crtc_commit(struct drm_crtc *crtc)
  2923. {
  2924. i9xx_crtc_enable(crtc);
  2925. }
  2926. static void ironlake_crtc_prepare(struct drm_crtc *crtc)
  2927. {
  2928. ironlake_crtc_disable(crtc);
  2929. }
  2930. static void ironlake_crtc_commit(struct drm_crtc *crtc)
  2931. {
  2932. ironlake_crtc_enable(crtc);
  2933. }
  2934. void intel_encoder_prepare(struct drm_encoder *encoder)
  2935. {
  2936. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2937. /* lvds has its own version of prepare see intel_lvds_prepare */
  2938. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  2939. }
  2940. void intel_encoder_commit(struct drm_encoder *encoder)
  2941. {
  2942. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  2943. struct drm_device *dev = encoder->dev;
  2944. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  2945. struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
  2946. /* lvds has its own version of commit see intel_lvds_commit */
  2947. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  2948. if (HAS_PCH_CPT(dev))
  2949. intel_cpt_verify_modeset(dev, intel_crtc->pipe);
  2950. }
  2951. void intel_encoder_destroy(struct drm_encoder *encoder)
  2952. {
  2953. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  2954. drm_encoder_cleanup(encoder);
  2955. kfree(intel_encoder);
  2956. }
  2957. static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
  2958. struct drm_display_mode *mode,
  2959. struct drm_display_mode *adjusted_mode)
  2960. {
  2961. struct drm_device *dev = crtc->dev;
  2962. if (HAS_PCH_SPLIT(dev)) {
  2963. /* FDI link clock is fixed at 2.7G */
  2964. if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
  2965. return false;
  2966. }
  2967. /* All interlaced capable intel hw wants timings in frames. */
  2968. drm_mode_set_crtcinfo(adjusted_mode, 0);
  2969. return true;
  2970. }
  2971. static int i945_get_display_clock_speed(struct drm_device *dev)
  2972. {
  2973. return 400000;
  2974. }
  2975. static int i915_get_display_clock_speed(struct drm_device *dev)
  2976. {
  2977. return 333000;
  2978. }
  2979. static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
  2980. {
  2981. return 200000;
  2982. }
  2983. static int i915gm_get_display_clock_speed(struct drm_device *dev)
  2984. {
  2985. u16 gcfgc = 0;
  2986. pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
  2987. if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
  2988. return 133000;
  2989. else {
  2990. switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
  2991. case GC_DISPLAY_CLOCK_333_MHZ:
  2992. return 333000;
  2993. default:
  2994. case GC_DISPLAY_CLOCK_190_200_MHZ:
  2995. return 190000;
  2996. }
  2997. }
  2998. }
  2999. static int i865_get_display_clock_speed(struct drm_device *dev)
  3000. {
  3001. return 266000;
  3002. }
  3003. static int i855_get_display_clock_speed(struct drm_device *dev)
  3004. {
  3005. u16 hpllcc = 0;
  3006. /* Assume that the hardware is in the high speed state. This
  3007. * should be the default.
  3008. */
  3009. switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
  3010. case GC_CLOCK_133_200:
  3011. case GC_CLOCK_100_200:
  3012. return 200000;
  3013. case GC_CLOCK_166_250:
  3014. return 250000;
  3015. case GC_CLOCK_100_133:
  3016. return 133000;
  3017. }
  3018. /* Shouldn't happen */
  3019. return 0;
  3020. }
  3021. static int i830_get_display_clock_speed(struct drm_device *dev)
  3022. {
  3023. return 133000;
  3024. }
  3025. struct fdi_m_n {
  3026. u32 tu;
  3027. u32 gmch_m;
  3028. u32 gmch_n;
  3029. u32 link_m;
  3030. u32 link_n;
  3031. };
  3032. static void
  3033. fdi_reduce_ratio(u32 *num, u32 *den)
  3034. {
  3035. while (*num > 0xffffff || *den > 0xffffff) {
  3036. *num >>= 1;
  3037. *den >>= 1;
  3038. }
  3039. }
  3040. static void
  3041. ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
  3042. int link_clock, struct fdi_m_n *m_n)
  3043. {
  3044. m_n->tu = 64; /* default size */
  3045. /* BUG_ON(pixel_clock > INT_MAX / 36); */
  3046. m_n->gmch_m = bits_per_pixel * pixel_clock;
  3047. m_n->gmch_n = link_clock * nlanes * 8;
  3048. fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
  3049. m_n->link_m = pixel_clock;
  3050. m_n->link_n = link_clock;
  3051. fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
  3052. }
  3053. struct intel_watermark_params {
  3054. unsigned long fifo_size;
  3055. unsigned long max_wm;
  3056. unsigned long default_wm;
  3057. unsigned long guard_size;
  3058. unsigned long cacheline_size;
  3059. };
  3060. /* Pineview has different values for various configs */
  3061. static const struct intel_watermark_params pineview_display_wm = {
  3062. PINEVIEW_DISPLAY_FIFO,
  3063. PINEVIEW_MAX_WM,
  3064. PINEVIEW_DFT_WM,
  3065. PINEVIEW_GUARD_WM,
  3066. PINEVIEW_FIFO_LINE_SIZE
  3067. };
  3068. static const struct intel_watermark_params pineview_display_hplloff_wm = {
  3069. PINEVIEW_DISPLAY_FIFO,
  3070. PINEVIEW_MAX_WM,
  3071. PINEVIEW_DFT_HPLLOFF_WM,
  3072. PINEVIEW_GUARD_WM,
  3073. PINEVIEW_FIFO_LINE_SIZE
  3074. };
  3075. static const struct intel_watermark_params pineview_cursor_wm = {
  3076. PINEVIEW_CURSOR_FIFO,
  3077. PINEVIEW_CURSOR_MAX_WM,
  3078. PINEVIEW_CURSOR_DFT_WM,
  3079. PINEVIEW_CURSOR_GUARD_WM,
  3080. PINEVIEW_FIFO_LINE_SIZE,
  3081. };
  3082. static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
  3083. PINEVIEW_CURSOR_FIFO,
  3084. PINEVIEW_CURSOR_MAX_WM,
  3085. PINEVIEW_CURSOR_DFT_WM,
  3086. PINEVIEW_CURSOR_GUARD_WM,
  3087. PINEVIEW_FIFO_LINE_SIZE
  3088. };
  3089. static const struct intel_watermark_params g4x_wm_info = {
  3090. G4X_FIFO_SIZE,
  3091. G4X_MAX_WM,
  3092. G4X_MAX_WM,
  3093. 2,
  3094. G4X_FIFO_LINE_SIZE,
  3095. };
  3096. static const struct intel_watermark_params g4x_cursor_wm_info = {
  3097. I965_CURSOR_FIFO,
  3098. I965_CURSOR_MAX_WM,
  3099. I965_CURSOR_DFT_WM,
  3100. 2,
  3101. G4X_FIFO_LINE_SIZE,
  3102. };
  3103. static const struct intel_watermark_params i965_cursor_wm_info = {
  3104. I965_CURSOR_FIFO,
  3105. I965_CURSOR_MAX_WM,
  3106. I965_CURSOR_DFT_WM,
  3107. 2,
  3108. I915_FIFO_LINE_SIZE,
  3109. };
  3110. static const struct intel_watermark_params i945_wm_info = {
  3111. I945_FIFO_SIZE,
  3112. I915_MAX_WM,
  3113. 1,
  3114. 2,
  3115. I915_FIFO_LINE_SIZE
  3116. };
  3117. static const struct intel_watermark_params i915_wm_info = {
  3118. I915_FIFO_SIZE,
  3119. I915_MAX_WM,
  3120. 1,
  3121. 2,
  3122. I915_FIFO_LINE_SIZE
  3123. };
  3124. static const struct intel_watermark_params i855_wm_info = {
  3125. I855GM_FIFO_SIZE,
  3126. I915_MAX_WM,
  3127. 1,
  3128. 2,
  3129. I830_FIFO_LINE_SIZE
  3130. };
  3131. static const struct intel_watermark_params i830_wm_info = {
  3132. I830_FIFO_SIZE,
  3133. I915_MAX_WM,
  3134. 1,
  3135. 2,
  3136. I830_FIFO_LINE_SIZE
  3137. };
  3138. static const struct intel_watermark_params ironlake_display_wm_info = {
  3139. ILK_DISPLAY_FIFO,
  3140. ILK_DISPLAY_MAXWM,
  3141. ILK_DISPLAY_DFTWM,
  3142. 2,
  3143. ILK_FIFO_LINE_SIZE
  3144. };
  3145. static const struct intel_watermark_params ironlake_cursor_wm_info = {
  3146. ILK_CURSOR_FIFO,
  3147. ILK_CURSOR_MAXWM,
  3148. ILK_CURSOR_DFTWM,
  3149. 2,
  3150. ILK_FIFO_LINE_SIZE
  3151. };
  3152. static const struct intel_watermark_params ironlake_display_srwm_info = {
  3153. ILK_DISPLAY_SR_FIFO,
  3154. ILK_DISPLAY_MAX_SRWM,
  3155. ILK_DISPLAY_DFT_SRWM,
  3156. 2,
  3157. ILK_FIFO_LINE_SIZE
  3158. };
  3159. static const struct intel_watermark_params ironlake_cursor_srwm_info = {
  3160. ILK_CURSOR_SR_FIFO,
  3161. ILK_CURSOR_MAX_SRWM,
  3162. ILK_CURSOR_DFT_SRWM,
  3163. 2,
  3164. ILK_FIFO_LINE_SIZE
  3165. };
  3166. static const struct intel_watermark_params sandybridge_display_wm_info = {
  3167. SNB_DISPLAY_FIFO,
  3168. SNB_DISPLAY_MAXWM,
  3169. SNB_DISPLAY_DFTWM,
  3170. 2,
  3171. SNB_FIFO_LINE_SIZE
  3172. };
  3173. static const struct intel_watermark_params sandybridge_cursor_wm_info = {
  3174. SNB_CURSOR_FIFO,
  3175. SNB_CURSOR_MAXWM,
  3176. SNB_CURSOR_DFTWM,
  3177. 2,
  3178. SNB_FIFO_LINE_SIZE
  3179. };
  3180. static const struct intel_watermark_params sandybridge_display_srwm_info = {
  3181. SNB_DISPLAY_SR_FIFO,
  3182. SNB_DISPLAY_MAX_SRWM,
  3183. SNB_DISPLAY_DFT_SRWM,
  3184. 2,
  3185. SNB_FIFO_LINE_SIZE
  3186. };
  3187. static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
  3188. SNB_CURSOR_SR_FIFO,
  3189. SNB_CURSOR_MAX_SRWM,
  3190. SNB_CURSOR_DFT_SRWM,
  3191. 2,
  3192. SNB_FIFO_LINE_SIZE
  3193. };
  3194. /**
  3195. * intel_calculate_wm - calculate watermark level
  3196. * @clock_in_khz: pixel clock
  3197. * @wm: chip FIFO params
  3198. * @pixel_size: display pixel size
  3199. * @latency_ns: memory latency for the platform
  3200. *
  3201. * Calculate the watermark level (the level at which the display plane will
  3202. * start fetching from memory again). Each chip has a different display
  3203. * FIFO size and allocation, so the caller needs to figure that out and pass
  3204. * in the correct intel_watermark_params structure.
  3205. *
  3206. * As the pixel clock runs, the FIFO will be drained at a rate that depends
  3207. * on the pixel size. When it reaches the watermark level, it'll start
  3208. * fetching FIFO line sized based chunks from memory until the FIFO fills
  3209. * past the watermark point. If the FIFO drains completely, a FIFO underrun
  3210. * will occur, and a display engine hang could result.
  3211. */
  3212. static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
  3213. const struct intel_watermark_params *wm,
  3214. int fifo_size,
  3215. int pixel_size,
  3216. unsigned long latency_ns)
  3217. {
  3218. long entries_required, wm_size;
  3219. /*
  3220. * Note: we need to make sure we don't overflow for various clock &
  3221. * latency values.
  3222. * clocks go from a few thousand to several hundred thousand.
  3223. * latency is usually a few thousand
  3224. */
  3225. entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
  3226. 1000;
  3227. entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
  3228. DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
  3229. wm_size = fifo_size - (entries_required + wm->guard_size);
  3230. DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
  3231. /* Don't promote wm_size to unsigned... */
  3232. if (wm_size > (long)wm->max_wm)
  3233. wm_size = wm->max_wm;
  3234. if (wm_size <= 0)
  3235. wm_size = wm->default_wm;
  3236. return wm_size;
  3237. }
  3238. struct cxsr_latency {
  3239. int is_desktop;
  3240. int is_ddr3;
  3241. unsigned long fsb_freq;
  3242. unsigned long mem_freq;
  3243. unsigned long display_sr;
  3244. unsigned long display_hpll_disable;
  3245. unsigned long cursor_sr;
  3246. unsigned long cursor_hpll_disable;
  3247. };
  3248. static const struct cxsr_latency cxsr_latency_table[] = {
  3249. {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
  3250. {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
  3251. {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
  3252. {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
  3253. {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
  3254. {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
  3255. {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
  3256. {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
  3257. {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
  3258. {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
  3259. {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
  3260. {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
  3261. {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
  3262. {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
  3263. {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
  3264. {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
  3265. {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
  3266. {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
  3267. {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
  3268. {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
  3269. {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
  3270. {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
  3271. {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
  3272. {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
  3273. {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
  3274. {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
  3275. {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
  3276. {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
  3277. {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
  3278. {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
  3279. };
  3280. static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
  3281. int is_ddr3,
  3282. int fsb,
  3283. int mem)
  3284. {
  3285. const struct cxsr_latency *latency;
  3286. int i;
  3287. if (fsb == 0 || mem == 0)
  3288. return NULL;
  3289. for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
  3290. latency = &cxsr_latency_table[i];
  3291. if (is_desktop == latency->is_desktop &&
  3292. is_ddr3 == latency->is_ddr3 &&
  3293. fsb == latency->fsb_freq && mem == latency->mem_freq)
  3294. return latency;
  3295. }
  3296. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  3297. return NULL;
  3298. }
  3299. static void pineview_disable_cxsr(struct drm_device *dev)
  3300. {
  3301. struct drm_i915_private *dev_priv = dev->dev_private;
  3302. /* deactivate cxsr */
  3303. I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
  3304. }
  3305. /*
  3306. * Latency for FIFO fetches is dependent on several factors:
  3307. * - memory configuration (speed, channels)
  3308. * - chipset
  3309. * - current MCH state
  3310. * It can be fairly high in some situations, so here we assume a fairly
  3311. * pessimal value. It's a tradeoff between extra memory fetches (if we
  3312. * set this value too high, the FIFO will fetch frequently to stay full)
  3313. * and power consumption (set it too low to save power and we might see
  3314. * FIFO underruns and display "flicker").
  3315. *
  3316. * A value of 5us seems to be a good balance; safe for very low end
  3317. * platforms but not overly aggressive on lower latency configs.
  3318. */
  3319. static const int latency_ns = 5000;
  3320. static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
  3321. {
  3322. struct drm_i915_private *dev_priv = dev->dev_private;
  3323. uint32_t dsparb = I915_READ(DSPARB);
  3324. int size;
  3325. size = dsparb & 0x7f;
  3326. if (plane)
  3327. size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
  3328. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  3329. plane ? "B" : "A", size);
  3330. return size;
  3331. }
  3332. static int i85x_get_fifo_size(struct drm_device *dev, int plane)
  3333. {
  3334. struct drm_i915_private *dev_priv = dev->dev_private;
  3335. uint32_t dsparb = I915_READ(DSPARB);
  3336. int size;
  3337. size = dsparb & 0x1ff;
  3338. if (plane)
  3339. size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
  3340. size >>= 1; /* Convert to cachelines */
  3341. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  3342. plane ? "B" : "A", size);
  3343. return size;
  3344. }
  3345. static int i845_get_fifo_size(struct drm_device *dev, int plane)
  3346. {
  3347. struct drm_i915_private *dev_priv = dev->dev_private;
  3348. uint32_t dsparb = I915_READ(DSPARB);
  3349. int size;
  3350. size = dsparb & 0x7f;
  3351. size >>= 2; /* Convert to cachelines */
  3352. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  3353. plane ? "B" : "A",
  3354. size);
  3355. return size;
  3356. }
  3357. static int i830_get_fifo_size(struct drm_device *dev, int plane)
  3358. {
  3359. struct drm_i915_private *dev_priv = dev->dev_private;
  3360. uint32_t dsparb = I915_READ(DSPARB);
  3361. int size;
  3362. size = dsparb & 0x7f;
  3363. size >>= 1; /* Convert to cachelines */
  3364. DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
  3365. plane ? "B" : "A", size);
  3366. return size;
  3367. }
  3368. static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
  3369. {
  3370. struct drm_crtc *crtc, *enabled = NULL;
  3371. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  3372. if (crtc->enabled && crtc->fb) {
  3373. if (enabled)
  3374. return NULL;
  3375. enabled = crtc;
  3376. }
  3377. }
  3378. return enabled;
  3379. }
  3380. static void pineview_update_wm(struct drm_device *dev)
  3381. {
  3382. struct drm_i915_private *dev_priv = dev->dev_private;
  3383. struct drm_crtc *crtc;
  3384. const struct cxsr_latency *latency;
  3385. u32 reg;
  3386. unsigned long wm;
  3387. latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
  3388. dev_priv->fsb_freq, dev_priv->mem_freq);
  3389. if (!latency) {
  3390. DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
  3391. pineview_disable_cxsr(dev);
  3392. return;
  3393. }
  3394. crtc = single_enabled_crtc(dev);
  3395. if (crtc) {
  3396. int clock = crtc->mode.clock;
  3397. int pixel_size = crtc->fb->bits_per_pixel / 8;
  3398. /* Display SR */
  3399. wm = intel_calculate_wm(clock, &pineview_display_wm,
  3400. pineview_display_wm.fifo_size,
  3401. pixel_size, latency->display_sr);
  3402. reg = I915_READ(DSPFW1);
  3403. reg &= ~DSPFW_SR_MASK;
  3404. reg |= wm << DSPFW_SR_SHIFT;
  3405. I915_WRITE(DSPFW1, reg);
  3406. DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
  3407. /* cursor SR */
  3408. wm = intel_calculate_wm(clock, &pineview_cursor_wm,
  3409. pineview_display_wm.fifo_size,
  3410. pixel_size, latency->cursor_sr);
  3411. reg = I915_READ(DSPFW3);
  3412. reg &= ~DSPFW_CURSOR_SR_MASK;
  3413. reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
  3414. I915_WRITE(DSPFW3, reg);
  3415. /* Display HPLL off SR */
  3416. wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
  3417. pineview_display_hplloff_wm.fifo_size,
  3418. pixel_size, latency->display_hpll_disable);
  3419. reg = I915_READ(DSPFW3);
  3420. reg &= ~DSPFW_HPLL_SR_MASK;
  3421. reg |= wm & DSPFW_HPLL_SR_MASK;
  3422. I915_WRITE(DSPFW3, reg);
  3423. /* cursor HPLL off SR */
  3424. wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
  3425. pineview_display_hplloff_wm.fifo_size,
  3426. pixel_size, latency->cursor_hpll_disable);
  3427. reg = I915_READ(DSPFW3);
  3428. reg &= ~DSPFW_HPLL_CURSOR_MASK;
  3429. reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
  3430. I915_WRITE(DSPFW3, reg);
  3431. DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
  3432. /* activate cxsr */
  3433. I915_WRITE(DSPFW3,
  3434. I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
  3435. DRM_DEBUG_KMS("Self-refresh is enabled\n");
  3436. } else {
  3437. pineview_disable_cxsr(dev);
  3438. DRM_DEBUG_KMS("Self-refresh is disabled\n");
  3439. }
  3440. }
  3441. static bool g4x_compute_wm0(struct drm_device *dev,
  3442. int plane,
  3443. const struct intel_watermark_params *display,
  3444. int display_latency_ns,
  3445. const struct intel_watermark_params *cursor,
  3446. int cursor_latency_ns,
  3447. int *plane_wm,
  3448. int *cursor_wm)
  3449. {
  3450. struct drm_crtc *crtc;
  3451. int htotal, hdisplay, clock, pixel_size;
  3452. int line_time_us, line_count;
  3453. int entries, tlb_miss;
  3454. crtc = intel_get_crtc_for_plane(dev, plane);
  3455. if (crtc->fb == NULL || !crtc->enabled) {
  3456. *cursor_wm = cursor->guard_size;
  3457. *plane_wm = display->guard_size;
  3458. return false;
  3459. }
  3460. htotal = crtc->mode.htotal;
  3461. hdisplay = crtc->mode.hdisplay;
  3462. clock = crtc->mode.clock;
  3463. pixel_size = crtc->fb->bits_per_pixel / 8;
  3464. /* Use the small buffer method to calculate plane watermark */
  3465. entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  3466. tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
  3467. if (tlb_miss > 0)
  3468. entries += tlb_miss;
  3469. entries = DIV_ROUND_UP(entries, display->cacheline_size);
  3470. *plane_wm = entries + display->guard_size;
  3471. if (*plane_wm > (int)display->max_wm)
  3472. *plane_wm = display->max_wm;
  3473. /* Use the large buffer method to calculate cursor watermark */
  3474. line_time_us = ((htotal * 1000) / clock);
  3475. line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
  3476. entries = line_count * 64 * pixel_size;
  3477. tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
  3478. if (tlb_miss > 0)
  3479. entries += tlb_miss;
  3480. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  3481. *cursor_wm = entries + cursor->guard_size;
  3482. if (*cursor_wm > (int)cursor->max_wm)
  3483. *cursor_wm = (int)cursor->max_wm;
  3484. return true;
  3485. }
  3486. /*
  3487. * Check the wm result.
  3488. *
  3489. * If any calculated watermark values is larger than the maximum value that
  3490. * can be programmed into the associated watermark register, that watermark
  3491. * must be disabled.
  3492. */
  3493. static bool g4x_check_srwm(struct drm_device *dev,
  3494. int display_wm, int cursor_wm,
  3495. const struct intel_watermark_params *display,
  3496. const struct intel_watermark_params *cursor)
  3497. {
  3498. DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
  3499. display_wm, cursor_wm);
  3500. if (display_wm > display->max_wm) {
  3501. DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
  3502. display_wm, display->max_wm);
  3503. return false;
  3504. }
  3505. if (cursor_wm > cursor->max_wm) {
  3506. DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
  3507. cursor_wm, cursor->max_wm);
  3508. return false;
  3509. }
  3510. if (!(display_wm || cursor_wm)) {
  3511. DRM_DEBUG_KMS("SR latency is 0, disabling\n");
  3512. return false;
  3513. }
  3514. return true;
  3515. }
  3516. static bool g4x_compute_srwm(struct drm_device *dev,
  3517. int plane,
  3518. int latency_ns,
  3519. const struct intel_watermark_params *display,
  3520. const struct intel_watermark_params *cursor,
  3521. int *display_wm, int *cursor_wm)
  3522. {
  3523. struct drm_crtc *crtc;
  3524. int hdisplay, htotal, pixel_size, clock;
  3525. unsigned long line_time_us;
  3526. int line_count, line_size;
  3527. int small, large;
  3528. int entries;
  3529. if (!latency_ns) {
  3530. *display_wm = *cursor_wm = 0;
  3531. return false;
  3532. }
  3533. crtc = intel_get_crtc_for_plane(dev, plane);
  3534. hdisplay = crtc->mode.hdisplay;
  3535. htotal = crtc->mode.htotal;
  3536. clock = crtc->mode.clock;
  3537. pixel_size = crtc->fb->bits_per_pixel / 8;
  3538. line_time_us = (htotal * 1000) / clock;
  3539. line_count = (latency_ns / line_time_us + 1000) / 1000;
  3540. line_size = hdisplay * pixel_size;
  3541. /* Use the minimum of the small and large buffer method for primary */
  3542. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  3543. large = line_count * line_size;
  3544. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  3545. *display_wm = entries + display->guard_size;
  3546. /* calculate the self-refresh watermark for display cursor */
  3547. entries = line_count * pixel_size * 64;
  3548. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  3549. *cursor_wm = entries + cursor->guard_size;
  3550. return g4x_check_srwm(dev,
  3551. *display_wm, *cursor_wm,
  3552. display, cursor);
  3553. }
  3554. #define single_plane_enabled(mask) is_power_of_2(mask)
  3555. static void g4x_update_wm(struct drm_device *dev)
  3556. {
  3557. static const int sr_latency_ns = 12000;
  3558. struct drm_i915_private *dev_priv = dev->dev_private;
  3559. int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
  3560. int plane_sr, cursor_sr;
  3561. unsigned int enabled = 0;
  3562. if (g4x_compute_wm0(dev, 0,
  3563. &g4x_wm_info, latency_ns,
  3564. &g4x_cursor_wm_info, latency_ns,
  3565. &planea_wm, &cursora_wm))
  3566. enabled |= 1;
  3567. if (g4x_compute_wm0(dev, 1,
  3568. &g4x_wm_info, latency_ns,
  3569. &g4x_cursor_wm_info, latency_ns,
  3570. &planeb_wm, &cursorb_wm))
  3571. enabled |= 2;
  3572. plane_sr = cursor_sr = 0;
  3573. if (single_plane_enabled(enabled) &&
  3574. g4x_compute_srwm(dev, ffs(enabled) - 1,
  3575. sr_latency_ns,
  3576. &g4x_wm_info,
  3577. &g4x_cursor_wm_info,
  3578. &plane_sr, &cursor_sr))
  3579. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  3580. else
  3581. I915_WRITE(FW_BLC_SELF,
  3582. I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
  3583. DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
  3584. planea_wm, cursora_wm,
  3585. planeb_wm, cursorb_wm,
  3586. plane_sr, cursor_sr);
  3587. I915_WRITE(DSPFW1,
  3588. (plane_sr << DSPFW_SR_SHIFT) |
  3589. (cursorb_wm << DSPFW_CURSORB_SHIFT) |
  3590. (planeb_wm << DSPFW_PLANEB_SHIFT) |
  3591. planea_wm);
  3592. I915_WRITE(DSPFW2,
  3593. (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
  3594. (cursora_wm << DSPFW_CURSORA_SHIFT));
  3595. /* HPLL off in SR has some issues on G4x... disable it */
  3596. I915_WRITE(DSPFW3,
  3597. (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
  3598. (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  3599. }
  3600. static void i965_update_wm(struct drm_device *dev)
  3601. {
  3602. struct drm_i915_private *dev_priv = dev->dev_private;
  3603. struct drm_crtc *crtc;
  3604. int srwm = 1;
  3605. int cursor_sr = 16;
  3606. /* Calc sr entries for one plane configs */
  3607. crtc = single_enabled_crtc(dev);
  3608. if (crtc) {
  3609. /* self-refresh has much higher latency */
  3610. static const int sr_latency_ns = 12000;
  3611. int clock = crtc->mode.clock;
  3612. int htotal = crtc->mode.htotal;
  3613. int hdisplay = crtc->mode.hdisplay;
  3614. int pixel_size = crtc->fb->bits_per_pixel / 8;
  3615. unsigned long line_time_us;
  3616. int entries;
  3617. line_time_us = ((htotal * 1000) / clock);
  3618. /* Use ns/us then divide to preserve precision */
  3619. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  3620. pixel_size * hdisplay;
  3621. entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
  3622. srwm = I965_FIFO_SIZE - entries;
  3623. if (srwm < 0)
  3624. srwm = 1;
  3625. srwm &= 0x1ff;
  3626. DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
  3627. entries, srwm);
  3628. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  3629. pixel_size * 64;
  3630. entries = DIV_ROUND_UP(entries,
  3631. i965_cursor_wm_info.cacheline_size);
  3632. cursor_sr = i965_cursor_wm_info.fifo_size -
  3633. (entries + i965_cursor_wm_info.guard_size);
  3634. if (cursor_sr > i965_cursor_wm_info.max_wm)
  3635. cursor_sr = i965_cursor_wm_info.max_wm;
  3636. DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
  3637. "cursor %d\n", srwm, cursor_sr);
  3638. if (IS_CRESTLINE(dev))
  3639. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
  3640. } else {
  3641. /* Turn off self refresh if both pipes are enabled */
  3642. if (IS_CRESTLINE(dev))
  3643. I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
  3644. & ~FW_BLC_SELF_EN);
  3645. }
  3646. DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
  3647. srwm);
  3648. /* 965 has limitations... */
  3649. I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
  3650. (8 << 16) | (8 << 8) | (8 << 0));
  3651. I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
  3652. /* update cursor SR watermark */
  3653. I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
  3654. }
  3655. static void i9xx_update_wm(struct drm_device *dev)
  3656. {
  3657. struct drm_i915_private *dev_priv = dev->dev_private;
  3658. const struct intel_watermark_params *wm_info;
  3659. uint32_t fwater_lo;
  3660. uint32_t fwater_hi;
  3661. int cwm, srwm = 1;
  3662. int fifo_size;
  3663. int planea_wm, planeb_wm;
  3664. struct drm_crtc *crtc, *enabled = NULL;
  3665. if (IS_I945GM(dev))
  3666. wm_info = &i945_wm_info;
  3667. else if (!IS_GEN2(dev))
  3668. wm_info = &i915_wm_info;
  3669. else
  3670. wm_info = &i855_wm_info;
  3671. fifo_size = dev_priv->display.get_fifo_size(dev, 0);
  3672. crtc = intel_get_crtc_for_plane(dev, 0);
  3673. if (crtc->enabled && crtc->fb) {
  3674. planea_wm = intel_calculate_wm(crtc->mode.clock,
  3675. wm_info, fifo_size,
  3676. crtc->fb->bits_per_pixel / 8,
  3677. latency_ns);
  3678. enabled = crtc;
  3679. } else
  3680. planea_wm = fifo_size - wm_info->guard_size;
  3681. fifo_size = dev_priv->display.get_fifo_size(dev, 1);
  3682. crtc = intel_get_crtc_for_plane(dev, 1);
  3683. if (crtc->enabled && crtc->fb) {
  3684. planeb_wm = intel_calculate_wm(crtc->mode.clock,
  3685. wm_info, fifo_size,
  3686. crtc->fb->bits_per_pixel / 8,
  3687. latency_ns);
  3688. if (enabled == NULL)
  3689. enabled = crtc;
  3690. else
  3691. enabled = NULL;
  3692. } else
  3693. planeb_wm = fifo_size - wm_info->guard_size;
  3694. DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
  3695. /*
  3696. * Overlay gets an aggressive default since video jitter is bad.
  3697. */
  3698. cwm = 2;
  3699. /* Play safe and disable self-refresh before adjusting watermarks. */
  3700. if (IS_I945G(dev) || IS_I945GM(dev))
  3701. I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
  3702. else if (IS_I915GM(dev))
  3703. I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
  3704. /* Calc sr entries for one plane configs */
  3705. if (HAS_FW_BLC(dev) && enabled) {
  3706. /* self-refresh has much higher latency */
  3707. static const int sr_latency_ns = 6000;
  3708. int clock = enabled->mode.clock;
  3709. int htotal = enabled->mode.htotal;
  3710. int hdisplay = enabled->mode.hdisplay;
  3711. int pixel_size = enabled->fb->bits_per_pixel / 8;
  3712. unsigned long line_time_us;
  3713. int entries;
  3714. line_time_us = (htotal * 1000) / clock;
  3715. /* Use ns/us then divide to preserve precision */
  3716. entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
  3717. pixel_size * hdisplay;
  3718. entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
  3719. DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
  3720. srwm = wm_info->fifo_size - entries;
  3721. if (srwm < 0)
  3722. srwm = 1;
  3723. if (IS_I945G(dev) || IS_I945GM(dev))
  3724. I915_WRITE(FW_BLC_SELF,
  3725. FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
  3726. else if (IS_I915GM(dev))
  3727. I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
  3728. }
  3729. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
  3730. planea_wm, planeb_wm, cwm, srwm);
  3731. fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
  3732. fwater_hi = (cwm & 0x1f);
  3733. /* Set request length to 8 cachelines per fetch */
  3734. fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
  3735. fwater_hi = fwater_hi | (1 << 8);
  3736. I915_WRITE(FW_BLC, fwater_lo);
  3737. I915_WRITE(FW_BLC2, fwater_hi);
  3738. if (HAS_FW_BLC(dev)) {
  3739. if (enabled) {
  3740. if (IS_I945G(dev) || IS_I945GM(dev))
  3741. I915_WRITE(FW_BLC_SELF,
  3742. FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
  3743. else if (IS_I915GM(dev))
  3744. I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
  3745. DRM_DEBUG_KMS("memory self refresh enabled\n");
  3746. } else
  3747. DRM_DEBUG_KMS("memory self refresh disabled\n");
  3748. }
  3749. }
  3750. static void i830_update_wm(struct drm_device *dev)
  3751. {
  3752. struct drm_i915_private *dev_priv = dev->dev_private;
  3753. struct drm_crtc *crtc;
  3754. uint32_t fwater_lo;
  3755. int planea_wm;
  3756. crtc = single_enabled_crtc(dev);
  3757. if (crtc == NULL)
  3758. return;
  3759. planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
  3760. dev_priv->display.get_fifo_size(dev, 0),
  3761. crtc->fb->bits_per_pixel / 8,
  3762. latency_ns);
  3763. fwater_lo = I915_READ(FW_BLC) & ~0xfff;
  3764. fwater_lo |= (3<<8) | planea_wm;
  3765. DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
  3766. I915_WRITE(FW_BLC, fwater_lo);
  3767. }
  3768. #define ILK_LP0_PLANE_LATENCY 700
  3769. #define ILK_LP0_CURSOR_LATENCY 1300
  3770. /*
  3771. * Check the wm result.
  3772. *
  3773. * If any calculated watermark values is larger than the maximum value that
  3774. * can be programmed into the associated watermark register, that watermark
  3775. * must be disabled.
  3776. */
  3777. static bool ironlake_check_srwm(struct drm_device *dev, int level,
  3778. int fbc_wm, int display_wm, int cursor_wm,
  3779. const struct intel_watermark_params *display,
  3780. const struct intel_watermark_params *cursor)
  3781. {
  3782. struct drm_i915_private *dev_priv = dev->dev_private;
  3783. DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
  3784. " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
  3785. if (fbc_wm > SNB_FBC_MAX_SRWM) {
  3786. DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
  3787. fbc_wm, SNB_FBC_MAX_SRWM, level);
  3788. /* fbc has it's own way to disable FBC WM */
  3789. I915_WRITE(DISP_ARB_CTL,
  3790. I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
  3791. return false;
  3792. }
  3793. if (display_wm > display->max_wm) {
  3794. DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
  3795. display_wm, SNB_DISPLAY_MAX_SRWM, level);
  3796. return false;
  3797. }
  3798. if (cursor_wm > cursor->max_wm) {
  3799. DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
  3800. cursor_wm, SNB_CURSOR_MAX_SRWM, level);
  3801. return false;
  3802. }
  3803. if (!(fbc_wm || display_wm || cursor_wm)) {
  3804. DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
  3805. return false;
  3806. }
  3807. return true;
  3808. }
  3809. /*
  3810. * Compute watermark values of WM[1-3],
  3811. */
  3812. static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
  3813. int latency_ns,
  3814. const struct intel_watermark_params *display,
  3815. const struct intel_watermark_params *cursor,
  3816. int *fbc_wm, int *display_wm, int *cursor_wm)
  3817. {
  3818. struct drm_crtc *crtc;
  3819. unsigned long line_time_us;
  3820. int hdisplay, htotal, pixel_size, clock;
  3821. int line_count, line_size;
  3822. int small, large;
  3823. int entries;
  3824. if (!latency_ns) {
  3825. *fbc_wm = *display_wm = *cursor_wm = 0;
  3826. return false;
  3827. }
  3828. crtc = intel_get_crtc_for_plane(dev, plane);
  3829. hdisplay = crtc->mode.hdisplay;
  3830. htotal = crtc->mode.htotal;
  3831. clock = crtc->mode.clock;
  3832. pixel_size = crtc->fb->bits_per_pixel / 8;
  3833. line_time_us = (htotal * 1000) / clock;
  3834. line_count = (latency_ns / line_time_us + 1000) / 1000;
  3835. line_size = hdisplay * pixel_size;
  3836. /* Use the minimum of the small and large buffer method for primary */
  3837. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  3838. large = line_count * line_size;
  3839. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  3840. *display_wm = entries + display->guard_size;
  3841. /*
  3842. * Spec says:
  3843. * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
  3844. */
  3845. *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
  3846. /* calculate the self-refresh watermark for display cursor */
  3847. entries = line_count * pixel_size * 64;
  3848. entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
  3849. *cursor_wm = entries + cursor->guard_size;
  3850. return ironlake_check_srwm(dev, level,
  3851. *fbc_wm, *display_wm, *cursor_wm,
  3852. display, cursor);
  3853. }
  3854. static void ironlake_update_wm(struct drm_device *dev)
  3855. {
  3856. struct drm_i915_private *dev_priv = dev->dev_private;
  3857. int fbc_wm, plane_wm, cursor_wm;
  3858. unsigned int enabled;
  3859. enabled = 0;
  3860. if (g4x_compute_wm0(dev, 0,
  3861. &ironlake_display_wm_info,
  3862. ILK_LP0_PLANE_LATENCY,
  3863. &ironlake_cursor_wm_info,
  3864. ILK_LP0_CURSOR_LATENCY,
  3865. &plane_wm, &cursor_wm)) {
  3866. I915_WRITE(WM0_PIPEA_ILK,
  3867. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  3868. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  3869. " plane %d, " "cursor: %d\n",
  3870. plane_wm, cursor_wm);
  3871. enabled |= 1;
  3872. }
  3873. if (g4x_compute_wm0(dev, 1,
  3874. &ironlake_display_wm_info,
  3875. ILK_LP0_PLANE_LATENCY,
  3876. &ironlake_cursor_wm_info,
  3877. ILK_LP0_CURSOR_LATENCY,
  3878. &plane_wm, &cursor_wm)) {
  3879. I915_WRITE(WM0_PIPEB_ILK,
  3880. (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
  3881. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  3882. " plane %d, cursor: %d\n",
  3883. plane_wm, cursor_wm);
  3884. enabled |= 2;
  3885. }
  3886. /*
  3887. * Calculate and update the self-refresh watermark only when one
  3888. * display plane is used.
  3889. */
  3890. I915_WRITE(WM3_LP_ILK, 0);
  3891. I915_WRITE(WM2_LP_ILK, 0);
  3892. I915_WRITE(WM1_LP_ILK, 0);
  3893. if (!single_plane_enabled(enabled))
  3894. return;
  3895. enabled = ffs(enabled) - 1;
  3896. /* WM1 */
  3897. if (!ironlake_compute_srwm(dev, 1, enabled,
  3898. ILK_READ_WM1_LATENCY() * 500,
  3899. &ironlake_display_srwm_info,
  3900. &ironlake_cursor_srwm_info,
  3901. &fbc_wm, &plane_wm, &cursor_wm))
  3902. return;
  3903. I915_WRITE(WM1_LP_ILK,
  3904. WM1_LP_SR_EN |
  3905. (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  3906. (fbc_wm << WM1_LP_FBC_SHIFT) |
  3907. (plane_wm << WM1_LP_SR_SHIFT) |
  3908. cursor_wm);
  3909. /* WM2 */
  3910. if (!ironlake_compute_srwm(dev, 2, enabled,
  3911. ILK_READ_WM2_LATENCY() * 500,
  3912. &ironlake_display_srwm_info,
  3913. &ironlake_cursor_srwm_info,
  3914. &fbc_wm, &plane_wm, &cursor_wm))
  3915. return;
  3916. I915_WRITE(WM2_LP_ILK,
  3917. WM2_LP_EN |
  3918. (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  3919. (fbc_wm << WM1_LP_FBC_SHIFT) |
  3920. (plane_wm << WM1_LP_SR_SHIFT) |
  3921. cursor_wm);
  3922. /*
  3923. * WM3 is unsupported on ILK, probably because we don't have latency
  3924. * data for that power state
  3925. */
  3926. }
  3927. void sandybridge_update_wm(struct drm_device *dev)
  3928. {
  3929. struct drm_i915_private *dev_priv = dev->dev_private;
  3930. int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
  3931. u32 val;
  3932. int fbc_wm, plane_wm, cursor_wm;
  3933. unsigned int enabled;
  3934. enabled = 0;
  3935. if (g4x_compute_wm0(dev, 0,
  3936. &sandybridge_display_wm_info, latency,
  3937. &sandybridge_cursor_wm_info, latency,
  3938. &plane_wm, &cursor_wm)) {
  3939. val = I915_READ(WM0_PIPEA_ILK);
  3940. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  3941. I915_WRITE(WM0_PIPEA_ILK, val |
  3942. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  3943. DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
  3944. " plane %d, " "cursor: %d\n",
  3945. plane_wm, cursor_wm);
  3946. enabled |= 1;
  3947. }
  3948. if (g4x_compute_wm0(dev, 1,
  3949. &sandybridge_display_wm_info, latency,
  3950. &sandybridge_cursor_wm_info, latency,
  3951. &plane_wm, &cursor_wm)) {
  3952. val = I915_READ(WM0_PIPEB_ILK);
  3953. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  3954. I915_WRITE(WM0_PIPEB_ILK, val |
  3955. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  3956. DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
  3957. " plane %d, cursor: %d\n",
  3958. plane_wm, cursor_wm);
  3959. enabled |= 2;
  3960. }
  3961. /* IVB has 3 pipes */
  3962. if (IS_IVYBRIDGE(dev) &&
  3963. g4x_compute_wm0(dev, 2,
  3964. &sandybridge_display_wm_info, latency,
  3965. &sandybridge_cursor_wm_info, latency,
  3966. &plane_wm, &cursor_wm)) {
  3967. val = I915_READ(WM0_PIPEC_IVB);
  3968. val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
  3969. I915_WRITE(WM0_PIPEC_IVB, val |
  3970. ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
  3971. DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
  3972. " plane %d, cursor: %d\n",
  3973. plane_wm, cursor_wm);
  3974. enabled |= 3;
  3975. }
  3976. /*
  3977. * Calculate and update the self-refresh watermark only when one
  3978. * display plane is used.
  3979. *
  3980. * SNB support 3 levels of watermark.
  3981. *
  3982. * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
  3983. * and disabled in the descending order
  3984. *
  3985. */
  3986. I915_WRITE(WM3_LP_ILK, 0);
  3987. I915_WRITE(WM2_LP_ILK, 0);
  3988. I915_WRITE(WM1_LP_ILK, 0);
  3989. if (!single_plane_enabled(enabled) ||
  3990. dev_priv->sprite_scaling_enabled)
  3991. return;
  3992. enabled = ffs(enabled) - 1;
  3993. /* WM1 */
  3994. if (!ironlake_compute_srwm(dev, 1, enabled,
  3995. SNB_READ_WM1_LATENCY() * 500,
  3996. &sandybridge_display_srwm_info,
  3997. &sandybridge_cursor_srwm_info,
  3998. &fbc_wm, &plane_wm, &cursor_wm))
  3999. return;
  4000. I915_WRITE(WM1_LP_ILK,
  4001. WM1_LP_SR_EN |
  4002. (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  4003. (fbc_wm << WM1_LP_FBC_SHIFT) |
  4004. (plane_wm << WM1_LP_SR_SHIFT) |
  4005. cursor_wm);
  4006. /* WM2 */
  4007. if (!ironlake_compute_srwm(dev, 2, enabled,
  4008. SNB_READ_WM2_LATENCY() * 500,
  4009. &sandybridge_display_srwm_info,
  4010. &sandybridge_cursor_srwm_info,
  4011. &fbc_wm, &plane_wm, &cursor_wm))
  4012. return;
  4013. I915_WRITE(WM2_LP_ILK,
  4014. WM2_LP_EN |
  4015. (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  4016. (fbc_wm << WM1_LP_FBC_SHIFT) |
  4017. (plane_wm << WM1_LP_SR_SHIFT) |
  4018. cursor_wm);
  4019. /* WM3 */
  4020. if (!ironlake_compute_srwm(dev, 3, enabled,
  4021. SNB_READ_WM3_LATENCY() * 500,
  4022. &sandybridge_display_srwm_info,
  4023. &sandybridge_cursor_srwm_info,
  4024. &fbc_wm, &plane_wm, &cursor_wm))
  4025. return;
  4026. I915_WRITE(WM3_LP_ILK,
  4027. WM3_LP_EN |
  4028. (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
  4029. (fbc_wm << WM1_LP_FBC_SHIFT) |
  4030. (plane_wm << WM1_LP_SR_SHIFT) |
  4031. cursor_wm);
  4032. }
  4033. static bool
  4034. sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
  4035. uint32_t sprite_width, int pixel_size,
  4036. const struct intel_watermark_params *display,
  4037. int display_latency_ns, int *sprite_wm)
  4038. {
  4039. struct drm_crtc *crtc;
  4040. int clock;
  4041. int entries, tlb_miss;
  4042. crtc = intel_get_crtc_for_plane(dev, plane);
  4043. if (crtc->fb == NULL || !crtc->enabled) {
  4044. *sprite_wm = display->guard_size;
  4045. return false;
  4046. }
  4047. clock = crtc->mode.clock;
  4048. /* Use the small buffer method to calculate the sprite watermark */
  4049. entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
  4050. tlb_miss = display->fifo_size*display->cacheline_size -
  4051. sprite_width * 8;
  4052. if (tlb_miss > 0)
  4053. entries += tlb_miss;
  4054. entries = DIV_ROUND_UP(entries, display->cacheline_size);
  4055. *sprite_wm = entries + display->guard_size;
  4056. if (*sprite_wm > (int)display->max_wm)
  4057. *sprite_wm = display->max_wm;
  4058. return true;
  4059. }
  4060. static bool
  4061. sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
  4062. uint32_t sprite_width, int pixel_size,
  4063. const struct intel_watermark_params *display,
  4064. int latency_ns, int *sprite_wm)
  4065. {
  4066. struct drm_crtc *crtc;
  4067. unsigned long line_time_us;
  4068. int clock;
  4069. int line_count, line_size;
  4070. int small, large;
  4071. int entries;
  4072. if (!latency_ns) {
  4073. *sprite_wm = 0;
  4074. return false;
  4075. }
  4076. crtc = intel_get_crtc_for_plane(dev, plane);
  4077. clock = crtc->mode.clock;
  4078. line_time_us = (sprite_width * 1000) / clock;
  4079. line_count = (latency_ns / line_time_us + 1000) / 1000;
  4080. line_size = sprite_width * pixel_size;
  4081. /* Use the minimum of the small and large buffer method for primary */
  4082. small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
  4083. large = line_count * line_size;
  4084. entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
  4085. *sprite_wm = entries + display->guard_size;
  4086. return *sprite_wm > 0x3ff ? false : true;
  4087. }
  4088. static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
  4089. uint32_t sprite_width, int pixel_size)
  4090. {
  4091. struct drm_i915_private *dev_priv = dev->dev_private;
  4092. int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
  4093. u32 val;
  4094. int sprite_wm, reg;
  4095. int ret;
  4096. switch (pipe) {
  4097. case 0:
  4098. reg = WM0_PIPEA_ILK;
  4099. break;
  4100. case 1:
  4101. reg = WM0_PIPEB_ILK;
  4102. break;
  4103. case 2:
  4104. reg = WM0_PIPEC_IVB;
  4105. break;
  4106. default:
  4107. return; /* bad pipe */
  4108. }
  4109. ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
  4110. &sandybridge_display_wm_info,
  4111. latency, &sprite_wm);
  4112. if (!ret) {
  4113. DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
  4114. pipe);
  4115. return;
  4116. }
  4117. val = I915_READ(reg);
  4118. val &= ~WM0_PIPE_SPRITE_MASK;
  4119. I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
  4120. DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
  4121. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  4122. pixel_size,
  4123. &sandybridge_display_srwm_info,
  4124. SNB_READ_WM1_LATENCY() * 500,
  4125. &sprite_wm);
  4126. if (!ret) {
  4127. DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
  4128. pipe);
  4129. return;
  4130. }
  4131. I915_WRITE(WM1S_LP_ILK, sprite_wm);
  4132. /* Only IVB has two more LP watermarks for sprite */
  4133. if (!IS_IVYBRIDGE(dev))
  4134. return;
  4135. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  4136. pixel_size,
  4137. &sandybridge_display_srwm_info,
  4138. SNB_READ_WM2_LATENCY() * 500,
  4139. &sprite_wm);
  4140. if (!ret) {
  4141. DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
  4142. pipe);
  4143. return;
  4144. }
  4145. I915_WRITE(WM2S_LP_IVB, sprite_wm);
  4146. ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
  4147. pixel_size,
  4148. &sandybridge_display_srwm_info,
  4149. SNB_READ_WM3_LATENCY() * 500,
  4150. &sprite_wm);
  4151. if (!ret) {
  4152. DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
  4153. pipe);
  4154. return;
  4155. }
  4156. I915_WRITE(WM3S_LP_IVB, sprite_wm);
  4157. }
  4158. /**
  4159. * intel_update_watermarks - update FIFO watermark values based on current modes
  4160. *
  4161. * Calculate watermark values for the various WM regs based on current mode
  4162. * and plane configuration.
  4163. *
  4164. * There are several cases to deal with here:
  4165. * - normal (i.e. non-self-refresh)
  4166. * - self-refresh (SR) mode
  4167. * - lines are large relative to FIFO size (buffer can hold up to 2)
  4168. * - lines are small relative to FIFO size (buffer can hold more than 2
  4169. * lines), so need to account for TLB latency
  4170. *
  4171. * The normal calculation is:
  4172. * watermark = dotclock * bytes per pixel * latency
  4173. * where latency is platform & configuration dependent (we assume pessimal
  4174. * values here).
  4175. *
  4176. * The SR calculation is:
  4177. * watermark = (trunc(latency/line time)+1) * surface width *
  4178. * bytes per pixel
  4179. * where
  4180. * line time = htotal / dotclock
  4181. * surface width = hdisplay for normal plane and 64 for cursor
  4182. * and latency is assumed to be high, as above.
  4183. *
  4184. * The final value programmed to the register should always be rounded up,
  4185. * and include an extra 2 entries to account for clock crossings.
  4186. *
  4187. * We don't use the sprite, so we can ignore that. And on Crestline we have
  4188. * to set the non-SR watermarks to 8.
  4189. */
  4190. static void intel_update_watermarks(struct drm_device *dev)
  4191. {
  4192. struct drm_i915_private *dev_priv = dev->dev_private;
  4193. if (dev_priv->display.update_wm)
  4194. dev_priv->display.update_wm(dev);
  4195. }
  4196. void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
  4197. uint32_t sprite_width, int pixel_size)
  4198. {
  4199. struct drm_i915_private *dev_priv = dev->dev_private;
  4200. if (dev_priv->display.update_sprite_wm)
  4201. dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
  4202. pixel_size);
  4203. }
  4204. static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
  4205. {
  4206. if (i915_panel_use_ssc >= 0)
  4207. return i915_panel_use_ssc != 0;
  4208. return dev_priv->lvds_use_ssc
  4209. && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
  4210. }
  4211. /**
  4212. * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
  4213. * @crtc: CRTC structure
  4214. * @mode: requested mode
  4215. *
  4216. * A pipe may be connected to one or more outputs. Based on the depth of the
  4217. * attached framebuffer, choose a good color depth to use on the pipe.
  4218. *
  4219. * If possible, match the pipe depth to the fb depth. In some cases, this
  4220. * isn't ideal, because the connected output supports a lesser or restricted
  4221. * set of depths. Resolve that here:
  4222. * LVDS typically supports only 6bpc, so clamp down in that case
  4223. * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
  4224. * Displays may support a restricted set as well, check EDID and clamp as
  4225. * appropriate.
  4226. * DP may want to dither down to 6bpc to fit larger modes
  4227. *
  4228. * RETURNS:
  4229. * Dithering requirement (i.e. false if display bpc and pipe bpc match,
  4230. * true if they don't match).
  4231. */
  4232. static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
  4233. unsigned int *pipe_bpp,
  4234. struct drm_display_mode *mode)
  4235. {
  4236. struct drm_device *dev = crtc->dev;
  4237. struct drm_i915_private *dev_priv = dev->dev_private;
  4238. struct drm_encoder *encoder;
  4239. struct drm_connector *connector;
  4240. unsigned int display_bpc = UINT_MAX, bpc;
  4241. /* Walk the encoders & connectors on this crtc, get min bpc */
  4242. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  4243. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  4244. if (encoder->crtc != crtc)
  4245. continue;
  4246. if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
  4247. unsigned int lvds_bpc;
  4248. if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
  4249. LVDS_A3_POWER_UP)
  4250. lvds_bpc = 8;
  4251. else
  4252. lvds_bpc = 6;
  4253. if (lvds_bpc < display_bpc) {
  4254. DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
  4255. display_bpc = lvds_bpc;
  4256. }
  4257. continue;
  4258. }
  4259. if (intel_encoder->type == INTEL_OUTPUT_EDP) {
  4260. /* Use VBT settings if we have an eDP panel */
  4261. unsigned int edp_bpc = dev_priv->edp.bpp / 3;
  4262. if (edp_bpc < display_bpc) {
  4263. DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
  4264. display_bpc = edp_bpc;
  4265. }
  4266. continue;
  4267. }
  4268. /* Not one of the known troublemakers, check the EDID */
  4269. list_for_each_entry(connector, &dev->mode_config.connector_list,
  4270. head) {
  4271. if (connector->encoder != encoder)
  4272. continue;
  4273. /* Don't use an invalid EDID bpc value */
  4274. if (connector->display_info.bpc &&
  4275. connector->display_info.bpc < display_bpc) {
  4276. DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
  4277. display_bpc = connector->display_info.bpc;
  4278. }
  4279. }
  4280. /*
  4281. * HDMI is either 12 or 8, so if the display lets 10bpc sneak
  4282. * through, clamp it down. (Note: >12bpc will be caught below.)
  4283. */
  4284. if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
  4285. if (display_bpc > 8 && display_bpc < 12) {
  4286. DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
  4287. display_bpc = 12;
  4288. } else {
  4289. DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
  4290. display_bpc = 8;
  4291. }
  4292. }
  4293. }
  4294. if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
  4295. DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
  4296. display_bpc = 6;
  4297. }
  4298. /*
  4299. * We could just drive the pipe at the highest bpc all the time and
  4300. * enable dithering as needed, but that costs bandwidth. So choose
  4301. * the minimum value that expresses the full color range of the fb but
  4302. * also stays within the max display bpc discovered above.
  4303. */
  4304. switch (crtc->fb->depth) {
  4305. case 8:
  4306. bpc = 8; /* since we go through a colormap */
  4307. break;
  4308. case 15:
  4309. case 16:
  4310. bpc = 6; /* min is 18bpp */
  4311. break;
  4312. case 24:
  4313. bpc = 8;
  4314. break;
  4315. case 30:
  4316. bpc = 10;
  4317. break;
  4318. case 48:
  4319. bpc = 12;
  4320. break;
  4321. default:
  4322. DRM_DEBUG("unsupported depth, assuming 24 bits\n");
  4323. bpc = min((unsigned int)8, display_bpc);
  4324. break;
  4325. }
  4326. display_bpc = min(display_bpc, bpc);
  4327. DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
  4328. bpc, display_bpc);
  4329. *pipe_bpp = display_bpc * 3;
  4330. return display_bpc != bpc;
  4331. }
  4332. static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
  4333. {
  4334. struct drm_device *dev = crtc->dev;
  4335. struct drm_i915_private *dev_priv = dev->dev_private;
  4336. int refclk;
  4337. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  4338. intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  4339. refclk = dev_priv->lvds_ssc_freq * 1000;
  4340. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  4341. refclk / 1000);
  4342. } else if (!IS_GEN2(dev)) {
  4343. refclk = 96000;
  4344. } else {
  4345. refclk = 48000;
  4346. }
  4347. return refclk;
  4348. }
  4349. static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
  4350. intel_clock_t *clock)
  4351. {
  4352. /* SDVO TV has fixed PLL values depend on its clock range,
  4353. this mirrors vbios setting. */
  4354. if (adjusted_mode->clock >= 100000
  4355. && adjusted_mode->clock < 140500) {
  4356. clock->p1 = 2;
  4357. clock->p2 = 10;
  4358. clock->n = 3;
  4359. clock->m1 = 16;
  4360. clock->m2 = 8;
  4361. } else if (adjusted_mode->clock >= 140500
  4362. && adjusted_mode->clock <= 200000) {
  4363. clock->p1 = 1;
  4364. clock->p2 = 10;
  4365. clock->n = 6;
  4366. clock->m1 = 12;
  4367. clock->m2 = 8;
  4368. }
  4369. }
  4370. static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
  4371. intel_clock_t *clock,
  4372. intel_clock_t *reduced_clock)
  4373. {
  4374. struct drm_device *dev = crtc->dev;
  4375. struct drm_i915_private *dev_priv = dev->dev_private;
  4376. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4377. int pipe = intel_crtc->pipe;
  4378. u32 fp, fp2 = 0;
  4379. if (IS_PINEVIEW(dev)) {
  4380. fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
  4381. if (reduced_clock)
  4382. fp2 = (1 << reduced_clock->n) << 16 |
  4383. reduced_clock->m1 << 8 | reduced_clock->m2;
  4384. } else {
  4385. fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
  4386. if (reduced_clock)
  4387. fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
  4388. reduced_clock->m2;
  4389. }
  4390. I915_WRITE(FP0(pipe), fp);
  4391. intel_crtc->lowfreq_avail = false;
  4392. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
  4393. reduced_clock && i915_powersave) {
  4394. I915_WRITE(FP1(pipe), fp2);
  4395. intel_crtc->lowfreq_avail = true;
  4396. } else {
  4397. I915_WRITE(FP1(pipe), fp);
  4398. }
  4399. }
  4400. static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
  4401. struct drm_display_mode *mode,
  4402. struct drm_display_mode *adjusted_mode,
  4403. int x, int y,
  4404. struct drm_framebuffer *old_fb)
  4405. {
  4406. struct drm_device *dev = crtc->dev;
  4407. struct drm_i915_private *dev_priv = dev->dev_private;
  4408. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4409. int pipe = intel_crtc->pipe;
  4410. int plane = intel_crtc->plane;
  4411. int refclk, num_connectors = 0;
  4412. intel_clock_t clock, reduced_clock;
  4413. u32 dpll, dspcntr, pipeconf, vsyncshift;
  4414. bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
  4415. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  4416. struct drm_mode_config *mode_config = &dev->mode_config;
  4417. struct intel_encoder *encoder;
  4418. const intel_limit_t *limit;
  4419. int ret;
  4420. u32 temp;
  4421. u32 lvds_sync = 0;
  4422. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  4423. if (encoder->base.crtc != crtc)
  4424. continue;
  4425. switch (encoder->type) {
  4426. case INTEL_OUTPUT_LVDS:
  4427. is_lvds = true;
  4428. break;
  4429. case INTEL_OUTPUT_SDVO:
  4430. case INTEL_OUTPUT_HDMI:
  4431. is_sdvo = true;
  4432. if (encoder->needs_tv_clock)
  4433. is_tv = true;
  4434. break;
  4435. case INTEL_OUTPUT_DVO:
  4436. is_dvo = true;
  4437. break;
  4438. case INTEL_OUTPUT_TVOUT:
  4439. is_tv = true;
  4440. break;
  4441. case INTEL_OUTPUT_ANALOG:
  4442. is_crt = true;
  4443. break;
  4444. case INTEL_OUTPUT_DISPLAYPORT:
  4445. is_dp = true;
  4446. break;
  4447. }
  4448. num_connectors++;
  4449. }
  4450. refclk = i9xx_get_refclk(crtc, num_connectors);
  4451. /*
  4452. * Returns a set of divisors for the desired target clock with the given
  4453. * refclk, or FALSE. The returned values represent the clock equation:
  4454. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4455. */
  4456. limit = intel_limit(crtc, refclk);
  4457. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
  4458. &clock);
  4459. if (!ok) {
  4460. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4461. return -EINVAL;
  4462. }
  4463. /* Ensure that the cursor is valid for the new mode before changing... */
  4464. intel_crtc_update_cursor(crtc, true);
  4465. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4466. /*
  4467. * Ensure we match the reduced clock's P to the target clock.
  4468. * If the clocks don't match, we can't switch the display clock
  4469. * by using the FP0/FP1. In such case we will disable the LVDS
  4470. * downclock feature.
  4471. */
  4472. has_reduced_clock = limit->find_pll(limit, crtc,
  4473. dev_priv->lvds_downclock,
  4474. refclk,
  4475. &clock,
  4476. &reduced_clock);
  4477. }
  4478. if (is_sdvo && is_tv)
  4479. i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
  4480. i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
  4481. &reduced_clock : NULL);
  4482. dpll = DPLL_VGA_MODE_DIS;
  4483. if (!IS_GEN2(dev)) {
  4484. if (is_lvds)
  4485. dpll |= DPLLB_MODE_LVDS;
  4486. else
  4487. dpll |= DPLLB_MODE_DAC_SERIAL;
  4488. if (is_sdvo) {
  4489. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4490. if (pixel_multiplier > 1) {
  4491. if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
  4492. dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
  4493. }
  4494. dpll |= DPLL_DVO_HIGH_SPEED;
  4495. }
  4496. if (is_dp)
  4497. dpll |= DPLL_DVO_HIGH_SPEED;
  4498. /* compute bitmask from p1 value */
  4499. if (IS_PINEVIEW(dev))
  4500. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
  4501. else {
  4502. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4503. if (IS_G4X(dev) && has_reduced_clock)
  4504. dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  4505. }
  4506. switch (clock.p2) {
  4507. case 5:
  4508. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  4509. break;
  4510. case 7:
  4511. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  4512. break;
  4513. case 10:
  4514. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  4515. break;
  4516. case 14:
  4517. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  4518. break;
  4519. }
  4520. if (INTEL_INFO(dev)->gen >= 4)
  4521. dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
  4522. } else {
  4523. if (is_lvds) {
  4524. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4525. } else {
  4526. if (clock.p1 == 2)
  4527. dpll |= PLL_P1_DIVIDE_BY_TWO;
  4528. else
  4529. dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  4530. if (clock.p2 == 4)
  4531. dpll |= PLL_P2_DIVIDE_BY_4;
  4532. }
  4533. }
  4534. if (is_sdvo && is_tv)
  4535. dpll |= PLL_REF_INPUT_TVCLKINBC;
  4536. else if (is_tv)
  4537. /* XXX: just matching BIOS for now */
  4538. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  4539. dpll |= 3;
  4540. else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  4541. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  4542. else
  4543. dpll |= PLL_REF_INPUT_DREFCLK;
  4544. /* setup pipeconf */
  4545. pipeconf = I915_READ(PIPECONF(pipe));
  4546. /* Set up the display plane register */
  4547. dspcntr = DISPPLANE_GAMMA_ENABLE;
  4548. if (pipe == 0)
  4549. dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
  4550. else
  4551. dspcntr |= DISPPLANE_SEL_PIPE_B;
  4552. if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
  4553. /* Enable pixel doubling when the dot clock is > 90% of the (display)
  4554. * core speed.
  4555. *
  4556. * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
  4557. * pipe == 0 check?
  4558. */
  4559. if (mode->clock >
  4560. dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
  4561. pipeconf |= PIPECONF_DOUBLE_WIDE;
  4562. else
  4563. pipeconf &= ~PIPECONF_DOUBLE_WIDE;
  4564. }
  4565. /* default to 8bpc */
  4566. pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
  4567. if (is_dp) {
  4568. if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
  4569. pipeconf |= PIPECONF_BPP_6 |
  4570. PIPECONF_DITHER_EN |
  4571. PIPECONF_DITHER_TYPE_SP;
  4572. }
  4573. }
  4574. dpll |= DPLL_VCO_ENABLE;
  4575. DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
  4576. drm_mode_debug_printmodeline(mode);
  4577. I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  4578. POSTING_READ(DPLL(pipe));
  4579. udelay(150);
  4580. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  4581. * This is an exception to the general rule that mode_set doesn't turn
  4582. * things on.
  4583. */
  4584. if (is_lvds) {
  4585. temp = I915_READ(LVDS);
  4586. temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  4587. if (pipe == 1) {
  4588. temp |= LVDS_PIPEB_SELECT;
  4589. } else {
  4590. temp &= ~LVDS_PIPEB_SELECT;
  4591. }
  4592. /* set the corresponsding LVDS_BORDER bit */
  4593. temp |= dev_priv->lvds_border_bits;
  4594. /* Set the B0-B3 data pairs corresponding to whether we're going to
  4595. * set the DPLLs for dual-channel mode or not.
  4596. */
  4597. if (clock.p2 == 7)
  4598. temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  4599. else
  4600. temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  4601. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  4602. * appropriately here, but we need to look more thoroughly into how
  4603. * panels behave in the two modes.
  4604. */
  4605. /* set the dithering flag on LVDS as needed */
  4606. if (INTEL_INFO(dev)->gen >= 4) {
  4607. if (dev_priv->lvds_dither)
  4608. temp |= LVDS_ENABLE_DITHER;
  4609. else
  4610. temp &= ~LVDS_ENABLE_DITHER;
  4611. }
  4612. if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  4613. lvds_sync |= LVDS_HSYNC_POLARITY;
  4614. if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  4615. lvds_sync |= LVDS_VSYNC_POLARITY;
  4616. if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
  4617. != lvds_sync) {
  4618. char flags[2] = "-+";
  4619. DRM_INFO("Changing LVDS panel from "
  4620. "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
  4621. flags[!(temp & LVDS_HSYNC_POLARITY)],
  4622. flags[!(temp & LVDS_VSYNC_POLARITY)],
  4623. flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
  4624. flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
  4625. temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
  4626. temp |= lvds_sync;
  4627. }
  4628. I915_WRITE(LVDS, temp);
  4629. }
  4630. if (is_dp) {
  4631. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  4632. }
  4633. I915_WRITE(DPLL(pipe), dpll);
  4634. /* Wait for the clocks to stabilize. */
  4635. POSTING_READ(DPLL(pipe));
  4636. udelay(150);
  4637. if (INTEL_INFO(dev)->gen >= 4) {
  4638. temp = 0;
  4639. if (is_sdvo) {
  4640. temp = intel_mode_get_pixel_multiplier(adjusted_mode);
  4641. if (temp > 1)
  4642. temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
  4643. else
  4644. temp = 0;
  4645. }
  4646. I915_WRITE(DPLL_MD(pipe), temp);
  4647. } else {
  4648. /* The pixel multiplier can only be updated once the
  4649. * DPLL is enabled and the clocks are stable.
  4650. *
  4651. * So write it again.
  4652. */
  4653. I915_WRITE(DPLL(pipe), dpll);
  4654. }
  4655. if (HAS_PIPE_CXSR(dev)) {
  4656. if (intel_crtc->lowfreq_avail) {
  4657. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  4658. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  4659. } else {
  4660. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  4661. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  4662. }
  4663. }
  4664. pipeconf &= ~PIPECONF_INTERLACE_MASK;
  4665. if (!IS_GEN2(dev) &&
  4666. adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  4667. pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
  4668. /* the chip adds 2 halflines automatically */
  4669. adjusted_mode->crtc_vtotal -= 1;
  4670. adjusted_mode->crtc_vblank_end -= 1;
  4671. vsyncshift = adjusted_mode->crtc_hsync_start
  4672. - adjusted_mode->crtc_htotal/2;
  4673. } else {
  4674. pipeconf |= PIPECONF_PROGRESSIVE;
  4675. vsyncshift = 0;
  4676. }
  4677. if (!IS_GEN3(dev))
  4678. I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
  4679. I915_WRITE(HTOTAL(pipe),
  4680. (adjusted_mode->crtc_hdisplay - 1) |
  4681. ((adjusted_mode->crtc_htotal - 1) << 16));
  4682. I915_WRITE(HBLANK(pipe),
  4683. (adjusted_mode->crtc_hblank_start - 1) |
  4684. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  4685. I915_WRITE(HSYNC(pipe),
  4686. (adjusted_mode->crtc_hsync_start - 1) |
  4687. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  4688. I915_WRITE(VTOTAL(pipe),
  4689. (adjusted_mode->crtc_vdisplay - 1) |
  4690. ((adjusted_mode->crtc_vtotal - 1) << 16));
  4691. I915_WRITE(VBLANK(pipe),
  4692. (adjusted_mode->crtc_vblank_start - 1) |
  4693. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  4694. I915_WRITE(VSYNC(pipe),
  4695. (adjusted_mode->crtc_vsync_start - 1) |
  4696. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  4697. /* pipesrc and dspsize control the size that is scaled from,
  4698. * which should always be the user's requested size.
  4699. */
  4700. I915_WRITE(DSPSIZE(plane),
  4701. ((mode->vdisplay - 1) << 16) |
  4702. (mode->hdisplay - 1));
  4703. I915_WRITE(DSPPOS(plane), 0);
  4704. I915_WRITE(PIPESRC(pipe),
  4705. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  4706. I915_WRITE(PIPECONF(pipe), pipeconf);
  4707. POSTING_READ(PIPECONF(pipe));
  4708. intel_enable_pipe(dev_priv, pipe, false);
  4709. intel_wait_for_vblank(dev, pipe);
  4710. I915_WRITE(DSPCNTR(plane), dspcntr);
  4711. POSTING_READ(DSPCNTR(plane));
  4712. intel_enable_plane(dev_priv, plane, pipe);
  4713. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  4714. intel_update_watermarks(dev);
  4715. return ret;
  4716. }
  4717. /*
  4718. * Initialize reference clocks when the driver loads
  4719. */
  4720. void ironlake_init_pch_refclk(struct drm_device *dev)
  4721. {
  4722. struct drm_i915_private *dev_priv = dev->dev_private;
  4723. struct drm_mode_config *mode_config = &dev->mode_config;
  4724. struct intel_encoder *encoder;
  4725. u32 temp;
  4726. bool has_lvds = false;
  4727. bool has_cpu_edp = false;
  4728. bool has_pch_edp = false;
  4729. bool has_panel = false;
  4730. bool has_ck505 = false;
  4731. bool can_ssc = false;
  4732. /* We need to take the global config into account */
  4733. list_for_each_entry(encoder, &mode_config->encoder_list,
  4734. base.head) {
  4735. switch (encoder->type) {
  4736. case INTEL_OUTPUT_LVDS:
  4737. has_panel = true;
  4738. has_lvds = true;
  4739. break;
  4740. case INTEL_OUTPUT_EDP:
  4741. has_panel = true;
  4742. if (intel_encoder_is_pch_edp(&encoder->base))
  4743. has_pch_edp = true;
  4744. else
  4745. has_cpu_edp = true;
  4746. break;
  4747. }
  4748. }
  4749. if (HAS_PCH_IBX(dev)) {
  4750. has_ck505 = dev_priv->display_clock_mode;
  4751. can_ssc = has_ck505;
  4752. } else {
  4753. has_ck505 = false;
  4754. can_ssc = true;
  4755. }
  4756. DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
  4757. has_panel, has_lvds, has_pch_edp, has_cpu_edp,
  4758. has_ck505);
  4759. /* Ironlake: try to setup display ref clock before DPLL
  4760. * enabling. This is only under driver's control after
  4761. * PCH B stepping, previous chipset stepping should be
  4762. * ignoring this setting.
  4763. */
  4764. temp = I915_READ(PCH_DREF_CONTROL);
  4765. /* Always enable nonspread source */
  4766. temp &= ~DREF_NONSPREAD_SOURCE_MASK;
  4767. if (has_ck505)
  4768. temp |= DREF_NONSPREAD_CK505_ENABLE;
  4769. else
  4770. temp |= DREF_NONSPREAD_SOURCE_ENABLE;
  4771. if (has_panel) {
  4772. temp &= ~DREF_SSC_SOURCE_MASK;
  4773. temp |= DREF_SSC_SOURCE_ENABLE;
  4774. /* SSC must be turned on before enabling the CPU output */
  4775. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4776. DRM_DEBUG_KMS("Using SSC on panel\n");
  4777. temp |= DREF_SSC1_ENABLE;
  4778. }
  4779. /* Get SSC going before enabling the outputs */
  4780. I915_WRITE(PCH_DREF_CONTROL, temp);
  4781. POSTING_READ(PCH_DREF_CONTROL);
  4782. udelay(200);
  4783. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4784. /* Enable CPU source on CPU attached eDP */
  4785. if (has_cpu_edp) {
  4786. if (intel_panel_use_ssc(dev_priv) && can_ssc) {
  4787. DRM_DEBUG_KMS("Using SSC on eDP\n");
  4788. temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
  4789. }
  4790. else
  4791. temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
  4792. } else
  4793. temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4794. I915_WRITE(PCH_DREF_CONTROL, temp);
  4795. POSTING_READ(PCH_DREF_CONTROL);
  4796. udelay(200);
  4797. } else {
  4798. DRM_DEBUG_KMS("Disabling SSC entirely\n");
  4799. temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
  4800. /* Turn off CPU output */
  4801. temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
  4802. I915_WRITE(PCH_DREF_CONTROL, temp);
  4803. POSTING_READ(PCH_DREF_CONTROL);
  4804. udelay(200);
  4805. /* Turn off the SSC source */
  4806. temp &= ~DREF_SSC_SOURCE_MASK;
  4807. temp |= DREF_SSC_SOURCE_DISABLE;
  4808. /* Turn off SSC1 */
  4809. temp &= ~ DREF_SSC1_ENABLE;
  4810. I915_WRITE(PCH_DREF_CONTROL, temp);
  4811. POSTING_READ(PCH_DREF_CONTROL);
  4812. udelay(200);
  4813. }
  4814. }
  4815. static int ironlake_get_refclk(struct drm_crtc *crtc)
  4816. {
  4817. struct drm_device *dev = crtc->dev;
  4818. struct drm_i915_private *dev_priv = dev->dev_private;
  4819. struct intel_encoder *encoder;
  4820. struct drm_mode_config *mode_config = &dev->mode_config;
  4821. struct intel_encoder *edp_encoder = NULL;
  4822. int num_connectors = 0;
  4823. bool is_lvds = false;
  4824. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  4825. if (encoder->base.crtc != crtc)
  4826. continue;
  4827. switch (encoder->type) {
  4828. case INTEL_OUTPUT_LVDS:
  4829. is_lvds = true;
  4830. break;
  4831. case INTEL_OUTPUT_EDP:
  4832. edp_encoder = encoder;
  4833. break;
  4834. }
  4835. num_connectors++;
  4836. }
  4837. if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
  4838. DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
  4839. dev_priv->lvds_ssc_freq);
  4840. return dev_priv->lvds_ssc_freq * 1000;
  4841. }
  4842. return 120000;
  4843. }
  4844. static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
  4845. struct drm_display_mode *mode,
  4846. struct drm_display_mode *adjusted_mode,
  4847. int x, int y,
  4848. struct drm_framebuffer *old_fb)
  4849. {
  4850. struct drm_device *dev = crtc->dev;
  4851. struct drm_i915_private *dev_priv = dev->dev_private;
  4852. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  4853. int pipe = intel_crtc->pipe;
  4854. int plane = intel_crtc->plane;
  4855. int refclk, num_connectors = 0;
  4856. intel_clock_t clock, reduced_clock;
  4857. u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
  4858. bool ok, has_reduced_clock = false, is_sdvo = false;
  4859. bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
  4860. struct intel_encoder *has_edp_encoder = NULL;
  4861. struct drm_mode_config *mode_config = &dev->mode_config;
  4862. struct intel_encoder *encoder;
  4863. const intel_limit_t *limit;
  4864. int ret;
  4865. struct fdi_m_n m_n = {0};
  4866. u32 temp;
  4867. u32 lvds_sync = 0;
  4868. int target_clock, pixel_multiplier, lane, link_bw, factor;
  4869. unsigned int pipe_bpp;
  4870. bool dither;
  4871. list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
  4872. if (encoder->base.crtc != crtc)
  4873. continue;
  4874. switch (encoder->type) {
  4875. case INTEL_OUTPUT_LVDS:
  4876. is_lvds = true;
  4877. break;
  4878. case INTEL_OUTPUT_SDVO:
  4879. case INTEL_OUTPUT_HDMI:
  4880. is_sdvo = true;
  4881. if (encoder->needs_tv_clock)
  4882. is_tv = true;
  4883. break;
  4884. case INTEL_OUTPUT_TVOUT:
  4885. is_tv = true;
  4886. break;
  4887. case INTEL_OUTPUT_ANALOG:
  4888. is_crt = true;
  4889. break;
  4890. case INTEL_OUTPUT_DISPLAYPORT:
  4891. is_dp = true;
  4892. break;
  4893. case INTEL_OUTPUT_EDP:
  4894. has_edp_encoder = encoder;
  4895. break;
  4896. }
  4897. num_connectors++;
  4898. }
  4899. refclk = ironlake_get_refclk(crtc);
  4900. /*
  4901. * Returns a set of divisors for the desired target clock with the given
  4902. * refclk, or FALSE. The returned values represent the clock equation:
  4903. * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
  4904. */
  4905. limit = intel_limit(crtc, refclk);
  4906. ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
  4907. &clock);
  4908. if (!ok) {
  4909. DRM_ERROR("Couldn't find PLL settings for mode!\n");
  4910. return -EINVAL;
  4911. }
  4912. /* Ensure that the cursor is valid for the new mode before changing... */
  4913. intel_crtc_update_cursor(crtc, true);
  4914. if (is_lvds && dev_priv->lvds_downclock_avail) {
  4915. /*
  4916. * Ensure we match the reduced clock's P to the target clock.
  4917. * If the clocks don't match, we can't switch the display clock
  4918. * by using the FP0/FP1. In such case we will disable the LVDS
  4919. * downclock feature.
  4920. */
  4921. has_reduced_clock = limit->find_pll(limit, crtc,
  4922. dev_priv->lvds_downclock,
  4923. refclk,
  4924. &clock,
  4925. &reduced_clock);
  4926. }
  4927. /* SDVO TV has fixed PLL values depend on its clock range,
  4928. this mirrors vbios setting. */
  4929. if (is_sdvo && is_tv) {
  4930. if (adjusted_mode->clock >= 100000
  4931. && adjusted_mode->clock < 140500) {
  4932. clock.p1 = 2;
  4933. clock.p2 = 10;
  4934. clock.n = 3;
  4935. clock.m1 = 16;
  4936. clock.m2 = 8;
  4937. } else if (adjusted_mode->clock >= 140500
  4938. && adjusted_mode->clock <= 200000) {
  4939. clock.p1 = 1;
  4940. clock.p2 = 10;
  4941. clock.n = 6;
  4942. clock.m1 = 12;
  4943. clock.m2 = 8;
  4944. }
  4945. }
  4946. /* FDI link */
  4947. pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  4948. lane = 0;
  4949. /* CPU eDP doesn't require FDI link, so just set DP M/N
  4950. according to current link config */
  4951. if (has_edp_encoder &&
  4952. !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  4953. target_clock = mode->clock;
  4954. intel_edp_link_config(has_edp_encoder,
  4955. &lane, &link_bw);
  4956. } else {
  4957. /* [e]DP over FDI requires target mode clock
  4958. instead of link clock */
  4959. if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
  4960. target_clock = mode->clock;
  4961. else
  4962. target_clock = adjusted_mode->clock;
  4963. /* FDI is a binary signal running at ~2.7GHz, encoding
  4964. * each output octet as 10 bits. The actual frequency
  4965. * is stored as a divider into a 100MHz clock, and the
  4966. * mode pixel clock is stored in units of 1KHz.
  4967. * Hence the bw of each lane in terms of the mode signal
  4968. * is:
  4969. */
  4970. link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
  4971. }
  4972. /* determine panel color depth */
  4973. temp = I915_READ(PIPECONF(pipe));
  4974. temp &= ~PIPE_BPC_MASK;
  4975. dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
  4976. switch (pipe_bpp) {
  4977. case 18:
  4978. temp |= PIPE_6BPC;
  4979. break;
  4980. case 24:
  4981. temp |= PIPE_8BPC;
  4982. break;
  4983. case 30:
  4984. temp |= PIPE_10BPC;
  4985. break;
  4986. case 36:
  4987. temp |= PIPE_12BPC;
  4988. break;
  4989. default:
  4990. WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
  4991. pipe_bpp);
  4992. temp |= PIPE_8BPC;
  4993. pipe_bpp = 24;
  4994. break;
  4995. }
  4996. intel_crtc->bpp = pipe_bpp;
  4997. I915_WRITE(PIPECONF(pipe), temp);
  4998. if (!lane) {
  4999. /*
  5000. * Account for spread spectrum to avoid
  5001. * oversubscribing the link. Max center spread
  5002. * is 2.5%; use 5% for safety's sake.
  5003. */
  5004. u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
  5005. lane = bps / (link_bw * 8) + 1;
  5006. }
  5007. intel_crtc->fdi_lanes = lane;
  5008. if (pixel_multiplier > 1)
  5009. link_bw *= pixel_multiplier;
  5010. ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
  5011. &m_n);
  5012. fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
  5013. if (has_reduced_clock)
  5014. fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
  5015. reduced_clock.m2;
  5016. /* Enable autotuning of the PLL clock (if permissible) */
  5017. factor = 21;
  5018. if (is_lvds) {
  5019. if ((intel_panel_use_ssc(dev_priv) &&
  5020. dev_priv->lvds_ssc_freq == 100) ||
  5021. (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
  5022. factor = 25;
  5023. } else if (is_sdvo && is_tv)
  5024. factor = 20;
  5025. if (clock.m < factor * clock.n)
  5026. fp |= FP_CB_TUNE;
  5027. dpll = 0;
  5028. if (is_lvds)
  5029. dpll |= DPLLB_MODE_LVDS;
  5030. else
  5031. dpll |= DPLLB_MODE_DAC_SERIAL;
  5032. if (is_sdvo) {
  5033. int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
  5034. if (pixel_multiplier > 1) {
  5035. dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
  5036. }
  5037. dpll |= DPLL_DVO_HIGH_SPEED;
  5038. }
  5039. if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
  5040. dpll |= DPLL_DVO_HIGH_SPEED;
  5041. /* compute bitmask from p1 value */
  5042. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
  5043. /* also FPA1 */
  5044. dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
  5045. switch (clock.p2) {
  5046. case 5:
  5047. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
  5048. break;
  5049. case 7:
  5050. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
  5051. break;
  5052. case 10:
  5053. dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
  5054. break;
  5055. case 14:
  5056. dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
  5057. break;
  5058. }
  5059. if (is_sdvo && is_tv)
  5060. dpll |= PLL_REF_INPUT_TVCLKINBC;
  5061. else if (is_tv)
  5062. /* XXX: just matching BIOS for now */
  5063. /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
  5064. dpll |= 3;
  5065. else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
  5066. dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
  5067. else
  5068. dpll |= PLL_REF_INPUT_DREFCLK;
  5069. /* setup pipeconf */
  5070. pipeconf = I915_READ(PIPECONF(pipe));
  5071. /* Set up the display plane register */
  5072. dspcntr = DISPPLANE_GAMMA_ENABLE;
  5073. DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
  5074. drm_mode_debug_printmodeline(mode);
  5075. /* PCH eDP needs FDI, but CPU eDP does not */
  5076. if (!intel_crtc->no_pll) {
  5077. if (!has_edp_encoder ||
  5078. intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  5079. I915_WRITE(PCH_FP0(pipe), fp);
  5080. I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
  5081. POSTING_READ(PCH_DPLL(pipe));
  5082. udelay(150);
  5083. }
  5084. } else {
  5085. if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
  5086. fp == I915_READ(PCH_FP0(0))) {
  5087. intel_crtc->use_pll_a = true;
  5088. DRM_DEBUG_KMS("using pipe a dpll\n");
  5089. } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
  5090. fp == I915_READ(PCH_FP0(1))) {
  5091. intel_crtc->use_pll_a = false;
  5092. DRM_DEBUG_KMS("using pipe b dpll\n");
  5093. } else {
  5094. DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
  5095. return -EINVAL;
  5096. }
  5097. }
  5098. /* The LVDS pin pair needs to be on before the DPLLs are enabled.
  5099. * This is an exception to the general rule that mode_set doesn't turn
  5100. * things on.
  5101. */
  5102. if (is_lvds) {
  5103. temp = I915_READ(PCH_LVDS);
  5104. temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
  5105. if (HAS_PCH_CPT(dev)) {
  5106. temp &= ~PORT_TRANS_SEL_MASK;
  5107. temp |= PORT_TRANS_SEL_CPT(pipe);
  5108. } else {
  5109. if (pipe == 1)
  5110. temp |= LVDS_PIPEB_SELECT;
  5111. else
  5112. temp &= ~LVDS_PIPEB_SELECT;
  5113. }
  5114. /* set the corresponsding LVDS_BORDER bit */
  5115. temp |= dev_priv->lvds_border_bits;
  5116. /* Set the B0-B3 data pairs corresponding to whether we're going to
  5117. * set the DPLLs for dual-channel mode or not.
  5118. */
  5119. if (clock.p2 == 7)
  5120. temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
  5121. else
  5122. temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
  5123. /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
  5124. * appropriately here, but we need to look more thoroughly into how
  5125. * panels behave in the two modes.
  5126. */
  5127. if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
  5128. lvds_sync |= LVDS_HSYNC_POLARITY;
  5129. if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
  5130. lvds_sync |= LVDS_VSYNC_POLARITY;
  5131. if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
  5132. != lvds_sync) {
  5133. char flags[2] = "-+";
  5134. DRM_INFO("Changing LVDS panel from "
  5135. "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
  5136. flags[!(temp & LVDS_HSYNC_POLARITY)],
  5137. flags[!(temp & LVDS_VSYNC_POLARITY)],
  5138. flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
  5139. flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
  5140. temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
  5141. temp |= lvds_sync;
  5142. }
  5143. I915_WRITE(PCH_LVDS, temp);
  5144. }
  5145. pipeconf &= ~PIPECONF_DITHER_EN;
  5146. pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
  5147. if ((is_lvds && dev_priv->lvds_dither) || dither) {
  5148. pipeconf |= PIPECONF_DITHER_EN;
  5149. pipeconf |= PIPECONF_DITHER_TYPE_SP;
  5150. }
  5151. if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  5152. intel_dp_set_m_n(crtc, mode, adjusted_mode);
  5153. } else {
  5154. /* For non-DP output, clear any trans DP clock recovery setting.*/
  5155. I915_WRITE(TRANSDATA_M1(pipe), 0);
  5156. I915_WRITE(TRANSDATA_N1(pipe), 0);
  5157. I915_WRITE(TRANSDPLINK_M1(pipe), 0);
  5158. I915_WRITE(TRANSDPLINK_N1(pipe), 0);
  5159. }
  5160. if (!intel_crtc->no_pll &&
  5161. (!has_edp_encoder ||
  5162. intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
  5163. I915_WRITE(PCH_DPLL(pipe), dpll);
  5164. /* Wait for the clocks to stabilize. */
  5165. POSTING_READ(PCH_DPLL(pipe));
  5166. udelay(150);
  5167. /* The pixel multiplier can only be updated once the
  5168. * DPLL is enabled and the clocks are stable.
  5169. *
  5170. * So write it again.
  5171. */
  5172. I915_WRITE(PCH_DPLL(pipe), dpll);
  5173. }
  5174. intel_crtc->lowfreq_avail = false;
  5175. if (!intel_crtc->no_pll) {
  5176. if (is_lvds && has_reduced_clock && i915_powersave) {
  5177. I915_WRITE(PCH_FP1(pipe), fp2);
  5178. intel_crtc->lowfreq_avail = true;
  5179. if (HAS_PIPE_CXSR(dev)) {
  5180. DRM_DEBUG_KMS("enabling CxSR downclocking\n");
  5181. pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
  5182. }
  5183. } else {
  5184. I915_WRITE(PCH_FP1(pipe), fp);
  5185. if (HAS_PIPE_CXSR(dev)) {
  5186. DRM_DEBUG_KMS("disabling CxSR downclocking\n");
  5187. pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
  5188. }
  5189. }
  5190. }
  5191. pipeconf &= ~PIPECONF_INTERLACE_MASK;
  5192. if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
  5193. pipeconf |= PIPECONF_INTERLACED_ILK;
  5194. /* the chip adds 2 halflines automatically */
  5195. adjusted_mode->crtc_vtotal -= 1;
  5196. adjusted_mode->crtc_vblank_end -= 1;
  5197. I915_WRITE(VSYNCSHIFT(pipe),
  5198. adjusted_mode->crtc_hsync_start
  5199. - adjusted_mode->crtc_htotal/2);
  5200. } else {
  5201. pipeconf |= PIPECONF_PROGRESSIVE;
  5202. I915_WRITE(VSYNCSHIFT(pipe), 0);
  5203. }
  5204. I915_WRITE(HTOTAL(pipe),
  5205. (adjusted_mode->crtc_hdisplay - 1) |
  5206. ((adjusted_mode->crtc_htotal - 1) << 16));
  5207. I915_WRITE(HBLANK(pipe),
  5208. (adjusted_mode->crtc_hblank_start - 1) |
  5209. ((adjusted_mode->crtc_hblank_end - 1) << 16));
  5210. I915_WRITE(HSYNC(pipe),
  5211. (adjusted_mode->crtc_hsync_start - 1) |
  5212. ((adjusted_mode->crtc_hsync_end - 1) << 16));
  5213. I915_WRITE(VTOTAL(pipe),
  5214. (adjusted_mode->crtc_vdisplay - 1) |
  5215. ((adjusted_mode->crtc_vtotal - 1) << 16));
  5216. I915_WRITE(VBLANK(pipe),
  5217. (adjusted_mode->crtc_vblank_start - 1) |
  5218. ((adjusted_mode->crtc_vblank_end - 1) << 16));
  5219. I915_WRITE(VSYNC(pipe),
  5220. (adjusted_mode->crtc_vsync_start - 1) |
  5221. ((adjusted_mode->crtc_vsync_end - 1) << 16));
  5222. /* pipesrc controls the size that is scaled from, which should
  5223. * always be the user's requested size.
  5224. */
  5225. I915_WRITE(PIPESRC(pipe),
  5226. ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
  5227. I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
  5228. I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
  5229. I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
  5230. I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
  5231. if (has_edp_encoder &&
  5232. !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
  5233. ironlake_set_pll_edp(crtc, adjusted_mode->clock);
  5234. }
  5235. I915_WRITE(PIPECONF(pipe), pipeconf);
  5236. POSTING_READ(PIPECONF(pipe));
  5237. intel_wait_for_vblank(dev, pipe);
  5238. I915_WRITE(DSPCNTR(plane), dspcntr);
  5239. POSTING_READ(DSPCNTR(plane));
  5240. ret = intel_pipe_set_base(crtc, x, y, old_fb);
  5241. intel_update_watermarks(dev);
  5242. return ret;
  5243. }
  5244. static int intel_crtc_mode_set(struct drm_crtc *crtc,
  5245. struct drm_display_mode *mode,
  5246. struct drm_display_mode *adjusted_mode,
  5247. int x, int y,
  5248. struct drm_framebuffer *old_fb)
  5249. {
  5250. struct drm_device *dev = crtc->dev;
  5251. struct drm_i915_private *dev_priv = dev->dev_private;
  5252. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5253. int pipe = intel_crtc->pipe;
  5254. int ret;
  5255. drm_vblank_pre_modeset(dev, pipe);
  5256. ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
  5257. x, y, old_fb);
  5258. drm_vblank_post_modeset(dev, pipe);
  5259. if (ret)
  5260. intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
  5261. else
  5262. intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
  5263. return ret;
  5264. }
  5265. static bool intel_eld_uptodate(struct drm_connector *connector,
  5266. int reg_eldv, uint32_t bits_eldv,
  5267. int reg_elda, uint32_t bits_elda,
  5268. int reg_edid)
  5269. {
  5270. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5271. uint8_t *eld = connector->eld;
  5272. uint32_t i;
  5273. i = I915_READ(reg_eldv);
  5274. i &= bits_eldv;
  5275. if (!eld[0])
  5276. return !i;
  5277. if (!i)
  5278. return false;
  5279. i = I915_READ(reg_elda);
  5280. i &= ~bits_elda;
  5281. I915_WRITE(reg_elda, i);
  5282. for (i = 0; i < eld[2]; i++)
  5283. if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
  5284. return false;
  5285. return true;
  5286. }
  5287. static void g4x_write_eld(struct drm_connector *connector,
  5288. struct drm_crtc *crtc)
  5289. {
  5290. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5291. uint8_t *eld = connector->eld;
  5292. uint32_t eldv;
  5293. uint32_t len;
  5294. uint32_t i;
  5295. i = I915_READ(G4X_AUD_VID_DID);
  5296. if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
  5297. eldv = G4X_ELDV_DEVCL_DEVBLC;
  5298. else
  5299. eldv = G4X_ELDV_DEVCTG;
  5300. if (intel_eld_uptodate(connector,
  5301. G4X_AUD_CNTL_ST, eldv,
  5302. G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
  5303. G4X_HDMIW_HDMIEDID))
  5304. return;
  5305. i = I915_READ(G4X_AUD_CNTL_ST);
  5306. i &= ~(eldv | G4X_ELD_ADDR);
  5307. len = (i >> 9) & 0x1f; /* ELD buffer size */
  5308. I915_WRITE(G4X_AUD_CNTL_ST, i);
  5309. if (!eld[0])
  5310. return;
  5311. len = min_t(uint8_t, eld[2], len);
  5312. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5313. for (i = 0; i < len; i++)
  5314. I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
  5315. i = I915_READ(G4X_AUD_CNTL_ST);
  5316. i |= eldv;
  5317. I915_WRITE(G4X_AUD_CNTL_ST, i);
  5318. }
  5319. static void ironlake_write_eld(struct drm_connector *connector,
  5320. struct drm_crtc *crtc)
  5321. {
  5322. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  5323. uint8_t *eld = connector->eld;
  5324. uint32_t eldv;
  5325. uint32_t i;
  5326. int len;
  5327. int hdmiw_hdmiedid;
  5328. int aud_config;
  5329. int aud_cntl_st;
  5330. int aud_cntrl_st2;
  5331. if (HAS_PCH_IBX(connector->dev)) {
  5332. hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
  5333. aud_config = IBX_AUD_CONFIG_A;
  5334. aud_cntl_st = IBX_AUD_CNTL_ST_A;
  5335. aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
  5336. } else {
  5337. hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
  5338. aud_config = CPT_AUD_CONFIG_A;
  5339. aud_cntl_st = CPT_AUD_CNTL_ST_A;
  5340. aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
  5341. }
  5342. i = to_intel_crtc(crtc)->pipe;
  5343. hdmiw_hdmiedid += i * 0x100;
  5344. aud_cntl_st += i * 0x100;
  5345. aud_config += i * 0x100;
  5346. DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
  5347. i = I915_READ(aud_cntl_st);
  5348. i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
  5349. if (!i) {
  5350. DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
  5351. /* operate blindly on all ports */
  5352. eldv = IBX_ELD_VALIDB;
  5353. eldv |= IBX_ELD_VALIDB << 4;
  5354. eldv |= IBX_ELD_VALIDB << 8;
  5355. } else {
  5356. DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
  5357. eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
  5358. }
  5359. if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
  5360. DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
  5361. eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
  5362. I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
  5363. } else
  5364. I915_WRITE(aud_config, 0);
  5365. if (intel_eld_uptodate(connector,
  5366. aud_cntrl_st2, eldv,
  5367. aud_cntl_st, IBX_ELD_ADDRESS,
  5368. hdmiw_hdmiedid))
  5369. return;
  5370. i = I915_READ(aud_cntrl_st2);
  5371. i &= ~eldv;
  5372. I915_WRITE(aud_cntrl_st2, i);
  5373. if (!eld[0])
  5374. return;
  5375. i = I915_READ(aud_cntl_st);
  5376. i &= ~IBX_ELD_ADDRESS;
  5377. I915_WRITE(aud_cntl_st, i);
  5378. len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
  5379. DRM_DEBUG_DRIVER("ELD size %d\n", len);
  5380. for (i = 0; i < len; i++)
  5381. I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
  5382. i = I915_READ(aud_cntrl_st2);
  5383. i |= eldv;
  5384. I915_WRITE(aud_cntrl_st2, i);
  5385. }
  5386. void intel_write_eld(struct drm_encoder *encoder,
  5387. struct drm_display_mode *mode)
  5388. {
  5389. struct drm_crtc *crtc = encoder->crtc;
  5390. struct drm_connector *connector;
  5391. struct drm_device *dev = encoder->dev;
  5392. struct drm_i915_private *dev_priv = dev->dev_private;
  5393. connector = drm_select_eld(encoder, mode);
  5394. if (!connector)
  5395. return;
  5396. DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5397. connector->base.id,
  5398. drm_get_connector_name(connector),
  5399. connector->encoder->base.id,
  5400. drm_get_encoder_name(connector->encoder));
  5401. connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
  5402. if (dev_priv->display.write_eld)
  5403. dev_priv->display.write_eld(connector, crtc);
  5404. }
  5405. /** Loads the palette/gamma unit for the CRTC with the prepared values */
  5406. void intel_crtc_load_lut(struct drm_crtc *crtc)
  5407. {
  5408. struct drm_device *dev = crtc->dev;
  5409. struct drm_i915_private *dev_priv = dev->dev_private;
  5410. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5411. int palreg = PALETTE(intel_crtc->pipe);
  5412. int i;
  5413. /* The clocks have to be on to load the palette. */
  5414. if (!crtc->enabled)
  5415. return;
  5416. /* use legacy palette for Ironlake */
  5417. if (HAS_PCH_SPLIT(dev))
  5418. palreg = LGC_PALETTE(intel_crtc->pipe);
  5419. for (i = 0; i < 256; i++) {
  5420. I915_WRITE(palreg + 4 * i,
  5421. (intel_crtc->lut_r[i] << 16) |
  5422. (intel_crtc->lut_g[i] << 8) |
  5423. intel_crtc->lut_b[i]);
  5424. }
  5425. }
  5426. static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
  5427. {
  5428. struct drm_device *dev = crtc->dev;
  5429. struct drm_i915_private *dev_priv = dev->dev_private;
  5430. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5431. bool visible = base != 0;
  5432. u32 cntl;
  5433. if (intel_crtc->cursor_visible == visible)
  5434. return;
  5435. cntl = I915_READ(_CURACNTR);
  5436. if (visible) {
  5437. /* On these chipsets we can only modify the base whilst
  5438. * the cursor is disabled.
  5439. */
  5440. I915_WRITE(_CURABASE, base);
  5441. cntl &= ~(CURSOR_FORMAT_MASK);
  5442. /* XXX width must be 64, stride 256 => 0x00 << 28 */
  5443. cntl |= CURSOR_ENABLE |
  5444. CURSOR_GAMMA_ENABLE |
  5445. CURSOR_FORMAT_ARGB;
  5446. } else
  5447. cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
  5448. I915_WRITE(_CURACNTR, cntl);
  5449. intel_crtc->cursor_visible = visible;
  5450. }
  5451. static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
  5452. {
  5453. struct drm_device *dev = crtc->dev;
  5454. struct drm_i915_private *dev_priv = dev->dev_private;
  5455. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5456. int pipe = intel_crtc->pipe;
  5457. bool visible = base != 0;
  5458. if (intel_crtc->cursor_visible != visible) {
  5459. uint32_t cntl = I915_READ(CURCNTR(pipe));
  5460. if (base) {
  5461. cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
  5462. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5463. cntl |= pipe << 28; /* Connect to correct pipe */
  5464. } else {
  5465. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5466. cntl |= CURSOR_MODE_DISABLE;
  5467. }
  5468. I915_WRITE(CURCNTR(pipe), cntl);
  5469. intel_crtc->cursor_visible = visible;
  5470. }
  5471. /* and commit changes on next vblank */
  5472. I915_WRITE(CURBASE(pipe), base);
  5473. }
  5474. static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
  5475. {
  5476. struct drm_device *dev = crtc->dev;
  5477. struct drm_i915_private *dev_priv = dev->dev_private;
  5478. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5479. int pipe = intel_crtc->pipe;
  5480. bool visible = base != 0;
  5481. if (intel_crtc->cursor_visible != visible) {
  5482. uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
  5483. if (base) {
  5484. cntl &= ~CURSOR_MODE;
  5485. cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
  5486. } else {
  5487. cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
  5488. cntl |= CURSOR_MODE_DISABLE;
  5489. }
  5490. I915_WRITE(CURCNTR_IVB(pipe), cntl);
  5491. intel_crtc->cursor_visible = visible;
  5492. }
  5493. /* and commit changes on next vblank */
  5494. I915_WRITE(CURBASE_IVB(pipe), base);
  5495. }
  5496. /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
  5497. static void intel_crtc_update_cursor(struct drm_crtc *crtc,
  5498. bool on)
  5499. {
  5500. struct drm_device *dev = crtc->dev;
  5501. struct drm_i915_private *dev_priv = dev->dev_private;
  5502. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5503. int pipe = intel_crtc->pipe;
  5504. int x = intel_crtc->cursor_x;
  5505. int y = intel_crtc->cursor_y;
  5506. u32 base, pos;
  5507. bool visible;
  5508. pos = 0;
  5509. if (on && crtc->enabled && crtc->fb) {
  5510. base = intel_crtc->cursor_addr;
  5511. if (x > (int) crtc->fb->width)
  5512. base = 0;
  5513. if (y > (int) crtc->fb->height)
  5514. base = 0;
  5515. } else
  5516. base = 0;
  5517. if (x < 0) {
  5518. if (x + intel_crtc->cursor_width < 0)
  5519. base = 0;
  5520. pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
  5521. x = -x;
  5522. }
  5523. pos |= x << CURSOR_X_SHIFT;
  5524. if (y < 0) {
  5525. if (y + intel_crtc->cursor_height < 0)
  5526. base = 0;
  5527. pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
  5528. y = -y;
  5529. }
  5530. pos |= y << CURSOR_Y_SHIFT;
  5531. visible = base != 0;
  5532. if (!visible && !intel_crtc->cursor_visible)
  5533. return;
  5534. if (IS_IVYBRIDGE(dev)) {
  5535. I915_WRITE(CURPOS_IVB(pipe), pos);
  5536. ivb_update_cursor(crtc, base);
  5537. } else {
  5538. I915_WRITE(CURPOS(pipe), pos);
  5539. if (IS_845G(dev) || IS_I865G(dev))
  5540. i845_update_cursor(crtc, base);
  5541. else
  5542. i9xx_update_cursor(crtc, base);
  5543. }
  5544. if (visible)
  5545. intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
  5546. }
  5547. static int intel_crtc_cursor_set(struct drm_crtc *crtc,
  5548. struct drm_file *file,
  5549. uint32_t handle,
  5550. uint32_t width, uint32_t height)
  5551. {
  5552. struct drm_device *dev = crtc->dev;
  5553. struct drm_i915_private *dev_priv = dev->dev_private;
  5554. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5555. struct drm_i915_gem_object *obj;
  5556. uint32_t addr;
  5557. int ret;
  5558. DRM_DEBUG_KMS("\n");
  5559. /* if we want to turn off the cursor ignore width and height */
  5560. if (!handle) {
  5561. DRM_DEBUG_KMS("cursor off\n");
  5562. addr = 0;
  5563. obj = NULL;
  5564. mutex_lock(&dev->struct_mutex);
  5565. goto finish;
  5566. }
  5567. /* Currently we only support 64x64 cursors */
  5568. if (width != 64 || height != 64) {
  5569. DRM_ERROR("we currently only support 64x64 cursors\n");
  5570. return -EINVAL;
  5571. }
  5572. obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
  5573. if (&obj->base == NULL)
  5574. return -ENOENT;
  5575. if (obj->base.size < width * height * 4) {
  5576. DRM_ERROR("buffer is to small\n");
  5577. ret = -ENOMEM;
  5578. goto fail;
  5579. }
  5580. /* we only need to pin inside GTT if cursor is non-phy */
  5581. mutex_lock(&dev->struct_mutex);
  5582. if (!dev_priv->info->cursor_needs_physical) {
  5583. if (obj->tiling_mode) {
  5584. DRM_ERROR("cursor cannot be tiled\n");
  5585. ret = -EINVAL;
  5586. goto fail_locked;
  5587. }
  5588. ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
  5589. if (ret) {
  5590. DRM_ERROR("failed to move cursor bo into the GTT\n");
  5591. goto fail_locked;
  5592. }
  5593. ret = i915_gem_object_put_fence(obj);
  5594. if (ret) {
  5595. DRM_ERROR("failed to release fence for cursor");
  5596. goto fail_unpin;
  5597. }
  5598. addr = obj->gtt_offset;
  5599. } else {
  5600. int align = IS_I830(dev) ? 16 * 1024 : 256;
  5601. ret = i915_gem_attach_phys_object(dev, obj,
  5602. (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
  5603. align);
  5604. if (ret) {
  5605. DRM_ERROR("failed to attach phys object\n");
  5606. goto fail_locked;
  5607. }
  5608. addr = obj->phys_obj->handle->busaddr;
  5609. }
  5610. if (IS_GEN2(dev))
  5611. I915_WRITE(CURSIZE, (height << 12) | width);
  5612. finish:
  5613. if (intel_crtc->cursor_bo) {
  5614. if (dev_priv->info->cursor_needs_physical) {
  5615. if (intel_crtc->cursor_bo != obj)
  5616. i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
  5617. } else
  5618. i915_gem_object_unpin(intel_crtc->cursor_bo);
  5619. drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
  5620. }
  5621. mutex_unlock(&dev->struct_mutex);
  5622. intel_crtc->cursor_addr = addr;
  5623. intel_crtc->cursor_bo = obj;
  5624. intel_crtc->cursor_width = width;
  5625. intel_crtc->cursor_height = height;
  5626. intel_crtc_update_cursor(crtc, true);
  5627. return 0;
  5628. fail_unpin:
  5629. i915_gem_object_unpin(obj);
  5630. fail_locked:
  5631. mutex_unlock(&dev->struct_mutex);
  5632. fail:
  5633. drm_gem_object_unreference_unlocked(&obj->base);
  5634. return ret;
  5635. }
  5636. static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  5637. {
  5638. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5639. intel_crtc->cursor_x = x;
  5640. intel_crtc->cursor_y = y;
  5641. intel_crtc_update_cursor(crtc, true);
  5642. return 0;
  5643. }
  5644. /** Sets the color ramps on behalf of RandR */
  5645. void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  5646. u16 blue, int regno)
  5647. {
  5648. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5649. intel_crtc->lut_r[regno] = red >> 8;
  5650. intel_crtc->lut_g[regno] = green >> 8;
  5651. intel_crtc->lut_b[regno] = blue >> 8;
  5652. }
  5653. void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  5654. u16 *blue, int regno)
  5655. {
  5656. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5657. *red = intel_crtc->lut_r[regno] << 8;
  5658. *green = intel_crtc->lut_g[regno] << 8;
  5659. *blue = intel_crtc->lut_b[regno] << 8;
  5660. }
  5661. static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  5662. u16 *blue, uint32_t start, uint32_t size)
  5663. {
  5664. int end = (start + size > 256) ? 256 : start + size, i;
  5665. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5666. for (i = start; i < end; i++) {
  5667. intel_crtc->lut_r[i] = red[i] >> 8;
  5668. intel_crtc->lut_g[i] = green[i] >> 8;
  5669. intel_crtc->lut_b[i] = blue[i] >> 8;
  5670. }
  5671. intel_crtc_load_lut(crtc);
  5672. }
  5673. /**
  5674. * Get a pipe with a simple mode set on it for doing load-based monitor
  5675. * detection.
  5676. *
  5677. * It will be up to the load-detect code to adjust the pipe as appropriate for
  5678. * its requirements. The pipe will be connected to no other encoders.
  5679. *
  5680. * Currently this code will only succeed if there is a pipe with no encoders
  5681. * configured for it. In the future, it could choose to temporarily disable
  5682. * some outputs to free up a pipe for its use.
  5683. *
  5684. * \return crtc, or NULL if no pipes are available.
  5685. */
  5686. /* VESA 640x480x72Hz mode to set on the pipe */
  5687. static struct drm_display_mode load_detect_mode = {
  5688. DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
  5689. 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
  5690. };
  5691. static struct drm_framebuffer *
  5692. intel_framebuffer_create(struct drm_device *dev,
  5693. struct drm_mode_fb_cmd2 *mode_cmd,
  5694. struct drm_i915_gem_object *obj)
  5695. {
  5696. struct intel_framebuffer *intel_fb;
  5697. int ret;
  5698. intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
  5699. if (!intel_fb) {
  5700. drm_gem_object_unreference_unlocked(&obj->base);
  5701. return ERR_PTR(-ENOMEM);
  5702. }
  5703. ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
  5704. if (ret) {
  5705. drm_gem_object_unreference_unlocked(&obj->base);
  5706. kfree(intel_fb);
  5707. return ERR_PTR(ret);
  5708. }
  5709. return &intel_fb->base;
  5710. }
  5711. static u32
  5712. intel_framebuffer_pitch_for_width(int width, int bpp)
  5713. {
  5714. u32 pitch = DIV_ROUND_UP(width * bpp, 8);
  5715. return ALIGN(pitch, 64);
  5716. }
  5717. static u32
  5718. intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
  5719. {
  5720. u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
  5721. return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
  5722. }
  5723. static struct drm_framebuffer *
  5724. intel_framebuffer_create_for_mode(struct drm_device *dev,
  5725. struct drm_display_mode *mode,
  5726. int depth, int bpp)
  5727. {
  5728. struct drm_i915_gem_object *obj;
  5729. struct drm_mode_fb_cmd2 mode_cmd;
  5730. obj = i915_gem_alloc_object(dev,
  5731. intel_framebuffer_size_for_mode(mode, bpp));
  5732. if (obj == NULL)
  5733. return ERR_PTR(-ENOMEM);
  5734. mode_cmd.width = mode->hdisplay;
  5735. mode_cmd.height = mode->vdisplay;
  5736. mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
  5737. bpp);
  5738. mode_cmd.pixel_format = 0;
  5739. return intel_framebuffer_create(dev, &mode_cmd, obj);
  5740. }
  5741. static struct drm_framebuffer *
  5742. mode_fits_in_fbdev(struct drm_device *dev,
  5743. struct drm_display_mode *mode)
  5744. {
  5745. struct drm_i915_private *dev_priv = dev->dev_private;
  5746. struct drm_i915_gem_object *obj;
  5747. struct drm_framebuffer *fb;
  5748. if (dev_priv->fbdev == NULL)
  5749. return NULL;
  5750. obj = dev_priv->fbdev->ifb.obj;
  5751. if (obj == NULL)
  5752. return NULL;
  5753. fb = &dev_priv->fbdev->ifb.base;
  5754. if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
  5755. fb->bits_per_pixel))
  5756. return NULL;
  5757. if (obj->base.size < mode->vdisplay * fb->pitches[0])
  5758. return NULL;
  5759. return fb;
  5760. }
  5761. bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
  5762. struct drm_connector *connector,
  5763. struct drm_display_mode *mode,
  5764. struct intel_load_detect_pipe *old)
  5765. {
  5766. struct intel_crtc *intel_crtc;
  5767. struct drm_crtc *possible_crtc;
  5768. struct drm_encoder *encoder = &intel_encoder->base;
  5769. struct drm_crtc *crtc = NULL;
  5770. struct drm_device *dev = encoder->dev;
  5771. struct drm_framebuffer *old_fb;
  5772. int i = -1;
  5773. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5774. connector->base.id, drm_get_connector_name(connector),
  5775. encoder->base.id, drm_get_encoder_name(encoder));
  5776. /*
  5777. * Algorithm gets a little messy:
  5778. *
  5779. * - if the connector already has an assigned crtc, use it (but make
  5780. * sure it's on first)
  5781. *
  5782. * - try to find the first unused crtc that can drive this connector,
  5783. * and use that if we find one
  5784. */
  5785. /* See if we already have a CRTC for this connector */
  5786. if (encoder->crtc) {
  5787. crtc = encoder->crtc;
  5788. intel_crtc = to_intel_crtc(crtc);
  5789. old->dpms_mode = intel_crtc->dpms_mode;
  5790. old->load_detect_temp = false;
  5791. /* Make sure the crtc and connector are running */
  5792. if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
  5793. struct drm_encoder_helper_funcs *encoder_funcs;
  5794. struct drm_crtc_helper_funcs *crtc_funcs;
  5795. crtc_funcs = crtc->helper_private;
  5796. crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
  5797. encoder_funcs = encoder->helper_private;
  5798. encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
  5799. }
  5800. return true;
  5801. }
  5802. /* Find an unused one (if possible) */
  5803. list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
  5804. i++;
  5805. if (!(encoder->possible_crtcs & (1 << i)))
  5806. continue;
  5807. if (!possible_crtc->enabled) {
  5808. crtc = possible_crtc;
  5809. break;
  5810. }
  5811. }
  5812. /*
  5813. * If we didn't find an unused CRTC, don't use any.
  5814. */
  5815. if (!crtc) {
  5816. DRM_DEBUG_KMS("no pipe available for load-detect\n");
  5817. return false;
  5818. }
  5819. encoder->crtc = crtc;
  5820. connector->encoder = encoder;
  5821. intel_crtc = to_intel_crtc(crtc);
  5822. old->dpms_mode = intel_crtc->dpms_mode;
  5823. old->load_detect_temp = true;
  5824. old->release_fb = NULL;
  5825. if (!mode)
  5826. mode = &load_detect_mode;
  5827. old_fb = crtc->fb;
  5828. /* We need a framebuffer large enough to accommodate all accesses
  5829. * that the plane may generate whilst we perform load detection.
  5830. * We can not rely on the fbcon either being present (we get called
  5831. * during its initialisation to detect all boot displays, or it may
  5832. * not even exist) or that it is large enough to satisfy the
  5833. * requested mode.
  5834. */
  5835. crtc->fb = mode_fits_in_fbdev(dev, mode);
  5836. if (crtc->fb == NULL) {
  5837. DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
  5838. crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
  5839. old->release_fb = crtc->fb;
  5840. } else
  5841. DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
  5842. if (IS_ERR(crtc->fb)) {
  5843. DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
  5844. crtc->fb = old_fb;
  5845. return false;
  5846. }
  5847. if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
  5848. DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
  5849. if (old->release_fb)
  5850. old->release_fb->funcs->destroy(old->release_fb);
  5851. crtc->fb = old_fb;
  5852. return false;
  5853. }
  5854. /* let the connector get through one full cycle before testing */
  5855. intel_wait_for_vblank(dev, intel_crtc->pipe);
  5856. return true;
  5857. }
  5858. void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
  5859. struct drm_connector *connector,
  5860. struct intel_load_detect_pipe *old)
  5861. {
  5862. struct drm_encoder *encoder = &intel_encoder->base;
  5863. struct drm_device *dev = encoder->dev;
  5864. struct drm_crtc *crtc = encoder->crtc;
  5865. struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
  5866. struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
  5867. DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
  5868. connector->base.id, drm_get_connector_name(connector),
  5869. encoder->base.id, drm_get_encoder_name(encoder));
  5870. if (old->load_detect_temp) {
  5871. connector->encoder = NULL;
  5872. drm_helper_disable_unused_functions(dev);
  5873. if (old->release_fb)
  5874. old->release_fb->funcs->destroy(old->release_fb);
  5875. return;
  5876. }
  5877. /* Switch crtc and encoder back off if necessary */
  5878. if (old->dpms_mode != DRM_MODE_DPMS_ON) {
  5879. encoder_funcs->dpms(encoder, old->dpms_mode);
  5880. crtc_funcs->dpms(crtc, old->dpms_mode);
  5881. }
  5882. }
  5883. /* Returns the clock of the currently programmed mode of the given pipe. */
  5884. static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
  5885. {
  5886. struct drm_i915_private *dev_priv = dev->dev_private;
  5887. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5888. int pipe = intel_crtc->pipe;
  5889. u32 dpll = I915_READ(DPLL(pipe));
  5890. u32 fp;
  5891. intel_clock_t clock;
  5892. if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
  5893. fp = I915_READ(FP0(pipe));
  5894. else
  5895. fp = I915_READ(FP1(pipe));
  5896. clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
  5897. if (IS_PINEVIEW(dev)) {
  5898. clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
  5899. clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5900. } else {
  5901. clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
  5902. clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
  5903. }
  5904. if (!IS_GEN2(dev)) {
  5905. if (IS_PINEVIEW(dev))
  5906. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
  5907. DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
  5908. else
  5909. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
  5910. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5911. switch (dpll & DPLL_MODE_MASK) {
  5912. case DPLLB_MODE_DAC_SERIAL:
  5913. clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
  5914. 5 : 10;
  5915. break;
  5916. case DPLLB_MODE_LVDS:
  5917. clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
  5918. 7 : 14;
  5919. break;
  5920. default:
  5921. DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
  5922. "mode\n", (int)(dpll & DPLL_MODE_MASK));
  5923. return 0;
  5924. }
  5925. /* XXX: Handle the 100Mhz refclk */
  5926. intel_clock(dev, 96000, &clock);
  5927. } else {
  5928. bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
  5929. if (is_lvds) {
  5930. clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
  5931. DPLL_FPA01_P1_POST_DIV_SHIFT);
  5932. clock.p2 = 14;
  5933. if ((dpll & PLL_REF_INPUT_MASK) ==
  5934. PLLB_REF_INPUT_SPREADSPECTRUMIN) {
  5935. /* XXX: might not be 66MHz */
  5936. intel_clock(dev, 66000, &clock);
  5937. } else
  5938. intel_clock(dev, 48000, &clock);
  5939. } else {
  5940. if (dpll & PLL_P1_DIVIDE_BY_TWO)
  5941. clock.p1 = 2;
  5942. else {
  5943. clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
  5944. DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
  5945. }
  5946. if (dpll & PLL_P2_DIVIDE_BY_4)
  5947. clock.p2 = 4;
  5948. else
  5949. clock.p2 = 2;
  5950. intel_clock(dev, 48000, &clock);
  5951. }
  5952. }
  5953. /* XXX: It would be nice to validate the clocks, but we can't reuse
  5954. * i830PllIsValid() because it relies on the xf86_config connector
  5955. * configuration being accurate, which it isn't necessarily.
  5956. */
  5957. return clock.dot;
  5958. }
  5959. /** Returns the currently programmed mode of the given pipe. */
  5960. struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
  5961. struct drm_crtc *crtc)
  5962. {
  5963. struct drm_i915_private *dev_priv = dev->dev_private;
  5964. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  5965. int pipe = intel_crtc->pipe;
  5966. struct drm_display_mode *mode;
  5967. int htot = I915_READ(HTOTAL(pipe));
  5968. int hsync = I915_READ(HSYNC(pipe));
  5969. int vtot = I915_READ(VTOTAL(pipe));
  5970. int vsync = I915_READ(VSYNC(pipe));
  5971. mode = kzalloc(sizeof(*mode), GFP_KERNEL);
  5972. if (!mode)
  5973. return NULL;
  5974. mode->clock = intel_crtc_clock_get(dev, crtc);
  5975. mode->hdisplay = (htot & 0xffff) + 1;
  5976. mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
  5977. mode->hsync_start = (hsync & 0xffff) + 1;
  5978. mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
  5979. mode->vdisplay = (vtot & 0xffff) + 1;
  5980. mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
  5981. mode->vsync_start = (vsync & 0xffff) + 1;
  5982. mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
  5983. drm_mode_set_name(mode);
  5984. drm_mode_set_crtcinfo(mode, 0);
  5985. return mode;
  5986. }
  5987. #define GPU_IDLE_TIMEOUT 500 /* ms */
  5988. /* When this timer fires, we've been idle for awhile */
  5989. static void intel_gpu_idle_timer(unsigned long arg)
  5990. {
  5991. struct drm_device *dev = (struct drm_device *)arg;
  5992. drm_i915_private_t *dev_priv = dev->dev_private;
  5993. if (!list_empty(&dev_priv->mm.active_list)) {
  5994. /* Still processing requests, so just re-arm the timer. */
  5995. mod_timer(&dev_priv->idle_timer, jiffies +
  5996. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  5997. return;
  5998. }
  5999. dev_priv->busy = false;
  6000. queue_work(dev_priv->wq, &dev_priv->idle_work);
  6001. }
  6002. #define CRTC_IDLE_TIMEOUT 1000 /* ms */
  6003. static void intel_crtc_idle_timer(unsigned long arg)
  6004. {
  6005. struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
  6006. struct drm_crtc *crtc = &intel_crtc->base;
  6007. drm_i915_private_t *dev_priv = crtc->dev->dev_private;
  6008. struct intel_framebuffer *intel_fb;
  6009. intel_fb = to_intel_framebuffer(crtc->fb);
  6010. if (intel_fb && intel_fb->obj->active) {
  6011. /* The framebuffer is still being accessed by the GPU. */
  6012. mod_timer(&intel_crtc->idle_timer, jiffies +
  6013. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  6014. return;
  6015. }
  6016. intel_crtc->busy = false;
  6017. queue_work(dev_priv->wq, &dev_priv->idle_work);
  6018. }
  6019. static void intel_increase_pllclock(struct drm_crtc *crtc)
  6020. {
  6021. struct drm_device *dev = crtc->dev;
  6022. drm_i915_private_t *dev_priv = dev->dev_private;
  6023. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6024. int pipe = intel_crtc->pipe;
  6025. int dpll_reg = DPLL(pipe);
  6026. int dpll;
  6027. if (HAS_PCH_SPLIT(dev))
  6028. return;
  6029. if (!dev_priv->lvds_downclock_avail)
  6030. return;
  6031. dpll = I915_READ(dpll_reg);
  6032. if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
  6033. DRM_DEBUG_DRIVER("upclocking LVDS\n");
  6034. /* Unlock panel regs */
  6035. I915_WRITE(PP_CONTROL,
  6036. I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
  6037. dpll &= ~DISPLAY_RATE_SELECT_FPA1;
  6038. I915_WRITE(dpll_reg, dpll);
  6039. intel_wait_for_vblank(dev, pipe);
  6040. dpll = I915_READ(dpll_reg);
  6041. if (dpll & DISPLAY_RATE_SELECT_FPA1)
  6042. DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
  6043. /* ...and lock them again */
  6044. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  6045. }
  6046. /* Schedule downclock */
  6047. mod_timer(&intel_crtc->idle_timer, jiffies +
  6048. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  6049. }
  6050. static void intel_decrease_pllclock(struct drm_crtc *crtc)
  6051. {
  6052. struct drm_device *dev = crtc->dev;
  6053. drm_i915_private_t *dev_priv = dev->dev_private;
  6054. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6055. int pipe = intel_crtc->pipe;
  6056. int dpll_reg = DPLL(pipe);
  6057. int dpll = I915_READ(dpll_reg);
  6058. if (HAS_PCH_SPLIT(dev))
  6059. return;
  6060. if (!dev_priv->lvds_downclock_avail)
  6061. return;
  6062. /*
  6063. * Since this is called by a timer, we should never get here in
  6064. * the manual case.
  6065. */
  6066. if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
  6067. DRM_DEBUG_DRIVER("downclocking LVDS\n");
  6068. /* Unlock panel regs */
  6069. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
  6070. PANEL_UNLOCK_REGS);
  6071. dpll |= DISPLAY_RATE_SELECT_FPA1;
  6072. I915_WRITE(dpll_reg, dpll);
  6073. intel_wait_for_vblank(dev, pipe);
  6074. dpll = I915_READ(dpll_reg);
  6075. if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
  6076. DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
  6077. /* ...and lock them again */
  6078. I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
  6079. }
  6080. }
  6081. /**
  6082. * intel_idle_update - adjust clocks for idleness
  6083. * @work: work struct
  6084. *
  6085. * Either the GPU or display (or both) went idle. Check the busy status
  6086. * here and adjust the CRTC and GPU clocks as necessary.
  6087. */
  6088. static void intel_idle_update(struct work_struct *work)
  6089. {
  6090. drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
  6091. idle_work);
  6092. struct drm_device *dev = dev_priv->dev;
  6093. struct drm_crtc *crtc;
  6094. struct intel_crtc *intel_crtc;
  6095. if (!i915_powersave)
  6096. return;
  6097. mutex_lock(&dev->struct_mutex);
  6098. i915_update_gfx_val(dev_priv);
  6099. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6100. /* Skip inactive CRTCs */
  6101. if (!crtc->fb)
  6102. continue;
  6103. intel_crtc = to_intel_crtc(crtc);
  6104. if (!intel_crtc->busy)
  6105. intel_decrease_pllclock(crtc);
  6106. }
  6107. mutex_unlock(&dev->struct_mutex);
  6108. }
  6109. /**
  6110. * intel_mark_busy - mark the GPU and possibly the display busy
  6111. * @dev: drm device
  6112. * @obj: object we're operating on
  6113. *
  6114. * Callers can use this function to indicate that the GPU is busy processing
  6115. * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
  6116. * buffer), we'll also mark the display as busy, so we know to increase its
  6117. * clock frequency.
  6118. */
  6119. void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
  6120. {
  6121. drm_i915_private_t *dev_priv = dev->dev_private;
  6122. struct drm_crtc *crtc = NULL;
  6123. struct intel_framebuffer *intel_fb;
  6124. struct intel_crtc *intel_crtc;
  6125. if (!drm_core_check_feature(dev, DRIVER_MODESET))
  6126. return;
  6127. if (!dev_priv->busy)
  6128. dev_priv->busy = true;
  6129. else
  6130. mod_timer(&dev_priv->idle_timer, jiffies +
  6131. msecs_to_jiffies(GPU_IDLE_TIMEOUT));
  6132. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  6133. if (!crtc->fb)
  6134. continue;
  6135. intel_crtc = to_intel_crtc(crtc);
  6136. intel_fb = to_intel_framebuffer(crtc->fb);
  6137. if (intel_fb->obj == obj) {
  6138. if (!intel_crtc->busy) {
  6139. /* Non-busy -> busy, upclock */
  6140. intel_increase_pllclock(crtc);
  6141. intel_crtc->busy = true;
  6142. } else {
  6143. /* Busy -> busy, put off timer */
  6144. mod_timer(&intel_crtc->idle_timer, jiffies +
  6145. msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
  6146. }
  6147. }
  6148. }
  6149. }
  6150. static void intel_crtc_destroy(struct drm_crtc *crtc)
  6151. {
  6152. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6153. struct drm_device *dev = crtc->dev;
  6154. struct intel_unpin_work *work;
  6155. unsigned long flags;
  6156. spin_lock_irqsave(&dev->event_lock, flags);
  6157. work = intel_crtc->unpin_work;
  6158. intel_crtc->unpin_work = NULL;
  6159. spin_unlock_irqrestore(&dev->event_lock, flags);
  6160. if (work) {
  6161. cancel_work_sync(&work->work);
  6162. kfree(work);
  6163. }
  6164. drm_crtc_cleanup(crtc);
  6165. kfree(intel_crtc);
  6166. }
  6167. static void intel_unpin_work_fn(struct work_struct *__work)
  6168. {
  6169. struct intel_unpin_work *work =
  6170. container_of(__work, struct intel_unpin_work, work);
  6171. mutex_lock(&work->dev->struct_mutex);
  6172. intel_unpin_fb_obj(work->old_fb_obj);
  6173. drm_gem_object_unreference(&work->pending_flip_obj->base);
  6174. drm_gem_object_unreference(&work->old_fb_obj->base);
  6175. intel_update_fbc(work->dev);
  6176. mutex_unlock(&work->dev->struct_mutex);
  6177. kfree(work);
  6178. }
  6179. static void do_intel_finish_page_flip(struct drm_device *dev,
  6180. struct drm_crtc *crtc)
  6181. {
  6182. drm_i915_private_t *dev_priv = dev->dev_private;
  6183. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6184. struct intel_unpin_work *work;
  6185. struct drm_i915_gem_object *obj;
  6186. struct drm_pending_vblank_event *e;
  6187. struct timeval tnow, tvbl;
  6188. unsigned long flags;
  6189. /* Ignore early vblank irqs */
  6190. if (intel_crtc == NULL)
  6191. return;
  6192. do_gettimeofday(&tnow);
  6193. spin_lock_irqsave(&dev->event_lock, flags);
  6194. work = intel_crtc->unpin_work;
  6195. if (work == NULL || !work->pending) {
  6196. spin_unlock_irqrestore(&dev->event_lock, flags);
  6197. return;
  6198. }
  6199. intel_crtc->unpin_work = NULL;
  6200. if (work->event) {
  6201. e = work->event;
  6202. e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
  6203. /* Called before vblank count and timestamps have
  6204. * been updated for the vblank interval of flip
  6205. * completion? Need to increment vblank count and
  6206. * add one videorefresh duration to returned timestamp
  6207. * to account for this. We assume this happened if we
  6208. * get called over 0.9 frame durations after the last
  6209. * timestamped vblank.
  6210. *
  6211. * This calculation can not be used with vrefresh rates
  6212. * below 5Hz (10Hz to be on the safe side) without
  6213. * promoting to 64 integers.
  6214. */
  6215. if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
  6216. 9 * crtc->framedur_ns) {
  6217. e->event.sequence++;
  6218. tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
  6219. crtc->framedur_ns);
  6220. }
  6221. e->event.tv_sec = tvbl.tv_sec;
  6222. e->event.tv_usec = tvbl.tv_usec;
  6223. list_add_tail(&e->base.link,
  6224. &e->base.file_priv->event_list);
  6225. wake_up_interruptible(&e->base.file_priv->event_wait);
  6226. }
  6227. drm_vblank_put(dev, intel_crtc->pipe);
  6228. spin_unlock_irqrestore(&dev->event_lock, flags);
  6229. obj = work->old_fb_obj;
  6230. atomic_clear_mask(1 << intel_crtc->plane,
  6231. &obj->pending_flip.counter);
  6232. if (atomic_read(&obj->pending_flip) == 0)
  6233. wake_up(&dev_priv->pending_flip_queue);
  6234. schedule_work(&work->work);
  6235. trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
  6236. }
  6237. void intel_finish_page_flip(struct drm_device *dev, int pipe)
  6238. {
  6239. drm_i915_private_t *dev_priv = dev->dev_private;
  6240. struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
  6241. do_intel_finish_page_flip(dev, crtc);
  6242. }
  6243. void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
  6244. {
  6245. drm_i915_private_t *dev_priv = dev->dev_private;
  6246. struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
  6247. do_intel_finish_page_flip(dev, crtc);
  6248. }
  6249. void intel_prepare_page_flip(struct drm_device *dev, int plane)
  6250. {
  6251. drm_i915_private_t *dev_priv = dev->dev_private;
  6252. struct intel_crtc *intel_crtc =
  6253. to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
  6254. unsigned long flags;
  6255. spin_lock_irqsave(&dev->event_lock, flags);
  6256. if (intel_crtc->unpin_work) {
  6257. if ((++intel_crtc->unpin_work->pending) > 1)
  6258. DRM_ERROR("Prepared flip multiple times\n");
  6259. } else {
  6260. DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
  6261. }
  6262. spin_unlock_irqrestore(&dev->event_lock, flags);
  6263. }
  6264. static int intel_gen2_queue_flip(struct drm_device *dev,
  6265. struct drm_crtc *crtc,
  6266. struct drm_framebuffer *fb,
  6267. struct drm_i915_gem_object *obj)
  6268. {
  6269. struct drm_i915_private *dev_priv = dev->dev_private;
  6270. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6271. unsigned long offset;
  6272. u32 flip_mask;
  6273. int ret;
  6274. ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
  6275. if (ret)
  6276. goto out;
  6277. /* Offset into the new buffer for cases of shared fbs between CRTCs */
  6278. offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
  6279. ret = BEGIN_LP_RING(6);
  6280. if (ret)
  6281. goto out;
  6282. /* Can't queue multiple flips, so wait for the previous
  6283. * one to finish before executing the next.
  6284. */
  6285. if (intel_crtc->plane)
  6286. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  6287. else
  6288. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  6289. OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
  6290. OUT_RING(MI_NOOP);
  6291. OUT_RING(MI_DISPLAY_FLIP |
  6292. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6293. OUT_RING(fb->pitches[0]);
  6294. OUT_RING(obj->gtt_offset + offset);
  6295. OUT_RING(0); /* aux display base address, unused */
  6296. ADVANCE_LP_RING();
  6297. out:
  6298. return ret;
  6299. }
  6300. static int intel_gen3_queue_flip(struct drm_device *dev,
  6301. struct drm_crtc *crtc,
  6302. struct drm_framebuffer *fb,
  6303. struct drm_i915_gem_object *obj)
  6304. {
  6305. struct drm_i915_private *dev_priv = dev->dev_private;
  6306. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6307. unsigned long offset;
  6308. u32 flip_mask;
  6309. int ret;
  6310. ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
  6311. if (ret)
  6312. goto out;
  6313. /* Offset into the new buffer for cases of shared fbs between CRTCs */
  6314. offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
  6315. ret = BEGIN_LP_RING(6);
  6316. if (ret)
  6317. goto out;
  6318. if (intel_crtc->plane)
  6319. flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
  6320. else
  6321. flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
  6322. OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
  6323. OUT_RING(MI_NOOP);
  6324. OUT_RING(MI_DISPLAY_FLIP_I915 |
  6325. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6326. OUT_RING(fb->pitches[0]);
  6327. OUT_RING(obj->gtt_offset + offset);
  6328. OUT_RING(MI_NOOP);
  6329. ADVANCE_LP_RING();
  6330. out:
  6331. return ret;
  6332. }
  6333. static int intel_gen4_queue_flip(struct drm_device *dev,
  6334. struct drm_crtc *crtc,
  6335. struct drm_framebuffer *fb,
  6336. struct drm_i915_gem_object *obj)
  6337. {
  6338. struct drm_i915_private *dev_priv = dev->dev_private;
  6339. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6340. uint32_t pf, pipesrc;
  6341. int ret;
  6342. ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
  6343. if (ret)
  6344. goto out;
  6345. ret = BEGIN_LP_RING(4);
  6346. if (ret)
  6347. goto out;
  6348. /* i965+ uses the linear or tiled offsets from the
  6349. * Display Registers (which do not change across a page-flip)
  6350. * so we need only reprogram the base address.
  6351. */
  6352. OUT_RING(MI_DISPLAY_FLIP |
  6353. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6354. OUT_RING(fb->pitches[0]);
  6355. OUT_RING(obj->gtt_offset | obj->tiling_mode);
  6356. /* XXX Enabling the panel-fitter across page-flip is so far
  6357. * untested on non-native modes, so ignore it for now.
  6358. * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
  6359. */
  6360. pf = 0;
  6361. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  6362. OUT_RING(pf | pipesrc);
  6363. ADVANCE_LP_RING();
  6364. out:
  6365. return ret;
  6366. }
  6367. static int intel_gen6_queue_flip(struct drm_device *dev,
  6368. struct drm_crtc *crtc,
  6369. struct drm_framebuffer *fb,
  6370. struct drm_i915_gem_object *obj)
  6371. {
  6372. struct drm_i915_private *dev_priv = dev->dev_private;
  6373. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6374. uint32_t pf, pipesrc;
  6375. int ret;
  6376. ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
  6377. if (ret)
  6378. goto out;
  6379. ret = BEGIN_LP_RING(4);
  6380. if (ret)
  6381. goto out;
  6382. OUT_RING(MI_DISPLAY_FLIP |
  6383. MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
  6384. OUT_RING(fb->pitches[0] | obj->tiling_mode);
  6385. OUT_RING(obj->gtt_offset);
  6386. pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
  6387. pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
  6388. OUT_RING(pf | pipesrc);
  6389. ADVANCE_LP_RING();
  6390. out:
  6391. return ret;
  6392. }
  6393. /*
  6394. * On gen7 we currently use the blit ring because (in early silicon at least)
  6395. * the render ring doesn't give us interrpts for page flip completion, which
  6396. * means clients will hang after the first flip is queued. Fortunately the
  6397. * blit ring generates interrupts properly, so use it instead.
  6398. */
  6399. static int intel_gen7_queue_flip(struct drm_device *dev,
  6400. struct drm_crtc *crtc,
  6401. struct drm_framebuffer *fb,
  6402. struct drm_i915_gem_object *obj)
  6403. {
  6404. struct drm_i915_private *dev_priv = dev->dev_private;
  6405. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6406. struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
  6407. int ret;
  6408. ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
  6409. if (ret)
  6410. goto out;
  6411. ret = intel_ring_begin(ring, 4);
  6412. if (ret)
  6413. goto out;
  6414. intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
  6415. intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
  6416. intel_ring_emit(ring, (obj->gtt_offset));
  6417. intel_ring_emit(ring, (MI_NOOP));
  6418. intel_ring_advance(ring);
  6419. out:
  6420. return ret;
  6421. }
  6422. static int intel_default_queue_flip(struct drm_device *dev,
  6423. struct drm_crtc *crtc,
  6424. struct drm_framebuffer *fb,
  6425. struct drm_i915_gem_object *obj)
  6426. {
  6427. return -ENODEV;
  6428. }
  6429. static int intel_crtc_page_flip(struct drm_crtc *crtc,
  6430. struct drm_framebuffer *fb,
  6431. struct drm_pending_vblank_event *event)
  6432. {
  6433. struct drm_device *dev = crtc->dev;
  6434. struct drm_i915_private *dev_priv = dev->dev_private;
  6435. struct intel_framebuffer *intel_fb;
  6436. struct drm_i915_gem_object *obj;
  6437. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6438. struct intel_unpin_work *work;
  6439. unsigned long flags;
  6440. int ret;
  6441. work = kzalloc(sizeof *work, GFP_KERNEL);
  6442. if (work == NULL)
  6443. return -ENOMEM;
  6444. work->event = event;
  6445. work->dev = crtc->dev;
  6446. intel_fb = to_intel_framebuffer(crtc->fb);
  6447. work->old_fb_obj = intel_fb->obj;
  6448. INIT_WORK(&work->work, intel_unpin_work_fn);
  6449. ret = drm_vblank_get(dev, intel_crtc->pipe);
  6450. if (ret)
  6451. goto free_work;
  6452. /* We borrow the event spin lock for protecting unpin_work */
  6453. spin_lock_irqsave(&dev->event_lock, flags);
  6454. if (intel_crtc->unpin_work) {
  6455. spin_unlock_irqrestore(&dev->event_lock, flags);
  6456. kfree(work);
  6457. drm_vblank_put(dev, intel_crtc->pipe);
  6458. DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
  6459. return -EBUSY;
  6460. }
  6461. intel_crtc->unpin_work = work;
  6462. spin_unlock_irqrestore(&dev->event_lock, flags);
  6463. intel_fb = to_intel_framebuffer(fb);
  6464. obj = intel_fb->obj;
  6465. mutex_lock(&dev->struct_mutex);
  6466. /* Reference the objects for the scheduled work. */
  6467. drm_gem_object_reference(&work->old_fb_obj->base);
  6468. drm_gem_object_reference(&obj->base);
  6469. crtc->fb = fb;
  6470. work->pending_flip_obj = obj;
  6471. work->enable_stall_check = true;
  6472. /* Block clients from rendering to the new back buffer until
  6473. * the flip occurs and the object is no longer visible.
  6474. */
  6475. atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
  6476. ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
  6477. if (ret)
  6478. goto cleanup_pending;
  6479. intel_disable_fbc(dev);
  6480. mutex_unlock(&dev->struct_mutex);
  6481. trace_i915_flip_request(intel_crtc->plane, obj);
  6482. return 0;
  6483. cleanup_pending:
  6484. atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
  6485. drm_gem_object_unreference(&work->old_fb_obj->base);
  6486. drm_gem_object_unreference(&obj->base);
  6487. mutex_unlock(&dev->struct_mutex);
  6488. spin_lock_irqsave(&dev->event_lock, flags);
  6489. intel_crtc->unpin_work = NULL;
  6490. spin_unlock_irqrestore(&dev->event_lock, flags);
  6491. drm_vblank_put(dev, intel_crtc->pipe);
  6492. free_work:
  6493. kfree(work);
  6494. return ret;
  6495. }
  6496. static void intel_sanitize_modesetting(struct drm_device *dev,
  6497. int pipe, int plane)
  6498. {
  6499. struct drm_i915_private *dev_priv = dev->dev_private;
  6500. u32 reg, val;
  6501. if (HAS_PCH_SPLIT(dev))
  6502. return;
  6503. /* Who knows what state these registers were left in by the BIOS or
  6504. * grub?
  6505. *
  6506. * If we leave the registers in a conflicting state (e.g. with the
  6507. * display plane reading from the other pipe than the one we intend
  6508. * to use) then when we attempt to teardown the active mode, we will
  6509. * not disable the pipes and planes in the correct order -- leaving
  6510. * a plane reading from a disabled pipe and possibly leading to
  6511. * undefined behaviour.
  6512. */
  6513. reg = DSPCNTR(plane);
  6514. val = I915_READ(reg);
  6515. if ((val & DISPLAY_PLANE_ENABLE) == 0)
  6516. return;
  6517. if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
  6518. return;
  6519. /* This display plane is active and attached to the other CPU pipe. */
  6520. pipe = !pipe;
  6521. /* Disable the plane and wait for it to stop reading from the pipe. */
  6522. intel_disable_plane(dev_priv, plane, pipe);
  6523. intel_disable_pipe(dev_priv, pipe);
  6524. }
  6525. static void intel_crtc_reset(struct drm_crtc *crtc)
  6526. {
  6527. struct drm_device *dev = crtc->dev;
  6528. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  6529. /* Reset flags back to the 'unknown' status so that they
  6530. * will be correctly set on the initial modeset.
  6531. */
  6532. intel_crtc->dpms_mode = -1;
  6533. /* We need to fix up any BIOS configuration that conflicts with
  6534. * our expectations.
  6535. */
  6536. intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
  6537. }
  6538. static struct drm_crtc_helper_funcs intel_helper_funcs = {
  6539. .dpms = intel_crtc_dpms,
  6540. .mode_fixup = intel_crtc_mode_fixup,
  6541. .mode_set = intel_crtc_mode_set,
  6542. .mode_set_base = intel_pipe_set_base,
  6543. .mode_set_base_atomic = intel_pipe_set_base_atomic,
  6544. .load_lut = intel_crtc_load_lut,
  6545. .disable = intel_crtc_disable,
  6546. };
  6547. static const struct drm_crtc_funcs intel_crtc_funcs = {
  6548. .reset = intel_crtc_reset,
  6549. .cursor_set = intel_crtc_cursor_set,
  6550. .cursor_move = intel_crtc_cursor_move,
  6551. .gamma_set = intel_crtc_gamma_set,
  6552. .set_config = drm_crtc_helper_set_config,
  6553. .destroy = intel_crtc_destroy,
  6554. .page_flip = intel_crtc_page_flip,
  6555. };
  6556. static void intel_crtc_init(struct drm_device *dev, int pipe)
  6557. {
  6558. drm_i915_private_t *dev_priv = dev->dev_private;
  6559. struct intel_crtc *intel_crtc;
  6560. int i;
  6561. intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  6562. if (intel_crtc == NULL)
  6563. return;
  6564. drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
  6565. drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
  6566. for (i = 0; i < 256; i++) {
  6567. intel_crtc->lut_r[i] = i;
  6568. intel_crtc->lut_g[i] = i;
  6569. intel_crtc->lut_b[i] = i;
  6570. }
  6571. /* Swap pipes & planes for FBC on pre-965 */
  6572. intel_crtc->pipe = pipe;
  6573. intel_crtc->plane = pipe;
  6574. if (IS_MOBILE(dev) && IS_GEN3(dev)) {
  6575. DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
  6576. intel_crtc->plane = !pipe;
  6577. }
  6578. BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
  6579. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
  6580. dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
  6581. dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
  6582. intel_crtc_reset(&intel_crtc->base);
  6583. intel_crtc->active = true; /* force the pipe off on setup_init_config */
  6584. intel_crtc->bpp = 24; /* default for pre-Ironlake */
  6585. if (HAS_PCH_SPLIT(dev)) {
  6586. if (pipe == 2 && IS_IVYBRIDGE(dev))
  6587. intel_crtc->no_pll = true;
  6588. intel_helper_funcs.prepare = ironlake_crtc_prepare;
  6589. intel_helper_funcs.commit = ironlake_crtc_commit;
  6590. } else {
  6591. intel_helper_funcs.prepare = i9xx_crtc_prepare;
  6592. intel_helper_funcs.commit = i9xx_crtc_commit;
  6593. }
  6594. drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
  6595. intel_crtc->busy = false;
  6596. setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
  6597. (unsigned long)intel_crtc);
  6598. }
  6599. int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
  6600. struct drm_file *file)
  6601. {
  6602. drm_i915_private_t *dev_priv = dev->dev_private;
  6603. struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
  6604. struct drm_mode_object *drmmode_obj;
  6605. struct intel_crtc *crtc;
  6606. if (!dev_priv) {
  6607. DRM_ERROR("called with no initialization\n");
  6608. return -EINVAL;
  6609. }
  6610. drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
  6611. DRM_MODE_OBJECT_CRTC);
  6612. if (!drmmode_obj) {
  6613. DRM_ERROR("no such CRTC id\n");
  6614. return -EINVAL;
  6615. }
  6616. crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
  6617. pipe_from_crtc_id->pipe = crtc->pipe;
  6618. return 0;
  6619. }
  6620. static int intel_encoder_clones(struct drm_device *dev, int type_mask)
  6621. {
  6622. struct intel_encoder *encoder;
  6623. int index_mask = 0;
  6624. int entry = 0;
  6625. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  6626. if (type_mask & encoder->clone_mask)
  6627. index_mask |= (1 << entry);
  6628. entry++;
  6629. }
  6630. return index_mask;
  6631. }
  6632. static bool has_edp_a(struct drm_device *dev)
  6633. {
  6634. struct drm_i915_private *dev_priv = dev->dev_private;
  6635. if (!IS_MOBILE(dev))
  6636. return false;
  6637. if ((I915_READ(DP_A) & DP_DETECTED) == 0)
  6638. return false;
  6639. if (IS_GEN5(dev) &&
  6640. (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
  6641. return false;
  6642. return true;
  6643. }
  6644. static void intel_setup_outputs(struct drm_device *dev)
  6645. {
  6646. struct drm_i915_private *dev_priv = dev->dev_private;
  6647. struct intel_encoder *encoder;
  6648. bool dpd_is_edp = false;
  6649. bool has_lvds = false;
  6650. if (IS_MOBILE(dev) && !IS_I830(dev))
  6651. has_lvds = intel_lvds_init(dev);
  6652. if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
  6653. /* disable the panel fitter on everything but LVDS */
  6654. I915_WRITE(PFIT_CONTROL, 0);
  6655. }
  6656. if (HAS_PCH_SPLIT(dev)) {
  6657. dpd_is_edp = intel_dpd_is_edp(dev);
  6658. if (has_edp_a(dev))
  6659. intel_dp_init(dev, DP_A);
  6660. if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  6661. intel_dp_init(dev, PCH_DP_D);
  6662. }
  6663. intel_crt_init(dev);
  6664. if (HAS_PCH_SPLIT(dev)) {
  6665. int found;
  6666. if (I915_READ(HDMIB) & PORT_DETECTED) {
  6667. /* PCH SDVOB multiplex with HDMIB */
  6668. found = intel_sdvo_init(dev, PCH_SDVOB);
  6669. if (!found)
  6670. intel_hdmi_init(dev, HDMIB);
  6671. if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
  6672. intel_dp_init(dev, PCH_DP_B);
  6673. }
  6674. if (I915_READ(HDMIC) & PORT_DETECTED)
  6675. intel_hdmi_init(dev, HDMIC);
  6676. if (I915_READ(HDMID) & PORT_DETECTED)
  6677. intel_hdmi_init(dev, HDMID);
  6678. if (I915_READ(PCH_DP_C) & DP_DETECTED)
  6679. intel_dp_init(dev, PCH_DP_C);
  6680. if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
  6681. intel_dp_init(dev, PCH_DP_D);
  6682. } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
  6683. bool found = false;
  6684. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  6685. DRM_DEBUG_KMS("probing SDVOB\n");
  6686. found = intel_sdvo_init(dev, SDVOB);
  6687. if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
  6688. DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
  6689. intel_hdmi_init(dev, SDVOB);
  6690. }
  6691. if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
  6692. DRM_DEBUG_KMS("probing DP_B\n");
  6693. intel_dp_init(dev, DP_B);
  6694. }
  6695. }
  6696. /* Before G4X SDVOC doesn't have its own detect register */
  6697. if (I915_READ(SDVOB) & SDVO_DETECTED) {
  6698. DRM_DEBUG_KMS("probing SDVOC\n");
  6699. found = intel_sdvo_init(dev, SDVOC);
  6700. }
  6701. if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
  6702. if (SUPPORTS_INTEGRATED_HDMI(dev)) {
  6703. DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
  6704. intel_hdmi_init(dev, SDVOC);
  6705. }
  6706. if (SUPPORTS_INTEGRATED_DP(dev)) {
  6707. DRM_DEBUG_KMS("probing DP_C\n");
  6708. intel_dp_init(dev, DP_C);
  6709. }
  6710. }
  6711. if (SUPPORTS_INTEGRATED_DP(dev) &&
  6712. (I915_READ(DP_D) & DP_DETECTED)) {
  6713. DRM_DEBUG_KMS("probing DP_D\n");
  6714. intel_dp_init(dev, DP_D);
  6715. }
  6716. } else if (IS_GEN2(dev))
  6717. intel_dvo_init(dev);
  6718. if (SUPPORTS_TV(dev))
  6719. intel_tv_init(dev);
  6720. list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  6721. encoder->base.possible_crtcs = encoder->crtc_mask;
  6722. encoder->base.possible_clones =
  6723. intel_encoder_clones(dev, encoder->clone_mask);
  6724. }
  6725. /* disable all the possible outputs/crtcs before entering KMS mode */
  6726. drm_helper_disable_unused_functions(dev);
  6727. if (HAS_PCH_SPLIT(dev))
  6728. ironlake_init_pch_refclk(dev);
  6729. }
  6730. static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
  6731. {
  6732. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  6733. drm_framebuffer_cleanup(fb);
  6734. drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
  6735. kfree(intel_fb);
  6736. }
  6737. static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
  6738. struct drm_file *file,
  6739. unsigned int *handle)
  6740. {
  6741. struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  6742. struct drm_i915_gem_object *obj = intel_fb->obj;
  6743. return drm_gem_handle_create(file, &obj->base, handle);
  6744. }
  6745. static const struct drm_framebuffer_funcs intel_fb_funcs = {
  6746. .destroy = intel_user_framebuffer_destroy,
  6747. .create_handle = intel_user_framebuffer_create_handle,
  6748. };
  6749. int intel_framebuffer_init(struct drm_device *dev,
  6750. struct intel_framebuffer *intel_fb,
  6751. struct drm_mode_fb_cmd2 *mode_cmd,
  6752. struct drm_i915_gem_object *obj)
  6753. {
  6754. int ret;
  6755. if (obj->tiling_mode == I915_TILING_Y)
  6756. return -EINVAL;
  6757. if (mode_cmd->pitches[0] & 63)
  6758. return -EINVAL;
  6759. switch (mode_cmd->pixel_format) {
  6760. case DRM_FORMAT_RGB332:
  6761. case DRM_FORMAT_RGB565:
  6762. case DRM_FORMAT_XRGB8888:
  6763. case DRM_FORMAT_ARGB8888:
  6764. case DRM_FORMAT_XRGB2101010:
  6765. case DRM_FORMAT_ARGB2101010:
  6766. /* RGB formats are common across chipsets */
  6767. break;
  6768. case DRM_FORMAT_YUYV:
  6769. case DRM_FORMAT_UYVY:
  6770. case DRM_FORMAT_YVYU:
  6771. case DRM_FORMAT_VYUY:
  6772. break;
  6773. default:
  6774. DRM_DEBUG_KMS("unsupported pixel format %u\n",
  6775. mode_cmd->pixel_format);
  6776. return -EINVAL;
  6777. }
  6778. ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
  6779. if (ret) {
  6780. DRM_ERROR("framebuffer init failed %d\n", ret);
  6781. return ret;
  6782. }
  6783. drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
  6784. intel_fb->obj = obj;
  6785. return 0;
  6786. }
  6787. static struct drm_framebuffer *
  6788. intel_user_framebuffer_create(struct drm_device *dev,
  6789. struct drm_file *filp,
  6790. struct drm_mode_fb_cmd2 *mode_cmd)
  6791. {
  6792. struct drm_i915_gem_object *obj;
  6793. obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
  6794. mode_cmd->handles[0]));
  6795. if (&obj->base == NULL)
  6796. return ERR_PTR(-ENOENT);
  6797. return intel_framebuffer_create(dev, mode_cmd, obj);
  6798. }
  6799. static const struct drm_mode_config_funcs intel_mode_funcs = {
  6800. .fb_create = intel_user_framebuffer_create,
  6801. .output_poll_changed = intel_fb_output_poll_changed,
  6802. };
  6803. static struct drm_i915_gem_object *
  6804. intel_alloc_context_page(struct drm_device *dev)
  6805. {
  6806. struct drm_i915_gem_object *ctx;
  6807. int ret;
  6808. WARN_ON(!mutex_is_locked(&dev->struct_mutex));
  6809. ctx = i915_gem_alloc_object(dev, 4096);
  6810. if (!ctx) {
  6811. DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
  6812. return NULL;
  6813. }
  6814. ret = i915_gem_object_pin(ctx, 4096, true);
  6815. if (ret) {
  6816. DRM_ERROR("failed to pin power context: %d\n", ret);
  6817. goto err_unref;
  6818. }
  6819. ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
  6820. if (ret) {
  6821. DRM_ERROR("failed to set-domain on power context: %d\n", ret);
  6822. goto err_unpin;
  6823. }
  6824. return ctx;
  6825. err_unpin:
  6826. i915_gem_object_unpin(ctx);
  6827. err_unref:
  6828. drm_gem_object_unreference(&ctx->base);
  6829. mutex_unlock(&dev->struct_mutex);
  6830. return NULL;
  6831. }
  6832. bool ironlake_set_drps(struct drm_device *dev, u8 val)
  6833. {
  6834. struct drm_i915_private *dev_priv = dev->dev_private;
  6835. u16 rgvswctl;
  6836. rgvswctl = I915_READ16(MEMSWCTL);
  6837. if (rgvswctl & MEMCTL_CMD_STS) {
  6838. DRM_DEBUG("gpu busy, RCS change rejected\n");
  6839. return false; /* still busy with another command */
  6840. }
  6841. rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
  6842. (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
  6843. I915_WRITE16(MEMSWCTL, rgvswctl);
  6844. POSTING_READ16(MEMSWCTL);
  6845. rgvswctl |= MEMCTL_CMD_STS;
  6846. I915_WRITE16(MEMSWCTL, rgvswctl);
  6847. return true;
  6848. }
  6849. void ironlake_enable_drps(struct drm_device *dev)
  6850. {
  6851. struct drm_i915_private *dev_priv = dev->dev_private;
  6852. u32 rgvmodectl = I915_READ(MEMMODECTL);
  6853. u8 fmax, fmin, fstart, vstart;
  6854. /* Enable temp reporting */
  6855. I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
  6856. I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
  6857. /* 100ms RC evaluation intervals */
  6858. I915_WRITE(RCUPEI, 100000);
  6859. I915_WRITE(RCDNEI, 100000);
  6860. /* Set max/min thresholds to 90ms and 80ms respectively */
  6861. I915_WRITE(RCBMAXAVG, 90000);
  6862. I915_WRITE(RCBMINAVG, 80000);
  6863. I915_WRITE(MEMIHYST, 1);
  6864. /* Set up min, max, and cur for interrupt handling */
  6865. fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
  6866. fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
  6867. fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
  6868. MEMMODE_FSTART_SHIFT;
  6869. vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
  6870. PXVFREQ_PX_SHIFT;
  6871. dev_priv->fmax = fmax; /* IPS callback will increase this */
  6872. dev_priv->fstart = fstart;
  6873. dev_priv->max_delay = fstart;
  6874. dev_priv->min_delay = fmin;
  6875. dev_priv->cur_delay = fstart;
  6876. DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
  6877. fmax, fmin, fstart);
  6878. I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
  6879. /*
  6880. * Interrupts will be enabled in ironlake_irq_postinstall
  6881. */
  6882. I915_WRITE(VIDSTART, vstart);
  6883. POSTING_READ(VIDSTART);
  6884. rgvmodectl |= MEMMODE_SWMODE_EN;
  6885. I915_WRITE(MEMMODECTL, rgvmodectl);
  6886. if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
  6887. DRM_ERROR("stuck trying to change perf mode\n");
  6888. msleep(1);
  6889. ironlake_set_drps(dev, fstart);
  6890. dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
  6891. I915_READ(0x112e0);
  6892. dev_priv->last_time1 = jiffies_to_msecs(jiffies);
  6893. dev_priv->last_count2 = I915_READ(0x112f4);
  6894. getrawmonotonic(&dev_priv->last_time2);
  6895. }
  6896. void ironlake_disable_drps(struct drm_device *dev)
  6897. {
  6898. struct drm_i915_private *dev_priv = dev->dev_private;
  6899. u16 rgvswctl = I915_READ16(MEMSWCTL);
  6900. /* Ack interrupts, disable EFC interrupt */
  6901. I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
  6902. I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
  6903. I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
  6904. I915_WRITE(DEIIR, DE_PCU_EVENT);
  6905. I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
  6906. /* Go back to the starting frequency */
  6907. ironlake_set_drps(dev, dev_priv->fstart);
  6908. msleep(1);
  6909. rgvswctl |= MEMCTL_CMD_STS;
  6910. I915_WRITE(MEMSWCTL, rgvswctl);
  6911. msleep(1);
  6912. }
  6913. void gen6_set_rps(struct drm_device *dev, u8 val)
  6914. {
  6915. struct drm_i915_private *dev_priv = dev->dev_private;
  6916. u32 swreq;
  6917. swreq = (val & 0x3ff) << 25;
  6918. I915_WRITE(GEN6_RPNSWREQ, swreq);
  6919. }
  6920. void gen6_disable_rps(struct drm_device *dev)
  6921. {
  6922. struct drm_i915_private *dev_priv = dev->dev_private;
  6923. I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
  6924. I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
  6925. I915_WRITE(GEN6_PMIER, 0);
  6926. /* Complete PM interrupt masking here doesn't race with the rps work
  6927. * item again unmasking PM interrupts because that is using a different
  6928. * register (PMIMR) to mask PM interrupts. The only risk is in leaving
  6929. * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
  6930. spin_lock_irq(&dev_priv->rps_lock);
  6931. dev_priv->pm_iir = 0;
  6932. spin_unlock_irq(&dev_priv->rps_lock);
  6933. I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
  6934. }
  6935. static unsigned long intel_pxfreq(u32 vidfreq)
  6936. {
  6937. unsigned long freq;
  6938. int div = (vidfreq & 0x3f0000) >> 16;
  6939. int post = (vidfreq & 0x3000) >> 12;
  6940. int pre = (vidfreq & 0x7);
  6941. if (!pre)
  6942. return 0;
  6943. freq = ((div * 133333) / ((1<<post) * pre));
  6944. return freq;
  6945. }
  6946. void intel_init_emon(struct drm_device *dev)
  6947. {
  6948. struct drm_i915_private *dev_priv = dev->dev_private;
  6949. u32 lcfuse;
  6950. u8 pxw[16];
  6951. int i;
  6952. /* Disable to program */
  6953. I915_WRITE(ECR, 0);
  6954. POSTING_READ(ECR);
  6955. /* Program energy weights for various events */
  6956. I915_WRITE(SDEW, 0x15040d00);
  6957. I915_WRITE(CSIEW0, 0x007f0000);
  6958. I915_WRITE(CSIEW1, 0x1e220004);
  6959. I915_WRITE(CSIEW2, 0x04000004);
  6960. for (i = 0; i < 5; i++)
  6961. I915_WRITE(PEW + (i * 4), 0);
  6962. for (i = 0; i < 3; i++)
  6963. I915_WRITE(DEW + (i * 4), 0);
  6964. /* Program P-state weights to account for frequency power adjustment */
  6965. for (i = 0; i < 16; i++) {
  6966. u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
  6967. unsigned long freq = intel_pxfreq(pxvidfreq);
  6968. unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
  6969. PXVFREQ_PX_SHIFT;
  6970. unsigned long val;
  6971. val = vid * vid;
  6972. val *= (freq / 1000);
  6973. val *= 255;
  6974. val /= (127*127*900);
  6975. if (val > 0xff)
  6976. DRM_ERROR("bad pxval: %ld\n", val);
  6977. pxw[i] = val;
  6978. }
  6979. /* Render standby states get 0 weight */
  6980. pxw[14] = 0;
  6981. pxw[15] = 0;
  6982. for (i = 0; i < 4; i++) {
  6983. u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
  6984. (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
  6985. I915_WRITE(PXW + (i * 4), val);
  6986. }
  6987. /* Adjust magic regs to magic values (more experimental results) */
  6988. I915_WRITE(OGW0, 0);
  6989. I915_WRITE(OGW1, 0);
  6990. I915_WRITE(EG0, 0x00007f00);
  6991. I915_WRITE(EG1, 0x0000000e);
  6992. I915_WRITE(EG2, 0x000e0000);
  6993. I915_WRITE(EG3, 0x68000300);
  6994. I915_WRITE(EG4, 0x42000000);
  6995. I915_WRITE(EG5, 0x00140031);
  6996. I915_WRITE(EG6, 0);
  6997. I915_WRITE(EG7, 0);
  6998. for (i = 0; i < 8; i++)
  6999. I915_WRITE(PXWL + (i * 4), 0);
  7000. /* Enable PMON + select events */
  7001. I915_WRITE(ECR, 0x80000019);
  7002. lcfuse = I915_READ(LCFUSE02);
  7003. dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
  7004. }
  7005. static bool intel_enable_rc6(struct drm_device *dev)
  7006. {
  7007. /*
  7008. * Respect the kernel parameter if it is set
  7009. */
  7010. if (i915_enable_rc6 >= 0)
  7011. return i915_enable_rc6;
  7012. /*
  7013. * Disable RC6 on Ironlake
  7014. */
  7015. if (INTEL_INFO(dev)->gen == 5)
  7016. return 0;
  7017. /*
  7018. * Disable rc6 on Sandybridge
  7019. */
  7020. if (INTEL_INFO(dev)->gen == 6) {
  7021. DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
  7022. return 0;
  7023. }
  7024. DRM_DEBUG_DRIVER("RC6 enabled\n");
  7025. return 1;
  7026. }
  7027. void gen6_enable_rps(struct drm_i915_private *dev_priv)
  7028. {
  7029. u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
  7030. u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
  7031. u32 pcu_mbox, rc6_mask = 0;
  7032. u32 gtfifodbg;
  7033. int cur_freq, min_freq, max_freq;
  7034. int i;
  7035. /* Here begins a magic sequence of register writes to enable
  7036. * auto-downclocking.
  7037. *
  7038. * Perhaps there might be some value in exposing these to
  7039. * userspace...
  7040. */
  7041. I915_WRITE(GEN6_RC_STATE, 0);
  7042. mutex_lock(&dev_priv->dev->struct_mutex);
  7043. /* Clear the DBG now so we don't confuse earlier errors */
  7044. if ((gtfifodbg = I915_READ(GTFIFODBG))) {
  7045. DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
  7046. I915_WRITE(GTFIFODBG, gtfifodbg);
  7047. }
  7048. gen6_gt_force_wake_get(dev_priv);
  7049. /* disable the counters and set deterministic thresholds */
  7050. I915_WRITE(GEN6_RC_CONTROL, 0);
  7051. I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
  7052. I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
  7053. I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
  7054. I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
  7055. I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
  7056. for (i = 0; i < I915_NUM_RINGS; i++)
  7057. I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
  7058. I915_WRITE(GEN6_RC_SLEEP, 0);
  7059. I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
  7060. I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
  7061. I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
  7062. I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
  7063. if (intel_enable_rc6(dev_priv->dev))
  7064. rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
  7065. GEN6_RC_CTL_RC6_ENABLE;
  7066. I915_WRITE(GEN6_RC_CONTROL,
  7067. rc6_mask |
  7068. GEN6_RC_CTL_EI_MODE(1) |
  7069. GEN6_RC_CTL_HW_ENABLE);
  7070. I915_WRITE(GEN6_RPNSWREQ,
  7071. GEN6_FREQUENCY(10) |
  7072. GEN6_OFFSET(0) |
  7073. GEN6_AGGRESSIVE_TURBO);
  7074. I915_WRITE(GEN6_RC_VIDEO_FREQ,
  7075. GEN6_FREQUENCY(12));
  7076. I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
  7077. I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
  7078. 18 << 24 |
  7079. 6 << 16);
  7080. I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
  7081. I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
  7082. I915_WRITE(GEN6_RP_UP_EI, 100000);
  7083. I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
  7084. I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
  7085. I915_WRITE(GEN6_RP_CONTROL,
  7086. GEN6_RP_MEDIA_TURBO |
  7087. GEN6_RP_MEDIA_HW_MODE |
  7088. GEN6_RP_MEDIA_IS_GFX |
  7089. GEN6_RP_ENABLE |
  7090. GEN6_RP_UP_BUSY_AVG |
  7091. GEN6_RP_DOWN_IDLE_CONT);
  7092. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  7093. 500))
  7094. DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
  7095. I915_WRITE(GEN6_PCODE_DATA, 0);
  7096. I915_WRITE(GEN6_PCODE_MAILBOX,
  7097. GEN6_PCODE_READY |
  7098. GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
  7099. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  7100. 500))
  7101. DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
  7102. min_freq = (rp_state_cap & 0xff0000) >> 16;
  7103. max_freq = rp_state_cap & 0xff;
  7104. cur_freq = (gt_perf_status & 0xff00) >> 8;
  7105. /* Check for overclock support */
  7106. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  7107. 500))
  7108. DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
  7109. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
  7110. pcu_mbox = I915_READ(GEN6_PCODE_DATA);
  7111. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
  7112. 500))
  7113. DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
  7114. if (pcu_mbox & (1<<31)) { /* OC supported */
  7115. max_freq = pcu_mbox & 0xff;
  7116. DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
  7117. }
  7118. /* In units of 100MHz */
  7119. dev_priv->max_delay = max_freq;
  7120. dev_priv->min_delay = min_freq;
  7121. dev_priv->cur_delay = cur_freq;
  7122. /* requires MSI enabled */
  7123. I915_WRITE(GEN6_PMIER,
  7124. GEN6_PM_MBOX_EVENT |
  7125. GEN6_PM_THERMAL_EVENT |
  7126. GEN6_PM_RP_DOWN_TIMEOUT |
  7127. GEN6_PM_RP_UP_THRESHOLD |
  7128. GEN6_PM_RP_DOWN_THRESHOLD |
  7129. GEN6_PM_RP_UP_EI_EXPIRED |
  7130. GEN6_PM_RP_DOWN_EI_EXPIRED);
  7131. spin_lock_irq(&dev_priv->rps_lock);
  7132. WARN_ON(dev_priv->pm_iir != 0);
  7133. I915_WRITE(GEN6_PMIMR, 0);
  7134. spin_unlock_irq(&dev_priv->rps_lock);
  7135. /* enable all PM interrupts */
  7136. I915_WRITE(GEN6_PMINTRMSK, 0);
  7137. gen6_gt_force_wake_put(dev_priv);
  7138. mutex_unlock(&dev_priv->dev->struct_mutex);
  7139. }
  7140. void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
  7141. {
  7142. int min_freq = 15;
  7143. int gpu_freq, ia_freq, max_ia_freq;
  7144. int scaling_factor = 180;
  7145. max_ia_freq = cpufreq_quick_get_max(0);
  7146. /*
  7147. * Default to measured freq if none found, PCU will ensure we don't go
  7148. * over
  7149. */
  7150. if (!max_ia_freq)
  7151. max_ia_freq = tsc_khz;
  7152. /* Convert from kHz to MHz */
  7153. max_ia_freq /= 1000;
  7154. mutex_lock(&dev_priv->dev->struct_mutex);
  7155. /*
  7156. * For each potential GPU frequency, load a ring frequency we'd like
  7157. * to use for memory access. We do this by specifying the IA frequency
  7158. * the PCU should use as a reference to determine the ring frequency.
  7159. */
  7160. for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
  7161. gpu_freq--) {
  7162. int diff = dev_priv->max_delay - gpu_freq;
  7163. /*
  7164. * For GPU frequencies less than 750MHz, just use the lowest
  7165. * ring freq.
  7166. */
  7167. if (gpu_freq < min_freq)
  7168. ia_freq = 800;
  7169. else
  7170. ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
  7171. ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
  7172. I915_WRITE(GEN6_PCODE_DATA,
  7173. (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
  7174. gpu_freq);
  7175. I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
  7176. GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
  7177. if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
  7178. GEN6_PCODE_READY) == 0, 10)) {
  7179. DRM_ERROR("pcode write of freq table timed out\n");
  7180. continue;
  7181. }
  7182. }
  7183. mutex_unlock(&dev_priv->dev->struct_mutex);
  7184. }
  7185. static void ironlake_init_clock_gating(struct drm_device *dev)
  7186. {
  7187. struct drm_i915_private *dev_priv = dev->dev_private;
  7188. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  7189. /* Required for FBC */
  7190. dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
  7191. DPFCRUNIT_CLOCK_GATE_DISABLE |
  7192. DPFDUNIT_CLOCK_GATE_DISABLE;
  7193. /* Required for CxSR */
  7194. dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
  7195. I915_WRITE(PCH_3DCGDIS0,
  7196. MARIUNIT_CLOCK_GATE_DISABLE |
  7197. SVSMUNIT_CLOCK_GATE_DISABLE);
  7198. I915_WRITE(PCH_3DCGDIS1,
  7199. VFMUNIT_CLOCK_GATE_DISABLE);
  7200. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  7201. /*
  7202. * According to the spec the following bits should be set in
  7203. * order to enable memory self-refresh
  7204. * The bit 22/21 of 0x42004
  7205. * The bit 5 of 0x42020
  7206. * The bit 15 of 0x45000
  7207. */
  7208. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  7209. (I915_READ(ILK_DISPLAY_CHICKEN2) |
  7210. ILK_DPARB_GATE | ILK_VSDPFD_FULL));
  7211. I915_WRITE(ILK_DSPCLK_GATE,
  7212. (I915_READ(ILK_DSPCLK_GATE) |
  7213. ILK_DPARB_CLK_GATE));
  7214. I915_WRITE(DISP_ARB_CTL,
  7215. (I915_READ(DISP_ARB_CTL) |
  7216. DISP_FBC_WM_DIS));
  7217. I915_WRITE(WM3_LP_ILK, 0);
  7218. I915_WRITE(WM2_LP_ILK, 0);
  7219. I915_WRITE(WM1_LP_ILK, 0);
  7220. /*
  7221. * Based on the document from hardware guys the following bits
  7222. * should be set unconditionally in order to enable FBC.
  7223. * The bit 22 of 0x42000
  7224. * The bit 22 of 0x42004
  7225. * The bit 7,8,9 of 0x42020.
  7226. */
  7227. if (IS_IRONLAKE_M(dev)) {
  7228. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  7229. I915_READ(ILK_DISPLAY_CHICKEN1) |
  7230. ILK_FBCQ_DIS);
  7231. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  7232. I915_READ(ILK_DISPLAY_CHICKEN2) |
  7233. ILK_DPARB_GATE);
  7234. I915_WRITE(ILK_DSPCLK_GATE,
  7235. I915_READ(ILK_DSPCLK_GATE) |
  7236. ILK_DPFC_DIS1 |
  7237. ILK_DPFC_DIS2 |
  7238. ILK_CLK_FBC);
  7239. }
  7240. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  7241. I915_READ(ILK_DISPLAY_CHICKEN2) |
  7242. ILK_ELPIN_409_SELECT);
  7243. I915_WRITE(_3D_CHICKEN2,
  7244. _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
  7245. _3D_CHICKEN2_WM_READ_PIPELINED);
  7246. }
  7247. static void gen6_init_clock_gating(struct drm_device *dev)
  7248. {
  7249. struct drm_i915_private *dev_priv = dev->dev_private;
  7250. int pipe;
  7251. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  7252. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  7253. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  7254. I915_READ(ILK_DISPLAY_CHICKEN2) |
  7255. ILK_ELPIN_409_SELECT);
  7256. I915_WRITE(WM3_LP_ILK, 0);
  7257. I915_WRITE(WM2_LP_ILK, 0);
  7258. I915_WRITE(WM1_LP_ILK, 0);
  7259. /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
  7260. * gating disable must be set. Failure to set it results in
  7261. * flickering pixels due to Z write ordering failures after
  7262. * some amount of runtime in the Mesa "fire" demo, and Unigine
  7263. * Sanctuary and Tropics, and apparently anything else with
  7264. * alpha test or pixel discard.
  7265. *
  7266. * According to the spec, bit 11 (RCCUNIT) must also be set,
  7267. * but we didn't debug actual testcases to find it out.
  7268. */
  7269. I915_WRITE(GEN6_UCGCTL2,
  7270. GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
  7271. GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
  7272. /*
  7273. * According to the spec the following bits should be
  7274. * set in order to enable memory self-refresh and fbc:
  7275. * The bit21 and bit22 of 0x42000
  7276. * The bit21 and bit22 of 0x42004
  7277. * The bit5 and bit7 of 0x42020
  7278. * The bit14 of 0x70180
  7279. * The bit14 of 0x71180
  7280. */
  7281. I915_WRITE(ILK_DISPLAY_CHICKEN1,
  7282. I915_READ(ILK_DISPLAY_CHICKEN1) |
  7283. ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
  7284. I915_WRITE(ILK_DISPLAY_CHICKEN2,
  7285. I915_READ(ILK_DISPLAY_CHICKEN2) |
  7286. ILK_DPARB_GATE | ILK_VSDPFD_FULL);
  7287. I915_WRITE(ILK_DSPCLK_GATE,
  7288. I915_READ(ILK_DSPCLK_GATE) |
  7289. ILK_DPARB_CLK_GATE |
  7290. ILK_DPFD_CLK_GATE);
  7291. for_each_pipe(pipe) {
  7292. I915_WRITE(DSPCNTR(pipe),
  7293. I915_READ(DSPCNTR(pipe)) |
  7294. DISPPLANE_TRICKLE_FEED_DISABLE);
  7295. intel_flush_display_plane(dev_priv, pipe);
  7296. }
  7297. }
  7298. static void ivybridge_init_clock_gating(struct drm_device *dev)
  7299. {
  7300. struct drm_i915_private *dev_priv = dev->dev_private;
  7301. int pipe;
  7302. uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
  7303. I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
  7304. I915_WRITE(WM3_LP_ILK, 0);
  7305. I915_WRITE(WM2_LP_ILK, 0);
  7306. I915_WRITE(WM1_LP_ILK, 0);
  7307. I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  7308. I915_WRITE(IVB_CHICKEN3,
  7309. CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
  7310. CHICKEN3_DGMG_DONE_FIX_DISABLE);
  7311. for_each_pipe(pipe) {
  7312. I915_WRITE(DSPCNTR(pipe),
  7313. I915_READ(DSPCNTR(pipe)) |
  7314. DISPPLANE_TRICKLE_FEED_DISABLE);
  7315. intel_flush_display_plane(dev_priv, pipe);
  7316. }
  7317. }
  7318. static void g4x_init_clock_gating(struct drm_device *dev)
  7319. {
  7320. struct drm_i915_private *dev_priv = dev->dev_private;
  7321. uint32_t dspclk_gate;
  7322. I915_WRITE(RENCLK_GATE_D1, 0);
  7323. I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
  7324. GS_UNIT_CLOCK_GATE_DISABLE |
  7325. CL_UNIT_CLOCK_GATE_DISABLE);
  7326. I915_WRITE(RAMCLK_GATE_D, 0);
  7327. dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
  7328. OVRUNIT_CLOCK_GATE_DISABLE |
  7329. OVCUNIT_CLOCK_GATE_DISABLE;
  7330. if (IS_GM45(dev))
  7331. dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
  7332. I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
  7333. }
  7334. static void crestline_init_clock_gating(struct drm_device *dev)
  7335. {
  7336. struct drm_i915_private *dev_priv = dev->dev_private;
  7337. I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
  7338. I915_WRITE(RENCLK_GATE_D2, 0);
  7339. I915_WRITE(DSPCLK_GATE_D, 0);
  7340. I915_WRITE(RAMCLK_GATE_D, 0);
  7341. I915_WRITE16(DEUC, 0);
  7342. }
  7343. static void broadwater_init_clock_gating(struct drm_device *dev)
  7344. {
  7345. struct drm_i915_private *dev_priv = dev->dev_private;
  7346. I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
  7347. I965_RCC_CLOCK_GATE_DISABLE |
  7348. I965_RCPB_CLOCK_GATE_DISABLE |
  7349. I965_ISC_CLOCK_GATE_DISABLE |
  7350. I965_FBC_CLOCK_GATE_DISABLE);
  7351. I915_WRITE(RENCLK_GATE_D2, 0);
  7352. }
  7353. static void gen3_init_clock_gating(struct drm_device *dev)
  7354. {
  7355. struct drm_i915_private *dev_priv = dev->dev_private;
  7356. u32 dstate = I915_READ(D_STATE);
  7357. dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
  7358. DSTATE_DOT_CLOCK_GATING;
  7359. I915_WRITE(D_STATE, dstate);
  7360. }
  7361. static void i85x_init_clock_gating(struct drm_device *dev)
  7362. {
  7363. struct drm_i915_private *dev_priv = dev->dev_private;
  7364. I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
  7365. }
  7366. static void i830_init_clock_gating(struct drm_device *dev)
  7367. {
  7368. struct drm_i915_private *dev_priv = dev->dev_private;
  7369. I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
  7370. }
  7371. static void ibx_init_clock_gating(struct drm_device *dev)
  7372. {
  7373. struct drm_i915_private *dev_priv = dev->dev_private;
  7374. /*
  7375. * On Ibex Peak and Cougar Point, we need to disable clock
  7376. * gating for the panel power sequencer or it will fail to
  7377. * start up when no ports are active.
  7378. */
  7379. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  7380. }
  7381. static void cpt_init_clock_gating(struct drm_device *dev)
  7382. {
  7383. struct drm_i915_private *dev_priv = dev->dev_private;
  7384. int pipe;
  7385. /*
  7386. * On Ibex Peak and Cougar Point, we need to disable clock
  7387. * gating for the panel power sequencer or it will fail to
  7388. * start up when no ports are active.
  7389. */
  7390. I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
  7391. I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
  7392. DPLS_EDP_PPS_FIX_DIS);
  7393. /* Without this, mode sets may fail silently on FDI */
  7394. for_each_pipe(pipe)
  7395. I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
  7396. }
  7397. static void ironlake_teardown_rc6(struct drm_device *dev)
  7398. {
  7399. struct drm_i915_private *dev_priv = dev->dev_private;
  7400. if (dev_priv->renderctx) {
  7401. i915_gem_object_unpin(dev_priv->renderctx);
  7402. drm_gem_object_unreference(&dev_priv->renderctx->base);
  7403. dev_priv->renderctx = NULL;
  7404. }
  7405. if (dev_priv->pwrctx) {
  7406. i915_gem_object_unpin(dev_priv->pwrctx);
  7407. drm_gem_object_unreference(&dev_priv->pwrctx->base);
  7408. dev_priv->pwrctx = NULL;
  7409. }
  7410. }
  7411. static void ironlake_disable_rc6(struct drm_device *dev)
  7412. {
  7413. struct drm_i915_private *dev_priv = dev->dev_private;
  7414. if (I915_READ(PWRCTXA)) {
  7415. /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
  7416. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
  7417. wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
  7418. 50);
  7419. I915_WRITE(PWRCTXA, 0);
  7420. POSTING_READ(PWRCTXA);
  7421. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  7422. POSTING_READ(RSTDBYCTL);
  7423. }
  7424. ironlake_teardown_rc6(dev);
  7425. }
  7426. static int ironlake_setup_rc6(struct drm_device *dev)
  7427. {
  7428. struct drm_i915_private *dev_priv = dev->dev_private;
  7429. if (dev_priv->renderctx == NULL)
  7430. dev_priv->renderctx = intel_alloc_context_page(dev);
  7431. if (!dev_priv->renderctx)
  7432. return -ENOMEM;
  7433. if (dev_priv->pwrctx == NULL)
  7434. dev_priv->pwrctx = intel_alloc_context_page(dev);
  7435. if (!dev_priv->pwrctx) {
  7436. ironlake_teardown_rc6(dev);
  7437. return -ENOMEM;
  7438. }
  7439. return 0;
  7440. }
  7441. void ironlake_enable_rc6(struct drm_device *dev)
  7442. {
  7443. struct drm_i915_private *dev_priv = dev->dev_private;
  7444. int ret;
  7445. /* rc6 disabled by default due to repeated reports of hanging during
  7446. * boot and resume.
  7447. */
  7448. if (!intel_enable_rc6(dev))
  7449. return;
  7450. mutex_lock(&dev->struct_mutex);
  7451. ret = ironlake_setup_rc6(dev);
  7452. if (ret) {
  7453. mutex_unlock(&dev->struct_mutex);
  7454. return;
  7455. }
  7456. /*
  7457. * GPU can automatically power down the render unit if given a page
  7458. * to save state.
  7459. */
  7460. ret = BEGIN_LP_RING(6);
  7461. if (ret) {
  7462. ironlake_teardown_rc6(dev);
  7463. mutex_unlock(&dev->struct_mutex);
  7464. return;
  7465. }
  7466. OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
  7467. OUT_RING(MI_SET_CONTEXT);
  7468. OUT_RING(dev_priv->renderctx->gtt_offset |
  7469. MI_MM_SPACE_GTT |
  7470. MI_SAVE_EXT_STATE_EN |
  7471. MI_RESTORE_EXT_STATE_EN |
  7472. MI_RESTORE_INHIBIT);
  7473. OUT_RING(MI_SUSPEND_FLUSH);
  7474. OUT_RING(MI_NOOP);
  7475. OUT_RING(MI_FLUSH);
  7476. ADVANCE_LP_RING();
  7477. /*
  7478. * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
  7479. * does an implicit flush, combined with MI_FLUSH above, it should be
  7480. * safe to assume that renderctx is valid
  7481. */
  7482. ret = intel_wait_ring_idle(LP_RING(dev_priv));
  7483. if (ret) {
  7484. DRM_ERROR("failed to enable ironlake power power savings\n");
  7485. ironlake_teardown_rc6(dev);
  7486. mutex_unlock(&dev->struct_mutex);
  7487. return;
  7488. }
  7489. I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
  7490. I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
  7491. mutex_unlock(&dev->struct_mutex);
  7492. }
  7493. void intel_init_clock_gating(struct drm_device *dev)
  7494. {
  7495. struct drm_i915_private *dev_priv = dev->dev_private;
  7496. dev_priv->display.init_clock_gating(dev);
  7497. if (dev_priv->display.init_pch_clock_gating)
  7498. dev_priv->display.init_pch_clock_gating(dev);
  7499. }
  7500. /* Set up chip specific display functions */
  7501. static void intel_init_display(struct drm_device *dev)
  7502. {
  7503. struct drm_i915_private *dev_priv = dev->dev_private;
  7504. /* We always want a DPMS function */
  7505. if (HAS_PCH_SPLIT(dev)) {
  7506. dev_priv->display.dpms = ironlake_crtc_dpms;
  7507. dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
  7508. dev_priv->display.update_plane = ironlake_update_plane;
  7509. } else {
  7510. dev_priv->display.dpms = i9xx_crtc_dpms;
  7511. dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
  7512. dev_priv->display.update_plane = i9xx_update_plane;
  7513. }
  7514. if (I915_HAS_FBC(dev)) {
  7515. if (HAS_PCH_SPLIT(dev)) {
  7516. dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
  7517. dev_priv->display.enable_fbc = ironlake_enable_fbc;
  7518. dev_priv->display.disable_fbc = ironlake_disable_fbc;
  7519. } else if (IS_GM45(dev)) {
  7520. dev_priv->display.fbc_enabled = g4x_fbc_enabled;
  7521. dev_priv->display.enable_fbc = g4x_enable_fbc;
  7522. dev_priv->display.disable_fbc = g4x_disable_fbc;
  7523. } else if (IS_CRESTLINE(dev)) {
  7524. dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
  7525. dev_priv->display.enable_fbc = i8xx_enable_fbc;
  7526. dev_priv->display.disable_fbc = i8xx_disable_fbc;
  7527. }
  7528. /* 855GM needs testing */
  7529. }
  7530. /* Returns the core display clock speed */
  7531. if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
  7532. dev_priv->display.get_display_clock_speed =
  7533. i945_get_display_clock_speed;
  7534. else if (IS_I915G(dev))
  7535. dev_priv->display.get_display_clock_speed =
  7536. i915_get_display_clock_speed;
  7537. else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
  7538. dev_priv->display.get_display_clock_speed =
  7539. i9xx_misc_get_display_clock_speed;
  7540. else if (IS_I915GM(dev))
  7541. dev_priv->display.get_display_clock_speed =
  7542. i915gm_get_display_clock_speed;
  7543. else if (IS_I865G(dev))
  7544. dev_priv->display.get_display_clock_speed =
  7545. i865_get_display_clock_speed;
  7546. else if (IS_I85X(dev))
  7547. dev_priv->display.get_display_clock_speed =
  7548. i855_get_display_clock_speed;
  7549. else /* 852, 830 */
  7550. dev_priv->display.get_display_clock_speed =
  7551. i830_get_display_clock_speed;
  7552. /* For FIFO watermark updates */
  7553. if (HAS_PCH_SPLIT(dev)) {
  7554. dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
  7555. dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
  7556. /* IVB configs may use multi-threaded forcewake */
  7557. if (IS_IVYBRIDGE(dev)) {
  7558. u32 ecobus;
  7559. /* A small trick here - if the bios hasn't configured MT forcewake,
  7560. * and if the device is in RC6, then force_wake_mt_get will not wake
  7561. * the device and the ECOBUS read will return zero. Which will be
  7562. * (correctly) interpreted by the test below as MT forcewake being
  7563. * disabled.
  7564. */
  7565. mutex_lock(&dev->struct_mutex);
  7566. __gen6_gt_force_wake_mt_get(dev_priv);
  7567. ecobus = I915_READ_NOTRACE(ECOBUS);
  7568. __gen6_gt_force_wake_mt_put(dev_priv);
  7569. mutex_unlock(&dev->struct_mutex);
  7570. if (ecobus & FORCEWAKE_MT_ENABLE) {
  7571. DRM_DEBUG_KMS("Using MT version of forcewake\n");
  7572. dev_priv->display.force_wake_get =
  7573. __gen6_gt_force_wake_mt_get;
  7574. dev_priv->display.force_wake_put =
  7575. __gen6_gt_force_wake_mt_put;
  7576. }
  7577. }
  7578. if (HAS_PCH_IBX(dev))
  7579. dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
  7580. else if (HAS_PCH_CPT(dev))
  7581. dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
  7582. if (IS_GEN5(dev)) {
  7583. if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
  7584. dev_priv->display.update_wm = ironlake_update_wm;
  7585. else {
  7586. DRM_DEBUG_KMS("Failed to get proper latency. "
  7587. "Disable CxSR\n");
  7588. dev_priv->display.update_wm = NULL;
  7589. }
  7590. dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
  7591. dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
  7592. dev_priv->display.write_eld = ironlake_write_eld;
  7593. } else if (IS_GEN6(dev)) {
  7594. if (SNB_READ_WM0_LATENCY()) {
  7595. dev_priv->display.update_wm = sandybridge_update_wm;
  7596. dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  7597. } else {
  7598. DRM_DEBUG_KMS("Failed to read display plane latency. "
  7599. "Disable CxSR\n");
  7600. dev_priv->display.update_wm = NULL;
  7601. }
  7602. dev_priv->display.fdi_link_train = gen6_fdi_link_train;
  7603. dev_priv->display.init_clock_gating = gen6_init_clock_gating;
  7604. dev_priv->display.write_eld = ironlake_write_eld;
  7605. } else if (IS_IVYBRIDGE(dev)) {
  7606. /* FIXME: detect B0+ stepping and use auto training */
  7607. dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
  7608. if (SNB_READ_WM0_LATENCY()) {
  7609. dev_priv->display.update_wm = sandybridge_update_wm;
  7610. dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
  7611. } else {
  7612. DRM_DEBUG_KMS("Failed to read display plane latency. "
  7613. "Disable CxSR\n");
  7614. dev_priv->display.update_wm = NULL;
  7615. }
  7616. dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
  7617. dev_priv->display.write_eld = ironlake_write_eld;
  7618. } else
  7619. dev_priv->display.update_wm = NULL;
  7620. } else if (IS_PINEVIEW(dev)) {
  7621. if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
  7622. dev_priv->is_ddr3,
  7623. dev_priv->fsb_freq,
  7624. dev_priv->mem_freq)) {
  7625. DRM_INFO("failed to find known CxSR latency "
  7626. "(found ddr%s fsb freq %d, mem freq %d), "
  7627. "disabling CxSR\n",
  7628. (dev_priv->is_ddr3 == 1) ? "3" : "2",
  7629. dev_priv->fsb_freq, dev_priv->mem_freq);
  7630. /* Disable CxSR and never update its watermark again */
  7631. pineview_disable_cxsr(dev);
  7632. dev_priv->display.update_wm = NULL;
  7633. } else
  7634. dev_priv->display.update_wm = pineview_update_wm;
  7635. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  7636. } else if (IS_G4X(dev)) {
  7637. dev_priv->display.write_eld = g4x_write_eld;
  7638. dev_priv->display.update_wm = g4x_update_wm;
  7639. dev_priv->display.init_clock_gating = g4x_init_clock_gating;
  7640. } else if (IS_GEN4(dev)) {
  7641. dev_priv->display.update_wm = i965_update_wm;
  7642. if (IS_CRESTLINE(dev))
  7643. dev_priv->display.init_clock_gating = crestline_init_clock_gating;
  7644. else if (IS_BROADWATER(dev))
  7645. dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
  7646. } else if (IS_GEN3(dev)) {
  7647. dev_priv->display.update_wm = i9xx_update_wm;
  7648. dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
  7649. dev_priv->display.init_clock_gating = gen3_init_clock_gating;
  7650. } else if (IS_I865G(dev)) {
  7651. dev_priv->display.update_wm = i830_update_wm;
  7652. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  7653. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  7654. } else if (IS_I85X(dev)) {
  7655. dev_priv->display.update_wm = i9xx_update_wm;
  7656. dev_priv->display.get_fifo_size = i85x_get_fifo_size;
  7657. dev_priv->display.init_clock_gating = i85x_init_clock_gating;
  7658. } else {
  7659. dev_priv->display.update_wm = i830_update_wm;
  7660. dev_priv->display.init_clock_gating = i830_init_clock_gating;
  7661. if (IS_845G(dev))
  7662. dev_priv->display.get_fifo_size = i845_get_fifo_size;
  7663. else
  7664. dev_priv->display.get_fifo_size = i830_get_fifo_size;
  7665. }
  7666. /* Default just returns -ENODEV to indicate unsupported */
  7667. dev_priv->display.queue_flip = intel_default_queue_flip;
  7668. switch (INTEL_INFO(dev)->gen) {
  7669. case 2:
  7670. dev_priv->display.queue_flip = intel_gen2_queue_flip;
  7671. break;
  7672. case 3:
  7673. dev_priv->display.queue_flip = intel_gen3_queue_flip;
  7674. break;
  7675. case 4:
  7676. case 5:
  7677. dev_priv->display.queue_flip = intel_gen4_queue_flip;
  7678. break;
  7679. case 6:
  7680. dev_priv->display.queue_flip = intel_gen6_queue_flip;
  7681. break;
  7682. case 7:
  7683. dev_priv->display.queue_flip = intel_gen7_queue_flip;
  7684. break;
  7685. }
  7686. }
  7687. /*
  7688. * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
  7689. * resume, or other times. This quirk makes sure that's the case for
  7690. * affected systems.
  7691. */
  7692. static void quirk_pipea_force(struct drm_device *dev)
  7693. {
  7694. struct drm_i915_private *dev_priv = dev->dev_private;
  7695. dev_priv->quirks |= QUIRK_PIPEA_FORCE;
  7696. DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
  7697. }
  7698. /*
  7699. * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
  7700. */
  7701. static void quirk_ssc_force_disable(struct drm_device *dev)
  7702. {
  7703. struct drm_i915_private *dev_priv = dev->dev_private;
  7704. dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
  7705. }
  7706. struct intel_quirk {
  7707. int device;
  7708. int subsystem_vendor;
  7709. int subsystem_device;
  7710. void (*hook)(struct drm_device *dev);
  7711. };
  7712. struct intel_quirk intel_quirks[] = {
  7713. /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
  7714. { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
  7715. /* HP Mini needs pipe A force quirk (LP: #322104) */
  7716. { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
  7717. /* Thinkpad R31 needs pipe A force quirk */
  7718. { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
  7719. /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
  7720. { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
  7721. /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
  7722. { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
  7723. /* ThinkPad X40 needs pipe A force quirk */
  7724. /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
  7725. { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
  7726. /* 855 & before need to leave pipe A & dpll A up */
  7727. { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  7728. { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
  7729. /* Lenovo U160 cannot use SSC on LVDS */
  7730. { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
  7731. /* Sony Vaio Y cannot use SSC on LVDS */
  7732. { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
  7733. };
  7734. static void intel_init_quirks(struct drm_device *dev)
  7735. {
  7736. struct pci_dev *d = dev->pdev;
  7737. int i;
  7738. for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
  7739. struct intel_quirk *q = &intel_quirks[i];
  7740. if (d->device == q->device &&
  7741. (d->subsystem_vendor == q->subsystem_vendor ||
  7742. q->subsystem_vendor == PCI_ANY_ID) &&
  7743. (d->subsystem_device == q->subsystem_device ||
  7744. q->subsystem_device == PCI_ANY_ID))
  7745. q->hook(dev);
  7746. }
  7747. }
  7748. /* Disable the VGA plane that we never use */
  7749. static void i915_disable_vga(struct drm_device *dev)
  7750. {
  7751. struct drm_i915_private *dev_priv = dev->dev_private;
  7752. u8 sr1;
  7753. u32 vga_reg;
  7754. if (HAS_PCH_SPLIT(dev))
  7755. vga_reg = CPU_VGACNTRL;
  7756. else
  7757. vga_reg = VGACNTRL;
  7758. vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
  7759. outb(1, VGA_SR_INDEX);
  7760. sr1 = inb(VGA_SR_DATA);
  7761. outb(sr1 | 1<<5, VGA_SR_DATA);
  7762. vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
  7763. udelay(300);
  7764. I915_WRITE(vga_reg, VGA_DISP_DISABLE);
  7765. POSTING_READ(vga_reg);
  7766. }
  7767. void intel_modeset_init(struct drm_device *dev)
  7768. {
  7769. struct drm_i915_private *dev_priv = dev->dev_private;
  7770. int i, ret;
  7771. drm_mode_config_init(dev);
  7772. dev->mode_config.min_width = 0;
  7773. dev->mode_config.min_height = 0;
  7774. dev->mode_config.funcs = (void *)&intel_mode_funcs;
  7775. intel_init_quirks(dev);
  7776. intel_init_display(dev);
  7777. if (IS_GEN2(dev)) {
  7778. dev->mode_config.max_width = 2048;
  7779. dev->mode_config.max_height = 2048;
  7780. } else if (IS_GEN3(dev)) {
  7781. dev->mode_config.max_width = 4096;
  7782. dev->mode_config.max_height = 4096;
  7783. } else {
  7784. dev->mode_config.max_width = 8192;
  7785. dev->mode_config.max_height = 8192;
  7786. }
  7787. dev->mode_config.fb_base = dev->agp->base;
  7788. DRM_DEBUG_KMS("%d display pipe%s available.\n",
  7789. dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
  7790. for (i = 0; i < dev_priv->num_pipe; i++) {
  7791. intel_crtc_init(dev, i);
  7792. ret = intel_plane_init(dev, i);
  7793. if (ret)
  7794. DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
  7795. }
  7796. /* Just disable it once at startup */
  7797. i915_disable_vga(dev);
  7798. intel_setup_outputs(dev);
  7799. intel_init_clock_gating(dev);
  7800. if (IS_IRONLAKE_M(dev)) {
  7801. ironlake_enable_drps(dev);
  7802. intel_init_emon(dev);
  7803. }
  7804. if (IS_GEN6(dev) || IS_GEN7(dev)) {
  7805. gen6_enable_rps(dev_priv);
  7806. gen6_update_ring_freq(dev_priv);
  7807. }
  7808. INIT_WORK(&dev_priv->idle_work, intel_idle_update);
  7809. setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
  7810. (unsigned long)dev);
  7811. }
  7812. void intel_modeset_gem_init(struct drm_device *dev)
  7813. {
  7814. if (IS_IRONLAKE_M(dev))
  7815. ironlake_enable_rc6(dev);
  7816. intel_setup_overlay(dev);
  7817. }
  7818. void intel_modeset_cleanup(struct drm_device *dev)
  7819. {
  7820. struct drm_i915_private *dev_priv = dev->dev_private;
  7821. struct drm_crtc *crtc;
  7822. struct intel_crtc *intel_crtc;
  7823. drm_kms_helper_poll_fini(dev);
  7824. mutex_lock(&dev->struct_mutex);
  7825. intel_unregister_dsm_handler();
  7826. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  7827. /* Skip inactive CRTCs */
  7828. if (!crtc->fb)
  7829. continue;
  7830. intel_crtc = to_intel_crtc(crtc);
  7831. intel_increase_pllclock(crtc);
  7832. }
  7833. intel_disable_fbc(dev);
  7834. if (IS_IRONLAKE_M(dev))
  7835. ironlake_disable_drps(dev);
  7836. if (IS_GEN6(dev) || IS_GEN7(dev))
  7837. gen6_disable_rps(dev);
  7838. if (IS_IRONLAKE_M(dev))
  7839. ironlake_disable_rc6(dev);
  7840. mutex_unlock(&dev->struct_mutex);
  7841. /* Disable the irq before mode object teardown, for the irq might
  7842. * enqueue unpin/hotplug work. */
  7843. drm_irq_uninstall(dev);
  7844. cancel_work_sync(&dev_priv->hotplug_work);
  7845. cancel_work_sync(&dev_priv->rps_work);
  7846. /* flush any delayed tasks or pending work */
  7847. flush_scheduled_work();
  7848. /* Shut off idle work before the crtcs get freed. */
  7849. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  7850. intel_crtc = to_intel_crtc(crtc);
  7851. del_timer_sync(&intel_crtc->idle_timer);
  7852. }
  7853. del_timer_sync(&dev_priv->idle_timer);
  7854. cancel_work_sync(&dev_priv->idle_work);
  7855. drm_mode_config_cleanup(dev);
  7856. }
  7857. /*
  7858. * Return which encoder is currently attached for connector.
  7859. */
  7860. struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
  7861. {
  7862. return &intel_attached_encoder(connector)->base;
  7863. }
  7864. void intel_connector_attach_encoder(struct intel_connector *connector,
  7865. struct intel_encoder *encoder)
  7866. {
  7867. connector->encoder = encoder;
  7868. drm_mode_connector_attach_encoder(&connector->base,
  7869. &encoder->base);
  7870. }
  7871. /*
  7872. * set vga decode state - true == enable VGA decode
  7873. */
  7874. int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
  7875. {
  7876. struct drm_i915_private *dev_priv = dev->dev_private;
  7877. u16 gmch_ctrl;
  7878. pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
  7879. if (state)
  7880. gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
  7881. else
  7882. gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
  7883. pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
  7884. return 0;
  7885. }
  7886. #ifdef CONFIG_DEBUG_FS
  7887. #include <linux/seq_file.h>
  7888. struct intel_display_error_state {
  7889. struct intel_cursor_error_state {
  7890. u32 control;
  7891. u32 position;
  7892. u32 base;
  7893. u32 size;
  7894. } cursor[2];
  7895. struct intel_pipe_error_state {
  7896. u32 conf;
  7897. u32 source;
  7898. u32 htotal;
  7899. u32 hblank;
  7900. u32 hsync;
  7901. u32 vtotal;
  7902. u32 vblank;
  7903. u32 vsync;
  7904. } pipe[2];
  7905. struct intel_plane_error_state {
  7906. u32 control;
  7907. u32 stride;
  7908. u32 size;
  7909. u32 pos;
  7910. u32 addr;
  7911. u32 surface;
  7912. u32 tile_offset;
  7913. } plane[2];
  7914. };
  7915. struct intel_display_error_state *
  7916. intel_display_capture_error_state(struct drm_device *dev)
  7917. {
  7918. drm_i915_private_t *dev_priv = dev->dev_private;
  7919. struct intel_display_error_state *error;
  7920. int i;
  7921. error = kmalloc(sizeof(*error), GFP_ATOMIC);
  7922. if (error == NULL)
  7923. return NULL;
  7924. for (i = 0; i < 2; i++) {
  7925. error->cursor[i].control = I915_READ(CURCNTR(i));
  7926. error->cursor[i].position = I915_READ(CURPOS(i));
  7927. error->cursor[i].base = I915_READ(CURBASE(i));
  7928. error->plane[i].control = I915_READ(DSPCNTR(i));
  7929. error->plane[i].stride = I915_READ(DSPSTRIDE(i));
  7930. error->plane[i].size = I915_READ(DSPSIZE(i));
  7931. error->plane[i].pos = I915_READ(DSPPOS(i));
  7932. error->plane[i].addr = I915_READ(DSPADDR(i));
  7933. if (INTEL_INFO(dev)->gen >= 4) {
  7934. error->plane[i].surface = I915_READ(DSPSURF(i));
  7935. error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
  7936. }
  7937. error->pipe[i].conf = I915_READ(PIPECONF(i));
  7938. error->pipe[i].source = I915_READ(PIPESRC(i));
  7939. error->pipe[i].htotal = I915_READ(HTOTAL(i));
  7940. error->pipe[i].hblank = I915_READ(HBLANK(i));
  7941. error->pipe[i].hsync = I915_READ(HSYNC(i));
  7942. error->pipe[i].vtotal = I915_READ(VTOTAL(i));
  7943. error->pipe[i].vblank = I915_READ(VBLANK(i));
  7944. error->pipe[i].vsync = I915_READ(VSYNC(i));
  7945. }
  7946. return error;
  7947. }
  7948. void
  7949. intel_display_print_error_state(struct seq_file *m,
  7950. struct drm_device *dev,
  7951. struct intel_display_error_state *error)
  7952. {
  7953. int i;
  7954. for (i = 0; i < 2; i++) {
  7955. seq_printf(m, "Pipe [%d]:\n", i);
  7956. seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
  7957. seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
  7958. seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
  7959. seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
  7960. seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
  7961. seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
  7962. seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
  7963. seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
  7964. seq_printf(m, "Plane [%d]:\n", i);
  7965. seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
  7966. seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
  7967. seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
  7968. seq_printf(m, " POS: %08x\n", error->plane[i].pos);
  7969. seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
  7970. if (INTEL_INFO(dev)->gen >= 4) {
  7971. seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
  7972. seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
  7973. }
  7974. seq_printf(m, "Cursor [%d]:\n", i);
  7975. seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
  7976. seq_printf(m, " POS: %08x\n", error->cursor[i].position);
  7977. seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
  7978. }
  7979. }
  7980. #endif