be_main.c 68 KB

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  1. /*
  2. * Copyright (C) 2005 - 2010 ServerEngines
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Contact Information:
  11. * linux-drivers@serverengines.com
  12. *
  13. * ServerEngines
  14. * 209 N. Fair Oaks Ave
  15. * Sunnyvale, CA 94085
  16. */
  17. #include "be.h"
  18. #include "be_cmds.h"
  19. #include <asm/div64.h>
  20. MODULE_VERSION(DRV_VER);
  21. MODULE_DEVICE_TABLE(pci, be_dev_ids);
  22. MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
  23. MODULE_AUTHOR("ServerEngines Corporation");
  24. MODULE_LICENSE("GPL");
  25. static unsigned int rx_frag_size = 2048;
  26. static unsigned int num_vfs;
  27. module_param(rx_frag_size, uint, S_IRUGO);
  28. module_param(num_vfs, uint, S_IRUGO);
  29. MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
  30. MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
  31. static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
  32. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  33. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  34. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  35. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  36. { 0 }
  37. };
  38. MODULE_DEVICE_TABLE(pci, be_dev_ids);
  39. static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
  40. {
  41. struct be_dma_mem *mem = &q->dma_mem;
  42. if (mem->va)
  43. pci_free_consistent(adapter->pdev, mem->size,
  44. mem->va, mem->dma);
  45. }
  46. static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
  47. u16 len, u16 entry_size)
  48. {
  49. struct be_dma_mem *mem = &q->dma_mem;
  50. memset(q, 0, sizeof(*q));
  51. q->len = len;
  52. q->entry_size = entry_size;
  53. mem->size = len * entry_size;
  54. mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
  55. if (!mem->va)
  56. return -1;
  57. memset(mem->va, 0, mem->size);
  58. return 0;
  59. }
  60. static void be_intr_set(struct be_adapter *adapter, bool enable)
  61. {
  62. u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  63. u32 reg = ioread32(addr);
  64. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  65. if (adapter->eeh_err)
  66. return;
  67. if (!enabled && enable)
  68. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  69. else if (enabled && !enable)
  70. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  71. else
  72. return;
  73. iowrite32(reg, addr);
  74. }
  75. static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
  76. {
  77. u32 val = 0;
  78. val |= qid & DB_RQ_RING_ID_MASK;
  79. val |= posted << DB_RQ_NUM_POSTED_SHIFT;
  80. iowrite32(val, adapter->db + DB_RQ_OFFSET);
  81. }
  82. static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
  83. {
  84. u32 val = 0;
  85. val |= qid & DB_TXULP_RING_ID_MASK;
  86. val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
  87. iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
  88. }
  89. static void be_eq_notify(struct be_adapter *adapter, u16 qid,
  90. bool arm, bool clear_int, u16 num_popped)
  91. {
  92. u32 val = 0;
  93. val |= qid & DB_EQ_RING_ID_MASK;
  94. if (adapter->eeh_err)
  95. return;
  96. if (arm)
  97. val |= 1 << DB_EQ_REARM_SHIFT;
  98. if (clear_int)
  99. val |= 1 << DB_EQ_CLR_SHIFT;
  100. val |= 1 << DB_EQ_EVNT_SHIFT;
  101. val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
  102. iowrite32(val, adapter->db + DB_EQ_OFFSET);
  103. }
  104. void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
  105. {
  106. u32 val = 0;
  107. val |= qid & DB_CQ_RING_ID_MASK;
  108. if (adapter->eeh_err)
  109. return;
  110. if (arm)
  111. val |= 1 << DB_CQ_REARM_SHIFT;
  112. val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
  113. iowrite32(val, adapter->db + DB_CQ_OFFSET);
  114. }
  115. static int be_mac_addr_set(struct net_device *netdev, void *p)
  116. {
  117. struct be_adapter *adapter = netdev_priv(netdev);
  118. struct sockaddr *addr = p;
  119. int status = 0;
  120. if (!is_valid_ether_addr(addr->sa_data))
  121. return -EADDRNOTAVAIL;
  122. /* MAC addr configuration will be done in hardware for VFs
  123. * by their corresponding PFs. Just copy to netdev addr here
  124. */
  125. if (!be_physfn(adapter))
  126. goto netdev_addr;
  127. status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
  128. if (status)
  129. return status;
  130. status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
  131. adapter->if_handle, &adapter->pmac_id);
  132. netdev_addr:
  133. if (!status)
  134. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  135. return status;
  136. }
  137. void netdev_stats_update(struct be_adapter *adapter)
  138. {
  139. struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
  140. struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
  141. struct be_port_rxf_stats *port_stats =
  142. &rxf_stats->port[adapter->port_num];
  143. struct net_device_stats *dev_stats = &adapter->netdev->stats;
  144. struct be_erx_stats *erx_stats = &hw_stats->erx;
  145. dev_stats->rx_packets = drvr_stats(adapter)->be_rx_pkts;
  146. dev_stats->tx_packets = drvr_stats(adapter)->be_tx_pkts;
  147. dev_stats->rx_bytes = drvr_stats(adapter)->be_rx_bytes;
  148. dev_stats->tx_bytes = drvr_stats(adapter)->be_tx_bytes;
  149. /* bad pkts received */
  150. dev_stats->rx_errors = port_stats->rx_crc_errors +
  151. port_stats->rx_alignment_symbol_errors +
  152. port_stats->rx_in_range_errors +
  153. port_stats->rx_out_range_errors +
  154. port_stats->rx_frame_too_long +
  155. port_stats->rx_dropped_too_small +
  156. port_stats->rx_dropped_too_short +
  157. port_stats->rx_dropped_header_too_small +
  158. port_stats->rx_dropped_tcp_length +
  159. port_stats->rx_dropped_runt +
  160. port_stats->rx_tcp_checksum_errs +
  161. port_stats->rx_ip_checksum_errs +
  162. port_stats->rx_udp_checksum_errs;
  163. /* no space in linux buffers: best possible approximation */
  164. dev_stats->rx_dropped =
  165. erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
  166. /* detailed rx errors */
  167. dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
  168. port_stats->rx_out_range_errors +
  169. port_stats->rx_frame_too_long;
  170. /* receive ring buffer overflow */
  171. dev_stats->rx_over_errors = 0;
  172. dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
  173. /* frame alignment errors */
  174. dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
  175. /* receiver fifo overrun */
  176. /* drops_no_pbuf is no per i/f, it's per BE card */
  177. dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
  178. port_stats->rx_input_fifo_overflow +
  179. rxf_stats->rx_drops_no_pbuf;
  180. /* receiver missed packetd */
  181. dev_stats->rx_missed_errors = 0;
  182. /* packet transmit problems */
  183. dev_stats->tx_errors = 0;
  184. /* no space available in linux */
  185. dev_stats->tx_dropped = 0;
  186. dev_stats->multicast = port_stats->rx_multicast_frames;
  187. dev_stats->collisions = 0;
  188. /* detailed tx_errors */
  189. dev_stats->tx_aborted_errors = 0;
  190. dev_stats->tx_carrier_errors = 0;
  191. dev_stats->tx_fifo_errors = 0;
  192. dev_stats->tx_heartbeat_errors = 0;
  193. dev_stats->tx_window_errors = 0;
  194. }
  195. void be_link_status_update(struct be_adapter *adapter, bool link_up)
  196. {
  197. struct net_device *netdev = adapter->netdev;
  198. /* If link came up or went down */
  199. if (adapter->link_up != link_up) {
  200. adapter->link_speed = -1;
  201. if (link_up) {
  202. netif_start_queue(netdev);
  203. netif_carrier_on(netdev);
  204. printk(KERN_INFO "%s: Link up\n", netdev->name);
  205. } else {
  206. netif_stop_queue(netdev);
  207. netif_carrier_off(netdev);
  208. printk(KERN_INFO "%s: Link down\n", netdev->name);
  209. }
  210. adapter->link_up = link_up;
  211. }
  212. }
  213. /* Update the EQ delay n BE based on the RX frags consumed / sec */
  214. static void be_rx_eqd_update(struct be_adapter *adapter)
  215. {
  216. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  217. struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
  218. ulong now = jiffies;
  219. u32 eqd;
  220. if (!rx_eq->enable_aic)
  221. return;
  222. /* Wrapped around */
  223. if (time_before(now, stats->rx_fps_jiffies)) {
  224. stats->rx_fps_jiffies = now;
  225. return;
  226. }
  227. /* Update once a second */
  228. if ((now - stats->rx_fps_jiffies) < HZ)
  229. return;
  230. stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
  231. ((now - stats->rx_fps_jiffies) / HZ);
  232. stats->rx_fps_jiffies = now;
  233. stats->be_prev_rx_frags = stats->be_rx_frags;
  234. eqd = stats->be_rx_fps / 110000;
  235. eqd = eqd << 3;
  236. if (eqd > rx_eq->max_eqd)
  237. eqd = rx_eq->max_eqd;
  238. if (eqd < rx_eq->min_eqd)
  239. eqd = rx_eq->min_eqd;
  240. if (eqd < 10)
  241. eqd = 0;
  242. if (eqd != rx_eq->cur_eqd)
  243. be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
  244. rx_eq->cur_eqd = eqd;
  245. }
  246. static struct net_device_stats *be_get_stats(struct net_device *dev)
  247. {
  248. return &dev->stats;
  249. }
  250. static u32 be_calc_rate(u64 bytes, unsigned long ticks)
  251. {
  252. u64 rate = bytes;
  253. do_div(rate, ticks / HZ);
  254. rate <<= 3; /* bytes/sec -> bits/sec */
  255. do_div(rate, 1000000ul); /* MB/Sec */
  256. return rate;
  257. }
  258. static void be_tx_rate_update(struct be_adapter *adapter)
  259. {
  260. struct be_drvr_stats *stats = drvr_stats(adapter);
  261. ulong now = jiffies;
  262. /* Wrapped around? */
  263. if (time_before(now, stats->be_tx_jiffies)) {
  264. stats->be_tx_jiffies = now;
  265. return;
  266. }
  267. /* Update tx rate once in two seconds */
  268. if ((now - stats->be_tx_jiffies) > 2 * HZ) {
  269. stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
  270. - stats->be_tx_bytes_prev,
  271. now - stats->be_tx_jiffies);
  272. stats->be_tx_jiffies = now;
  273. stats->be_tx_bytes_prev = stats->be_tx_bytes;
  274. }
  275. }
  276. static void be_tx_stats_update(struct be_adapter *adapter,
  277. u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
  278. {
  279. struct be_drvr_stats *stats = drvr_stats(adapter);
  280. stats->be_tx_reqs++;
  281. stats->be_tx_wrbs += wrb_cnt;
  282. stats->be_tx_bytes += copied;
  283. stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
  284. if (stopped)
  285. stats->be_tx_stops++;
  286. }
  287. /* Determine number of WRB entries needed to xmit data in an skb */
  288. static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
  289. {
  290. int cnt = (skb->len > skb->data_len);
  291. cnt += skb_shinfo(skb)->nr_frags;
  292. /* to account for hdr wrb */
  293. cnt++;
  294. if (cnt & 1) {
  295. /* add a dummy to make it an even num */
  296. cnt++;
  297. *dummy = true;
  298. } else
  299. *dummy = false;
  300. BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
  301. return cnt;
  302. }
  303. static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
  304. {
  305. wrb->frag_pa_hi = upper_32_bits(addr);
  306. wrb->frag_pa_lo = addr & 0xFFFFFFFF;
  307. wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
  308. }
  309. static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
  310. bool vlan, u32 wrb_cnt, u32 len)
  311. {
  312. memset(hdr, 0, sizeof(*hdr));
  313. AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
  314. if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) {
  315. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
  316. AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
  317. hdr, skb_shinfo(skb)->gso_size);
  318. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  319. if (is_tcp_pkt(skb))
  320. AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
  321. else if (is_udp_pkt(skb))
  322. AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
  323. }
  324. if (vlan && vlan_tx_tag_present(skb)) {
  325. AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
  326. AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
  327. hdr, vlan_tx_tag_get(skb));
  328. }
  329. AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
  330. AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
  331. AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
  332. AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
  333. }
  334. static void unmap_tx_frag(struct pci_dev *pdev, struct be_eth_wrb *wrb,
  335. bool unmap_single)
  336. {
  337. dma_addr_t dma;
  338. be_dws_le_to_cpu(wrb, sizeof(*wrb));
  339. dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
  340. if (wrb->frag_len) {
  341. if (unmap_single)
  342. pci_unmap_single(pdev, dma, wrb->frag_len,
  343. PCI_DMA_TODEVICE);
  344. else
  345. pci_unmap_page(pdev, dma, wrb->frag_len,
  346. PCI_DMA_TODEVICE);
  347. }
  348. }
  349. static int make_tx_wrbs(struct be_adapter *adapter,
  350. struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
  351. {
  352. dma_addr_t busaddr;
  353. int i, copied = 0;
  354. struct pci_dev *pdev = adapter->pdev;
  355. struct sk_buff *first_skb = skb;
  356. struct be_queue_info *txq = &adapter->tx_obj.q;
  357. struct be_eth_wrb *wrb;
  358. struct be_eth_hdr_wrb *hdr;
  359. bool map_single = false;
  360. u16 map_head;
  361. hdr = queue_head_node(txq);
  362. queue_head_inc(txq);
  363. map_head = txq->head;
  364. if (skb->len > skb->data_len) {
  365. int len = skb_headlen(skb);
  366. busaddr = pci_map_single(pdev, skb->data, len,
  367. PCI_DMA_TODEVICE);
  368. if (pci_dma_mapping_error(pdev, busaddr))
  369. goto dma_err;
  370. map_single = true;
  371. wrb = queue_head_node(txq);
  372. wrb_fill(wrb, busaddr, len);
  373. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  374. queue_head_inc(txq);
  375. copied += len;
  376. }
  377. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  378. struct skb_frag_struct *frag =
  379. &skb_shinfo(skb)->frags[i];
  380. busaddr = pci_map_page(pdev, frag->page,
  381. frag->page_offset,
  382. frag->size, PCI_DMA_TODEVICE);
  383. if (pci_dma_mapping_error(pdev, busaddr))
  384. goto dma_err;
  385. wrb = queue_head_node(txq);
  386. wrb_fill(wrb, busaddr, frag->size);
  387. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  388. queue_head_inc(txq);
  389. copied += frag->size;
  390. }
  391. if (dummy_wrb) {
  392. wrb = queue_head_node(txq);
  393. wrb_fill(wrb, 0, 0);
  394. be_dws_cpu_to_le(wrb, sizeof(*wrb));
  395. queue_head_inc(txq);
  396. }
  397. wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
  398. wrb_cnt, copied);
  399. be_dws_cpu_to_le(hdr, sizeof(*hdr));
  400. return copied;
  401. dma_err:
  402. txq->head = map_head;
  403. while (copied) {
  404. wrb = queue_head_node(txq);
  405. unmap_tx_frag(pdev, wrb, map_single);
  406. map_single = false;
  407. copied -= wrb->frag_len;
  408. queue_head_inc(txq);
  409. }
  410. return 0;
  411. }
  412. static netdev_tx_t be_xmit(struct sk_buff *skb,
  413. struct net_device *netdev)
  414. {
  415. struct be_adapter *adapter = netdev_priv(netdev);
  416. struct be_tx_obj *tx_obj = &adapter->tx_obj;
  417. struct be_queue_info *txq = &tx_obj->q;
  418. u32 wrb_cnt = 0, copied = 0;
  419. u32 start = txq->head;
  420. bool dummy_wrb, stopped = false;
  421. wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
  422. copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
  423. if (copied) {
  424. /* record the sent skb in the sent_skb table */
  425. BUG_ON(tx_obj->sent_skb_list[start]);
  426. tx_obj->sent_skb_list[start] = skb;
  427. /* Ensure txq has space for the next skb; Else stop the queue
  428. * *BEFORE* ringing the tx doorbell, so that we serialze the
  429. * tx compls of the current transmit which'll wake up the queue
  430. */
  431. atomic_add(wrb_cnt, &txq->used);
  432. if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
  433. txq->len) {
  434. netif_stop_queue(netdev);
  435. stopped = true;
  436. }
  437. be_txq_notify(adapter, txq->id, wrb_cnt);
  438. be_tx_stats_update(adapter, wrb_cnt, copied,
  439. skb_shinfo(skb)->gso_segs, stopped);
  440. } else {
  441. txq->head = start;
  442. dev_kfree_skb_any(skb);
  443. }
  444. return NETDEV_TX_OK;
  445. }
  446. static int be_change_mtu(struct net_device *netdev, int new_mtu)
  447. {
  448. struct be_adapter *adapter = netdev_priv(netdev);
  449. if (new_mtu < BE_MIN_MTU ||
  450. new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
  451. (ETH_HLEN + ETH_FCS_LEN))) {
  452. dev_info(&adapter->pdev->dev,
  453. "MTU must be between %d and %d bytes\n",
  454. BE_MIN_MTU,
  455. (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
  456. return -EINVAL;
  457. }
  458. dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
  459. netdev->mtu, new_mtu);
  460. netdev->mtu = new_mtu;
  461. return 0;
  462. }
  463. /*
  464. * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
  465. * If the user configures more, place BE in vlan promiscuous mode.
  466. */
  467. static int be_vid_config(struct be_adapter *adapter)
  468. {
  469. u16 vtag[BE_NUM_VLANS_SUPPORTED];
  470. u16 ntags = 0, i;
  471. int status = 0;
  472. if (adapter->vlans_added <= adapter->max_vlans) {
  473. /* Construct VLAN Table to give to HW */
  474. for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
  475. if (adapter->vlan_tag[i]) {
  476. vtag[ntags] = cpu_to_le16(i);
  477. ntags++;
  478. }
  479. }
  480. status = be_cmd_vlan_config(adapter, adapter->if_handle,
  481. vtag, ntags, 1, 0);
  482. } else {
  483. status = be_cmd_vlan_config(adapter, adapter->if_handle,
  484. NULL, 0, 1, 1);
  485. }
  486. return status;
  487. }
  488. static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
  489. {
  490. struct be_adapter *adapter = netdev_priv(netdev);
  491. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  492. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  493. be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
  494. be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
  495. adapter->vlan_grp = grp;
  496. be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
  497. be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
  498. }
  499. static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
  500. {
  501. struct be_adapter *adapter = netdev_priv(netdev);
  502. if (!be_physfn(adapter))
  503. return;
  504. adapter->vlan_tag[vid] = 1;
  505. adapter->vlans_added++;
  506. if (adapter->vlans_added <= (adapter->max_vlans + 1))
  507. be_vid_config(adapter);
  508. }
  509. static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
  510. {
  511. struct be_adapter *adapter = netdev_priv(netdev);
  512. if (!be_physfn(adapter))
  513. return;
  514. adapter->vlan_tag[vid] = 0;
  515. vlan_group_set_device(adapter->vlan_grp, vid, NULL);
  516. adapter->vlans_added--;
  517. if (adapter->vlans_added <= adapter->max_vlans)
  518. be_vid_config(adapter);
  519. }
  520. static void be_set_multicast_list(struct net_device *netdev)
  521. {
  522. struct be_adapter *adapter = netdev_priv(netdev);
  523. if (netdev->flags & IFF_PROMISC) {
  524. be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
  525. adapter->promiscuous = true;
  526. goto done;
  527. }
  528. /* BE was previously in promiscous mode; disable it */
  529. if (adapter->promiscuous) {
  530. adapter->promiscuous = false;
  531. be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
  532. }
  533. /* Enable multicast promisc if num configured exceeds what we support */
  534. if (netdev->flags & IFF_ALLMULTI ||
  535. netdev_mc_count(netdev) > BE_MAX_MC) {
  536. be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
  537. &adapter->mc_cmd_mem);
  538. goto done;
  539. }
  540. be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
  541. &adapter->mc_cmd_mem);
  542. done:
  543. return;
  544. }
  545. static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
  546. {
  547. struct be_adapter *adapter = netdev_priv(netdev);
  548. int status;
  549. if (!adapter->sriov_enabled)
  550. return -EPERM;
  551. if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
  552. return -EINVAL;
  553. status = be_cmd_pmac_del(adapter, adapter->vf_if_handle[vf],
  554. adapter->vf_pmac_id[vf]);
  555. status = be_cmd_pmac_add(adapter, mac, adapter->vf_if_handle[vf],
  556. &adapter->vf_pmac_id[vf]);
  557. if (!status)
  558. dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
  559. mac, vf);
  560. return status;
  561. }
  562. static void be_rx_rate_update(struct be_adapter *adapter)
  563. {
  564. struct be_drvr_stats *stats = drvr_stats(adapter);
  565. ulong now = jiffies;
  566. /* Wrapped around */
  567. if (time_before(now, stats->be_rx_jiffies)) {
  568. stats->be_rx_jiffies = now;
  569. return;
  570. }
  571. /* Update the rate once in two seconds */
  572. if ((now - stats->be_rx_jiffies) < 2 * HZ)
  573. return;
  574. stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
  575. - stats->be_rx_bytes_prev,
  576. now - stats->be_rx_jiffies);
  577. stats->be_rx_jiffies = now;
  578. stats->be_rx_bytes_prev = stats->be_rx_bytes;
  579. }
  580. static void be_rx_stats_update(struct be_adapter *adapter,
  581. u32 pktsize, u16 numfrags)
  582. {
  583. struct be_drvr_stats *stats = drvr_stats(adapter);
  584. stats->be_rx_compl++;
  585. stats->be_rx_frags += numfrags;
  586. stats->be_rx_bytes += pktsize;
  587. stats->be_rx_pkts++;
  588. }
  589. static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
  590. {
  591. u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
  592. l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
  593. ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
  594. ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
  595. if (ip_version) {
  596. tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
  597. udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
  598. }
  599. ipv6_chk = (ip_version && (tcpf || udpf));
  600. return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
  601. }
  602. static struct be_rx_page_info *
  603. get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
  604. {
  605. struct be_rx_page_info *rx_page_info;
  606. struct be_queue_info *rxq = &adapter->rx_obj.q;
  607. rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
  608. BUG_ON(!rx_page_info->page);
  609. if (rx_page_info->last_page_user) {
  610. pci_unmap_page(adapter->pdev, dma_unmap_addr(rx_page_info, bus),
  611. adapter->big_page_size, PCI_DMA_FROMDEVICE);
  612. rx_page_info->last_page_user = false;
  613. }
  614. atomic_dec(&rxq->used);
  615. return rx_page_info;
  616. }
  617. /* Throwaway the data in the Rx completion */
  618. static void be_rx_compl_discard(struct be_adapter *adapter,
  619. struct be_eth_rx_compl *rxcp)
  620. {
  621. struct be_queue_info *rxq = &adapter->rx_obj.q;
  622. struct be_rx_page_info *page_info;
  623. u16 rxq_idx, i, num_rcvd;
  624. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  625. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  626. for (i = 0; i < num_rcvd; i++) {
  627. page_info = get_rx_page_info(adapter, rxq_idx);
  628. put_page(page_info->page);
  629. memset(page_info, 0, sizeof(*page_info));
  630. index_inc(&rxq_idx, rxq->len);
  631. }
  632. }
  633. /*
  634. * skb_fill_rx_data forms a complete skb for an ether frame
  635. * indicated by rxcp.
  636. */
  637. static void skb_fill_rx_data(struct be_adapter *adapter,
  638. struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
  639. u16 num_rcvd)
  640. {
  641. struct be_queue_info *rxq = &adapter->rx_obj.q;
  642. struct be_rx_page_info *page_info;
  643. u16 rxq_idx, i, j;
  644. u32 pktsize, hdr_len, curr_frag_len, size;
  645. u8 *start;
  646. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  647. pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
  648. page_info = get_rx_page_info(adapter, rxq_idx);
  649. start = page_address(page_info->page) + page_info->page_offset;
  650. prefetch(start);
  651. /* Copy data in the first descriptor of this completion */
  652. curr_frag_len = min(pktsize, rx_frag_size);
  653. /* Copy the header portion into skb_data */
  654. hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
  655. memcpy(skb->data, start, hdr_len);
  656. skb->len = curr_frag_len;
  657. if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
  658. /* Complete packet has now been moved to data */
  659. put_page(page_info->page);
  660. skb->data_len = 0;
  661. skb->tail += curr_frag_len;
  662. } else {
  663. skb_shinfo(skb)->nr_frags = 1;
  664. skb_shinfo(skb)->frags[0].page = page_info->page;
  665. skb_shinfo(skb)->frags[0].page_offset =
  666. page_info->page_offset + hdr_len;
  667. skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
  668. skb->data_len = curr_frag_len - hdr_len;
  669. skb->tail += hdr_len;
  670. }
  671. page_info->page = NULL;
  672. if (pktsize <= rx_frag_size) {
  673. BUG_ON(num_rcvd != 1);
  674. goto done;
  675. }
  676. /* More frags present for this completion */
  677. size = pktsize;
  678. for (i = 1, j = 0; i < num_rcvd; i++) {
  679. size -= curr_frag_len;
  680. index_inc(&rxq_idx, rxq->len);
  681. page_info = get_rx_page_info(adapter, rxq_idx);
  682. curr_frag_len = min(size, rx_frag_size);
  683. /* Coalesce all frags from the same physical page in one slot */
  684. if (page_info->page_offset == 0) {
  685. /* Fresh page */
  686. j++;
  687. skb_shinfo(skb)->frags[j].page = page_info->page;
  688. skb_shinfo(skb)->frags[j].page_offset =
  689. page_info->page_offset;
  690. skb_shinfo(skb)->frags[j].size = 0;
  691. skb_shinfo(skb)->nr_frags++;
  692. } else {
  693. put_page(page_info->page);
  694. }
  695. skb_shinfo(skb)->frags[j].size += curr_frag_len;
  696. skb->len += curr_frag_len;
  697. skb->data_len += curr_frag_len;
  698. page_info->page = NULL;
  699. }
  700. BUG_ON(j > MAX_SKB_FRAGS);
  701. done:
  702. be_rx_stats_update(adapter, pktsize, num_rcvd);
  703. }
  704. /* Process the RX completion indicated by rxcp when GRO is disabled */
  705. static void be_rx_compl_process(struct be_adapter *adapter,
  706. struct be_eth_rx_compl *rxcp)
  707. {
  708. struct sk_buff *skb;
  709. u32 vlanf, vid;
  710. u16 num_rcvd;
  711. u8 vtm;
  712. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  713. /* Is it a flush compl that has no data */
  714. if (unlikely(num_rcvd == 0))
  715. return;
  716. skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
  717. if (unlikely(!skb)) {
  718. if (net_ratelimit())
  719. dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
  720. be_rx_compl_discard(adapter, rxcp);
  721. return;
  722. }
  723. skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
  724. if (do_pkt_csum(rxcp, adapter->rx_csum))
  725. skb->ip_summed = CHECKSUM_NONE;
  726. else
  727. skb->ip_summed = CHECKSUM_UNNECESSARY;
  728. skb->truesize = skb->len + sizeof(struct sk_buff);
  729. skb->protocol = eth_type_trans(skb, adapter->netdev);
  730. vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
  731. vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
  732. /* vlanf could be wrongly set in some cards.
  733. * ignore if vtm is not set */
  734. if ((adapter->cap & 0x400) && !vtm)
  735. vlanf = 0;
  736. if (unlikely(vlanf)) {
  737. if (!adapter->vlan_grp || adapter->vlans_added == 0) {
  738. kfree_skb(skb);
  739. return;
  740. }
  741. vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
  742. vid = swab16(vid);
  743. vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
  744. } else {
  745. netif_receive_skb(skb);
  746. }
  747. }
  748. /* Process the RX completion indicated by rxcp when GRO is enabled */
  749. static void be_rx_compl_process_gro(struct be_adapter *adapter,
  750. struct be_eth_rx_compl *rxcp)
  751. {
  752. struct be_rx_page_info *page_info;
  753. struct sk_buff *skb = NULL;
  754. struct be_queue_info *rxq = &adapter->rx_obj.q;
  755. struct be_eq_obj *eq_obj = &adapter->rx_eq;
  756. u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
  757. u16 i, rxq_idx = 0, vid, j;
  758. u8 vtm;
  759. num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
  760. /* Is it a flush compl that has no data */
  761. if (unlikely(num_rcvd == 0))
  762. return;
  763. pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
  764. vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
  765. rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
  766. vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
  767. /* vlanf could be wrongly set in some cards.
  768. * ignore if vtm is not set */
  769. if ((adapter->cap & 0x400) && !vtm)
  770. vlanf = 0;
  771. skb = napi_get_frags(&eq_obj->napi);
  772. if (!skb) {
  773. be_rx_compl_discard(adapter, rxcp);
  774. return;
  775. }
  776. remaining = pkt_size;
  777. for (i = 0, j = -1; i < num_rcvd; i++) {
  778. page_info = get_rx_page_info(adapter, rxq_idx);
  779. curr_frag_len = min(remaining, rx_frag_size);
  780. /* Coalesce all frags from the same physical page in one slot */
  781. if (i == 0 || page_info->page_offset == 0) {
  782. /* First frag or Fresh page */
  783. j++;
  784. skb_shinfo(skb)->frags[j].page = page_info->page;
  785. skb_shinfo(skb)->frags[j].page_offset =
  786. page_info->page_offset;
  787. skb_shinfo(skb)->frags[j].size = 0;
  788. } else {
  789. put_page(page_info->page);
  790. }
  791. skb_shinfo(skb)->frags[j].size += curr_frag_len;
  792. remaining -= curr_frag_len;
  793. index_inc(&rxq_idx, rxq->len);
  794. memset(page_info, 0, sizeof(*page_info));
  795. }
  796. BUG_ON(j > MAX_SKB_FRAGS);
  797. skb_shinfo(skb)->nr_frags = j + 1;
  798. skb->len = pkt_size;
  799. skb->data_len = pkt_size;
  800. skb->truesize += pkt_size;
  801. skb->ip_summed = CHECKSUM_UNNECESSARY;
  802. if (likely(!vlanf)) {
  803. napi_gro_frags(&eq_obj->napi);
  804. } else {
  805. vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
  806. vid = swab16(vid);
  807. if (!adapter->vlan_grp || adapter->vlans_added == 0)
  808. return;
  809. vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
  810. }
  811. be_rx_stats_update(adapter, pkt_size, num_rcvd);
  812. }
  813. static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
  814. {
  815. struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
  816. if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
  817. return NULL;
  818. be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
  819. queue_tail_inc(&adapter->rx_obj.cq);
  820. return rxcp;
  821. }
  822. /* To reset the valid bit, we need to reset the whole word as
  823. * when walking the queue the valid entries are little-endian
  824. * and invalid entries are host endian
  825. */
  826. static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
  827. {
  828. rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
  829. }
  830. static inline struct page *be_alloc_pages(u32 size)
  831. {
  832. gfp_t alloc_flags = GFP_ATOMIC;
  833. u32 order = get_order(size);
  834. if (order > 0)
  835. alloc_flags |= __GFP_COMP;
  836. return alloc_pages(alloc_flags, order);
  837. }
  838. /*
  839. * Allocate a page, split it to fragments of size rx_frag_size and post as
  840. * receive buffers to BE
  841. */
  842. static void be_post_rx_frags(struct be_adapter *adapter)
  843. {
  844. struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
  845. struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
  846. struct be_queue_info *rxq = &adapter->rx_obj.q;
  847. struct page *pagep = NULL;
  848. struct be_eth_rx_d *rxd;
  849. u64 page_dmaaddr = 0, frag_dmaaddr;
  850. u32 posted, page_offset = 0;
  851. page_info = &page_info_tbl[rxq->head];
  852. for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
  853. if (!pagep) {
  854. pagep = be_alloc_pages(adapter->big_page_size);
  855. if (unlikely(!pagep)) {
  856. drvr_stats(adapter)->be_ethrx_post_fail++;
  857. break;
  858. }
  859. page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
  860. adapter->big_page_size,
  861. PCI_DMA_FROMDEVICE);
  862. page_info->page_offset = 0;
  863. } else {
  864. get_page(pagep);
  865. page_info->page_offset = page_offset + rx_frag_size;
  866. }
  867. page_offset = page_info->page_offset;
  868. page_info->page = pagep;
  869. dma_unmap_addr_set(page_info, bus, page_dmaaddr);
  870. frag_dmaaddr = page_dmaaddr + page_info->page_offset;
  871. rxd = queue_head_node(rxq);
  872. rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
  873. rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
  874. /* Any space left in the current big page for another frag? */
  875. if ((page_offset + rx_frag_size + rx_frag_size) >
  876. adapter->big_page_size) {
  877. pagep = NULL;
  878. page_info->last_page_user = true;
  879. }
  880. prev_page_info = page_info;
  881. queue_head_inc(rxq);
  882. page_info = &page_info_tbl[rxq->head];
  883. }
  884. if (pagep)
  885. prev_page_info->last_page_user = true;
  886. if (posted) {
  887. atomic_add(posted, &rxq->used);
  888. be_rxq_notify(adapter, rxq->id, posted);
  889. } else if (atomic_read(&rxq->used) == 0) {
  890. /* Let be_worker replenish when memory is available */
  891. adapter->rx_post_starved = true;
  892. }
  893. }
  894. static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
  895. {
  896. struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
  897. if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
  898. return NULL;
  899. be_dws_le_to_cpu(txcp, sizeof(*txcp));
  900. txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
  901. queue_tail_inc(tx_cq);
  902. return txcp;
  903. }
  904. static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
  905. {
  906. struct be_queue_info *txq = &adapter->tx_obj.q;
  907. struct be_eth_wrb *wrb;
  908. struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
  909. struct sk_buff *sent_skb;
  910. u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
  911. bool unmap_skb_hdr = true;
  912. sent_skb = sent_skbs[txq->tail];
  913. BUG_ON(!sent_skb);
  914. sent_skbs[txq->tail] = NULL;
  915. /* skip header wrb */
  916. queue_tail_inc(txq);
  917. do {
  918. cur_index = txq->tail;
  919. wrb = queue_tail_node(txq);
  920. unmap_tx_frag(adapter->pdev, wrb, (unmap_skb_hdr &&
  921. skb_headlen(sent_skb)));
  922. unmap_skb_hdr = false;
  923. num_wrbs++;
  924. queue_tail_inc(txq);
  925. } while (cur_index != last_index);
  926. atomic_sub(num_wrbs, &txq->used);
  927. kfree_skb(sent_skb);
  928. }
  929. static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
  930. {
  931. struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
  932. if (!eqe->evt)
  933. return NULL;
  934. eqe->evt = le32_to_cpu(eqe->evt);
  935. queue_tail_inc(&eq_obj->q);
  936. return eqe;
  937. }
  938. static int event_handle(struct be_adapter *adapter,
  939. struct be_eq_obj *eq_obj)
  940. {
  941. struct be_eq_entry *eqe;
  942. u16 num = 0;
  943. while ((eqe = event_get(eq_obj)) != NULL) {
  944. eqe->evt = 0;
  945. num++;
  946. }
  947. /* Deal with any spurious interrupts that come
  948. * without events
  949. */
  950. be_eq_notify(adapter, eq_obj->q.id, true, true, num);
  951. if (num)
  952. napi_schedule(&eq_obj->napi);
  953. return num;
  954. }
  955. /* Just read and notify events without processing them.
  956. * Used at the time of destroying event queues */
  957. static void be_eq_clean(struct be_adapter *adapter,
  958. struct be_eq_obj *eq_obj)
  959. {
  960. struct be_eq_entry *eqe;
  961. u16 num = 0;
  962. while ((eqe = event_get(eq_obj)) != NULL) {
  963. eqe->evt = 0;
  964. num++;
  965. }
  966. if (num)
  967. be_eq_notify(adapter, eq_obj->q.id, false, true, num);
  968. }
  969. static void be_rx_q_clean(struct be_adapter *adapter)
  970. {
  971. struct be_rx_page_info *page_info;
  972. struct be_queue_info *rxq = &adapter->rx_obj.q;
  973. struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
  974. struct be_eth_rx_compl *rxcp;
  975. u16 tail;
  976. /* First cleanup pending rx completions */
  977. while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
  978. be_rx_compl_discard(adapter, rxcp);
  979. be_rx_compl_reset(rxcp);
  980. be_cq_notify(adapter, rx_cq->id, true, 1);
  981. }
  982. /* Then free posted rx buffer that were not used */
  983. tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
  984. for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
  985. page_info = get_rx_page_info(adapter, tail);
  986. put_page(page_info->page);
  987. memset(page_info, 0, sizeof(*page_info));
  988. }
  989. BUG_ON(atomic_read(&rxq->used));
  990. }
  991. static void be_tx_compl_clean(struct be_adapter *adapter)
  992. {
  993. struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
  994. struct be_queue_info *txq = &adapter->tx_obj.q;
  995. struct be_eth_tx_compl *txcp;
  996. u16 end_idx, cmpl = 0, timeo = 0;
  997. struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
  998. struct sk_buff *sent_skb;
  999. bool dummy_wrb;
  1000. /* Wait for a max of 200ms for all the tx-completions to arrive. */
  1001. do {
  1002. while ((txcp = be_tx_compl_get(tx_cq))) {
  1003. end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
  1004. wrb_index, txcp);
  1005. be_tx_compl_process(adapter, end_idx);
  1006. cmpl++;
  1007. }
  1008. if (cmpl) {
  1009. be_cq_notify(adapter, tx_cq->id, false, cmpl);
  1010. cmpl = 0;
  1011. }
  1012. if (atomic_read(&txq->used) == 0 || ++timeo > 200)
  1013. break;
  1014. mdelay(1);
  1015. } while (true);
  1016. if (atomic_read(&txq->used))
  1017. dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
  1018. atomic_read(&txq->used));
  1019. /* free posted tx for which compls will never arrive */
  1020. while (atomic_read(&txq->used)) {
  1021. sent_skb = sent_skbs[txq->tail];
  1022. end_idx = txq->tail;
  1023. index_adv(&end_idx,
  1024. wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
  1025. be_tx_compl_process(adapter, end_idx);
  1026. }
  1027. }
  1028. static void be_mcc_queues_destroy(struct be_adapter *adapter)
  1029. {
  1030. struct be_queue_info *q;
  1031. q = &adapter->mcc_obj.q;
  1032. if (q->created)
  1033. be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
  1034. be_queue_free(adapter, q);
  1035. q = &adapter->mcc_obj.cq;
  1036. if (q->created)
  1037. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1038. be_queue_free(adapter, q);
  1039. }
  1040. /* Must be called only after TX qs are created as MCC shares TX EQ */
  1041. static int be_mcc_queues_create(struct be_adapter *adapter)
  1042. {
  1043. struct be_queue_info *q, *cq;
  1044. /* Alloc MCC compl queue */
  1045. cq = &adapter->mcc_obj.cq;
  1046. if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
  1047. sizeof(struct be_mcc_compl)))
  1048. goto err;
  1049. /* Ask BE to create MCC compl queue; share TX's eq */
  1050. if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
  1051. goto mcc_cq_free;
  1052. /* Alloc MCC queue */
  1053. q = &adapter->mcc_obj.q;
  1054. if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  1055. goto mcc_cq_destroy;
  1056. /* Ask BE to create MCC queue */
  1057. if (be_cmd_mccq_create(adapter, q, cq))
  1058. goto mcc_q_free;
  1059. return 0;
  1060. mcc_q_free:
  1061. be_queue_free(adapter, q);
  1062. mcc_cq_destroy:
  1063. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1064. mcc_cq_free:
  1065. be_queue_free(adapter, cq);
  1066. err:
  1067. return -1;
  1068. }
  1069. static void be_tx_queues_destroy(struct be_adapter *adapter)
  1070. {
  1071. struct be_queue_info *q;
  1072. q = &adapter->tx_obj.q;
  1073. if (q->created)
  1074. be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
  1075. be_queue_free(adapter, q);
  1076. q = &adapter->tx_obj.cq;
  1077. if (q->created)
  1078. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1079. be_queue_free(adapter, q);
  1080. /* Clear any residual events */
  1081. be_eq_clean(adapter, &adapter->tx_eq);
  1082. q = &adapter->tx_eq.q;
  1083. if (q->created)
  1084. be_cmd_q_destroy(adapter, q, QTYPE_EQ);
  1085. be_queue_free(adapter, q);
  1086. }
  1087. static int be_tx_queues_create(struct be_adapter *adapter)
  1088. {
  1089. struct be_queue_info *eq, *q, *cq;
  1090. adapter->tx_eq.max_eqd = 0;
  1091. adapter->tx_eq.min_eqd = 0;
  1092. adapter->tx_eq.cur_eqd = 96;
  1093. adapter->tx_eq.enable_aic = false;
  1094. /* Alloc Tx Event queue */
  1095. eq = &adapter->tx_eq.q;
  1096. if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
  1097. return -1;
  1098. /* Ask BE to create Tx Event queue */
  1099. if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
  1100. goto tx_eq_free;
  1101. adapter->base_eq_id = adapter->tx_eq.q.id;
  1102. /* Alloc TX eth compl queue */
  1103. cq = &adapter->tx_obj.cq;
  1104. if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
  1105. sizeof(struct be_eth_tx_compl)))
  1106. goto tx_eq_destroy;
  1107. /* Ask BE to create Tx eth compl queue */
  1108. if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
  1109. goto tx_cq_free;
  1110. /* Alloc TX eth queue */
  1111. q = &adapter->tx_obj.q;
  1112. if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
  1113. goto tx_cq_destroy;
  1114. /* Ask BE to create Tx eth queue */
  1115. if (be_cmd_txq_create(adapter, q, cq))
  1116. goto tx_q_free;
  1117. return 0;
  1118. tx_q_free:
  1119. be_queue_free(adapter, q);
  1120. tx_cq_destroy:
  1121. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1122. tx_cq_free:
  1123. be_queue_free(adapter, cq);
  1124. tx_eq_destroy:
  1125. be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
  1126. tx_eq_free:
  1127. be_queue_free(adapter, eq);
  1128. return -1;
  1129. }
  1130. static void be_rx_queues_destroy(struct be_adapter *adapter)
  1131. {
  1132. struct be_queue_info *q;
  1133. q = &adapter->rx_obj.q;
  1134. if (q->created) {
  1135. be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
  1136. /* After the rxq is invalidated, wait for a grace time
  1137. * of 1ms for all dma to end and the flush compl to arrive
  1138. */
  1139. mdelay(1);
  1140. be_rx_q_clean(adapter);
  1141. }
  1142. be_queue_free(adapter, q);
  1143. q = &adapter->rx_obj.cq;
  1144. if (q->created)
  1145. be_cmd_q_destroy(adapter, q, QTYPE_CQ);
  1146. be_queue_free(adapter, q);
  1147. /* Clear any residual events */
  1148. be_eq_clean(adapter, &adapter->rx_eq);
  1149. q = &adapter->rx_eq.q;
  1150. if (q->created)
  1151. be_cmd_q_destroy(adapter, q, QTYPE_EQ);
  1152. be_queue_free(adapter, q);
  1153. }
  1154. static int be_rx_queues_create(struct be_adapter *adapter)
  1155. {
  1156. struct be_queue_info *eq, *q, *cq;
  1157. int rc;
  1158. adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
  1159. adapter->rx_eq.max_eqd = BE_MAX_EQD;
  1160. adapter->rx_eq.min_eqd = 0;
  1161. adapter->rx_eq.cur_eqd = 0;
  1162. adapter->rx_eq.enable_aic = true;
  1163. /* Alloc Rx Event queue */
  1164. eq = &adapter->rx_eq.q;
  1165. rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
  1166. sizeof(struct be_eq_entry));
  1167. if (rc)
  1168. return rc;
  1169. /* Ask BE to create Rx Event queue */
  1170. rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
  1171. if (rc)
  1172. goto rx_eq_free;
  1173. /* Alloc RX eth compl queue */
  1174. cq = &adapter->rx_obj.cq;
  1175. rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
  1176. sizeof(struct be_eth_rx_compl));
  1177. if (rc)
  1178. goto rx_eq_destroy;
  1179. /* Ask BE to create Rx eth compl queue */
  1180. rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
  1181. if (rc)
  1182. goto rx_cq_free;
  1183. /* Alloc RX eth queue */
  1184. q = &adapter->rx_obj.q;
  1185. rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
  1186. if (rc)
  1187. goto rx_cq_destroy;
  1188. /* Ask BE to create Rx eth queue */
  1189. rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
  1190. BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
  1191. if (rc)
  1192. goto rx_q_free;
  1193. return 0;
  1194. rx_q_free:
  1195. be_queue_free(adapter, q);
  1196. rx_cq_destroy:
  1197. be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
  1198. rx_cq_free:
  1199. be_queue_free(adapter, cq);
  1200. rx_eq_destroy:
  1201. be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
  1202. rx_eq_free:
  1203. be_queue_free(adapter, eq);
  1204. return rc;
  1205. }
  1206. /* There are 8 evt ids per func. Retruns the evt id's bit number */
  1207. static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
  1208. {
  1209. return eq_id - adapter->base_eq_id;
  1210. }
  1211. static irqreturn_t be_intx(int irq, void *dev)
  1212. {
  1213. struct be_adapter *adapter = dev;
  1214. int isr;
  1215. isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
  1216. (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
  1217. if (!isr)
  1218. return IRQ_NONE;
  1219. event_handle(adapter, &adapter->tx_eq);
  1220. event_handle(adapter, &adapter->rx_eq);
  1221. return IRQ_HANDLED;
  1222. }
  1223. static irqreturn_t be_msix_rx(int irq, void *dev)
  1224. {
  1225. struct be_adapter *adapter = dev;
  1226. event_handle(adapter, &adapter->rx_eq);
  1227. return IRQ_HANDLED;
  1228. }
  1229. static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
  1230. {
  1231. struct be_adapter *adapter = dev;
  1232. event_handle(adapter, &adapter->tx_eq);
  1233. return IRQ_HANDLED;
  1234. }
  1235. static inline bool do_gro(struct be_adapter *adapter,
  1236. struct be_eth_rx_compl *rxcp)
  1237. {
  1238. int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
  1239. int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
  1240. if (err)
  1241. drvr_stats(adapter)->be_rxcp_err++;
  1242. return (tcp_frame && !err) ? true : false;
  1243. }
  1244. int be_poll_rx(struct napi_struct *napi, int budget)
  1245. {
  1246. struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
  1247. struct be_adapter *adapter =
  1248. container_of(rx_eq, struct be_adapter, rx_eq);
  1249. struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
  1250. struct be_eth_rx_compl *rxcp;
  1251. u32 work_done;
  1252. adapter->stats.drvr_stats.be_rx_polls++;
  1253. for (work_done = 0; work_done < budget; work_done++) {
  1254. rxcp = be_rx_compl_get(adapter);
  1255. if (!rxcp)
  1256. break;
  1257. if (do_gro(adapter, rxcp))
  1258. be_rx_compl_process_gro(adapter, rxcp);
  1259. else
  1260. be_rx_compl_process(adapter, rxcp);
  1261. be_rx_compl_reset(rxcp);
  1262. }
  1263. /* Refill the queue */
  1264. if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
  1265. be_post_rx_frags(adapter);
  1266. /* All consumed */
  1267. if (work_done < budget) {
  1268. napi_complete(napi);
  1269. be_cq_notify(adapter, rx_cq->id, true, work_done);
  1270. } else {
  1271. /* More to be consumed; continue with interrupts disabled */
  1272. be_cq_notify(adapter, rx_cq->id, false, work_done);
  1273. }
  1274. return work_done;
  1275. }
  1276. /* As TX and MCC share the same EQ check for both TX and MCC completions.
  1277. * For TX/MCC we don't honour budget; consume everything
  1278. */
  1279. static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
  1280. {
  1281. struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
  1282. struct be_adapter *adapter =
  1283. container_of(tx_eq, struct be_adapter, tx_eq);
  1284. struct be_queue_info *txq = &adapter->tx_obj.q;
  1285. struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
  1286. struct be_eth_tx_compl *txcp;
  1287. int tx_compl = 0, mcc_compl, status = 0;
  1288. u16 end_idx;
  1289. while ((txcp = be_tx_compl_get(tx_cq))) {
  1290. end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
  1291. wrb_index, txcp);
  1292. be_tx_compl_process(adapter, end_idx);
  1293. tx_compl++;
  1294. }
  1295. mcc_compl = be_process_mcc(adapter, &status);
  1296. napi_complete(napi);
  1297. if (mcc_compl) {
  1298. struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
  1299. be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
  1300. }
  1301. if (tx_compl) {
  1302. be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
  1303. /* As Tx wrbs have been freed up, wake up netdev queue if
  1304. * it was stopped due to lack of tx wrbs.
  1305. */
  1306. if (netif_queue_stopped(adapter->netdev) &&
  1307. atomic_read(&txq->used) < txq->len / 2) {
  1308. netif_wake_queue(adapter->netdev);
  1309. }
  1310. drvr_stats(adapter)->be_tx_events++;
  1311. drvr_stats(adapter)->be_tx_compl += tx_compl;
  1312. }
  1313. return 1;
  1314. }
  1315. static void be_worker(struct work_struct *work)
  1316. {
  1317. struct be_adapter *adapter =
  1318. container_of(work, struct be_adapter, work.work);
  1319. be_cmd_get_stats(adapter, &adapter->stats.cmd);
  1320. /* Set EQ delay */
  1321. be_rx_eqd_update(adapter);
  1322. be_tx_rate_update(adapter);
  1323. be_rx_rate_update(adapter);
  1324. if (adapter->rx_post_starved) {
  1325. adapter->rx_post_starved = false;
  1326. be_post_rx_frags(adapter);
  1327. }
  1328. schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
  1329. }
  1330. static void be_msix_disable(struct be_adapter *adapter)
  1331. {
  1332. if (adapter->msix_enabled) {
  1333. pci_disable_msix(adapter->pdev);
  1334. adapter->msix_enabled = false;
  1335. }
  1336. }
  1337. static void be_msix_enable(struct be_adapter *adapter)
  1338. {
  1339. int i, status;
  1340. for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
  1341. adapter->msix_entries[i].entry = i;
  1342. status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
  1343. BE_NUM_MSIX_VECTORS);
  1344. if (status == 0)
  1345. adapter->msix_enabled = true;
  1346. }
  1347. static void be_sriov_enable(struct be_adapter *adapter)
  1348. {
  1349. #ifdef CONFIG_PCI_IOV
  1350. int status;
  1351. if (be_physfn(adapter) && num_vfs) {
  1352. status = pci_enable_sriov(adapter->pdev, num_vfs);
  1353. adapter->sriov_enabled = status ? false : true;
  1354. }
  1355. #endif
  1356. }
  1357. static void be_sriov_disable(struct be_adapter *adapter)
  1358. {
  1359. #ifdef CONFIG_PCI_IOV
  1360. if (adapter->sriov_enabled) {
  1361. pci_disable_sriov(adapter->pdev);
  1362. adapter->sriov_enabled = false;
  1363. }
  1364. #endif
  1365. }
  1366. static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
  1367. {
  1368. return adapter->msix_entries[
  1369. be_evt_bit_get(adapter, eq_id)].vector;
  1370. }
  1371. static int be_request_irq(struct be_adapter *adapter,
  1372. struct be_eq_obj *eq_obj,
  1373. void *handler, char *desc)
  1374. {
  1375. struct net_device *netdev = adapter->netdev;
  1376. int vec;
  1377. sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
  1378. vec = be_msix_vec_get(adapter, eq_obj->q.id);
  1379. return request_irq(vec, handler, 0, eq_obj->desc, adapter);
  1380. }
  1381. static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
  1382. {
  1383. int vec = be_msix_vec_get(adapter, eq_obj->q.id);
  1384. free_irq(vec, adapter);
  1385. }
  1386. static int be_msix_register(struct be_adapter *adapter)
  1387. {
  1388. int status;
  1389. status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
  1390. if (status)
  1391. goto err;
  1392. status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
  1393. if (status)
  1394. goto free_tx_irq;
  1395. return 0;
  1396. free_tx_irq:
  1397. be_free_irq(adapter, &adapter->tx_eq);
  1398. err:
  1399. dev_warn(&adapter->pdev->dev,
  1400. "MSIX Request IRQ failed - err %d\n", status);
  1401. pci_disable_msix(adapter->pdev);
  1402. adapter->msix_enabled = false;
  1403. return status;
  1404. }
  1405. static int be_irq_register(struct be_adapter *adapter)
  1406. {
  1407. struct net_device *netdev = adapter->netdev;
  1408. int status;
  1409. if (adapter->msix_enabled) {
  1410. status = be_msix_register(adapter);
  1411. if (status == 0)
  1412. goto done;
  1413. /* INTx is not supported for VF */
  1414. if (!be_physfn(adapter))
  1415. return status;
  1416. }
  1417. /* INTx */
  1418. netdev->irq = adapter->pdev->irq;
  1419. status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
  1420. adapter);
  1421. if (status) {
  1422. dev_err(&adapter->pdev->dev,
  1423. "INTx request IRQ failed - err %d\n", status);
  1424. return status;
  1425. }
  1426. done:
  1427. adapter->isr_registered = true;
  1428. return 0;
  1429. }
  1430. static void be_irq_unregister(struct be_adapter *adapter)
  1431. {
  1432. struct net_device *netdev = adapter->netdev;
  1433. if (!adapter->isr_registered)
  1434. return;
  1435. /* INTx */
  1436. if (!adapter->msix_enabled) {
  1437. free_irq(netdev->irq, adapter);
  1438. goto done;
  1439. }
  1440. /* MSIx */
  1441. be_free_irq(adapter, &adapter->tx_eq);
  1442. be_free_irq(adapter, &adapter->rx_eq);
  1443. done:
  1444. adapter->isr_registered = false;
  1445. }
  1446. static int be_open(struct net_device *netdev)
  1447. {
  1448. struct be_adapter *adapter = netdev_priv(netdev);
  1449. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  1450. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  1451. bool link_up;
  1452. int status;
  1453. u8 mac_speed;
  1454. u16 link_speed;
  1455. /* First time posting */
  1456. be_post_rx_frags(adapter);
  1457. napi_enable(&rx_eq->napi);
  1458. napi_enable(&tx_eq->napi);
  1459. be_irq_register(adapter);
  1460. be_intr_set(adapter, true);
  1461. /* The evt queues are created in unarmed state; arm them */
  1462. be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
  1463. be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
  1464. /* Rx compl queue may be in unarmed state; rearm it */
  1465. be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
  1466. /* Now that interrupts are on we can process async mcc */
  1467. be_async_mcc_enable(adapter);
  1468. status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
  1469. &link_speed);
  1470. if (status)
  1471. goto ret_sts;
  1472. be_link_status_update(adapter, link_up);
  1473. if (be_physfn(adapter))
  1474. status = be_vid_config(adapter);
  1475. if (status)
  1476. goto ret_sts;
  1477. if (be_physfn(adapter)) {
  1478. status = be_cmd_set_flow_control(adapter,
  1479. adapter->tx_fc, adapter->rx_fc);
  1480. if (status)
  1481. goto ret_sts;
  1482. }
  1483. schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
  1484. ret_sts:
  1485. return status;
  1486. }
  1487. static int be_setup_wol(struct be_adapter *adapter, bool enable)
  1488. {
  1489. struct be_dma_mem cmd;
  1490. int status = 0;
  1491. u8 mac[ETH_ALEN];
  1492. memset(mac, 0, ETH_ALEN);
  1493. cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
  1494. cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
  1495. if (cmd.va == NULL)
  1496. return -1;
  1497. memset(cmd.va, 0, cmd.size);
  1498. if (enable) {
  1499. status = pci_write_config_dword(adapter->pdev,
  1500. PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
  1501. if (status) {
  1502. dev_err(&adapter->pdev->dev,
  1503. "Could not enable Wake-on-lan\n");
  1504. pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
  1505. cmd.dma);
  1506. return status;
  1507. }
  1508. status = be_cmd_enable_magic_wol(adapter,
  1509. adapter->netdev->dev_addr, &cmd);
  1510. pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
  1511. pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
  1512. } else {
  1513. status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
  1514. pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
  1515. pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
  1516. }
  1517. pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
  1518. return status;
  1519. }
  1520. static int be_setup(struct be_adapter *adapter)
  1521. {
  1522. struct net_device *netdev = adapter->netdev;
  1523. u32 cap_flags, en_flags, vf = 0;
  1524. int status;
  1525. u8 mac[ETH_ALEN];
  1526. cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST;
  1527. if (be_physfn(adapter)) {
  1528. cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
  1529. BE_IF_FLAGS_PROMISCUOUS |
  1530. BE_IF_FLAGS_PASS_L3L4_ERRORS;
  1531. en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
  1532. }
  1533. status = be_cmd_if_create(adapter, cap_flags, en_flags,
  1534. netdev->dev_addr, false/* pmac_invalid */,
  1535. &adapter->if_handle, &adapter->pmac_id, 0);
  1536. if (status != 0)
  1537. goto do_none;
  1538. if (be_physfn(adapter)) {
  1539. while (vf < num_vfs) {
  1540. cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED
  1541. | BE_IF_FLAGS_BROADCAST;
  1542. status = be_cmd_if_create(adapter, cap_flags, en_flags,
  1543. mac, true, &adapter->vf_if_handle[vf],
  1544. NULL, vf+1);
  1545. if (status) {
  1546. dev_err(&adapter->pdev->dev,
  1547. "Interface Create failed for VF %d\n", vf);
  1548. goto if_destroy;
  1549. }
  1550. vf++;
  1551. } while (vf < num_vfs);
  1552. } else if (!be_physfn(adapter)) {
  1553. status = be_cmd_mac_addr_query(adapter, mac,
  1554. MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
  1555. if (!status) {
  1556. memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
  1557. memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
  1558. }
  1559. }
  1560. status = be_tx_queues_create(adapter);
  1561. if (status != 0)
  1562. goto if_destroy;
  1563. status = be_rx_queues_create(adapter);
  1564. if (status != 0)
  1565. goto tx_qs_destroy;
  1566. status = be_mcc_queues_create(adapter);
  1567. if (status != 0)
  1568. goto rx_qs_destroy;
  1569. adapter->link_speed = -1;
  1570. return 0;
  1571. rx_qs_destroy:
  1572. be_rx_queues_destroy(adapter);
  1573. tx_qs_destroy:
  1574. be_tx_queues_destroy(adapter);
  1575. if_destroy:
  1576. for (vf = 0; vf < num_vfs; vf++)
  1577. if (adapter->vf_if_handle[vf])
  1578. be_cmd_if_destroy(adapter, adapter->vf_if_handle[vf]);
  1579. be_cmd_if_destroy(adapter, adapter->if_handle);
  1580. do_none:
  1581. return status;
  1582. }
  1583. static int be_clear(struct be_adapter *adapter)
  1584. {
  1585. be_mcc_queues_destroy(adapter);
  1586. be_rx_queues_destroy(adapter);
  1587. be_tx_queues_destroy(adapter);
  1588. be_cmd_if_destroy(adapter, adapter->if_handle);
  1589. /* tell fw we're done with firing cmds */
  1590. be_cmd_fw_clean(adapter);
  1591. return 0;
  1592. }
  1593. static int be_close(struct net_device *netdev)
  1594. {
  1595. struct be_adapter *adapter = netdev_priv(netdev);
  1596. struct be_eq_obj *rx_eq = &adapter->rx_eq;
  1597. struct be_eq_obj *tx_eq = &adapter->tx_eq;
  1598. int vec;
  1599. cancel_delayed_work_sync(&adapter->work);
  1600. be_async_mcc_disable(adapter);
  1601. netif_stop_queue(netdev);
  1602. netif_carrier_off(netdev);
  1603. adapter->link_up = false;
  1604. be_intr_set(adapter, false);
  1605. if (adapter->msix_enabled) {
  1606. vec = be_msix_vec_get(adapter, tx_eq->q.id);
  1607. synchronize_irq(vec);
  1608. vec = be_msix_vec_get(adapter, rx_eq->q.id);
  1609. synchronize_irq(vec);
  1610. } else {
  1611. synchronize_irq(netdev->irq);
  1612. }
  1613. be_irq_unregister(adapter);
  1614. napi_disable(&rx_eq->napi);
  1615. napi_disable(&tx_eq->napi);
  1616. /* Wait for all pending tx completions to arrive so that
  1617. * all tx skbs are freed.
  1618. */
  1619. be_tx_compl_clean(adapter);
  1620. return 0;
  1621. }
  1622. #define FW_FILE_HDR_SIGN "ServerEngines Corp. "
  1623. char flash_cookie[2][16] = {"*** SE FLAS",
  1624. "H DIRECTORY *** "};
  1625. static bool be_flash_redboot(struct be_adapter *adapter,
  1626. const u8 *p, u32 img_start, int image_size,
  1627. int hdr_size)
  1628. {
  1629. u32 crc_offset;
  1630. u8 flashed_crc[4];
  1631. int status;
  1632. crc_offset = hdr_size + img_start + image_size - 4;
  1633. p += crc_offset;
  1634. status = be_cmd_get_flash_crc(adapter, flashed_crc,
  1635. (image_size - 4));
  1636. if (status) {
  1637. dev_err(&adapter->pdev->dev,
  1638. "could not get crc from flash, not flashing redboot\n");
  1639. return false;
  1640. }
  1641. /*update redboot only if crc does not match*/
  1642. if (!memcmp(flashed_crc, p, 4))
  1643. return false;
  1644. else
  1645. return true;
  1646. }
  1647. static int be_flash_data(struct be_adapter *adapter,
  1648. const struct firmware *fw,
  1649. struct be_dma_mem *flash_cmd, int num_of_images)
  1650. {
  1651. int status = 0, i, filehdr_size = 0;
  1652. u32 total_bytes = 0, flash_op;
  1653. int num_bytes;
  1654. const u8 *p = fw->data;
  1655. struct be_cmd_write_flashrom *req = flash_cmd->va;
  1656. struct flash_comp *pflashcomp;
  1657. int num_comp;
  1658. struct flash_comp gen3_flash_types[9] = {
  1659. { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
  1660. FLASH_IMAGE_MAX_SIZE_g3},
  1661. { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
  1662. FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
  1663. { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
  1664. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1665. { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
  1666. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1667. { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
  1668. FLASH_BIOS_IMAGE_MAX_SIZE_g3},
  1669. { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
  1670. FLASH_IMAGE_MAX_SIZE_g3},
  1671. { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
  1672. FLASH_IMAGE_MAX_SIZE_g3},
  1673. { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
  1674. FLASH_IMAGE_MAX_SIZE_g3},
  1675. { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
  1676. FLASH_NCSI_IMAGE_MAX_SIZE_g3}
  1677. };
  1678. struct flash_comp gen2_flash_types[8] = {
  1679. { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
  1680. FLASH_IMAGE_MAX_SIZE_g2},
  1681. { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
  1682. FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
  1683. { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
  1684. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1685. { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
  1686. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1687. { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
  1688. FLASH_BIOS_IMAGE_MAX_SIZE_g2},
  1689. { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
  1690. FLASH_IMAGE_MAX_SIZE_g2},
  1691. { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
  1692. FLASH_IMAGE_MAX_SIZE_g2},
  1693. { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
  1694. FLASH_IMAGE_MAX_SIZE_g2}
  1695. };
  1696. if (adapter->generation == BE_GEN3) {
  1697. pflashcomp = gen3_flash_types;
  1698. filehdr_size = sizeof(struct flash_file_hdr_g3);
  1699. num_comp = 9;
  1700. } else {
  1701. pflashcomp = gen2_flash_types;
  1702. filehdr_size = sizeof(struct flash_file_hdr_g2);
  1703. num_comp = 8;
  1704. }
  1705. for (i = 0; i < num_comp; i++) {
  1706. if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
  1707. memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
  1708. continue;
  1709. if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
  1710. (!be_flash_redboot(adapter, fw->data,
  1711. pflashcomp[i].offset, pflashcomp[i].size,
  1712. filehdr_size)))
  1713. continue;
  1714. p = fw->data;
  1715. p += filehdr_size + pflashcomp[i].offset
  1716. + (num_of_images * sizeof(struct image_hdr));
  1717. if (p + pflashcomp[i].size > fw->data + fw->size)
  1718. return -1;
  1719. total_bytes = pflashcomp[i].size;
  1720. while (total_bytes) {
  1721. if (total_bytes > 32*1024)
  1722. num_bytes = 32*1024;
  1723. else
  1724. num_bytes = total_bytes;
  1725. total_bytes -= num_bytes;
  1726. if (!total_bytes)
  1727. flash_op = FLASHROM_OPER_FLASH;
  1728. else
  1729. flash_op = FLASHROM_OPER_SAVE;
  1730. memcpy(req->params.data_buf, p, num_bytes);
  1731. p += num_bytes;
  1732. status = be_cmd_write_flashrom(adapter, flash_cmd,
  1733. pflashcomp[i].optype, flash_op, num_bytes);
  1734. if (status) {
  1735. dev_err(&adapter->pdev->dev,
  1736. "cmd to write to flash rom failed.\n");
  1737. return -1;
  1738. }
  1739. yield();
  1740. }
  1741. }
  1742. return 0;
  1743. }
  1744. static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
  1745. {
  1746. if (fhdr == NULL)
  1747. return 0;
  1748. if (fhdr->build[0] == '3')
  1749. return BE_GEN3;
  1750. else if (fhdr->build[0] == '2')
  1751. return BE_GEN2;
  1752. else
  1753. return 0;
  1754. }
  1755. int be_load_fw(struct be_adapter *adapter, u8 *func)
  1756. {
  1757. char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
  1758. const struct firmware *fw;
  1759. struct flash_file_hdr_g2 *fhdr;
  1760. struct flash_file_hdr_g3 *fhdr3;
  1761. struct image_hdr *img_hdr_ptr = NULL;
  1762. struct be_dma_mem flash_cmd;
  1763. int status, i = 0, num_imgs = 0;
  1764. const u8 *p;
  1765. strcpy(fw_file, func);
  1766. status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
  1767. if (status)
  1768. goto fw_exit;
  1769. p = fw->data;
  1770. fhdr = (struct flash_file_hdr_g2 *) p;
  1771. dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
  1772. flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
  1773. flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
  1774. &flash_cmd.dma);
  1775. if (!flash_cmd.va) {
  1776. status = -ENOMEM;
  1777. dev_err(&adapter->pdev->dev,
  1778. "Memory allocation failure while flashing\n");
  1779. goto fw_exit;
  1780. }
  1781. if ((adapter->generation == BE_GEN3) &&
  1782. (get_ufigen_type(fhdr) == BE_GEN3)) {
  1783. fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
  1784. num_imgs = le32_to_cpu(fhdr3->num_imgs);
  1785. for (i = 0; i < num_imgs; i++) {
  1786. img_hdr_ptr = (struct image_hdr *) (fw->data +
  1787. (sizeof(struct flash_file_hdr_g3) +
  1788. i * sizeof(struct image_hdr)));
  1789. if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
  1790. status = be_flash_data(adapter, fw, &flash_cmd,
  1791. num_imgs);
  1792. }
  1793. } else if ((adapter->generation == BE_GEN2) &&
  1794. (get_ufigen_type(fhdr) == BE_GEN2)) {
  1795. status = be_flash_data(adapter, fw, &flash_cmd, 0);
  1796. } else {
  1797. dev_err(&adapter->pdev->dev,
  1798. "UFI and Interface are not compatible for flashing\n");
  1799. status = -1;
  1800. }
  1801. pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
  1802. flash_cmd.dma);
  1803. if (status) {
  1804. dev_err(&adapter->pdev->dev, "Firmware load error\n");
  1805. goto fw_exit;
  1806. }
  1807. dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
  1808. fw_exit:
  1809. release_firmware(fw);
  1810. return status;
  1811. }
  1812. static struct net_device_ops be_netdev_ops = {
  1813. .ndo_open = be_open,
  1814. .ndo_stop = be_close,
  1815. .ndo_start_xmit = be_xmit,
  1816. .ndo_get_stats = be_get_stats,
  1817. .ndo_set_rx_mode = be_set_multicast_list,
  1818. .ndo_set_mac_address = be_mac_addr_set,
  1819. .ndo_change_mtu = be_change_mtu,
  1820. .ndo_validate_addr = eth_validate_addr,
  1821. .ndo_vlan_rx_register = be_vlan_register,
  1822. .ndo_vlan_rx_add_vid = be_vlan_add_vid,
  1823. .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
  1824. .ndo_set_vf_mac = be_set_vf_mac
  1825. };
  1826. static void be_netdev_init(struct net_device *netdev)
  1827. {
  1828. struct be_adapter *adapter = netdev_priv(netdev);
  1829. netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
  1830. NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
  1831. NETIF_F_GRO;
  1832. netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
  1833. netdev->flags |= IFF_MULTICAST;
  1834. adapter->rx_csum = true;
  1835. /* Default settings for Rx and Tx flow control */
  1836. adapter->rx_fc = true;
  1837. adapter->tx_fc = true;
  1838. netif_set_gso_max_size(netdev, 65535);
  1839. BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
  1840. SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
  1841. netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
  1842. BE_NAPI_WEIGHT);
  1843. netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
  1844. BE_NAPI_WEIGHT);
  1845. netif_carrier_off(netdev);
  1846. netif_stop_queue(netdev);
  1847. }
  1848. static void be_unmap_pci_bars(struct be_adapter *adapter)
  1849. {
  1850. if (adapter->csr)
  1851. iounmap(adapter->csr);
  1852. if (adapter->db)
  1853. iounmap(adapter->db);
  1854. if (adapter->pcicfg && be_physfn(adapter))
  1855. iounmap(adapter->pcicfg);
  1856. }
  1857. static int be_map_pci_bars(struct be_adapter *adapter)
  1858. {
  1859. u8 __iomem *addr;
  1860. int pcicfg_reg, db_reg;
  1861. if (be_physfn(adapter)) {
  1862. addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
  1863. pci_resource_len(adapter->pdev, 2));
  1864. if (addr == NULL)
  1865. return -ENOMEM;
  1866. adapter->csr = addr;
  1867. }
  1868. if (adapter->generation == BE_GEN2) {
  1869. pcicfg_reg = 1;
  1870. db_reg = 4;
  1871. } else {
  1872. pcicfg_reg = 0;
  1873. if (be_physfn(adapter))
  1874. db_reg = 4;
  1875. else
  1876. db_reg = 0;
  1877. }
  1878. addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
  1879. pci_resource_len(adapter->pdev, db_reg));
  1880. if (addr == NULL)
  1881. goto pci_map_err;
  1882. adapter->db = addr;
  1883. if (be_physfn(adapter)) {
  1884. addr = ioremap_nocache(
  1885. pci_resource_start(adapter->pdev, pcicfg_reg),
  1886. pci_resource_len(adapter->pdev, pcicfg_reg));
  1887. if (addr == NULL)
  1888. goto pci_map_err;
  1889. adapter->pcicfg = addr;
  1890. } else
  1891. adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
  1892. return 0;
  1893. pci_map_err:
  1894. be_unmap_pci_bars(adapter);
  1895. return -ENOMEM;
  1896. }
  1897. static void be_ctrl_cleanup(struct be_adapter *adapter)
  1898. {
  1899. struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
  1900. be_unmap_pci_bars(adapter);
  1901. if (mem->va)
  1902. pci_free_consistent(adapter->pdev, mem->size,
  1903. mem->va, mem->dma);
  1904. mem = &adapter->mc_cmd_mem;
  1905. if (mem->va)
  1906. pci_free_consistent(adapter->pdev, mem->size,
  1907. mem->va, mem->dma);
  1908. }
  1909. static int be_ctrl_init(struct be_adapter *adapter)
  1910. {
  1911. struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
  1912. struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
  1913. struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
  1914. int status;
  1915. status = be_map_pci_bars(adapter);
  1916. if (status)
  1917. goto done;
  1918. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  1919. mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
  1920. mbox_mem_alloc->size, &mbox_mem_alloc->dma);
  1921. if (!mbox_mem_alloc->va) {
  1922. status = -ENOMEM;
  1923. goto unmap_pci_bars;
  1924. }
  1925. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  1926. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  1927. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  1928. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  1929. mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
  1930. mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
  1931. &mc_cmd_mem->dma);
  1932. if (mc_cmd_mem->va == NULL) {
  1933. status = -ENOMEM;
  1934. goto free_mbox;
  1935. }
  1936. memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
  1937. spin_lock_init(&adapter->mbox_lock);
  1938. spin_lock_init(&adapter->mcc_lock);
  1939. spin_lock_init(&adapter->mcc_cq_lock);
  1940. init_completion(&adapter->flash_compl);
  1941. pci_save_state(adapter->pdev);
  1942. return 0;
  1943. free_mbox:
  1944. pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
  1945. mbox_mem_alloc->va, mbox_mem_alloc->dma);
  1946. unmap_pci_bars:
  1947. be_unmap_pci_bars(adapter);
  1948. done:
  1949. return status;
  1950. }
  1951. static void be_stats_cleanup(struct be_adapter *adapter)
  1952. {
  1953. struct be_stats_obj *stats = &adapter->stats;
  1954. struct be_dma_mem *cmd = &stats->cmd;
  1955. if (cmd->va)
  1956. pci_free_consistent(adapter->pdev, cmd->size,
  1957. cmd->va, cmd->dma);
  1958. }
  1959. static int be_stats_init(struct be_adapter *adapter)
  1960. {
  1961. struct be_stats_obj *stats = &adapter->stats;
  1962. struct be_dma_mem *cmd = &stats->cmd;
  1963. cmd->size = sizeof(struct be_cmd_req_get_stats);
  1964. cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
  1965. if (cmd->va == NULL)
  1966. return -1;
  1967. memset(cmd->va, 0, cmd->size);
  1968. return 0;
  1969. }
  1970. static void __devexit be_remove(struct pci_dev *pdev)
  1971. {
  1972. struct be_adapter *adapter = pci_get_drvdata(pdev);
  1973. if (!adapter)
  1974. return;
  1975. unregister_netdev(adapter->netdev);
  1976. be_clear(adapter);
  1977. be_stats_cleanup(adapter);
  1978. be_ctrl_cleanup(adapter);
  1979. be_sriov_disable(adapter);
  1980. be_msix_disable(adapter);
  1981. pci_set_drvdata(pdev, NULL);
  1982. pci_release_regions(pdev);
  1983. pci_disable_device(pdev);
  1984. free_netdev(adapter->netdev);
  1985. }
  1986. static int be_get_config(struct be_adapter *adapter)
  1987. {
  1988. int status;
  1989. u8 mac[ETH_ALEN];
  1990. status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
  1991. if (status)
  1992. return status;
  1993. status = be_cmd_query_fw_cfg(adapter,
  1994. &adapter->port_num, &adapter->cap);
  1995. if (status)
  1996. return status;
  1997. memset(mac, 0, ETH_ALEN);
  1998. if (be_physfn(adapter)) {
  1999. status = be_cmd_mac_addr_query(adapter, mac,
  2000. MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
  2001. if (status)
  2002. return status;
  2003. if (!is_valid_ether_addr(mac))
  2004. return -EADDRNOTAVAIL;
  2005. memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
  2006. memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
  2007. }
  2008. if (adapter->cap & 0x400)
  2009. adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
  2010. else
  2011. adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
  2012. return 0;
  2013. }
  2014. static int __devinit be_probe(struct pci_dev *pdev,
  2015. const struct pci_device_id *pdev_id)
  2016. {
  2017. int status = 0;
  2018. struct be_adapter *adapter;
  2019. struct net_device *netdev;
  2020. status = pci_enable_device(pdev);
  2021. if (status)
  2022. goto do_none;
  2023. status = pci_request_regions(pdev, DRV_NAME);
  2024. if (status)
  2025. goto disable_dev;
  2026. pci_set_master(pdev);
  2027. netdev = alloc_etherdev(sizeof(struct be_adapter));
  2028. if (netdev == NULL) {
  2029. status = -ENOMEM;
  2030. goto rel_reg;
  2031. }
  2032. adapter = netdev_priv(netdev);
  2033. switch (pdev->device) {
  2034. case BE_DEVICE_ID1:
  2035. case OC_DEVICE_ID1:
  2036. adapter->generation = BE_GEN2;
  2037. break;
  2038. case BE_DEVICE_ID2:
  2039. case OC_DEVICE_ID2:
  2040. adapter->generation = BE_GEN3;
  2041. break;
  2042. default:
  2043. adapter->generation = 0;
  2044. }
  2045. adapter->pdev = pdev;
  2046. pci_set_drvdata(pdev, adapter);
  2047. adapter->netdev = netdev;
  2048. be_netdev_init(netdev);
  2049. SET_NETDEV_DEV(netdev, &pdev->dev);
  2050. be_msix_enable(adapter);
  2051. status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  2052. if (!status) {
  2053. netdev->features |= NETIF_F_HIGHDMA;
  2054. } else {
  2055. status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2056. if (status) {
  2057. dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
  2058. goto free_netdev;
  2059. }
  2060. }
  2061. be_sriov_enable(adapter);
  2062. status = be_ctrl_init(adapter);
  2063. if (status)
  2064. goto free_netdev;
  2065. /* sync up with fw's ready state */
  2066. if (be_physfn(adapter)) {
  2067. status = be_cmd_POST(adapter);
  2068. if (status)
  2069. goto ctrl_clean;
  2070. }
  2071. /* tell fw we're ready to fire cmds */
  2072. status = be_cmd_fw_init(adapter);
  2073. if (status)
  2074. goto ctrl_clean;
  2075. if (be_physfn(adapter)) {
  2076. status = be_cmd_reset_function(adapter);
  2077. if (status)
  2078. goto ctrl_clean;
  2079. }
  2080. status = be_stats_init(adapter);
  2081. if (status)
  2082. goto ctrl_clean;
  2083. status = be_get_config(adapter);
  2084. if (status)
  2085. goto stats_clean;
  2086. INIT_DELAYED_WORK(&adapter->work, be_worker);
  2087. status = be_setup(adapter);
  2088. if (status)
  2089. goto stats_clean;
  2090. status = register_netdev(netdev);
  2091. if (status != 0)
  2092. goto unsetup;
  2093. dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
  2094. return 0;
  2095. unsetup:
  2096. be_clear(adapter);
  2097. stats_clean:
  2098. be_stats_cleanup(adapter);
  2099. ctrl_clean:
  2100. be_ctrl_cleanup(adapter);
  2101. free_netdev:
  2102. be_msix_disable(adapter);
  2103. be_sriov_disable(adapter);
  2104. free_netdev(adapter->netdev);
  2105. pci_set_drvdata(pdev, NULL);
  2106. rel_reg:
  2107. pci_release_regions(pdev);
  2108. disable_dev:
  2109. pci_disable_device(pdev);
  2110. do_none:
  2111. dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
  2112. return status;
  2113. }
  2114. static int be_suspend(struct pci_dev *pdev, pm_message_t state)
  2115. {
  2116. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2117. struct net_device *netdev = adapter->netdev;
  2118. if (adapter->wol)
  2119. be_setup_wol(adapter, true);
  2120. netif_device_detach(netdev);
  2121. if (netif_running(netdev)) {
  2122. rtnl_lock();
  2123. be_close(netdev);
  2124. rtnl_unlock();
  2125. }
  2126. be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
  2127. be_clear(adapter);
  2128. pci_save_state(pdev);
  2129. pci_disable_device(pdev);
  2130. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  2131. return 0;
  2132. }
  2133. static int be_resume(struct pci_dev *pdev)
  2134. {
  2135. int status = 0;
  2136. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2137. struct net_device *netdev = adapter->netdev;
  2138. netif_device_detach(netdev);
  2139. status = pci_enable_device(pdev);
  2140. if (status)
  2141. return status;
  2142. pci_set_power_state(pdev, 0);
  2143. pci_restore_state(pdev);
  2144. /* tell fw we're ready to fire cmds */
  2145. status = be_cmd_fw_init(adapter);
  2146. if (status)
  2147. return status;
  2148. be_setup(adapter);
  2149. if (netif_running(netdev)) {
  2150. rtnl_lock();
  2151. be_open(netdev);
  2152. rtnl_unlock();
  2153. }
  2154. netif_device_attach(netdev);
  2155. if (adapter->wol)
  2156. be_setup_wol(adapter, false);
  2157. return 0;
  2158. }
  2159. /*
  2160. * An FLR will stop BE from DMAing any data.
  2161. */
  2162. static void be_shutdown(struct pci_dev *pdev)
  2163. {
  2164. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2165. struct net_device *netdev = adapter->netdev;
  2166. netif_device_detach(netdev);
  2167. be_cmd_reset_function(adapter);
  2168. if (adapter->wol)
  2169. be_setup_wol(adapter, true);
  2170. pci_disable_device(pdev);
  2171. }
  2172. static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
  2173. pci_channel_state_t state)
  2174. {
  2175. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2176. struct net_device *netdev = adapter->netdev;
  2177. dev_err(&adapter->pdev->dev, "EEH error detected\n");
  2178. adapter->eeh_err = true;
  2179. netif_device_detach(netdev);
  2180. if (netif_running(netdev)) {
  2181. rtnl_lock();
  2182. be_close(netdev);
  2183. rtnl_unlock();
  2184. }
  2185. be_clear(adapter);
  2186. if (state == pci_channel_io_perm_failure)
  2187. return PCI_ERS_RESULT_DISCONNECT;
  2188. pci_disable_device(pdev);
  2189. return PCI_ERS_RESULT_NEED_RESET;
  2190. }
  2191. static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
  2192. {
  2193. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2194. int status;
  2195. dev_info(&adapter->pdev->dev, "EEH reset\n");
  2196. adapter->eeh_err = false;
  2197. status = pci_enable_device(pdev);
  2198. if (status)
  2199. return PCI_ERS_RESULT_DISCONNECT;
  2200. pci_set_master(pdev);
  2201. pci_set_power_state(pdev, 0);
  2202. pci_restore_state(pdev);
  2203. /* Check if card is ok and fw is ready */
  2204. status = be_cmd_POST(adapter);
  2205. if (status)
  2206. return PCI_ERS_RESULT_DISCONNECT;
  2207. return PCI_ERS_RESULT_RECOVERED;
  2208. }
  2209. static void be_eeh_resume(struct pci_dev *pdev)
  2210. {
  2211. int status = 0;
  2212. struct be_adapter *adapter = pci_get_drvdata(pdev);
  2213. struct net_device *netdev = adapter->netdev;
  2214. dev_info(&adapter->pdev->dev, "EEH resume\n");
  2215. pci_save_state(pdev);
  2216. /* tell fw we're ready to fire cmds */
  2217. status = be_cmd_fw_init(adapter);
  2218. if (status)
  2219. goto err;
  2220. status = be_setup(adapter);
  2221. if (status)
  2222. goto err;
  2223. if (netif_running(netdev)) {
  2224. status = be_open(netdev);
  2225. if (status)
  2226. goto err;
  2227. }
  2228. netif_device_attach(netdev);
  2229. return;
  2230. err:
  2231. dev_err(&adapter->pdev->dev, "EEH resume failed\n");
  2232. }
  2233. static struct pci_error_handlers be_eeh_handlers = {
  2234. .error_detected = be_eeh_err_detected,
  2235. .slot_reset = be_eeh_reset,
  2236. .resume = be_eeh_resume,
  2237. };
  2238. static struct pci_driver be_driver = {
  2239. .name = DRV_NAME,
  2240. .id_table = be_dev_ids,
  2241. .probe = be_probe,
  2242. .remove = be_remove,
  2243. .suspend = be_suspend,
  2244. .resume = be_resume,
  2245. .shutdown = be_shutdown,
  2246. .err_handler = &be_eeh_handlers
  2247. };
  2248. static int __init be_init_module(void)
  2249. {
  2250. if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
  2251. rx_frag_size != 2048) {
  2252. printk(KERN_WARNING DRV_NAME
  2253. " : Module param rx_frag_size must be 2048/4096/8192."
  2254. " Using 2048\n");
  2255. rx_frag_size = 2048;
  2256. }
  2257. if (num_vfs > 32) {
  2258. printk(KERN_WARNING DRV_NAME
  2259. " : Module param num_vfs must not be greater than 32."
  2260. "Using 32\n");
  2261. num_vfs = 32;
  2262. }
  2263. return pci_register_driver(&be_driver);
  2264. }
  2265. module_init(be_init_module);
  2266. static void __exit be_exit_module(void)
  2267. {
  2268. pci_unregister_driver(&be_driver);
  2269. }
  2270. module_exit(be_exit_module);