main.c 145 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
  4. Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
  5. Copyright (c) 2005-2009 Michael Buesch <m@bues.ch>
  6. Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
  7. Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  8. Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
  9. SDIO support
  10. Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
  11. Some parts of the code in this file are derived from the ipw2200
  12. driver Copyright(c) 2003 - 2004 Intel Corporation.
  13. This program is free software; you can redistribute it and/or modify
  14. it under the terms of the GNU General Public License as published by
  15. the Free Software Foundation; either version 2 of the License, or
  16. (at your option) any later version.
  17. This program is distributed in the hope that it will be useful,
  18. but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. GNU General Public License for more details.
  21. You should have received a copy of the GNU General Public License
  22. along with this program; see the file COPYING. If not, write to
  23. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  24. Boston, MA 02110-1301, USA.
  25. */
  26. #include <linux/delay.h>
  27. #include <linux/init.h>
  28. #include <linux/module.h>
  29. #include <linux/if_arp.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/firmware.h>
  32. #include <linux/workqueue.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/io.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/slab.h>
  37. #include <asm/unaligned.h>
  38. #include "b43.h"
  39. #include "main.h"
  40. #include "debugfs.h"
  41. #include "phy_common.h"
  42. #include "phy_g.h"
  43. #include "phy_n.h"
  44. #include "dma.h"
  45. #include "pio.h"
  46. #include "sysfs.h"
  47. #include "xmit.h"
  48. #include "lo.h"
  49. #include "pcmcia.h"
  50. #include "sdio.h"
  51. #include <linux/mmc/sdio_func.h>
  52. MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  53. MODULE_AUTHOR("Martin Langer");
  54. MODULE_AUTHOR("Stefano Brivio");
  55. MODULE_AUTHOR("Michael Buesch");
  56. MODULE_AUTHOR("Gábor Stefanik");
  57. MODULE_AUTHOR("Rafał Miłecki");
  58. MODULE_LICENSE("GPL");
  59. MODULE_FIRMWARE("b43/ucode11.fw");
  60. MODULE_FIRMWARE("b43/ucode13.fw");
  61. MODULE_FIRMWARE("b43/ucode14.fw");
  62. MODULE_FIRMWARE("b43/ucode15.fw");
  63. MODULE_FIRMWARE("b43/ucode16_mimo.fw");
  64. MODULE_FIRMWARE("b43/ucode5.fw");
  65. MODULE_FIRMWARE("b43/ucode9.fw");
  66. static int modparam_bad_frames_preempt;
  67. module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  68. MODULE_PARM_DESC(bad_frames_preempt,
  69. "enable(1) / disable(0) Bad Frames Preemption");
  70. static char modparam_fwpostfix[16];
  71. module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  72. MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  73. static int modparam_hwpctl;
  74. module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  75. MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  76. static int modparam_nohwcrypt;
  77. module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  78. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  79. static int modparam_hwtkip;
  80. module_param_named(hwtkip, modparam_hwtkip, int, 0444);
  81. MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
  82. static int modparam_qos = 1;
  83. module_param_named(qos, modparam_qos, int, 0444);
  84. MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
  85. static int modparam_btcoex = 1;
  86. module_param_named(btcoex, modparam_btcoex, int, 0444);
  87. MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
  88. int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
  89. module_param_named(verbose, b43_modparam_verbose, int, 0644);
  90. MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
  91. static int b43_modparam_pio = 0;
  92. module_param_named(pio, b43_modparam_pio, int, 0644);
  93. MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
  94. #ifdef CONFIG_B43_BCMA
  95. static const struct bcma_device_id b43_bcma_tbl[] = {
  96. BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x11, BCMA_ANY_CLASS),
  97. #ifdef CONFIG_B43_BCMA_EXTRA
  98. BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x17, BCMA_ANY_CLASS),
  99. BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x18, BCMA_ANY_CLASS),
  100. #endif
  101. BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_80211, 0x1D, BCMA_ANY_CLASS),
  102. BCMA_CORETABLE_END
  103. };
  104. MODULE_DEVICE_TABLE(bcma, b43_bcma_tbl);
  105. #endif
  106. #ifdef CONFIG_B43_SSB
  107. static const struct ssb_device_id b43_ssb_tbl[] = {
  108. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
  109. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
  110. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
  111. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
  112. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
  113. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
  114. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
  115. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
  116. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
  117. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
  118. SSB_DEVTABLE_END
  119. };
  120. MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
  121. #endif
  122. /* Channel and ratetables are shared for all devices.
  123. * They can't be const, because ieee80211 puts some precalculated
  124. * data in there. This data is the same for all devices, so we don't
  125. * get concurrency issues */
  126. #define RATETAB_ENT(_rateid, _flags) \
  127. { \
  128. .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
  129. .hw_value = (_rateid), \
  130. .flags = (_flags), \
  131. }
  132. /*
  133. * NOTE: When changing this, sync with xmit.c's
  134. * b43_plcp_get_bitrate_idx_* functions!
  135. */
  136. static struct ieee80211_rate __b43_ratetable[] = {
  137. RATETAB_ENT(B43_CCK_RATE_1MB, 0),
  138. RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
  139. RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
  140. RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
  141. RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
  142. RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
  143. RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
  144. RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
  145. RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
  146. RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
  147. RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
  148. RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
  149. };
  150. #define b43_a_ratetable (__b43_ratetable + 4)
  151. #define b43_a_ratetable_size 8
  152. #define b43_b_ratetable (__b43_ratetable + 0)
  153. #define b43_b_ratetable_size 4
  154. #define b43_g_ratetable (__b43_ratetable + 0)
  155. #define b43_g_ratetable_size 12
  156. #define CHAN4G(_channel, _freq, _flags) { \
  157. .band = IEEE80211_BAND_2GHZ, \
  158. .center_freq = (_freq), \
  159. .hw_value = (_channel), \
  160. .flags = (_flags), \
  161. .max_antenna_gain = 0, \
  162. .max_power = 30, \
  163. }
  164. static struct ieee80211_channel b43_2ghz_chantable[] = {
  165. CHAN4G(1, 2412, 0),
  166. CHAN4G(2, 2417, 0),
  167. CHAN4G(3, 2422, 0),
  168. CHAN4G(4, 2427, 0),
  169. CHAN4G(5, 2432, 0),
  170. CHAN4G(6, 2437, 0),
  171. CHAN4G(7, 2442, 0),
  172. CHAN4G(8, 2447, 0),
  173. CHAN4G(9, 2452, 0),
  174. CHAN4G(10, 2457, 0),
  175. CHAN4G(11, 2462, 0),
  176. CHAN4G(12, 2467, 0),
  177. CHAN4G(13, 2472, 0),
  178. CHAN4G(14, 2484, 0),
  179. };
  180. #undef CHAN4G
  181. #define CHAN5G(_channel, _flags) { \
  182. .band = IEEE80211_BAND_5GHZ, \
  183. .center_freq = 5000 + (5 * (_channel)), \
  184. .hw_value = (_channel), \
  185. .flags = (_flags), \
  186. .max_antenna_gain = 0, \
  187. .max_power = 30, \
  188. }
  189. static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
  190. CHAN5G(32, 0), CHAN5G(34, 0),
  191. CHAN5G(36, 0), CHAN5G(38, 0),
  192. CHAN5G(40, 0), CHAN5G(42, 0),
  193. CHAN5G(44, 0), CHAN5G(46, 0),
  194. CHAN5G(48, 0), CHAN5G(50, 0),
  195. CHAN5G(52, 0), CHAN5G(54, 0),
  196. CHAN5G(56, 0), CHAN5G(58, 0),
  197. CHAN5G(60, 0), CHAN5G(62, 0),
  198. CHAN5G(64, 0), CHAN5G(66, 0),
  199. CHAN5G(68, 0), CHAN5G(70, 0),
  200. CHAN5G(72, 0), CHAN5G(74, 0),
  201. CHAN5G(76, 0), CHAN5G(78, 0),
  202. CHAN5G(80, 0), CHAN5G(82, 0),
  203. CHAN5G(84, 0), CHAN5G(86, 0),
  204. CHAN5G(88, 0), CHAN5G(90, 0),
  205. CHAN5G(92, 0), CHAN5G(94, 0),
  206. CHAN5G(96, 0), CHAN5G(98, 0),
  207. CHAN5G(100, 0), CHAN5G(102, 0),
  208. CHAN5G(104, 0), CHAN5G(106, 0),
  209. CHAN5G(108, 0), CHAN5G(110, 0),
  210. CHAN5G(112, 0), CHAN5G(114, 0),
  211. CHAN5G(116, 0), CHAN5G(118, 0),
  212. CHAN5G(120, 0), CHAN5G(122, 0),
  213. CHAN5G(124, 0), CHAN5G(126, 0),
  214. CHAN5G(128, 0), CHAN5G(130, 0),
  215. CHAN5G(132, 0), CHAN5G(134, 0),
  216. CHAN5G(136, 0), CHAN5G(138, 0),
  217. CHAN5G(140, 0), CHAN5G(142, 0),
  218. CHAN5G(144, 0), CHAN5G(145, 0),
  219. CHAN5G(146, 0), CHAN5G(147, 0),
  220. CHAN5G(148, 0), CHAN5G(149, 0),
  221. CHAN5G(150, 0), CHAN5G(151, 0),
  222. CHAN5G(152, 0), CHAN5G(153, 0),
  223. CHAN5G(154, 0), CHAN5G(155, 0),
  224. CHAN5G(156, 0), CHAN5G(157, 0),
  225. CHAN5G(158, 0), CHAN5G(159, 0),
  226. CHAN5G(160, 0), CHAN5G(161, 0),
  227. CHAN5G(162, 0), CHAN5G(163, 0),
  228. CHAN5G(164, 0), CHAN5G(165, 0),
  229. CHAN5G(166, 0), CHAN5G(168, 0),
  230. CHAN5G(170, 0), CHAN5G(172, 0),
  231. CHAN5G(174, 0), CHAN5G(176, 0),
  232. CHAN5G(178, 0), CHAN5G(180, 0),
  233. CHAN5G(182, 0), CHAN5G(184, 0),
  234. CHAN5G(186, 0), CHAN5G(188, 0),
  235. CHAN5G(190, 0), CHAN5G(192, 0),
  236. CHAN5G(194, 0), CHAN5G(196, 0),
  237. CHAN5G(198, 0), CHAN5G(200, 0),
  238. CHAN5G(202, 0), CHAN5G(204, 0),
  239. CHAN5G(206, 0), CHAN5G(208, 0),
  240. CHAN5G(210, 0), CHAN5G(212, 0),
  241. CHAN5G(214, 0), CHAN5G(216, 0),
  242. CHAN5G(218, 0), CHAN5G(220, 0),
  243. CHAN5G(222, 0), CHAN5G(224, 0),
  244. CHAN5G(226, 0), CHAN5G(228, 0),
  245. };
  246. static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
  247. CHAN5G(34, 0), CHAN5G(36, 0),
  248. CHAN5G(38, 0), CHAN5G(40, 0),
  249. CHAN5G(42, 0), CHAN5G(44, 0),
  250. CHAN5G(46, 0), CHAN5G(48, 0),
  251. CHAN5G(52, 0), CHAN5G(56, 0),
  252. CHAN5G(60, 0), CHAN5G(64, 0),
  253. CHAN5G(100, 0), CHAN5G(104, 0),
  254. CHAN5G(108, 0), CHAN5G(112, 0),
  255. CHAN5G(116, 0), CHAN5G(120, 0),
  256. CHAN5G(124, 0), CHAN5G(128, 0),
  257. CHAN5G(132, 0), CHAN5G(136, 0),
  258. CHAN5G(140, 0), CHAN5G(149, 0),
  259. CHAN5G(153, 0), CHAN5G(157, 0),
  260. CHAN5G(161, 0), CHAN5G(165, 0),
  261. CHAN5G(184, 0), CHAN5G(188, 0),
  262. CHAN5G(192, 0), CHAN5G(196, 0),
  263. CHAN5G(200, 0), CHAN5G(204, 0),
  264. CHAN5G(208, 0), CHAN5G(212, 0),
  265. CHAN5G(216, 0),
  266. };
  267. #undef CHAN5G
  268. static struct ieee80211_supported_band b43_band_5GHz_nphy = {
  269. .band = IEEE80211_BAND_5GHZ,
  270. .channels = b43_5ghz_nphy_chantable,
  271. .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
  272. .bitrates = b43_a_ratetable,
  273. .n_bitrates = b43_a_ratetable_size,
  274. };
  275. static struct ieee80211_supported_band b43_band_5GHz_aphy = {
  276. .band = IEEE80211_BAND_5GHZ,
  277. .channels = b43_5ghz_aphy_chantable,
  278. .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
  279. .bitrates = b43_a_ratetable,
  280. .n_bitrates = b43_a_ratetable_size,
  281. };
  282. static struct ieee80211_supported_band b43_band_2GHz = {
  283. .band = IEEE80211_BAND_2GHZ,
  284. .channels = b43_2ghz_chantable,
  285. .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
  286. .bitrates = b43_g_ratetable,
  287. .n_bitrates = b43_g_ratetable_size,
  288. };
  289. static void b43_wireless_core_exit(struct b43_wldev *dev);
  290. static int b43_wireless_core_init(struct b43_wldev *dev);
  291. static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
  292. static int b43_wireless_core_start(struct b43_wldev *dev);
  293. static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
  294. struct ieee80211_vif *vif,
  295. struct ieee80211_bss_conf *conf,
  296. u32 changed);
  297. static int b43_ratelimit(struct b43_wl *wl)
  298. {
  299. if (!wl || !wl->current_dev)
  300. return 1;
  301. if (b43_status(wl->current_dev) < B43_STAT_STARTED)
  302. return 1;
  303. /* We are up and running.
  304. * Ratelimit the messages to avoid DoS over the net. */
  305. return net_ratelimit();
  306. }
  307. void b43info(struct b43_wl *wl, const char *fmt, ...)
  308. {
  309. struct va_format vaf;
  310. va_list args;
  311. if (b43_modparam_verbose < B43_VERBOSITY_INFO)
  312. return;
  313. if (!b43_ratelimit(wl))
  314. return;
  315. va_start(args, fmt);
  316. vaf.fmt = fmt;
  317. vaf.va = &args;
  318. printk(KERN_INFO "b43-%s: %pV",
  319. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
  320. va_end(args);
  321. }
  322. void b43err(struct b43_wl *wl, const char *fmt, ...)
  323. {
  324. struct va_format vaf;
  325. va_list args;
  326. if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
  327. return;
  328. if (!b43_ratelimit(wl))
  329. return;
  330. va_start(args, fmt);
  331. vaf.fmt = fmt;
  332. vaf.va = &args;
  333. printk(KERN_ERR "b43-%s ERROR: %pV",
  334. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
  335. va_end(args);
  336. }
  337. void b43warn(struct b43_wl *wl, const char *fmt, ...)
  338. {
  339. struct va_format vaf;
  340. va_list args;
  341. if (b43_modparam_verbose < B43_VERBOSITY_WARN)
  342. return;
  343. if (!b43_ratelimit(wl))
  344. return;
  345. va_start(args, fmt);
  346. vaf.fmt = fmt;
  347. vaf.va = &args;
  348. printk(KERN_WARNING "b43-%s warning: %pV",
  349. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
  350. va_end(args);
  351. }
  352. void b43dbg(struct b43_wl *wl, const char *fmt, ...)
  353. {
  354. struct va_format vaf;
  355. va_list args;
  356. if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
  357. return;
  358. va_start(args, fmt);
  359. vaf.fmt = fmt;
  360. vaf.va = &args;
  361. printk(KERN_DEBUG "b43-%s debug: %pV",
  362. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
  363. va_end(args);
  364. }
  365. static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
  366. {
  367. u32 macctl;
  368. B43_WARN_ON(offset % 4 != 0);
  369. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  370. if (macctl & B43_MACCTL_BE)
  371. val = swab32(val);
  372. b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
  373. mmiowb();
  374. b43_write32(dev, B43_MMIO_RAM_DATA, val);
  375. }
  376. static inline void b43_shm_control_word(struct b43_wldev *dev,
  377. u16 routing, u16 offset)
  378. {
  379. u32 control;
  380. /* "offset" is the WORD offset. */
  381. control = routing;
  382. control <<= 16;
  383. control |= offset;
  384. b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
  385. }
  386. u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
  387. {
  388. u32 ret;
  389. if (routing == B43_SHM_SHARED) {
  390. B43_WARN_ON(offset & 0x0001);
  391. if (offset & 0x0003) {
  392. /* Unaligned access */
  393. b43_shm_control_word(dev, routing, offset >> 2);
  394. ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
  395. b43_shm_control_word(dev, routing, (offset >> 2) + 1);
  396. ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
  397. goto out;
  398. }
  399. offset >>= 2;
  400. }
  401. b43_shm_control_word(dev, routing, offset);
  402. ret = b43_read32(dev, B43_MMIO_SHM_DATA);
  403. out:
  404. return ret;
  405. }
  406. u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
  407. {
  408. u16 ret;
  409. if (routing == B43_SHM_SHARED) {
  410. B43_WARN_ON(offset & 0x0001);
  411. if (offset & 0x0003) {
  412. /* Unaligned access */
  413. b43_shm_control_word(dev, routing, offset >> 2);
  414. ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
  415. goto out;
  416. }
  417. offset >>= 2;
  418. }
  419. b43_shm_control_word(dev, routing, offset);
  420. ret = b43_read16(dev, B43_MMIO_SHM_DATA);
  421. out:
  422. return ret;
  423. }
  424. void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
  425. {
  426. if (routing == B43_SHM_SHARED) {
  427. B43_WARN_ON(offset & 0x0001);
  428. if (offset & 0x0003) {
  429. /* Unaligned access */
  430. b43_shm_control_word(dev, routing, offset >> 2);
  431. b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
  432. value & 0xFFFF);
  433. b43_shm_control_word(dev, routing, (offset >> 2) + 1);
  434. b43_write16(dev, B43_MMIO_SHM_DATA,
  435. (value >> 16) & 0xFFFF);
  436. return;
  437. }
  438. offset >>= 2;
  439. }
  440. b43_shm_control_word(dev, routing, offset);
  441. b43_write32(dev, B43_MMIO_SHM_DATA, value);
  442. }
  443. void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
  444. {
  445. if (routing == B43_SHM_SHARED) {
  446. B43_WARN_ON(offset & 0x0001);
  447. if (offset & 0x0003) {
  448. /* Unaligned access */
  449. b43_shm_control_word(dev, routing, offset >> 2);
  450. b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
  451. return;
  452. }
  453. offset >>= 2;
  454. }
  455. b43_shm_control_word(dev, routing, offset);
  456. b43_write16(dev, B43_MMIO_SHM_DATA, value);
  457. }
  458. /* Read HostFlags */
  459. u64 b43_hf_read(struct b43_wldev *dev)
  460. {
  461. u64 ret;
  462. ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3);
  463. ret <<= 16;
  464. ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2);
  465. ret <<= 16;
  466. ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1);
  467. return ret;
  468. }
  469. /* Write HostFlags */
  470. void b43_hf_write(struct b43_wldev *dev, u64 value)
  471. {
  472. u16 lo, mi, hi;
  473. lo = (value & 0x00000000FFFFULL);
  474. mi = (value & 0x0000FFFF0000ULL) >> 16;
  475. hi = (value & 0xFFFF00000000ULL) >> 32;
  476. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF1, lo);
  477. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF2, mi);
  478. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTF3, hi);
  479. }
  480. /* Read the firmware capabilities bitmask (Opensource firmware only) */
  481. static u16 b43_fwcapa_read(struct b43_wldev *dev)
  482. {
  483. B43_WARN_ON(!dev->fw.opensource);
  484. return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
  485. }
  486. void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
  487. {
  488. u32 low, high;
  489. B43_WARN_ON(dev->dev->core_rev < 3);
  490. /* The hardware guarantees us an atomic read, if we
  491. * read the low register first. */
  492. low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
  493. high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
  494. *tsf = high;
  495. *tsf <<= 32;
  496. *tsf |= low;
  497. }
  498. static void b43_time_lock(struct b43_wldev *dev)
  499. {
  500. b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_TBTTHOLD);
  501. /* Commit the write */
  502. b43_read32(dev, B43_MMIO_MACCTL);
  503. }
  504. static void b43_time_unlock(struct b43_wldev *dev)
  505. {
  506. b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_TBTTHOLD, 0);
  507. /* Commit the write */
  508. b43_read32(dev, B43_MMIO_MACCTL);
  509. }
  510. static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
  511. {
  512. u32 low, high;
  513. B43_WARN_ON(dev->dev->core_rev < 3);
  514. low = tsf;
  515. high = (tsf >> 32);
  516. /* The hardware guarantees us an atomic write, if we
  517. * write the low register first. */
  518. b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
  519. mmiowb();
  520. b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
  521. mmiowb();
  522. }
  523. void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
  524. {
  525. b43_time_lock(dev);
  526. b43_tsf_write_locked(dev, tsf);
  527. b43_time_unlock(dev);
  528. }
  529. static
  530. void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
  531. {
  532. static const u8 zero_addr[ETH_ALEN] = { 0 };
  533. u16 data;
  534. if (!mac)
  535. mac = zero_addr;
  536. offset |= 0x0020;
  537. b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
  538. data = mac[0];
  539. data |= mac[1] << 8;
  540. b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
  541. data = mac[2];
  542. data |= mac[3] << 8;
  543. b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
  544. data = mac[4];
  545. data |= mac[5] << 8;
  546. b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
  547. }
  548. static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
  549. {
  550. const u8 *mac;
  551. const u8 *bssid;
  552. u8 mac_bssid[ETH_ALEN * 2];
  553. int i;
  554. u32 tmp;
  555. bssid = dev->wl->bssid;
  556. mac = dev->wl->mac_addr;
  557. b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
  558. memcpy(mac_bssid, mac, ETH_ALEN);
  559. memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
  560. /* Write our MAC address and BSSID to template ram */
  561. for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
  562. tmp = (u32) (mac_bssid[i + 0]);
  563. tmp |= (u32) (mac_bssid[i + 1]) << 8;
  564. tmp |= (u32) (mac_bssid[i + 2]) << 16;
  565. tmp |= (u32) (mac_bssid[i + 3]) << 24;
  566. b43_ram_write(dev, 0x20 + i, tmp);
  567. }
  568. }
  569. static void b43_upload_card_macaddress(struct b43_wldev *dev)
  570. {
  571. b43_write_mac_bssid_templates(dev);
  572. b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
  573. }
  574. static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
  575. {
  576. /* slot_time is in usec. */
  577. /* This test used to exit for all but a G PHY. */
  578. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
  579. return;
  580. b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
  581. /* Shared memory location 0x0010 is the slot time and should be
  582. * set to slot_time; however, this register is initially 0 and changing
  583. * the value adversely affects the transmit rate for BCM4311
  584. * devices. Until this behavior is unterstood, delete this step
  585. *
  586. * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
  587. */
  588. }
  589. static void b43_short_slot_timing_enable(struct b43_wldev *dev)
  590. {
  591. b43_set_slot_time(dev, 9);
  592. }
  593. static void b43_short_slot_timing_disable(struct b43_wldev *dev)
  594. {
  595. b43_set_slot_time(dev, 20);
  596. }
  597. /* DummyTransmission function, as documented on
  598. * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
  599. */
  600. void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
  601. {
  602. struct b43_phy *phy = &dev->phy;
  603. unsigned int i, max_loop;
  604. u16 value;
  605. u32 buffer[5] = {
  606. 0x00000000,
  607. 0x00D40000,
  608. 0x00000000,
  609. 0x01000000,
  610. 0x00000000,
  611. };
  612. if (ofdm) {
  613. max_loop = 0x1E;
  614. buffer[0] = 0x000201CC;
  615. } else {
  616. max_loop = 0xFA;
  617. buffer[0] = 0x000B846E;
  618. }
  619. for (i = 0; i < 5; i++)
  620. b43_ram_write(dev, i * 4, buffer[i]);
  621. b43_write16(dev, B43_MMIO_XMTSEL, 0x0000);
  622. if (dev->dev->core_rev < 11)
  623. b43_write16(dev, B43_MMIO_WEPCTL, 0x0000);
  624. else
  625. b43_write16(dev, B43_MMIO_WEPCTL, 0x0100);
  626. value = (ofdm ? 0x41 : 0x40);
  627. b43_write16(dev, B43_MMIO_TXE0_PHYCTL, value);
  628. if (phy->type == B43_PHYTYPE_N || phy->type == B43_PHYTYPE_LP ||
  629. phy->type == B43_PHYTYPE_LCN)
  630. b43_write16(dev, B43_MMIO_TXE0_PHYCTL1, 0x1A02);
  631. b43_write16(dev, B43_MMIO_TXE0_WM_0, 0x0000);
  632. b43_write16(dev, B43_MMIO_TXE0_WM_1, 0x0000);
  633. b43_write16(dev, B43_MMIO_XMTTPLATETXPTR, 0x0000);
  634. b43_write16(dev, B43_MMIO_XMTTXCNT, 0x0014);
  635. b43_write16(dev, B43_MMIO_XMTSEL, 0x0826);
  636. b43_write16(dev, B43_MMIO_TXE0_CTL, 0x0000);
  637. if (!pa_on && phy->type == B43_PHYTYPE_N)
  638. ; /*b43_nphy_pa_override(dev, false) */
  639. switch (phy->type) {
  640. case B43_PHYTYPE_N:
  641. case B43_PHYTYPE_LCN:
  642. b43_write16(dev, B43_MMIO_TXE0_AUX, 0x00D0);
  643. break;
  644. case B43_PHYTYPE_LP:
  645. b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0050);
  646. break;
  647. default:
  648. b43_write16(dev, B43_MMIO_TXE0_AUX, 0x0030);
  649. }
  650. b43_read16(dev, B43_MMIO_TXE0_AUX);
  651. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  652. b43_radio_write16(dev, 0x0051, 0x0017);
  653. for (i = 0x00; i < max_loop; i++) {
  654. value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
  655. if (value & 0x0080)
  656. break;
  657. udelay(10);
  658. }
  659. for (i = 0x00; i < 0x0A; i++) {
  660. value = b43_read16(dev, B43_MMIO_TXE0_STATUS);
  661. if (value & 0x0400)
  662. break;
  663. udelay(10);
  664. }
  665. for (i = 0x00; i < 0x19; i++) {
  666. value = b43_read16(dev, B43_MMIO_IFSSTAT);
  667. if (!(value & 0x0100))
  668. break;
  669. udelay(10);
  670. }
  671. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  672. b43_radio_write16(dev, 0x0051, 0x0037);
  673. }
  674. static void key_write(struct b43_wldev *dev,
  675. u8 index, u8 algorithm, const u8 *key)
  676. {
  677. unsigned int i;
  678. u32 offset;
  679. u16 value;
  680. u16 kidx;
  681. /* Key index/algo block */
  682. kidx = b43_kidx_to_fw(dev, index);
  683. value = ((kidx << 4) | algorithm);
  684. b43_shm_write16(dev, B43_SHM_SHARED,
  685. B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
  686. /* Write the key to the Key Table Pointer offset */
  687. offset = dev->ktp + (index * B43_SEC_KEYSIZE);
  688. for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
  689. value = key[i];
  690. value |= (u16) (key[i + 1]) << 8;
  691. b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
  692. }
  693. }
  694. static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
  695. {
  696. u32 addrtmp[2] = { 0, 0, };
  697. u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
  698. if (b43_new_kidx_api(dev))
  699. pairwise_keys_start = B43_NR_GROUP_KEYS;
  700. B43_WARN_ON(index < pairwise_keys_start);
  701. /* We have four default TX keys and possibly four default RX keys.
  702. * Physical mac 0 is mapped to physical key 4 or 8, depending
  703. * on the firmware version.
  704. * So we must adjust the index here.
  705. */
  706. index -= pairwise_keys_start;
  707. B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
  708. if (addr) {
  709. addrtmp[0] = addr[0];
  710. addrtmp[0] |= ((u32) (addr[1]) << 8);
  711. addrtmp[0] |= ((u32) (addr[2]) << 16);
  712. addrtmp[0] |= ((u32) (addr[3]) << 24);
  713. addrtmp[1] = addr[4];
  714. addrtmp[1] |= ((u32) (addr[5]) << 8);
  715. }
  716. /* Receive match transmitter address (RCMTA) mechanism */
  717. b43_shm_write32(dev, B43_SHM_RCMTA,
  718. (index * 2) + 0, addrtmp[0]);
  719. b43_shm_write16(dev, B43_SHM_RCMTA,
  720. (index * 2) + 1, addrtmp[1]);
  721. }
  722. /* The ucode will use phase1 key with TEK key to decrypt rx packets.
  723. * When a packet is received, the iv32 is checked.
  724. * - if it doesn't the packet is returned without modification (and software
  725. * decryption can be done). That's what happen when iv16 wrap.
  726. * - if it does, the rc4 key is computed, and decryption is tried.
  727. * Either it will success and B43_RX_MAC_DEC is returned,
  728. * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
  729. * and the packet is not usable (it got modified by the ucode).
  730. * So in order to never have B43_RX_MAC_DECERR, we should provide
  731. * a iv32 and phase1key that match. Because we drop packets in case of
  732. * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
  733. * packets will be lost without higher layer knowing (ie no resync possible
  734. * until next wrap).
  735. *
  736. * NOTE : this should support 50 key like RCMTA because
  737. * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
  738. */
  739. static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
  740. u16 *phase1key)
  741. {
  742. unsigned int i;
  743. u32 offset;
  744. u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
  745. if (!modparam_hwtkip)
  746. return;
  747. if (b43_new_kidx_api(dev))
  748. pairwise_keys_start = B43_NR_GROUP_KEYS;
  749. B43_WARN_ON(index < pairwise_keys_start);
  750. /* We have four default TX keys and possibly four default RX keys.
  751. * Physical mac 0 is mapped to physical key 4 or 8, depending
  752. * on the firmware version.
  753. * So we must adjust the index here.
  754. */
  755. index -= pairwise_keys_start;
  756. B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
  757. if (b43_debug(dev, B43_DBG_KEYS)) {
  758. b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
  759. index, iv32);
  760. }
  761. /* Write the key to the RX tkip shared mem */
  762. offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
  763. for (i = 0; i < 10; i += 2) {
  764. b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
  765. phase1key ? phase1key[i / 2] : 0);
  766. }
  767. b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
  768. b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
  769. }
  770. static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
  771. struct ieee80211_vif *vif,
  772. struct ieee80211_key_conf *keyconf,
  773. struct ieee80211_sta *sta,
  774. u32 iv32, u16 *phase1key)
  775. {
  776. struct b43_wl *wl = hw_to_b43_wl(hw);
  777. struct b43_wldev *dev;
  778. int index = keyconf->hw_key_idx;
  779. if (B43_WARN_ON(!modparam_hwtkip))
  780. return;
  781. /* This is only called from the RX path through mac80211, where
  782. * our mutex is already locked. */
  783. B43_WARN_ON(!mutex_is_locked(&wl->mutex));
  784. dev = wl->current_dev;
  785. B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
  786. keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
  787. rx_tkip_phase1_write(dev, index, iv32, phase1key);
  788. /* only pairwise TKIP keys are supported right now */
  789. if (WARN_ON(!sta))
  790. return;
  791. keymac_write(dev, index, sta->addr);
  792. }
  793. static void do_key_write(struct b43_wldev *dev,
  794. u8 index, u8 algorithm,
  795. const u8 *key, size_t key_len, const u8 *mac_addr)
  796. {
  797. u8 buf[B43_SEC_KEYSIZE] = { 0, };
  798. u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
  799. if (b43_new_kidx_api(dev))
  800. pairwise_keys_start = B43_NR_GROUP_KEYS;
  801. B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
  802. B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
  803. if (index >= pairwise_keys_start)
  804. keymac_write(dev, index, NULL); /* First zero out mac. */
  805. if (algorithm == B43_SEC_ALGO_TKIP) {
  806. /*
  807. * We should provide an initial iv32, phase1key pair.
  808. * We could start with iv32=0 and compute the corresponding
  809. * phase1key, but this means calling ieee80211_get_tkip_key
  810. * with a fake skb (or export other tkip function).
  811. * Because we are lazy we hope iv32 won't start with
  812. * 0xffffffff and let's b43_op_update_tkip_key provide a
  813. * correct pair.
  814. */
  815. rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
  816. } else if (index >= pairwise_keys_start) /* clear it */
  817. rx_tkip_phase1_write(dev, index, 0, NULL);
  818. if (key)
  819. memcpy(buf, key, key_len);
  820. key_write(dev, index, algorithm, buf);
  821. if (index >= pairwise_keys_start)
  822. keymac_write(dev, index, mac_addr);
  823. dev->key[index].algorithm = algorithm;
  824. }
  825. static int b43_key_write(struct b43_wldev *dev,
  826. int index, u8 algorithm,
  827. const u8 *key, size_t key_len,
  828. const u8 *mac_addr,
  829. struct ieee80211_key_conf *keyconf)
  830. {
  831. int i;
  832. int pairwise_keys_start;
  833. /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
  834. * - Temporal Encryption Key (128 bits)
  835. * - Temporal Authenticator Tx MIC Key (64 bits)
  836. * - Temporal Authenticator Rx MIC Key (64 bits)
  837. *
  838. * Hardware only store TEK
  839. */
  840. if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
  841. key_len = 16;
  842. if (key_len > B43_SEC_KEYSIZE)
  843. return -EINVAL;
  844. for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
  845. /* Check that we don't already have this key. */
  846. B43_WARN_ON(dev->key[i].keyconf == keyconf);
  847. }
  848. if (index < 0) {
  849. /* Pairwise key. Get an empty slot for the key. */
  850. if (b43_new_kidx_api(dev))
  851. pairwise_keys_start = B43_NR_GROUP_KEYS;
  852. else
  853. pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
  854. for (i = pairwise_keys_start;
  855. i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
  856. i++) {
  857. B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
  858. if (!dev->key[i].keyconf) {
  859. /* found empty */
  860. index = i;
  861. break;
  862. }
  863. }
  864. if (index < 0) {
  865. b43warn(dev->wl, "Out of hardware key memory\n");
  866. return -ENOSPC;
  867. }
  868. } else
  869. B43_WARN_ON(index > 3);
  870. do_key_write(dev, index, algorithm, key, key_len, mac_addr);
  871. if ((index <= 3) && !b43_new_kidx_api(dev)) {
  872. /* Default RX key */
  873. B43_WARN_ON(mac_addr);
  874. do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
  875. }
  876. keyconf->hw_key_idx = index;
  877. dev->key[index].keyconf = keyconf;
  878. return 0;
  879. }
  880. static int b43_key_clear(struct b43_wldev *dev, int index)
  881. {
  882. if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
  883. return -EINVAL;
  884. do_key_write(dev, index, B43_SEC_ALGO_NONE,
  885. NULL, B43_SEC_KEYSIZE, NULL);
  886. if ((index <= 3) && !b43_new_kidx_api(dev)) {
  887. do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
  888. NULL, B43_SEC_KEYSIZE, NULL);
  889. }
  890. dev->key[index].keyconf = NULL;
  891. return 0;
  892. }
  893. static void b43_clear_keys(struct b43_wldev *dev)
  894. {
  895. int i, count;
  896. if (b43_new_kidx_api(dev))
  897. count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
  898. else
  899. count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
  900. for (i = 0; i < count; i++)
  901. b43_key_clear(dev, i);
  902. }
  903. static void b43_dump_keymemory(struct b43_wldev *dev)
  904. {
  905. unsigned int i, index, count, offset, pairwise_keys_start;
  906. u8 mac[ETH_ALEN];
  907. u16 algo;
  908. u32 rcmta0;
  909. u16 rcmta1;
  910. u64 hf;
  911. struct b43_key *key;
  912. if (!b43_debug(dev, B43_DBG_KEYS))
  913. return;
  914. hf = b43_hf_read(dev);
  915. b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
  916. !!(hf & B43_HF_USEDEFKEYS));
  917. if (b43_new_kidx_api(dev)) {
  918. pairwise_keys_start = B43_NR_GROUP_KEYS;
  919. count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
  920. } else {
  921. pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
  922. count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
  923. }
  924. for (index = 0; index < count; index++) {
  925. key = &(dev->key[index]);
  926. printk(KERN_DEBUG "Key slot %02u: %s",
  927. index, (key->keyconf == NULL) ? " " : "*");
  928. offset = dev->ktp + (index * B43_SEC_KEYSIZE);
  929. for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
  930. u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
  931. printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
  932. }
  933. algo = b43_shm_read16(dev, B43_SHM_SHARED,
  934. B43_SHM_SH_KEYIDXBLOCK + (index * 2));
  935. printk(" Algo: %04X/%02X", algo, key->algorithm);
  936. if (index >= pairwise_keys_start) {
  937. if (key->algorithm == B43_SEC_ALGO_TKIP) {
  938. printk(" TKIP: ");
  939. offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
  940. for (i = 0; i < 14; i += 2) {
  941. u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
  942. printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
  943. }
  944. }
  945. rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
  946. ((index - pairwise_keys_start) * 2) + 0);
  947. rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
  948. ((index - pairwise_keys_start) * 2) + 1);
  949. *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
  950. *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
  951. printk(" MAC: %pM", mac);
  952. } else
  953. printk(" DEFAULT KEY");
  954. printk("\n");
  955. }
  956. }
  957. void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
  958. {
  959. u32 macctl;
  960. u16 ucstat;
  961. bool hwps;
  962. bool awake;
  963. int i;
  964. B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
  965. (ps_flags & B43_PS_DISABLED));
  966. B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
  967. if (ps_flags & B43_PS_ENABLED) {
  968. hwps = true;
  969. } else if (ps_flags & B43_PS_DISABLED) {
  970. hwps = false;
  971. } else {
  972. //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
  973. // and thus is not an AP and we are associated, set bit 25
  974. }
  975. if (ps_flags & B43_PS_AWAKE) {
  976. awake = true;
  977. } else if (ps_flags & B43_PS_ASLEEP) {
  978. awake = false;
  979. } else {
  980. //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
  981. // or we are associated, or FIXME, or the latest PS-Poll packet sent was
  982. // successful, set bit26
  983. }
  984. /* FIXME: For now we force awake-on and hwps-off */
  985. hwps = false;
  986. awake = true;
  987. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  988. if (hwps)
  989. macctl |= B43_MACCTL_HWPS;
  990. else
  991. macctl &= ~B43_MACCTL_HWPS;
  992. if (awake)
  993. macctl |= B43_MACCTL_AWAKE;
  994. else
  995. macctl &= ~B43_MACCTL_AWAKE;
  996. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  997. /* Commit write */
  998. b43_read32(dev, B43_MMIO_MACCTL);
  999. if (awake && dev->dev->core_rev >= 5) {
  1000. /* Wait for the microcode to wake up. */
  1001. for (i = 0; i < 100; i++) {
  1002. ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
  1003. B43_SHM_SH_UCODESTAT);
  1004. if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
  1005. break;
  1006. udelay(10);
  1007. }
  1008. }
  1009. }
  1010. #ifdef CONFIG_B43_BCMA
  1011. static void b43_bcma_phy_reset(struct b43_wldev *dev)
  1012. {
  1013. u32 flags;
  1014. /* Put PHY into reset */
  1015. flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
  1016. flags |= B43_BCMA_IOCTL_PHY_RESET;
  1017. flags |= B43_BCMA_IOCTL_PHY_BW_20MHZ; /* Make 20 MHz def */
  1018. bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
  1019. udelay(2);
  1020. /* Take PHY out of reset */
  1021. flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
  1022. flags &= ~B43_BCMA_IOCTL_PHY_RESET;
  1023. flags |= BCMA_IOCTL_FGC;
  1024. bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
  1025. udelay(1);
  1026. /* Do not force clock anymore */
  1027. flags = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
  1028. flags &= ~BCMA_IOCTL_FGC;
  1029. bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, flags);
  1030. udelay(1);
  1031. }
  1032. static void b43_bcma_wireless_core_reset(struct b43_wldev *dev, bool gmode)
  1033. {
  1034. u32 req = B43_BCMA_CLKCTLST_80211_PLL_REQ |
  1035. B43_BCMA_CLKCTLST_PHY_PLL_REQ;
  1036. u32 status = B43_BCMA_CLKCTLST_80211_PLL_ST |
  1037. B43_BCMA_CLKCTLST_PHY_PLL_ST;
  1038. b43_device_enable(dev, B43_BCMA_IOCTL_PHY_CLKEN);
  1039. bcma_core_set_clockmode(dev->dev->bdev, BCMA_CLKMODE_FAST);
  1040. b43_bcma_phy_reset(dev);
  1041. bcma_core_pll_ctl(dev->dev->bdev, req, status, true);
  1042. }
  1043. #endif
  1044. static void b43_ssb_wireless_core_reset(struct b43_wldev *dev, bool gmode)
  1045. {
  1046. struct ssb_device *sdev = dev->dev->sdev;
  1047. u32 tmslow;
  1048. u32 flags = 0;
  1049. if (gmode)
  1050. flags |= B43_TMSLOW_GMODE;
  1051. flags |= B43_TMSLOW_PHYCLKEN;
  1052. flags |= B43_TMSLOW_PHYRESET;
  1053. if (dev->phy.type == B43_PHYTYPE_N)
  1054. flags |= B43_TMSLOW_PHY_BANDWIDTH_20MHZ; /* Make 20 MHz def */
  1055. b43_device_enable(dev, flags);
  1056. msleep(2); /* Wait for the PLL to turn on. */
  1057. /* Now take the PHY out of Reset again */
  1058. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  1059. tmslow |= SSB_TMSLOW_FGC;
  1060. tmslow &= ~B43_TMSLOW_PHYRESET;
  1061. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  1062. ssb_read32(sdev, SSB_TMSLOW); /* flush */
  1063. msleep(1);
  1064. tmslow &= ~SSB_TMSLOW_FGC;
  1065. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  1066. ssb_read32(sdev, SSB_TMSLOW); /* flush */
  1067. msleep(1);
  1068. }
  1069. void b43_wireless_core_reset(struct b43_wldev *dev, bool gmode)
  1070. {
  1071. u32 macctl;
  1072. switch (dev->dev->bus_type) {
  1073. #ifdef CONFIG_B43_BCMA
  1074. case B43_BUS_BCMA:
  1075. b43_bcma_wireless_core_reset(dev, gmode);
  1076. break;
  1077. #endif
  1078. #ifdef CONFIG_B43_SSB
  1079. case B43_BUS_SSB:
  1080. b43_ssb_wireless_core_reset(dev, gmode);
  1081. break;
  1082. #endif
  1083. }
  1084. /* Turn Analog ON, but only if we already know the PHY-type.
  1085. * This protects against very early setup where we don't know the
  1086. * PHY-type, yet. wireless_core_reset will be called once again later,
  1087. * when we know the PHY-type. */
  1088. if (dev->phy.ops)
  1089. dev->phy.ops->switch_analog(dev, 1);
  1090. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  1091. macctl &= ~B43_MACCTL_GMODE;
  1092. if (gmode)
  1093. macctl |= B43_MACCTL_GMODE;
  1094. macctl |= B43_MACCTL_IHR_ENABLED;
  1095. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  1096. }
  1097. static void handle_irq_transmit_status(struct b43_wldev *dev)
  1098. {
  1099. u32 v0, v1;
  1100. u16 tmp;
  1101. struct b43_txstatus stat;
  1102. while (1) {
  1103. v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
  1104. if (!(v0 & 0x00000001))
  1105. break;
  1106. v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
  1107. stat.cookie = (v0 >> 16);
  1108. stat.seq = (v1 & 0x0000FFFF);
  1109. stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
  1110. tmp = (v0 & 0x0000FFFF);
  1111. stat.frame_count = ((tmp & 0xF000) >> 12);
  1112. stat.rts_count = ((tmp & 0x0F00) >> 8);
  1113. stat.supp_reason = ((tmp & 0x001C) >> 2);
  1114. stat.pm_indicated = !!(tmp & 0x0080);
  1115. stat.intermediate = !!(tmp & 0x0040);
  1116. stat.for_ampdu = !!(tmp & 0x0020);
  1117. stat.acked = !!(tmp & 0x0002);
  1118. b43_handle_txstatus(dev, &stat);
  1119. }
  1120. }
  1121. static void drain_txstatus_queue(struct b43_wldev *dev)
  1122. {
  1123. u32 dummy;
  1124. if (dev->dev->core_rev < 5)
  1125. return;
  1126. /* Read all entries from the microcode TXstatus FIFO
  1127. * and throw them away.
  1128. */
  1129. while (1) {
  1130. dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
  1131. if (!(dummy & 0x00000001))
  1132. break;
  1133. dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
  1134. }
  1135. }
  1136. static u32 b43_jssi_read(struct b43_wldev *dev)
  1137. {
  1138. u32 val = 0;
  1139. val = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1);
  1140. val <<= 16;
  1141. val |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0);
  1142. return val;
  1143. }
  1144. static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
  1145. {
  1146. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI0,
  1147. (jssi & 0x0000FFFF));
  1148. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_JSSI1,
  1149. (jssi & 0xFFFF0000) >> 16);
  1150. }
  1151. static void b43_generate_noise_sample(struct b43_wldev *dev)
  1152. {
  1153. b43_jssi_write(dev, 0x7F7F7F7F);
  1154. b43_write32(dev, B43_MMIO_MACCMD,
  1155. b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
  1156. }
  1157. static void b43_calculate_link_quality(struct b43_wldev *dev)
  1158. {
  1159. /* Top half of Link Quality calculation. */
  1160. if (dev->phy.type != B43_PHYTYPE_G)
  1161. return;
  1162. if (dev->noisecalc.calculation_running)
  1163. return;
  1164. dev->noisecalc.calculation_running = true;
  1165. dev->noisecalc.nr_samples = 0;
  1166. b43_generate_noise_sample(dev);
  1167. }
  1168. static void handle_irq_noise(struct b43_wldev *dev)
  1169. {
  1170. struct b43_phy_g *phy = dev->phy.g;
  1171. u16 tmp;
  1172. u8 noise[4];
  1173. u8 i, j;
  1174. s32 average;
  1175. /* Bottom half of Link Quality calculation. */
  1176. if (dev->phy.type != B43_PHYTYPE_G)
  1177. return;
  1178. /* Possible race condition: It might be possible that the user
  1179. * changed to a different channel in the meantime since we
  1180. * started the calculation. We ignore that fact, since it's
  1181. * not really that much of a problem. The background noise is
  1182. * an estimation only anyway. Slightly wrong results will get damped
  1183. * by the averaging of the 8 sample rounds. Additionally the
  1184. * value is shortlived. So it will be replaced by the next noise
  1185. * calculation round soon. */
  1186. B43_WARN_ON(!dev->noisecalc.calculation_running);
  1187. *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
  1188. if (noise[0] == 0x7F || noise[1] == 0x7F ||
  1189. noise[2] == 0x7F || noise[3] == 0x7F)
  1190. goto generate_new;
  1191. /* Get the noise samples. */
  1192. B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
  1193. i = dev->noisecalc.nr_samples;
  1194. noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  1195. noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  1196. noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  1197. noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  1198. dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
  1199. dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
  1200. dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
  1201. dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
  1202. dev->noisecalc.nr_samples++;
  1203. if (dev->noisecalc.nr_samples == 8) {
  1204. /* Calculate the Link Quality by the noise samples. */
  1205. average = 0;
  1206. for (i = 0; i < 8; i++) {
  1207. for (j = 0; j < 4; j++)
  1208. average += dev->noisecalc.samples[i][j];
  1209. }
  1210. average /= (8 * 4);
  1211. average *= 125;
  1212. average += 64;
  1213. average /= 128;
  1214. tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
  1215. tmp = (tmp / 128) & 0x1F;
  1216. if (tmp >= 8)
  1217. average += 2;
  1218. else
  1219. average -= 25;
  1220. if (tmp == 8)
  1221. average -= 72;
  1222. else
  1223. average -= 48;
  1224. dev->stats.link_noise = average;
  1225. dev->noisecalc.calculation_running = false;
  1226. return;
  1227. }
  1228. generate_new:
  1229. b43_generate_noise_sample(dev);
  1230. }
  1231. static void handle_irq_tbtt_indication(struct b43_wldev *dev)
  1232. {
  1233. if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
  1234. ///TODO: PS TBTT
  1235. } else {
  1236. if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
  1237. b43_power_saving_ctl_bits(dev, 0);
  1238. }
  1239. if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
  1240. dev->dfq_valid = true;
  1241. }
  1242. static void handle_irq_atim_end(struct b43_wldev *dev)
  1243. {
  1244. if (dev->dfq_valid) {
  1245. b43_write32(dev, B43_MMIO_MACCMD,
  1246. b43_read32(dev, B43_MMIO_MACCMD)
  1247. | B43_MACCMD_DFQ_VALID);
  1248. dev->dfq_valid = false;
  1249. }
  1250. }
  1251. static void handle_irq_pmq(struct b43_wldev *dev)
  1252. {
  1253. u32 tmp;
  1254. //TODO: AP mode.
  1255. while (1) {
  1256. tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
  1257. if (!(tmp & 0x00000008))
  1258. break;
  1259. }
  1260. /* 16bit write is odd, but correct. */
  1261. b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
  1262. }
  1263. static void b43_write_template_common(struct b43_wldev *dev,
  1264. const u8 *data, u16 size,
  1265. u16 ram_offset,
  1266. u16 shm_size_offset, u8 rate)
  1267. {
  1268. u32 i, tmp;
  1269. struct b43_plcp_hdr4 plcp;
  1270. plcp.data = 0;
  1271. b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  1272. b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
  1273. ram_offset += sizeof(u32);
  1274. /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
  1275. * So leave the first two bytes of the next write blank.
  1276. */
  1277. tmp = (u32) (data[0]) << 16;
  1278. tmp |= (u32) (data[1]) << 24;
  1279. b43_ram_write(dev, ram_offset, tmp);
  1280. ram_offset += sizeof(u32);
  1281. for (i = 2; i < size; i += sizeof(u32)) {
  1282. tmp = (u32) (data[i + 0]);
  1283. if (i + 1 < size)
  1284. tmp |= (u32) (data[i + 1]) << 8;
  1285. if (i + 2 < size)
  1286. tmp |= (u32) (data[i + 2]) << 16;
  1287. if (i + 3 < size)
  1288. tmp |= (u32) (data[i + 3]) << 24;
  1289. b43_ram_write(dev, ram_offset + i - 2, tmp);
  1290. }
  1291. b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
  1292. size + sizeof(struct b43_plcp_hdr6));
  1293. }
  1294. /* Check if the use of the antenna that ieee80211 told us to
  1295. * use is possible. This will fall back to DEFAULT.
  1296. * "antenna_nr" is the antenna identifier we got from ieee80211. */
  1297. u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
  1298. u8 antenna_nr)
  1299. {
  1300. u8 antenna_mask;
  1301. if (antenna_nr == 0) {
  1302. /* Zero means "use default antenna". That's always OK. */
  1303. return 0;
  1304. }
  1305. /* Get the mask of available antennas. */
  1306. if (dev->phy.gmode)
  1307. antenna_mask = dev->dev->bus_sprom->ant_available_bg;
  1308. else
  1309. antenna_mask = dev->dev->bus_sprom->ant_available_a;
  1310. if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
  1311. /* This antenna is not available. Fall back to default. */
  1312. return 0;
  1313. }
  1314. return antenna_nr;
  1315. }
  1316. /* Convert a b43 antenna number value to the PHY TX control value. */
  1317. static u16 b43_antenna_to_phyctl(int antenna)
  1318. {
  1319. switch (antenna) {
  1320. case B43_ANTENNA0:
  1321. return B43_TXH_PHY_ANT0;
  1322. case B43_ANTENNA1:
  1323. return B43_TXH_PHY_ANT1;
  1324. case B43_ANTENNA2:
  1325. return B43_TXH_PHY_ANT2;
  1326. case B43_ANTENNA3:
  1327. return B43_TXH_PHY_ANT3;
  1328. case B43_ANTENNA_AUTO0:
  1329. case B43_ANTENNA_AUTO1:
  1330. return B43_TXH_PHY_ANT01AUTO;
  1331. }
  1332. B43_WARN_ON(1);
  1333. return 0;
  1334. }
  1335. static void b43_write_beacon_template(struct b43_wldev *dev,
  1336. u16 ram_offset,
  1337. u16 shm_size_offset)
  1338. {
  1339. unsigned int i, len, variable_len;
  1340. const struct ieee80211_mgmt *bcn;
  1341. const u8 *ie;
  1342. bool tim_found = false;
  1343. unsigned int rate;
  1344. u16 ctl;
  1345. int antenna;
  1346. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
  1347. bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
  1348. len = min((size_t) dev->wl->current_beacon->len,
  1349. 0x200 - sizeof(struct b43_plcp_hdr6));
  1350. rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
  1351. b43_write_template_common(dev, (const u8 *)bcn,
  1352. len, ram_offset, shm_size_offset, rate);
  1353. /* Write the PHY TX control parameters. */
  1354. antenna = B43_ANTENNA_DEFAULT;
  1355. antenna = b43_antenna_to_phyctl(antenna);
  1356. ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
  1357. /* We can't send beacons with short preamble. Would get PHY errors. */
  1358. ctl &= ~B43_TXH_PHY_SHORTPRMBL;
  1359. ctl &= ~B43_TXH_PHY_ANT;
  1360. ctl &= ~B43_TXH_PHY_ENC;
  1361. ctl |= antenna;
  1362. if (b43_is_cck_rate(rate))
  1363. ctl |= B43_TXH_PHY_ENC_CCK;
  1364. else
  1365. ctl |= B43_TXH_PHY_ENC_OFDM;
  1366. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
  1367. /* Find the position of the TIM and the DTIM_period value
  1368. * and write them to SHM. */
  1369. ie = bcn->u.beacon.variable;
  1370. variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
  1371. for (i = 0; i < variable_len - 2; ) {
  1372. uint8_t ie_id, ie_len;
  1373. ie_id = ie[i];
  1374. ie_len = ie[i + 1];
  1375. if (ie_id == 5) {
  1376. u16 tim_position;
  1377. u16 dtim_period;
  1378. /* This is the TIM Information Element */
  1379. /* Check whether the ie_len is in the beacon data range. */
  1380. if (variable_len < ie_len + 2 + i)
  1381. break;
  1382. /* A valid TIM is at least 4 bytes long. */
  1383. if (ie_len < 4)
  1384. break;
  1385. tim_found = true;
  1386. tim_position = sizeof(struct b43_plcp_hdr6);
  1387. tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
  1388. tim_position += i;
  1389. dtim_period = ie[i + 3];
  1390. b43_shm_write16(dev, B43_SHM_SHARED,
  1391. B43_SHM_SH_TIMBPOS, tim_position);
  1392. b43_shm_write16(dev, B43_SHM_SHARED,
  1393. B43_SHM_SH_DTIMPER, dtim_period);
  1394. break;
  1395. }
  1396. i += ie_len + 2;
  1397. }
  1398. if (!tim_found) {
  1399. /*
  1400. * If ucode wants to modify TIM do it behind the beacon, this
  1401. * will happen, for example, when doing mesh networking.
  1402. */
  1403. b43_shm_write16(dev, B43_SHM_SHARED,
  1404. B43_SHM_SH_TIMBPOS,
  1405. len + sizeof(struct b43_plcp_hdr6));
  1406. b43_shm_write16(dev, B43_SHM_SHARED,
  1407. B43_SHM_SH_DTIMPER, 0);
  1408. }
  1409. b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
  1410. }
  1411. static void b43_upload_beacon0(struct b43_wldev *dev)
  1412. {
  1413. struct b43_wl *wl = dev->wl;
  1414. if (wl->beacon0_uploaded)
  1415. return;
  1416. b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE0, B43_SHM_SH_BTL0);
  1417. wl->beacon0_uploaded = true;
  1418. }
  1419. static void b43_upload_beacon1(struct b43_wldev *dev)
  1420. {
  1421. struct b43_wl *wl = dev->wl;
  1422. if (wl->beacon1_uploaded)
  1423. return;
  1424. b43_write_beacon_template(dev, B43_SHM_SH_BT_BASE1, B43_SHM_SH_BTL1);
  1425. wl->beacon1_uploaded = true;
  1426. }
  1427. static void handle_irq_beacon(struct b43_wldev *dev)
  1428. {
  1429. struct b43_wl *wl = dev->wl;
  1430. u32 cmd, beacon0_valid, beacon1_valid;
  1431. if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
  1432. !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) &&
  1433. !b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
  1434. return;
  1435. /* This is the bottom half of the asynchronous beacon update. */
  1436. /* Ignore interrupt in the future. */
  1437. dev->irq_mask &= ~B43_IRQ_BEACON;
  1438. cmd = b43_read32(dev, B43_MMIO_MACCMD);
  1439. beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
  1440. beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
  1441. /* Schedule interrupt manually, if busy. */
  1442. if (beacon0_valid && beacon1_valid) {
  1443. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
  1444. dev->irq_mask |= B43_IRQ_BEACON;
  1445. return;
  1446. }
  1447. if (unlikely(wl->beacon_templates_virgin)) {
  1448. /* We never uploaded a beacon before.
  1449. * Upload both templates now, but only mark one valid. */
  1450. wl->beacon_templates_virgin = false;
  1451. b43_upload_beacon0(dev);
  1452. b43_upload_beacon1(dev);
  1453. cmd = b43_read32(dev, B43_MMIO_MACCMD);
  1454. cmd |= B43_MACCMD_BEACON0_VALID;
  1455. b43_write32(dev, B43_MMIO_MACCMD, cmd);
  1456. } else {
  1457. if (!beacon0_valid) {
  1458. b43_upload_beacon0(dev);
  1459. cmd = b43_read32(dev, B43_MMIO_MACCMD);
  1460. cmd |= B43_MACCMD_BEACON0_VALID;
  1461. b43_write32(dev, B43_MMIO_MACCMD, cmd);
  1462. } else if (!beacon1_valid) {
  1463. b43_upload_beacon1(dev);
  1464. cmd = b43_read32(dev, B43_MMIO_MACCMD);
  1465. cmd |= B43_MACCMD_BEACON1_VALID;
  1466. b43_write32(dev, B43_MMIO_MACCMD, cmd);
  1467. }
  1468. }
  1469. }
  1470. static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
  1471. {
  1472. u32 old_irq_mask = dev->irq_mask;
  1473. /* update beacon right away or defer to irq */
  1474. handle_irq_beacon(dev);
  1475. if (old_irq_mask != dev->irq_mask) {
  1476. /* The handler updated the IRQ mask. */
  1477. B43_WARN_ON(!dev->irq_mask);
  1478. if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
  1479. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
  1480. } else {
  1481. /* Device interrupts are currently disabled. That means
  1482. * we just ran the hardirq handler and scheduled the
  1483. * IRQ thread. The thread will write the IRQ mask when
  1484. * it finished, so there's nothing to do here. Writing
  1485. * the mask _here_ would incorrectly re-enable IRQs. */
  1486. }
  1487. }
  1488. }
  1489. static void b43_beacon_update_trigger_work(struct work_struct *work)
  1490. {
  1491. struct b43_wl *wl = container_of(work, struct b43_wl,
  1492. beacon_update_trigger);
  1493. struct b43_wldev *dev;
  1494. mutex_lock(&wl->mutex);
  1495. dev = wl->current_dev;
  1496. if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
  1497. if (b43_bus_host_is_sdio(dev->dev)) {
  1498. /* wl->mutex is enough. */
  1499. b43_do_beacon_update_trigger_work(dev);
  1500. mmiowb();
  1501. } else {
  1502. spin_lock_irq(&wl->hardirq_lock);
  1503. b43_do_beacon_update_trigger_work(dev);
  1504. mmiowb();
  1505. spin_unlock_irq(&wl->hardirq_lock);
  1506. }
  1507. }
  1508. mutex_unlock(&wl->mutex);
  1509. }
  1510. /* Asynchronously update the packet templates in template RAM.
  1511. * Locking: Requires wl->mutex to be locked. */
  1512. static void b43_update_templates(struct b43_wl *wl)
  1513. {
  1514. struct sk_buff *beacon;
  1515. /* This is the top half of the ansynchronous beacon update.
  1516. * The bottom half is the beacon IRQ.
  1517. * Beacon update must be asynchronous to avoid sending an
  1518. * invalid beacon. This can happen for example, if the firmware
  1519. * transmits a beacon while we are updating it. */
  1520. /* We could modify the existing beacon and set the aid bit in
  1521. * the TIM field, but that would probably require resizing and
  1522. * moving of data within the beacon template.
  1523. * Simply request a new beacon and let mac80211 do the hard work. */
  1524. beacon = ieee80211_beacon_get(wl->hw, wl->vif);
  1525. if (unlikely(!beacon))
  1526. return;
  1527. if (wl->current_beacon)
  1528. dev_kfree_skb_any(wl->current_beacon);
  1529. wl->current_beacon = beacon;
  1530. wl->beacon0_uploaded = false;
  1531. wl->beacon1_uploaded = false;
  1532. ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
  1533. }
  1534. static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
  1535. {
  1536. b43_time_lock(dev);
  1537. if (dev->dev->core_rev >= 3) {
  1538. b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
  1539. b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
  1540. } else {
  1541. b43_write16(dev, 0x606, (beacon_int >> 6));
  1542. b43_write16(dev, 0x610, beacon_int);
  1543. }
  1544. b43_time_unlock(dev);
  1545. b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
  1546. }
  1547. static void b43_handle_firmware_panic(struct b43_wldev *dev)
  1548. {
  1549. u16 reason;
  1550. /* Read the register that contains the reason code for the panic. */
  1551. reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
  1552. b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
  1553. switch (reason) {
  1554. default:
  1555. b43dbg(dev->wl, "The panic reason is unknown.\n");
  1556. /* fallthrough */
  1557. case B43_FWPANIC_DIE:
  1558. /* Do not restart the controller or firmware.
  1559. * The device is nonfunctional from now on.
  1560. * Restarting would result in this panic to trigger again,
  1561. * so we avoid that recursion. */
  1562. break;
  1563. case B43_FWPANIC_RESTART:
  1564. b43_controller_restart(dev, "Microcode panic");
  1565. break;
  1566. }
  1567. }
  1568. static void handle_irq_ucode_debug(struct b43_wldev *dev)
  1569. {
  1570. unsigned int i, cnt;
  1571. u16 reason, marker_id, marker_line;
  1572. __le16 *buf;
  1573. /* The proprietary firmware doesn't have this IRQ. */
  1574. if (!dev->fw.opensource)
  1575. return;
  1576. /* Read the register that contains the reason code for this IRQ. */
  1577. reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
  1578. switch (reason) {
  1579. case B43_DEBUGIRQ_PANIC:
  1580. b43_handle_firmware_panic(dev);
  1581. break;
  1582. case B43_DEBUGIRQ_DUMP_SHM:
  1583. if (!B43_DEBUG)
  1584. break; /* Only with driver debugging enabled. */
  1585. buf = kmalloc(4096, GFP_ATOMIC);
  1586. if (!buf) {
  1587. b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
  1588. goto out;
  1589. }
  1590. for (i = 0; i < 4096; i += 2) {
  1591. u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
  1592. buf[i / 2] = cpu_to_le16(tmp);
  1593. }
  1594. b43info(dev->wl, "Shared memory dump:\n");
  1595. print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
  1596. 16, 2, buf, 4096, 1);
  1597. kfree(buf);
  1598. break;
  1599. case B43_DEBUGIRQ_DUMP_REGS:
  1600. if (!B43_DEBUG)
  1601. break; /* Only with driver debugging enabled. */
  1602. b43info(dev->wl, "Microcode register dump:\n");
  1603. for (i = 0, cnt = 0; i < 64; i++) {
  1604. u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
  1605. if (cnt == 0)
  1606. printk(KERN_INFO);
  1607. printk("r%02u: 0x%04X ", i, tmp);
  1608. cnt++;
  1609. if (cnt == 6) {
  1610. printk("\n");
  1611. cnt = 0;
  1612. }
  1613. }
  1614. printk("\n");
  1615. break;
  1616. case B43_DEBUGIRQ_MARKER:
  1617. if (!B43_DEBUG)
  1618. break; /* Only with driver debugging enabled. */
  1619. marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
  1620. B43_MARKER_ID_REG);
  1621. marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
  1622. B43_MARKER_LINE_REG);
  1623. b43info(dev->wl, "The firmware just executed the MARKER(%u) "
  1624. "at line number %u\n",
  1625. marker_id, marker_line);
  1626. break;
  1627. default:
  1628. b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
  1629. reason);
  1630. }
  1631. out:
  1632. /* Acknowledge the debug-IRQ, so the firmware can continue. */
  1633. b43_shm_write16(dev, B43_SHM_SCRATCH,
  1634. B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
  1635. }
  1636. static void b43_do_interrupt_thread(struct b43_wldev *dev)
  1637. {
  1638. u32 reason;
  1639. u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
  1640. u32 merged_dma_reason = 0;
  1641. int i;
  1642. if (unlikely(b43_status(dev) != B43_STAT_STARTED))
  1643. return;
  1644. reason = dev->irq_reason;
  1645. for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
  1646. dma_reason[i] = dev->dma_reason[i];
  1647. merged_dma_reason |= dma_reason[i];
  1648. }
  1649. if (unlikely(reason & B43_IRQ_MAC_TXERR))
  1650. b43err(dev->wl, "MAC transmission error\n");
  1651. if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
  1652. b43err(dev->wl, "PHY transmission error\n");
  1653. rmb();
  1654. if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
  1655. atomic_set(&dev->phy.txerr_cnt,
  1656. B43_PHY_TX_BADNESS_LIMIT);
  1657. b43err(dev->wl, "Too many PHY TX errors, "
  1658. "restarting the controller\n");
  1659. b43_controller_restart(dev, "PHY TX errors");
  1660. }
  1661. }
  1662. if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK))) {
  1663. b43err(dev->wl,
  1664. "Fatal DMA error: 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X, 0x%08X\n",
  1665. dma_reason[0], dma_reason[1],
  1666. dma_reason[2], dma_reason[3],
  1667. dma_reason[4], dma_reason[5]);
  1668. b43err(dev->wl, "This device does not support DMA "
  1669. "on your system. It will now be switched to PIO.\n");
  1670. /* Fall back to PIO transfers if we get fatal DMA errors! */
  1671. dev->use_pio = true;
  1672. b43_controller_restart(dev, "DMA error");
  1673. return;
  1674. }
  1675. if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
  1676. handle_irq_ucode_debug(dev);
  1677. if (reason & B43_IRQ_TBTT_INDI)
  1678. handle_irq_tbtt_indication(dev);
  1679. if (reason & B43_IRQ_ATIM_END)
  1680. handle_irq_atim_end(dev);
  1681. if (reason & B43_IRQ_BEACON)
  1682. handle_irq_beacon(dev);
  1683. if (reason & B43_IRQ_PMQ)
  1684. handle_irq_pmq(dev);
  1685. if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
  1686. ;/* TODO */
  1687. if (reason & B43_IRQ_NOISESAMPLE_OK)
  1688. handle_irq_noise(dev);
  1689. /* Check the DMA reason registers for received data. */
  1690. if (dma_reason[0] & B43_DMAIRQ_RDESC_UFLOW) {
  1691. if (B43_DEBUG)
  1692. b43warn(dev->wl, "RX descriptor underrun\n");
  1693. b43_dma_handle_rx_overflow(dev->dma.rx_ring);
  1694. }
  1695. if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
  1696. if (b43_using_pio_transfers(dev))
  1697. b43_pio_rx(dev->pio.rx_queue);
  1698. else
  1699. b43_dma_rx(dev->dma.rx_ring);
  1700. }
  1701. B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
  1702. B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
  1703. B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
  1704. B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
  1705. B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
  1706. if (reason & B43_IRQ_TX_OK)
  1707. handle_irq_transmit_status(dev);
  1708. /* Re-enable interrupts on the device by restoring the current interrupt mask. */
  1709. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
  1710. #if B43_DEBUG
  1711. if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
  1712. dev->irq_count++;
  1713. for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
  1714. if (reason & (1 << i))
  1715. dev->irq_bit_count[i]++;
  1716. }
  1717. }
  1718. #endif
  1719. }
  1720. /* Interrupt thread handler. Handles device interrupts in thread context. */
  1721. static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
  1722. {
  1723. struct b43_wldev *dev = dev_id;
  1724. mutex_lock(&dev->wl->mutex);
  1725. b43_do_interrupt_thread(dev);
  1726. mmiowb();
  1727. mutex_unlock(&dev->wl->mutex);
  1728. return IRQ_HANDLED;
  1729. }
  1730. static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
  1731. {
  1732. u32 reason;
  1733. /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
  1734. * On SDIO, this runs under wl->mutex. */
  1735. reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  1736. if (reason == 0xffffffff) /* shared IRQ */
  1737. return IRQ_NONE;
  1738. reason &= dev->irq_mask;
  1739. if (!reason)
  1740. return IRQ_NONE;
  1741. dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
  1742. & 0x0001FC00;
  1743. dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
  1744. & 0x0000DC00;
  1745. dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
  1746. & 0x0000DC00;
  1747. dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
  1748. & 0x0001DC00;
  1749. dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
  1750. & 0x0000DC00;
  1751. /* Unused ring
  1752. dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
  1753. & 0x0000DC00;
  1754. */
  1755. /* ACK the interrupt. */
  1756. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
  1757. b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
  1758. b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
  1759. b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
  1760. b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
  1761. b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
  1762. /* Unused ring
  1763. b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
  1764. */
  1765. /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
  1766. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
  1767. /* Save the reason bitmasks for the IRQ thread handler. */
  1768. dev->irq_reason = reason;
  1769. return IRQ_WAKE_THREAD;
  1770. }
  1771. /* Interrupt handler top-half. This runs with interrupts disabled. */
  1772. static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
  1773. {
  1774. struct b43_wldev *dev = dev_id;
  1775. irqreturn_t ret;
  1776. if (unlikely(b43_status(dev) < B43_STAT_STARTED))
  1777. return IRQ_NONE;
  1778. spin_lock(&dev->wl->hardirq_lock);
  1779. ret = b43_do_interrupt(dev);
  1780. mmiowb();
  1781. spin_unlock(&dev->wl->hardirq_lock);
  1782. return ret;
  1783. }
  1784. /* SDIO interrupt handler. This runs in process context. */
  1785. static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
  1786. {
  1787. struct b43_wl *wl = dev->wl;
  1788. irqreturn_t ret;
  1789. mutex_lock(&wl->mutex);
  1790. ret = b43_do_interrupt(dev);
  1791. if (ret == IRQ_WAKE_THREAD)
  1792. b43_do_interrupt_thread(dev);
  1793. mutex_unlock(&wl->mutex);
  1794. }
  1795. void b43_do_release_fw(struct b43_firmware_file *fw)
  1796. {
  1797. release_firmware(fw->data);
  1798. fw->data = NULL;
  1799. fw->filename = NULL;
  1800. }
  1801. static void b43_release_firmware(struct b43_wldev *dev)
  1802. {
  1803. b43_do_release_fw(&dev->fw.ucode);
  1804. b43_do_release_fw(&dev->fw.pcm);
  1805. b43_do_release_fw(&dev->fw.initvals);
  1806. b43_do_release_fw(&dev->fw.initvals_band);
  1807. }
  1808. static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
  1809. {
  1810. const char text[] =
  1811. "You must go to " \
  1812. "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
  1813. "and download the correct firmware for this driver version. " \
  1814. "Please carefully read all instructions on this website.\n";
  1815. if (error)
  1816. b43err(wl, text);
  1817. else
  1818. b43warn(wl, text);
  1819. }
  1820. static void b43_fw_cb(const struct firmware *firmware, void *context)
  1821. {
  1822. struct b43_request_fw_context *ctx = context;
  1823. ctx->blob = firmware;
  1824. complete(&ctx->fw_load_complete);
  1825. }
  1826. int b43_do_request_fw(struct b43_request_fw_context *ctx,
  1827. const char *name,
  1828. struct b43_firmware_file *fw, bool async)
  1829. {
  1830. struct b43_fw_header *hdr;
  1831. u32 size;
  1832. int err;
  1833. if (!name) {
  1834. /* Don't fetch anything. Free possibly cached firmware. */
  1835. /* FIXME: We should probably keep it anyway, to save some headache
  1836. * on suspend/resume with multiband devices. */
  1837. b43_do_release_fw(fw);
  1838. return 0;
  1839. }
  1840. if (fw->filename) {
  1841. if ((fw->type == ctx->req_type) &&
  1842. (strcmp(fw->filename, name) == 0))
  1843. return 0; /* Already have this fw. */
  1844. /* Free the cached firmware first. */
  1845. /* FIXME: We should probably do this later after we successfully
  1846. * got the new fw. This could reduce headache with multiband devices.
  1847. * We could also redesign this to cache the firmware for all possible
  1848. * bands all the time. */
  1849. b43_do_release_fw(fw);
  1850. }
  1851. switch (ctx->req_type) {
  1852. case B43_FWTYPE_PROPRIETARY:
  1853. snprintf(ctx->fwname, sizeof(ctx->fwname),
  1854. "b43%s/%s.fw",
  1855. modparam_fwpostfix, name);
  1856. break;
  1857. case B43_FWTYPE_OPENSOURCE:
  1858. snprintf(ctx->fwname, sizeof(ctx->fwname),
  1859. "b43-open%s/%s.fw",
  1860. modparam_fwpostfix, name);
  1861. break;
  1862. default:
  1863. B43_WARN_ON(1);
  1864. return -ENOSYS;
  1865. }
  1866. if (async) {
  1867. /* do this part asynchronously */
  1868. init_completion(&ctx->fw_load_complete);
  1869. err = request_firmware_nowait(THIS_MODULE, 1, ctx->fwname,
  1870. ctx->dev->dev->dev, GFP_KERNEL,
  1871. ctx, b43_fw_cb);
  1872. if (err < 0) {
  1873. pr_err("Unable to load firmware\n");
  1874. return err;
  1875. }
  1876. /* stall here until fw ready */
  1877. wait_for_completion(&ctx->fw_load_complete);
  1878. if (ctx->blob)
  1879. goto fw_ready;
  1880. /* On some ARM systems, the async request will fail, but the next sync
  1881. * request works. For this reason, we dall through here
  1882. */
  1883. }
  1884. err = request_firmware(&ctx->blob, ctx->fwname,
  1885. ctx->dev->dev->dev);
  1886. if (err == -ENOENT) {
  1887. snprintf(ctx->errors[ctx->req_type],
  1888. sizeof(ctx->errors[ctx->req_type]),
  1889. "Firmware file \"%s\" not found\n",
  1890. ctx->fwname);
  1891. return err;
  1892. } else if (err) {
  1893. snprintf(ctx->errors[ctx->req_type],
  1894. sizeof(ctx->errors[ctx->req_type]),
  1895. "Firmware file \"%s\" request failed (err=%d)\n",
  1896. ctx->fwname, err);
  1897. return err;
  1898. }
  1899. fw_ready:
  1900. if (ctx->blob->size < sizeof(struct b43_fw_header))
  1901. goto err_format;
  1902. hdr = (struct b43_fw_header *)(ctx->blob->data);
  1903. switch (hdr->type) {
  1904. case B43_FW_TYPE_UCODE:
  1905. case B43_FW_TYPE_PCM:
  1906. size = be32_to_cpu(hdr->size);
  1907. if (size != ctx->blob->size - sizeof(struct b43_fw_header))
  1908. goto err_format;
  1909. /* fallthrough */
  1910. case B43_FW_TYPE_IV:
  1911. if (hdr->ver != 1)
  1912. goto err_format;
  1913. break;
  1914. default:
  1915. goto err_format;
  1916. }
  1917. fw->data = ctx->blob;
  1918. fw->filename = name;
  1919. fw->type = ctx->req_type;
  1920. return 0;
  1921. err_format:
  1922. snprintf(ctx->errors[ctx->req_type],
  1923. sizeof(ctx->errors[ctx->req_type]),
  1924. "Firmware file \"%s\" format error.\n", ctx->fwname);
  1925. release_firmware(ctx->blob);
  1926. return -EPROTO;
  1927. }
  1928. static int b43_try_request_fw(struct b43_request_fw_context *ctx)
  1929. {
  1930. struct b43_wldev *dev = ctx->dev;
  1931. struct b43_firmware *fw = &ctx->dev->fw;
  1932. const u8 rev = ctx->dev->dev->core_rev;
  1933. const char *filename;
  1934. u32 tmshigh;
  1935. int err;
  1936. /* Files for HT and LCN were found by trying one by one */
  1937. /* Get microcode */
  1938. if ((rev >= 5) && (rev <= 10)) {
  1939. filename = "ucode5";
  1940. } else if ((rev >= 11) && (rev <= 12)) {
  1941. filename = "ucode11";
  1942. } else if (rev == 13) {
  1943. filename = "ucode13";
  1944. } else if (rev == 14) {
  1945. filename = "ucode14";
  1946. } else if (rev == 15) {
  1947. filename = "ucode15";
  1948. } else {
  1949. switch (dev->phy.type) {
  1950. case B43_PHYTYPE_N:
  1951. if (rev >= 16)
  1952. filename = "ucode16_mimo";
  1953. else
  1954. goto err_no_ucode;
  1955. break;
  1956. case B43_PHYTYPE_HT:
  1957. if (rev == 29)
  1958. filename = "ucode29_mimo";
  1959. else
  1960. goto err_no_ucode;
  1961. break;
  1962. case B43_PHYTYPE_LCN:
  1963. if (rev == 24)
  1964. filename = "ucode24_mimo";
  1965. else
  1966. goto err_no_ucode;
  1967. break;
  1968. default:
  1969. goto err_no_ucode;
  1970. }
  1971. }
  1972. err = b43_do_request_fw(ctx, filename, &fw->ucode, true);
  1973. if (err)
  1974. goto err_load;
  1975. /* Get PCM code */
  1976. if ((rev >= 5) && (rev <= 10))
  1977. filename = "pcm5";
  1978. else if (rev >= 11)
  1979. filename = NULL;
  1980. else
  1981. goto err_no_pcm;
  1982. fw->pcm_request_failed = false;
  1983. err = b43_do_request_fw(ctx, filename, &fw->pcm, false);
  1984. if (err == -ENOENT) {
  1985. /* We did not find a PCM file? Not fatal, but
  1986. * core rev <= 10 must do without hwcrypto then. */
  1987. fw->pcm_request_failed = true;
  1988. } else if (err)
  1989. goto err_load;
  1990. /* Get initvals */
  1991. switch (dev->phy.type) {
  1992. case B43_PHYTYPE_A:
  1993. if ((rev >= 5) && (rev <= 10)) {
  1994. tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
  1995. if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
  1996. filename = "a0g1initvals5";
  1997. else
  1998. filename = "a0g0initvals5";
  1999. } else
  2000. goto err_no_initvals;
  2001. break;
  2002. case B43_PHYTYPE_G:
  2003. if ((rev >= 5) && (rev <= 10))
  2004. filename = "b0g0initvals5";
  2005. else if (rev >= 13)
  2006. filename = "b0g0initvals13";
  2007. else
  2008. goto err_no_initvals;
  2009. break;
  2010. case B43_PHYTYPE_N:
  2011. if (rev >= 16)
  2012. filename = "n0initvals16";
  2013. else if ((rev >= 11) && (rev <= 12))
  2014. filename = "n0initvals11";
  2015. else
  2016. goto err_no_initvals;
  2017. break;
  2018. case B43_PHYTYPE_LP:
  2019. if (rev == 13)
  2020. filename = "lp0initvals13";
  2021. else if (rev == 14)
  2022. filename = "lp0initvals14";
  2023. else if (rev >= 15)
  2024. filename = "lp0initvals15";
  2025. else
  2026. goto err_no_initvals;
  2027. break;
  2028. case B43_PHYTYPE_HT:
  2029. if (rev == 29)
  2030. filename = "ht0initvals29";
  2031. else
  2032. goto err_no_initvals;
  2033. break;
  2034. case B43_PHYTYPE_LCN:
  2035. if (rev == 24)
  2036. filename = "lcn0initvals24";
  2037. else
  2038. goto err_no_initvals;
  2039. break;
  2040. default:
  2041. goto err_no_initvals;
  2042. }
  2043. err = b43_do_request_fw(ctx, filename, &fw->initvals, false);
  2044. if (err)
  2045. goto err_load;
  2046. /* Get bandswitch initvals */
  2047. switch (dev->phy.type) {
  2048. case B43_PHYTYPE_A:
  2049. if ((rev >= 5) && (rev <= 10)) {
  2050. tmshigh = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
  2051. if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
  2052. filename = "a0g1bsinitvals5";
  2053. else
  2054. filename = "a0g0bsinitvals5";
  2055. } else if (rev >= 11)
  2056. filename = NULL;
  2057. else
  2058. goto err_no_initvals;
  2059. break;
  2060. case B43_PHYTYPE_G:
  2061. if ((rev >= 5) && (rev <= 10))
  2062. filename = "b0g0bsinitvals5";
  2063. else if (rev >= 11)
  2064. filename = NULL;
  2065. else
  2066. goto err_no_initvals;
  2067. break;
  2068. case B43_PHYTYPE_N:
  2069. if (rev >= 16)
  2070. filename = "n0bsinitvals16";
  2071. else if ((rev >= 11) && (rev <= 12))
  2072. filename = "n0bsinitvals11";
  2073. else
  2074. goto err_no_initvals;
  2075. break;
  2076. case B43_PHYTYPE_LP:
  2077. if (rev == 13)
  2078. filename = "lp0bsinitvals13";
  2079. else if (rev == 14)
  2080. filename = "lp0bsinitvals14";
  2081. else if (rev >= 15)
  2082. filename = "lp0bsinitvals15";
  2083. else
  2084. goto err_no_initvals;
  2085. break;
  2086. case B43_PHYTYPE_HT:
  2087. if (rev == 29)
  2088. filename = "ht0bsinitvals29";
  2089. else
  2090. goto err_no_initvals;
  2091. break;
  2092. case B43_PHYTYPE_LCN:
  2093. if (rev == 24)
  2094. filename = "lcn0bsinitvals24";
  2095. else
  2096. goto err_no_initvals;
  2097. break;
  2098. default:
  2099. goto err_no_initvals;
  2100. }
  2101. err = b43_do_request_fw(ctx, filename, &fw->initvals_band, false);
  2102. if (err)
  2103. goto err_load;
  2104. fw->opensource = (ctx->req_type == B43_FWTYPE_OPENSOURCE);
  2105. return 0;
  2106. err_no_ucode:
  2107. err = ctx->fatal_failure = -EOPNOTSUPP;
  2108. b43err(dev->wl, "The driver does not know which firmware (ucode) "
  2109. "is required for your device (wl-core rev %u)\n", rev);
  2110. goto error;
  2111. err_no_pcm:
  2112. err = ctx->fatal_failure = -EOPNOTSUPP;
  2113. b43err(dev->wl, "The driver does not know which firmware (PCM) "
  2114. "is required for your device (wl-core rev %u)\n", rev);
  2115. goto error;
  2116. err_no_initvals:
  2117. err = ctx->fatal_failure = -EOPNOTSUPP;
  2118. b43err(dev->wl, "The driver does not know which firmware (initvals) "
  2119. "is required for your device (wl-core rev %u)\n", rev);
  2120. goto error;
  2121. err_load:
  2122. /* We failed to load this firmware image. The error message
  2123. * already is in ctx->errors. Return and let our caller decide
  2124. * what to do. */
  2125. goto error;
  2126. error:
  2127. b43_release_firmware(dev);
  2128. return err;
  2129. }
  2130. static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl);
  2131. static void b43_one_core_detach(struct b43_bus_dev *dev);
  2132. static void b43_request_firmware(struct work_struct *work)
  2133. {
  2134. struct b43_wl *wl = container_of(work,
  2135. struct b43_wl, firmware_load);
  2136. struct b43_wldev *dev = wl->current_dev;
  2137. struct b43_request_fw_context *ctx;
  2138. unsigned int i;
  2139. int err;
  2140. const char *errmsg;
  2141. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  2142. if (!ctx)
  2143. return;
  2144. ctx->dev = dev;
  2145. ctx->req_type = B43_FWTYPE_PROPRIETARY;
  2146. err = b43_try_request_fw(ctx);
  2147. if (!err)
  2148. goto start_ieee80211; /* Successfully loaded it. */
  2149. /* Was fw version known? */
  2150. if (ctx->fatal_failure)
  2151. goto out;
  2152. /* proprietary fw not found, try open source */
  2153. ctx->req_type = B43_FWTYPE_OPENSOURCE;
  2154. err = b43_try_request_fw(ctx);
  2155. if (!err)
  2156. goto start_ieee80211; /* Successfully loaded it. */
  2157. if(ctx->fatal_failure)
  2158. goto out;
  2159. /* Could not find a usable firmware. Print the errors. */
  2160. for (i = 0; i < B43_NR_FWTYPES; i++) {
  2161. errmsg = ctx->errors[i];
  2162. if (strlen(errmsg))
  2163. b43err(dev->wl, "%s", errmsg);
  2164. }
  2165. b43_print_fw_helptext(dev->wl, 1);
  2166. goto out;
  2167. start_ieee80211:
  2168. wl->hw->queues = B43_QOS_QUEUE_NUM;
  2169. if (!modparam_qos || dev->fw.opensource)
  2170. wl->hw->queues = 1;
  2171. err = ieee80211_register_hw(wl->hw);
  2172. if (err)
  2173. goto err_one_core_detach;
  2174. wl->hw_registred = true;
  2175. b43_leds_register(wl->current_dev);
  2176. goto out;
  2177. err_one_core_detach:
  2178. b43_one_core_detach(dev->dev);
  2179. out:
  2180. kfree(ctx);
  2181. }
  2182. static int b43_upload_microcode(struct b43_wldev *dev)
  2183. {
  2184. struct wiphy *wiphy = dev->wl->hw->wiphy;
  2185. const size_t hdr_len = sizeof(struct b43_fw_header);
  2186. const __be32 *data;
  2187. unsigned int i, len;
  2188. u16 fwrev, fwpatch, fwdate, fwtime;
  2189. u32 tmp, macctl;
  2190. int err = 0;
  2191. /* Jump the microcode PSM to offset 0 */
  2192. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  2193. B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
  2194. macctl |= B43_MACCTL_PSM_JMP0;
  2195. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  2196. /* Zero out all microcode PSM registers and shared memory. */
  2197. for (i = 0; i < 64; i++)
  2198. b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
  2199. for (i = 0; i < 4096; i += 2)
  2200. b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
  2201. /* Upload Microcode. */
  2202. data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
  2203. len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
  2204. b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
  2205. for (i = 0; i < len; i++) {
  2206. b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
  2207. udelay(10);
  2208. }
  2209. if (dev->fw.pcm.data) {
  2210. /* Upload PCM data. */
  2211. data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
  2212. len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
  2213. b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
  2214. b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
  2215. /* No need for autoinc bit in SHM_HW */
  2216. b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
  2217. for (i = 0; i < len; i++) {
  2218. b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
  2219. udelay(10);
  2220. }
  2221. }
  2222. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
  2223. /* Start the microcode PSM */
  2224. b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_JMP0,
  2225. B43_MACCTL_PSM_RUN);
  2226. /* Wait for the microcode to load and respond */
  2227. i = 0;
  2228. while (1) {
  2229. tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  2230. if (tmp == B43_IRQ_MAC_SUSPENDED)
  2231. break;
  2232. i++;
  2233. if (i >= 20) {
  2234. b43err(dev->wl, "Microcode not responding\n");
  2235. b43_print_fw_helptext(dev->wl, 1);
  2236. err = -ENODEV;
  2237. goto error;
  2238. }
  2239. msleep(50);
  2240. }
  2241. b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
  2242. /* Get and check the revisions. */
  2243. fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
  2244. fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
  2245. fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
  2246. fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
  2247. if (fwrev <= 0x128) {
  2248. b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
  2249. "binary drivers older than version 4.x is unsupported. "
  2250. "You must upgrade your firmware files.\n");
  2251. b43_print_fw_helptext(dev->wl, 1);
  2252. err = -EOPNOTSUPP;
  2253. goto error;
  2254. }
  2255. dev->fw.rev = fwrev;
  2256. dev->fw.patch = fwpatch;
  2257. if (dev->fw.rev >= 598)
  2258. dev->fw.hdr_format = B43_FW_HDR_598;
  2259. else if (dev->fw.rev >= 410)
  2260. dev->fw.hdr_format = B43_FW_HDR_410;
  2261. else
  2262. dev->fw.hdr_format = B43_FW_HDR_351;
  2263. WARN_ON(dev->fw.opensource != (fwdate == 0xFFFF));
  2264. dev->qos_enabled = dev->wl->hw->queues > 1;
  2265. /* Default to firmware/hardware crypto acceleration. */
  2266. dev->hwcrypto_enabled = true;
  2267. if (dev->fw.opensource) {
  2268. u16 fwcapa;
  2269. /* Patchlevel info is encoded in the "time" field. */
  2270. dev->fw.patch = fwtime;
  2271. b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
  2272. dev->fw.rev, dev->fw.patch);
  2273. fwcapa = b43_fwcapa_read(dev);
  2274. if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
  2275. b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
  2276. /* Disable hardware crypto and fall back to software crypto. */
  2277. dev->hwcrypto_enabled = false;
  2278. }
  2279. /* adding QoS support should use an offline discovery mechanism */
  2280. WARN(fwcapa & B43_FWCAPA_QOS, "QoS in OpenFW not supported\n");
  2281. } else {
  2282. b43info(dev->wl, "Loading firmware version %u.%u "
  2283. "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
  2284. fwrev, fwpatch,
  2285. (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
  2286. (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
  2287. if (dev->fw.pcm_request_failed) {
  2288. b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
  2289. "Hardware accelerated cryptography is disabled.\n");
  2290. b43_print_fw_helptext(dev->wl, 0);
  2291. }
  2292. }
  2293. snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
  2294. dev->fw.rev, dev->fw.patch);
  2295. wiphy->hw_version = dev->dev->core_id;
  2296. if (dev->fw.hdr_format == B43_FW_HDR_351) {
  2297. /* We're over the deadline, but we keep support for old fw
  2298. * until it turns out to be in major conflict with something new. */
  2299. b43warn(dev->wl, "You are using an old firmware image. "
  2300. "Support for old firmware will be removed soon "
  2301. "(official deadline was July 2008).\n");
  2302. b43_print_fw_helptext(dev->wl, 0);
  2303. }
  2304. return 0;
  2305. error:
  2306. /* Stop the microcode PSM. */
  2307. b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
  2308. B43_MACCTL_PSM_JMP0);
  2309. return err;
  2310. }
  2311. static int b43_write_initvals(struct b43_wldev *dev,
  2312. const struct b43_iv *ivals,
  2313. size_t count,
  2314. size_t array_size)
  2315. {
  2316. const struct b43_iv *iv;
  2317. u16 offset;
  2318. size_t i;
  2319. bool bit32;
  2320. BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
  2321. iv = ivals;
  2322. for (i = 0; i < count; i++) {
  2323. if (array_size < sizeof(iv->offset_size))
  2324. goto err_format;
  2325. array_size -= sizeof(iv->offset_size);
  2326. offset = be16_to_cpu(iv->offset_size);
  2327. bit32 = !!(offset & B43_IV_32BIT);
  2328. offset &= B43_IV_OFFSET_MASK;
  2329. if (offset >= 0x1000)
  2330. goto err_format;
  2331. if (bit32) {
  2332. u32 value;
  2333. if (array_size < sizeof(iv->data.d32))
  2334. goto err_format;
  2335. array_size -= sizeof(iv->data.d32);
  2336. value = get_unaligned_be32(&iv->data.d32);
  2337. b43_write32(dev, offset, value);
  2338. iv = (const struct b43_iv *)((const uint8_t *)iv +
  2339. sizeof(__be16) +
  2340. sizeof(__be32));
  2341. } else {
  2342. u16 value;
  2343. if (array_size < sizeof(iv->data.d16))
  2344. goto err_format;
  2345. array_size -= sizeof(iv->data.d16);
  2346. value = be16_to_cpu(iv->data.d16);
  2347. b43_write16(dev, offset, value);
  2348. iv = (const struct b43_iv *)((const uint8_t *)iv +
  2349. sizeof(__be16) +
  2350. sizeof(__be16));
  2351. }
  2352. }
  2353. if (array_size)
  2354. goto err_format;
  2355. return 0;
  2356. err_format:
  2357. b43err(dev->wl, "Initial Values Firmware file-format error.\n");
  2358. b43_print_fw_helptext(dev->wl, 1);
  2359. return -EPROTO;
  2360. }
  2361. static int b43_upload_initvals(struct b43_wldev *dev)
  2362. {
  2363. const size_t hdr_len = sizeof(struct b43_fw_header);
  2364. const struct b43_fw_header *hdr;
  2365. struct b43_firmware *fw = &dev->fw;
  2366. const struct b43_iv *ivals;
  2367. size_t count;
  2368. int err;
  2369. hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
  2370. ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
  2371. count = be32_to_cpu(hdr->size);
  2372. err = b43_write_initvals(dev, ivals, count,
  2373. fw->initvals.data->size - hdr_len);
  2374. if (err)
  2375. goto out;
  2376. if (fw->initvals_band.data) {
  2377. hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
  2378. ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
  2379. count = be32_to_cpu(hdr->size);
  2380. err = b43_write_initvals(dev, ivals, count,
  2381. fw->initvals_band.data->size - hdr_len);
  2382. if (err)
  2383. goto out;
  2384. }
  2385. out:
  2386. return err;
  2387. }
  2388. /* Initialize the GPIOs
  2389. * http://bcm-specs.sipsolutions.net/GPIO
  2390. */
  2391. static struct ssb_device *b43_ssb_gpio_dev(struct b43_wldev *dev)
  2392. {
  2393. struct ssb_bus *bus = dev->dev->sdev->bus;
  2394. #ifdef CONFIG_SSB_DRIVER_PCICORE
  2395. return (bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev);
  2396. #else
  2397. return bus->chipco.dev;
  2398. #endif
  2399. }
  2400. static int b43_gpio_init(struct b43_wldev *dev)
  2401. {
  2402. struct ssb_device *gpiodev;
  2403. u32 mask, set;
  2404. b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
  2405. b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xF);
  2406. mask = 0x0000001F;
  2407. set = 0x0000000F;
  2408. if (dev->dev->chip_id == 0x4301) {
  2409. mask |= 0x0060;
  2410. set |= 0x0060;
  2411. } else if (dev->dev->chip_id == 0x5354) {
  2412. /* Don't allow overtaking buttons GPIOs */
  2413. set &= 0x2; /* 0x2 is LED GPIO on BCM5354 */
  2414. }
  2415. if (0 /* FIXME: conditional unknown */ ) {
  2416. b43_write16(dev, B43_MMIO_GPIO_MASK,
  2417. b43_read16(dev, B43_MMIO_GPIO_MASK)
  2418. | 0x0100);
  2419. /* BT Coexistance Input */
  2420. mask |= 0x0080;
  2421. set |= 0x0080;
  2422. /* BT Coexistance Out */
  2423. mask |= 0x0100;
  2424. set |= 0x0100;
  2425. }
  2426. if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_PACTRL) {
  2427. /* PA is controlled by gpio 9, let ucode handle it */
  2428. b43_write16(dev, B43_MMIO_GPIO_MASK,
  2429. b43_read16(dev, B43_MMIO_GPIO_MASK)
  2430. | 0x0200);
  2431. mask |= 0x0200;
  2432. set |= 0x0200;
  2433. }
  2434. switch (dev->dev->bus_type) {
  2435. #ifdef CONFIG_B43_BCMA
  2436. case B43_BUS_BCMA:
  2437. bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, mask, set);
  2438. break;
  2439. #endif
  2440. #ifdef CONFIG_B43_SSB
  2441. case B43_BUS_SSB:
  2442. gpiodev = b43_ssb_gpio_dev(dev);
  2443. if (gpiodev)
  2444. ssb_write32(gpiodev, B43_GPIO_CONTROL,
  2445. (ssb_read32(gpiodev, B43_GPIO_CONTROL)
  2446. & ~mask) | set);
  2447. break;
  2448. #endif
  2449. }
  2450. return 0;
  2451. }
  2452. /* Turn off all GPIO stuff. Call this on module unload, for example. */
  2453. static void b43_gpio_cleanup(struct b43_wldev *dev)
  2454. {
  2455. struct ssb_device *gpiodev;
  2456. switch (dev->dev->bus_type) {
  2457. #ifdef CONFIG_B43_BCMA
  2458. case B43_BUS_BCMA:
  2459. bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, ~0, 0);
  2460. break;
  2461. #endif
  2462. #ifdef CONFIG_B43_SSB
  2463. case B43_BUS_SSB:
  2464. gpiodev = b43_ssb_gpio_dev(dev);
  2465. if (gpiodev)
  2466. ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
  2467. break;
  2468. #endif
  2469. }
  2470. }
  2471. /* http://bcm-specs.sipsolutions.net/EnableMac */
  2472. void b43_mac_enable(struct b43_wldev *dev)
  2473. {
  2474. if (b43_debug(dev, B43_DBG_FIRMWARE)) {
  2475. u16 fwstate;
  2476. fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
  2477. B43_SHM_SH_UCODESTAT);
  2478. if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
  2479. (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
  2480. b43err(dev->wl, "b43_mac_enable(): The firmware "
  2481. "should be suspended, but current state is %u\n",
  2482. fwstate);
  2483. }
  2484. }
  2485. dev->mac_suspended--;
  2486. B43_WARN_ON(dev->mac_suspended < 0);
  2487. if (dev->mac_suspended == 0) {
  2488. b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_ENABLED);
  2489. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
  2490. B43_IRQ_MAC_SUSPENDED);
  2491. /* Commit writes */
  2492. b43_read32(dev, B43_MMIO_MACCTL);
  2493. b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  2494. b43_power_saving_ctl_bits(dev, 0);
  2495. }
  2496. }
  2497. /* http://bcm-specs.sipsolutions.net/SuspendMAC */
  2498. void b43_mac_suspend(struct b43_wldev *dev)
  2499. {
  2500. int i;
  2501. u32 tmp;
  2502. might_sleep();
  2503. B43_WARN_ON(dev->mac_suspended < 0);
  2504. if (dev->mac_suspended == 0) {
  2505. b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
  2506. b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_ENABLED, 0);
  2507. /* force pci to flush the write */
  2508. b43_read32(dev, B43_MMIO_MACCTL);
  2509. for (i = 35; i; i--) {
  2510. tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  2511. if (tmp & B43_IRQ_MAC_SUSPENDED)
  2512. goto out;
  2513. udelay(10);
  2514. }
  2515. /* Hm, it seems this will take some time. Use msleep(). */
  2516. for (i = 40; i; i--) {
  2517. tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  2518. if (tmp & B43_IRQ_MAC_SUSPENDED)
  2519. goto out;
  2520. msleep(1);
  2521. }
  2522. b43err(dev->wl, "MAC suspend failed\n");
  2523. }
  2524. out:
  2525. dev->mac_suspended++;
  2526. }
  2527. /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
  2528. void b43_mac_phy_clock_set(struct b43_wldev *dev, bool on)
  2529. {
  2530. u32 tmp;
  2531. switch (dev->dev->bus_type) {
  2532. #ifdef CONFIG_B43_BCMA
  2533. case B43_BUS_BCMA:
  2534. tmp = bcma_aread32(dev->dev->bdev, BCMA_IOCTL);
  2535. if (on)
  2536. tmp |= B43_BCMA_IOCTL_MACPHYCLKEN;
  2537. else
  2538. tmp &= ~B43_BCMA_IOCTL_MACPHYCLKEN;
  2539. bcma_awrite32(dev->dev->bdev, BCMA_IOCTL, tmp);
  2540. break;
  2541. #endif
  2542. #ifdef CONFIG_B43_SSB
  2543. case B43_BUS_SSB:
  2544. tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
  2545. if (on)
  2546. tmp |= B43_TMSLOW_MACPHYCLKEN;
  2547. else
  2548. tmp &= ~B43_TMSLOW_MACPHYCLKEN;
  2549. ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
  2550. break;
  2551. #endif
  2552. }
  2553. }
  2554. static void b43_adjust_opmode(struct b43_wldev *dev)
  2555. {
  2556. struct b43_wl *wl = dev->wl;
  2557. u32 ctl;
  2558. u16 cfp_pretbtt;
  2559. ctl = b43_read32(dev, B43_MMIO_MACCTL);
  2560. /* Reset status to STA infrastructure mode. */
  2561. ctl &= ~B43_MACCTL_AP;
  2562. ctl &= ~B43_MACCTL_KEEP_CTL;
  2563. ctl &= ~B43_MACCTL_KEEP_BADPLCP;
  2564. ctl &= ~B43_MACCTL_KEEP_BAD;
  2565. ctl &= ~B43_MACCTL_PROMISC;
  2566. ctl &= ~B43_MACCTL_BEACPROMISC;
  2567. ctl |= B43_MACCTL_INFRA;
  2568. if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
  2569. b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
  2570. ctl |= B43_MACCTL_AP;
  2571. else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
  2572. ctl &= ~B43_MACCTL_INFRA;
  2573. if (wl->filter_flags & FIF_CONTROL)
  2574. ctl |= B43_MACCTL_KEEP_CTL;
  2575. if (wl->filter_flags & FIF_FCSFAIL)
  2576. ctl |= B43_MACCTL_KEEP_BAD;
  2577. if (wl->filter_flags & FIF_PLCPFAIL)
  2578. ctl |= B43_MACCTL_KEEP_BADPLCP;
  2579. if (wl->filter_flags & FIF_PROMISC_IN_BSS)
  2580. ctl |= B43_MACCTL_PROMISC;
  2581. if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
  2582. ctl |= B43_MACCTL_BEACPROMISC;
  2583. /* Workaround: On old hardware the HW-MAC-address-filter
  2584. * doesn't work properly, so always run promisc in filter
  2585. * it in software. */
  2586. if (dev->dev->core_rev <= 4)
  2587. ctl |= B43_MACCTL_PROMISC;
  2588. b43_write32(dev, B43_MMIO_MACCTL, ctl);
  2589. cfp_pretbtt = 2;
  2590. if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
  2591. if (dev->dev->chip_id == 0x4306 &&
  2592. dev->dev->chip_rev == 3)
  2593. cfp_pretbtt = 100;
  2594. else
  2595. cfp_pretbtt = 50;
  2596. }
  2597. b43_write16(dev, 0x612, cfp_pretbtt);
  2598. /* FIXME: We don't currently implement the PMQ mechanism,
  2599. * so always disable it. If we want to implement PMQ,
  2600. * we need to enable it here (clear DISCPMQ) in AP mode.
  2601. */
  2602. if (0 /* ctl & B43_MACCTL_AP */)
  2603. b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_DISCPMQ, 0);
  2604. else
  2605. b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_DISCPMQ);
  2606. }
  2607. static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
  2608. {
  2609. u16 offset;
  2610. if (is_ofdm) {
  2611. offset = 0x480;
  2612. offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
  2613. } else {
  2614. offset = 0x4C0;
  2615. offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
  2616. }
  2617. b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
  2618. b43_shm_read16(dev, B43_SHM_SHARED, offset));
  2619. }
  2620. static void b43_rate_memory_init(struct b43_wldev *dev)
  2621. {
  2622. switch (dev->phy.type) {
  2623. case B43_PHYTYPE_A:
  2624. case B43_PHYTYPE_G:
  2625. case B43_PHYTYPE_N:
  2626. case B43_PHYTYPE_LP:
  2627. case B43_PHYTYPE_HT:
  2628. case B43_PHYTYPE_LCN:
  2629. b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
  2630. b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
  2631. b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
  2632. b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
  2633. b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
  2634. b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
  2635. b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
  2636. if (dev->phy.type == B43_PHYTYPE_A)
  2637. break;
  2638. /* fallthrough */
  2639. case B43_PHYTYPE_B:
  2640. b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
  2641. b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
  2642. b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
  2643. b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
  2644. break;
  2645. default:
  2646. B43_WARN_ON(1);
  2647. }
  2648. }
  2649. /* Set the default values for the PHY TX Control Words. */
  2650. static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
  2651. {
  2652. u16 ctl = 0;
  2653. ctl |= B43_TXH_PHY_ENC_CCK;
  2654. ctl |= B43_TXH_PHY_ANT01AUTO;
  2655. ctl |= B43_TXH_PHY_TXPWR;
  2656. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
  2657. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
  2658. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
  2659. }
  2660. /* Set the TX-Antenna for management frames sent by firmware. */
  2661. static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
  2662. {
  2663. u16 ant;
  2664. u16 tmp;
  2665. ant = b43_antenna_to_phyctl(antenna);
  2666. /* For ACK/CTS */
  2667. tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
  2668. tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
  2669. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
  2670. /* For Probe Resposes */
  2671. tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
  2672. tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
  2673. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
  2674. }
  2675. /* This is the opposite of b43_chip_init() */
  2676. static void b43_chip_exit(struct b43_wldev *dev)
  2677. {
  2678. b43_phy_exit(dev);
  2679. b43_gpio_cleanup(dev);
  2680. /* firmware is released later */
  2681. }
  2682. /* Initialize the chip
  2683. * http://bcm-specs.sipsolutions.net/ChipInit
  2684. */
  2685. static int b43_chip_init(struct b43_wldev *dev)
  2686. {
  2687. struct b43_phy *phy = &dev->phy;
  2688. int err;
  2689. u32 macctl;
  2690. u16 value16;
  2691. /* Initialize the MAC control */
  2692. macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
  2693. if (dev->phy.gmode)
  2694. macctl |= B43_MACCTL_GMODE;
  2695. macctl |= B43_MACCTL_INFRA;
  2696. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  2697. err = b43_upload_microcode(dev);
  2698. if (err)
  2699. goto out; /* firmware is released later */
  2700. err = b43_gpio_init(dev);
  2701. if (err)
  2702. goto out; /* firmware is released later */
  2703. err = b43_upload_initvals(dev);
  2704. if (err)
  2705. goto err_gpio_clean;
  2706. /* Turn the Analog on and initialize the PHY. */
  2707. phy->ops->switch_analog(dev, 1);
  2708. err = b43_phy_init(dev);
  2709. if (err)
  2710. goto err_gpio_clean;
  2711. /* Disable Interference Mitigation. */
  2712. if (phy->ops->interf_mitigation)
  2713. phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
  2714. /* Select the antennae */
  2715. if (phy->ops->set_rx_antenna)
  2716. phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
  2717. b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
  2718. if (phy->type == B43_PHYTYPE_B) {
  2719. value16 = b43_read16(dev, 0x005E);
  2720. value16 |= 0x0004;
  2721. b43_write16(dev, 0x005E, value16);
  2722. }
  2723. b43_write32(dev, 0x0100, 0x01000000);
  2724. if (dev->dev->core_rev < 5)
  2725. b43_write32(dev, 0x010C, 0x01000000);
  2726. b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_INFRA, 0);
  2727. b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_INFRA);
  2728. /* Probe Response Timeout value */
  2729. /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
  2730. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 0);
  2731. /* Initially set the wireless operation mode. */
  2732. b43_adjust_opmode(dev);
  2733. if (dev->dev->core_rev < 3) {
  2734. b43_write16(dev, 0x060E, 0x0000);
  2735. b43_write16(dev, 0x0610, 0x8000);
  2736. b43_write16(dev, 0x0604, 0x0000);
  2737. b43_write16(dev, 0x0606, 0x0200);
  2738. } else {
  2739. b43_write32(dev, 0x0188, 0x80000000);
  2740. b43_write32(dev, 0x018C, 0x02000000);
  2741. }
  2742. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
  2743. b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001FC00);
  2744. b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
  2745. b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
  2746. b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
  2747. b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
  2748. b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
  2749. b43_mac_phy_clock_set(dev, true);
  2750. switch (dev->dev->bus_type) {
  2751. #ifdef CONFIG_B43_BCMA
  2752. case B43_BUS_BCMA:
  2753. /* FIXME: 0xE74 is quite common, but should be read from CC */
  2754. b43_write16(dev, B43_MMIO_POWERUP_DELAY, 0xE74);
  2755. break;
  2756. #endif
  2757. #ifdef CONFIG_B43_SSB
  2758. case B43_BUS_SSB:
  2759. b43_write16(dev, B43_MMIO_POWERUP_DELAY,
  2760. dev->dev->sdev->bus->chipco.fast_pwrup_delay);
  2761. break;
  2762. #endif
  2763. }
  2764. err = 0;
  2765. b43dbg(dev->wl, "Chip initialized\n");
  2766. out:
  2767. return err;
  2768. err_gpio_clean:
  2769. b43_gpio_cleanup(dev);
  2770. return err;
  2771. }
  2772. static void b43_periodic_every60sec(struct b43_wldev *dev)
  2773. {
  2774. const struct b43_phy_operations *ops = dev->phy.ops;
  2775. if (ops->pwork_60sec)
  2776. ops->pwork_60sec(dev);
  2777. /* Force check the TX power emission now. */
  2778. b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
  2779. }
  2780. static void b43_periodic_every30sec(struct b43_wldev *dev)
  2781. {
  2782. /* Update device statistics. */
  2783. b43_calculate_link_quality(dev);
  2784. }
  2785. static void b43_periodic_every15sec(struct b43_wldev *dev)
  2786. {
  2787. struct b43_phy *phy = &dev->phy;
  2788. u16 wdr;
  2789. if (dev->fw.opensource) {
  2790. /* Check if the firmware is still alive.
  2791. * It will reset the watchdog counter to 0 in its idle loop. */
  2792. wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
  2793. if (unlikely(wdr)) {
  2794. b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
  2795. b43_controller_restart(dev, "Firmware watchdog");
  2796. return;
  2797. } else {
  2798. b43_shm_write16(dev, B43_SHM_SCRATCH,
  2799. B43_WATCHDOG_REG, 1);
  2800. }
  2801. }
  2802. if (phy->ops->pwork_15sec)
  2803. phy->ops->pwork_15sec(dev);
  2804. atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
  2805. wmb();
  2806. #if B43_DEBUG
  2807. if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
  2808. unsigned int i;
  2809. b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
  2810. dev->irq_count / 15,
  2811. dev->tx_count / 15,
  2812. dev->rx_count / 15);
  2813. dev->irq_count = 0;
  2814. dev->tx_count = 0;
  2815. dev->rx_count = 0;
  2816. for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
  2817. if (dev->irq_bit_count[i]) {
  2818. b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
  2819. dev->irq_bit_count[i] / 15, i, (1 << i));
  2820. dev->irq_bit_count[i] = 0;
  2821. }
  2822. }
  2823. }
  2824. #endif
  2825. }
  2826. static void do_periodic_work(struct b43_wldev *dev)
  2827. {
  2828. unsigned int state;
  2829. state = dev->periodic_state;
  2830. if (state % 4 == 0)
  2831. b43_periodic_every60sec(dev);
  2832. if (state % 2 == 0)
  2833. b43_periodic_every30sec(dev);
  2834. b43_periodic_every15sec(dev);
  2835. }
  2836. /* Periodic work locking policy:
  2837. * The whole periodic work handler is protected by
  2838. * wl->mutex. If another lock is needed somewhere in the
  2839. * pwork callchain, it's acquired in-place, where it's needed.
  2840. */
  2841. static void b43_periodic_work_handler(struct work_struct *work)
  2842. {
  2843. struct b43_wldev *dev = container_of(work, struct b43_wldev,
  2844. periodic_work.work);
  2845. struct b43_wl *wl = dev->wl;
  2846. unsigned long delay;
  2847. mutex_lock(&wl->mutex);
  2848. if (unlikely(b43_status(dev) != B43_STAT_STARTED))
  2849. goto out;
  2850. if (b43_debug(dev, B43_DBG_PWORK_STOP))
  2851. goto out_requeue;
  2852. do_periodic_work(dev);
  2853. dev->periodic_state++;
  2854. out_requeue:
  2855. if (b43_debug(dev, B43_DBG_PWORK_FAST))
  2856. delay = msecs_to_jiffies(50);
  2857. else
  2858. delay = round_jiffies_relative(HZ * 15);
  2859. ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
  2860. out:
  2861. mutex_unlock(&wl->mutex);
  2862. }
  2863. static void b43_periodic_tasks_setup(struct b43_wldev *dev)
  2864. {
  2865. struct delayed_work *work = &dev->periodic_work;
  2866. dev->periodic_state = 0;
  2867. INIT_DELAYED_WORK(work, b43_periodic_work_handler);
  2868. ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
  2869. }
  2870. /* Check if communication with the device works correctly. */
  2871. static int b43_validate_chipaccess(struct b43_wldev *dev)
  2872. {
  2873. u32 v, backup0, backup4;
  2874. backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
  2875. backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
  2876. /* Check for read/write and endianness problems. */
  2877. b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
  2878. if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
  2879. goto error;
  2880. b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
  2881. if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
  2882. goto error;
  2883. /* Check if unaligned 32bit SHM_SHARED access works properly.
  2884. * However, don't bail out on failure, because it's noncritical. */
  2885. b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
  2886. b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
  2887. b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
  2888. b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
  2889. if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
  2890. b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
  2891. b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
  2892. if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
  2893. b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
  2894. b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
  2895. b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
  2896. b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
  2897. b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
  2898. b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
  2899. if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
  2900. /* The 32bit register shadows the two 16bit registers
  2901. * with update sideeffects. Validate this. */
  2902. b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
  2903. b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
  2904. if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
  2905. goto error;
  2906. if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
  2907. goto error;
  2908. }
  2909. b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
  2910. v = b43_read32(dev, B43_MMIO_MACCTL);
  2911. v |= B43_MACCTL_GMODE;
  2912. if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
  2913. goto error;
  2914. return 0;
  2915. error:
  2916. b43err(dev->wl, "Failed to validate the chipaccess\n");
  2917. return -ENODEV;
  2918. }
  2919. static void b43_security_init(struct b43_wldev *dev)
  2920. {
  2921. dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
  2922. /* KTP is a word address, but we address SHM bytewise.
  2923. * So multiply by two.
  2924. */
  2925. dev->ktp *= 2;
  2926. /* Number of RCMTA address slots */
  2927. b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
  2928. /* Clear the key memory. */
  2929. b43_clear_keys(dev);
  2930. }
  2931. #ifdef CONFIG_B43_HWRNG
  2932. static int b43_rng_read(struct hwrng *rng, u32 *data)
  2933. {
  2934. struct b43_wl *wl = (struct b43_wl *)rng->priv;
  2935. struct b43_wldev *dev;
  2936. int count = -ENODEV;
  2937. mutex_lock(&wl->mutex);
  2938. dev = wl->current_dev;
  2939. if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
  2940. *data = b43_read16(dev, B43_MMIO_RNG);
  2941. count = sizeof(u16);
  2942. }
  2943. mutex_unlock(&wl->mutex);
  2944. return count;
  2945. }
  2946. #endif /* CONFIG_B43_HWRNG */
  2947. static void b43_rng_exit(struct b43_wl *wl)
  2948. {
  2949. #ifdef CONFIG_B43_HWRNG
  2950. if (wl->rng_initialized)
  2951. hwrng_unregister(&wl->rng);
  2952. #endif /* CONFIG_B43_HWRNG */
  2953. }
  2954. static int b43_rng_init(struct b43_wl *wl)
  2955. {
  2956. int err = 0;
  2957. #ifdef CONFIG_B43_HWRNG
  2958. snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
  2959. "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
  2960. wl->rng.name = wl->rng_name;
  2961. wl->rng.data_read = b43_rng_read;
  2962. wl->rng.priv = (unsigned long)wl;
  2963. wl->rng_initialized = true;
  2964. err = hwrng_register(&wl->rng);
  2965. if (err) {
  2966. wl->rng_initialized = false;
  2967. b43err(wl, "Failed to register the random "
  2968. "number generator (%d)\n", err);
  2969. }
  2970. #endif /* CONFIG_B43_HWRNG */
  2971. return err;
  2972. }
  2973. static void b43_tx_work(struct work_struct *work)
  2974. {
  2975. struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
  2976. struct b43_wldev *dev;
  2977. struct sk_buff *skb;
  2978. int queue_num;
  2979. int err = 0;
  2980. mutex_lock(&wl->mutex);
  2981. dev = wl->current_dev;
  2982. if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
  2983. mutex_unlock(&wl->mutex);
  2984. return;
  2985. }
  2986. for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
  2987. while (skb_queue_len(&wl->tx_queue[queue_num])) {
  2988. skb = skb_dequeue(&wl->tx_queue[queue_num]);
  2989. if (b43_using_pio_transfers(dev))
  2990. err = b43_pio_tx(dev, skb);
  2991. else
  2992. err = b43_dma_tx(dev, skb);
  2993. if (err == -ENOSPC) {
  2994. wl->tx_queue_stopped[queue_num] = 1;
  2995. ieee80211_stop_queue(wl->hw, queue_num);
  2996. skb_queue_head(&wl->tx_queue[queue_num], skb);
  2997. break;
  2998. }
  2999. if (unlikely(err))
  3000. ieee80211_free_txskb(wl->hw, skb);
  3001. err = 0;
  3002. }
  3003. if (!err)
  3004. wl->tx_queue_stopped[queue_num] = 0;
  3005. }
  3006. #if B43_DEBUG
  3007. dev->tx_count++;
  3008. #endif
  3009. mutex_unlock(&wl->mutex);
  3010. }
  3011. static void b43_op_tx(struct ieee80211_hw *hw,
  3012. struct ieee80211_tx_control *control,
  3013. struct sk_buff *skb)
  3014. {
  3015. struct b43_wl *wl = hw_to_b43_wl(hw);
  3016. if (unlikely(skb->len < 2 + 2 + 6)) {
  3017. /* Too short, this can't be a valid frame. */
  3018. ieee80211_free_txskb(hw, skb);
  3019. return;
  3020. }
  3021. B43_WARN_ON(skb_shinfo(skb)->nr_frags);
  3022. skb_queue_tail(&wl->tx_queue[skb->queue_mapping], skb);
  3023. if (!wl->tx_queue_stopped[skb->queue_mapping]) {
  3024. ieee80211_queue_work(wl->hw, &wl->tx_work);
  3025. } else {
  3026. ieee80211_stop_queue(wl->hw, skb->queue_mapping);
  3027. }
  3028. }
  3029. static void b43_qos_params_upload(struct b43_wldev *dev,
  3030. const struct ieee80211_tx_queue_params *p,
  3031. u16 shm_offset)
  3032. {
  3033. u16 params[B43_NR_QOSPARAMS];
  3034. int bslots, tmp;
  3035. unsigned int i;
  3036. if (!dev->qos_enabled)
  3037. return;
  3038. bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
  3039. memset(&params, 0, sizeof(params));
  3040. params[B43_QOSPARAM_TXOP] = p->txop * 32;
  3041. params[B43_QOSPARAM_CWMIN] = p->cw_min;
  3042. params[B43_QOSPARAM_CWMAX] = p->cw_max;
  3043. params[B43_QOSPARAM_CWCUR] = p->cw_min;
  3044. params[B43_QOSPARAM_AIFS] = p->aifs;
  3045. params[B43_QOSPARAM_BSLOTS] = bslots;
  3046. params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
  3047. for (i = 0; i < ARRAY_SIZE(params); i++) {
  3048. if (i == B43_QOSPARAM_STATUS) {
  3049. tmp = b43_shm_read16(dev, B43_SHM_SHARED,
  3050. shm_offset + (i * 2));
  3051. /* Mark the parameters as updated. */
  3052. tmp |= 0x100;
  3053. b43_shm_write16(dev, B43_SHM_SHARED,
  3054. shm_offset + (i * 2),
  3055. tmp);
  3056. } else {
  3057. b43_shm_write16(dev, B43_SHM_SHARED,
  3058. shm_offset + (i * 2),
  3059. params[i]);
  3060. }
  3061. }
  3062. }
  3063. /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
  3064. static const u16 b43_qos_shm_offsets[] = {
  3065. /* [mac80211-queue-nr] = SHM_OFFSET, */
  3066. [0] = B43_QOS_VOICE,
  3067. [1] = B43_QOS_VIDEO,
  3068. [2] = B43_QOS_BESTEFFORT,
  3069. [3] = B43_QOS_BACKGROUND,
  3070. };
  3071. /* Update all QOS parameters in hardware. */
  3072. static void b43_qos_upload_all(struct b43_wldev *dev)
  3073. {
  3074. struct b43_wl *wl = dev->wl;
  3075. struct b43_qos_params *params;
  3076. unsigned int i;
  3077. if (!dev->qos_enabled)
  3078. return;
  3079. BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
  3080. ARRAY_SIZE(wl->qos_params));
  3081. b43_mac_suspend(dev);
  3082. for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
  3083. params = &(wl->qos_params[i]);
  3084. b43_qos_params_upload(dev, &(params->p),
  3085. b43_qos_shm_offsets[i]);
  3086. }
  3087. b43_mac_enable(dev);
  3088. }
  3089. static void b43_qos_clear(struct b43_wl *wl)
  3090. {
  3091. struct b43_qos_params *params;
  3092. unsigned int i;
  3093. /* Initialize QoS parameters to sane defaults. */
  3094. BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
  3095. ARRAY_SIZE(wl->qos_params));
  3096. for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
  3097. params = &(wl->qos_params[i]);
  3098. switch (b43_qos_shm_offsets[i]) {
  3099. case B43_QOS_VOICE:
  3100. params->p.txop = 0;
  3101. params->p.aifs = 2;
  3102. params->p.cw_min = 0x0001;
  3103. params->p.cw_max = 0x0001;
  3104. break;
  3105. case B43_QOS_VIDEO:
  3106. params->p.txop = 0;
  3107. params->p.aifs = 2;
  3108. params->p.cw_min = 0x0001;
  3109. params->p.cw_max = 0x0001;
  3110. break;
  3111. case B43_QOS_BESTEFFORT:
  3112. params->p.txop = 0;
  3113. params->p.aifs = 3;
  3114. params->p.cw_min = 0x0001;
  3115. params->p.cw_max = 0x03FF;
  3116. break;
  3117. case B43_QOS_BACKGROUND:
  3118. params->p.txop = 0;
  3119. params->p.aifs = 7;
  3120. params->p.cw_min = 0x0001;
  3121. params->p.cw_max = 0x03FF;
  3122. break;
  3123. default:
  3124. B43_WARN_ON(1);
  3125. }
  3126. }
  3127. }
  3128. /* Initialize the core's QOS capabilities */
  3129. static void b43_qos_init(struct b43_wldev *dev)
  3130. {
  3131. if (!dev->qos_enabled) {
  3132. /* Disable QOS support. */
  3133. b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
  3134. b43_write16(dev, B43_MMIO_IFSCTL,
  3135. b43_read16(dev, B43_MMIO_IFSCTL)
  3136. & ~B43_MMIO_IFSCTL_USE_EDCF);
  3137. b43dbg(dev->wl, "QoS disabled\n");
  3138. return;
  3139. }
  3140. /* Upload the current QOS parameters. */
  3141. b43_qos_upload_all(dev);
  3142. /* Enable QOS support. */
  3143. b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
  3144. b43_write16(dev, B43_MMIO_IFSCTL,
  3145. b43_read16(dev, B43_MMIO_IFSCTL)
  3146. | B43_MMIO_IFSCTL_USE_EDCF);
  3147. b43dbg(dev->wl, "QoS enabled\n");
  3148. }
  3149. static int b43_op_conf_tx(struct ieee80211_hw *hw,
  3150. struct ieee80211_vif *vif, u16 _queue,
  3151. const struct ieee80211_tx_queue_params *params)
  3152. {
  3153. struct b43_wl *wl = hw_to_b43_wl(hw);
  3154. struct b43_wldev *dev;
  3155. unsigned int queue = (unsigned int)_queue;
  3156. int err = -ENODEV;
  3157. if (queue >= ARRAY_SIZE(wl->qos_params)) {
  3158. /* Queue not available or don't support setting
  3159. * params on this queue. Return success to not
  3160. * confuse mac80211. */
  3161. return 0;
  3162. }
  3163. BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
  3164. ARRAY_SIZE(wl->qos_params));
  3165. mutex_lock(&wl->mutex);
  3166. dev = wl->current_dev;
  3167. if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
  3168. goto out_unlock;
  3169. memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
  3170. b43_mac_suspend(dev);
  3171. b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
  3172. b43_qos_shm_offsets[queue]);
  3173. b43_mac_enable(dev);
  3174. err = 0;
  3175. out_unlock:
  3176. mutex_unlock(&wl->mutex);
  3177. return err;
  3178. }
  3179. static int b43_op_get_stats(struct ieee80211_hw *hw,
  3180. struct ieee80211_low_level_stats *stats)
  3181. {
  3182. struct b43_wl *wl = hw_to_b43_wl(hw);
  3183. mutex_lock(&wl->mutex);
  3184. memcpy(stats, &wl->ieee_stats, sizeof(*stats));
  3185. mutex_unlock(&wl->mutex);
  3186. return 0;
  3187. }
  3188. static u64 b43_op_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  3189. {
  3190. struct b43_wl *wl = hw_to_b43_wl(hw);
  3191. struct b43_wldev *dev;
  3192. u64 tsf;
  3193. mutex_lock(&wl->mutex);
  3194. dev = wl->current_dev;
  3195. if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
  3196. b43_tsf_read(dev, &tsf);
  3197. else
  3198. tsf = 0;
  3199. mutex_unlock(&wl->mutex);
  3200. return tsf;
  3201. }
  3202. static void b43_op_set_tsf(struct ieee80211_hw *hw,
  3203. struct ieee80211_vif *vif, u64 tsf)
  3204. {
  3205. struct b43_wl *wl = hw_to_b43_wl(hw);
  3206. struct b43_wldev *dev;
  3207. mutex_lock(&wl->mutex);
  3208. dev = wl->current_dev;
  3209. if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
  3210. b43_tsf_write(dev, tsf);
  3211. mutex_unlock(&wl->mutex);
  3212. }
  3213. static void b43_put_phy_into_reset(struct b43_wldev *dev)
  3214. {
  3215. u32 tmp;
  3216. switch (dev->dev->bus_type) {
  3217. #ifdef CONFIG_B43_BCMA
  3218. case B43_BUS_BCMA:
  3219. b43err(dev->wl,
  3220. "Putting PHY into reset not supported on BCMA\n");
  3221. break;
  3222. #endif
  3223. #ifdef CONFIG_B43_SSB
  3224. case B43_BUS_SSB:
  3225. tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
  3226. tmp &= ~B43_TMSLOW_GMODE;
  3227. tmp |= B43_TMSLOW_PHYRESET;
  3228. tmp |= SSB_TMSLOW_FGC;
  3229. ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
  3230. msleep(1);
  3231. tmp = ssb_read32(dev->dev->sdev, SSB_TMSLOW);
  3232. tmp &= ~SSB_TMSLOW_FGC;
  3233. tmp |= B43_TMSLOW_PHYRESET;
  3234. ssb_write32(dev->dev->sdev, SSB_TMSLOW, tmp);
  3235. msleep(1);
  3236. break;
  3237. #endif
  3238. }
  3239. }
  3240. static const char *band_to_string(enum ieee80211_band band)
  3241. {
  3242. switch (band) {
  3243. case IEEE80211_BAND_5GHZ:
  3244. return "5";
  3245. case IEEE80211_BAND_2GHZ:
  3246. return "2.4";
  3247. default:
  3248. break;
  3249. }
  3250. B43_WARN_ON(1);
  3251. return "";
  3252. }
  3253. /* Expects wl->mutex locked */
  3254. static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
  3255. {
  3256. struct b43_wldev *up_dev = NULL;
  3257. struct b43_wldev *down_dev;
  3258. struct b43_wldev *d;
  3259. int err;
  3260. bool uninitialized_var(gmode);
  3261. int prev_status;
  3262. /* Find a device and PHY which supports the band. */
  3263. list_for_each_entry(d, &wl->devlist, list) {
  3264. switch (chan->band) {
  3265. case IEEE80211_BAND_5GHZ:
  3266. if (d->phy.supports_5ghz) {
  3267. up_dev = d;
  3268. gmode = false;
  3269. }
  3270. break;
  3271. case IEEE80211_BAND_2GHZ:
  3272. if (d->phy.supports_2ghz) {
  3273. up_dev = d;
  3274. gmode = true;
  3275. }
  3276. break;
  3277. default:
  3278. B43_WARN_ON(1);
  3279. return -EINVAL;
  3280. }
  3281. if (up_dev)
  3282. break;
  3283. }
  3284. if (!up_dev) {
  3285. b43err(wl, "Could not find a device for %s-GHz band operation\n",
  3286. band_to_string(chan->band));
  3287. return -ENODEV;
  3288. }
  3289. if ((up_dev == wl->current_dev) &&
  3290. (!!wl->current_dev->phy.gmode == !!gmode)) {
  3291. /* This device is already running. */
  3292. return 0;
  3293. }
  3294. b43dbg(wl, "Switching to %s-GHz band\n",
  3295. band_to_string(chan->band));
  3296. down_dev = wl->current_dev;
  3297. prev_status = b43_status(down_dev);
  3298. /* Shutdown the currently running core. */
  3299. if (prev_status >= B43_STAT_STARTED)
  3300. down_dev = b43_wireless_core_stop(down_dev);
  3301. if (prev_status >= B43_STAT_INITIALIZED)
  3302. b43_wireless_core_exit(down_dev);
  3303. if (down_dev != up_dev) {
  3304. /* We switch to a different core, so we put PHY into
  3305. * RESET on the old core. */
  3306. b43_put_phy_into_reset(down_dev);
  3307. }
  3308. /* Now start the new core. */
  3309. up_dev->phy.gmode = gmode;
  3310. if (prev_status >= B43_STAT_INITIALIZED) {
  3311. err = b43_wireless_core_init(up_dev);
  3312. if (err) {
  3313. b43err(wl, "Fatal: Could not initialize device for "
  3314. "selected %s-GHz band\n",
  3315. band_to_string(chan->band));
  3316. goto init_failure;
  3317. }
  3318. }
  3319. if (prev_status >= B43_STAT_STARTED) {
  3320. err = b43_wireless_core_start(up_dev);
  3321. if (err) {
  3322. b43err(wl, "Fatal: Could not start device for "
  3323. "selected %s-GHz band\n",
  3324. band_to_string(chan->band));
  3325. b43_wireless_core_exit(up_dev);
  3326. goto init_failure;
  3327. }
  3328. }
  3329. B43_WARN_ON(b43_status(up_dev) != prev_status);
  3330. wl->current_dev = up_dev;
  3331. return 0;
  3332. init_failure:
  3333. /* Whoops, failed to init the new core. No core is operating now. */
  3334. wl->current_dev = NULL;
  3335. return err;
  3336. }
  3337. /* Write the short and long frame retry limit values. */
  3338. static void b43_set_retry_limits(struct b43_wldev *dev,
  3339. unsigned int short_retry,
  3340. unsigned int long_retry)
  3341. {
  3342. /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
  3343. * the chip-internal counter. */
  3344. short_retry = min(short_retry, (unsigned int)0xF);
  3345. long_retry = min(long_retry, (unsigned int)0xF);
  3346. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
  3347. short_retry);
  3348. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
  3349. long_retry);
  3350. }
  3351. static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
  3352. {
  3353. struct b43_wl *wl = hw_to_b43_wl(hw);
  3354. struct b43_wldev *dev;
  3355. struct b43_phy *phy;
  3356. struct ieee80211_conf *conf = &hw->conf;
  3357. int antenna;
  3358. int err = 0;
  3359. bool reload_bss = false;
  3360. mutex_lock(&wl->mutex);
  3361. dev = wl->current_dev;
  3362. /* Switch the band (if necessary). This might change the active core. */
  3363. err = b43_switch_band(wl, conf->chandef.chan);
  3364. if (err)
  3365. goto out_unlock_mutex;
  3366. /* Need to reload all settings if the core changed */
  3367. if (dev != wl->current_dev) {
  3368. dev = wl->current_dev;
  3369. changed = ~0;
  3370. reload_bss = true;
  3371. }
  3372. phy = &dev->phy;
  3373. if (conf_is_ht(conf))
  3374. phy->is_40mhz =
  3375. (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
  3376. else
  3377. phy->is_40mhz = false;
  3378. b43_mac_suspend(dev);
  3379. if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
  3380. b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
  3381. conf->long_frame_max_tx_count);
  3382. changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
  3383. if (!changed)
  3384. goto out_mac_enable;
  3385. /* Switch to the requested channel.
  3386. * The firmware takes care of races with the TX handler. */
  3387. if (conf->chandef.chan->hw_value != phy->channel)
  3388. b43_switch_channel(dev, conf->chandef.chan->hw_value);
  3389. dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
  3390. /* Adjust the desired TX power level. */
  3391. if (conf->power_level != 0) {
  3392. if (conf->power_level != phy->desired_txpower) {
  3393. phy->desired_txpower = conf->power_level;
  3394. b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
  3395. B43_TXPWR_IGNORE_TSSI);
  3396. }
  3397. }
  3398. /* Antennas for RX and management frame TX. */
  3399. antenna = B43_ANTENNA_DEFAULT;
  3400. b43_mgmtframe_txantenna(dev, antenna);
  3401. antenna = B43_ANTENNA_DEFAULT;
  3402. if (phy->ops->set_rx_antenna)
  3403. phy->ops->set_rx_antenna(dev, antenna);
  3404. if (wl->radio_enabled != phy->radio_on) {
  3405. if (wl->radio_enabled) {
  3406. b43_software_rfkill(dev, false);
  3407. b43info(dev->wl, "Radio turned on by software\n");
  3408. if (!dev->radio_hw_enable) {
  3409. b43info(dev->wl, "The hardware RF-kill button "
  3410. "still turns the radio physically off. "
  3411. "Press the button to turn it on.\n");
  3412. }
  3413. } else {
  3414. b43_software_rfkill(dev, true);
  3415. b43info(dev->wl, "Radio turned off by software\n");
  3416. }
  3417. }
  3418. out_mac_enable:
  3419. b43_mac_enable(dev);
  3420. out_unlock_mutex:
  3421. mutex_unlock(&wl->mutex);
  3422. if (wl->vif && reload_bss)
  3423. b43_op_bss_info_changed(hw, wl->vif, &wl->vif->bss_conf, ~0);
  3424. return err;
  3425. }
  3426. static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
  3427. {
  3428. struct ieee80211_supported_band *sband =
  3429. dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
  3430. struct ieee80211_rate *rate;
  3431. int i;
  3432. u16 basic, direct, offset, basic_offset, rateptr;
  3433. for (i = 0; i < sband->n_bitrates; i++) {
  3434. rate = &sband->bitrates[i];
  3435. if (b43_is_cck_rate(rate->hw_value)) {
  3436. direct = B43_SHM_SH_CCKDIRECT;
  3437. basic = B43_SHM_SH_CCKBASIC;
  3438. offset = b43_plcp_get_ratecode_cck(rate->hw_value);
  3439. offset &= 0xF;
  3440. } else {
  3441. direct = B43_SHM_SH_OFDMDIRECT;
  3442. basic = B43_SHM_SH_OFDMBASIC;
  3443. offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
  3444. offset &= 0xF;
  3445. }
  3446. rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
  3447. if (b43_is_cck_rate(rate->hw_value)) {
  3448. basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
  3449. basic_offset &= 0xF;
  3450. } else {
  3451. basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
  3452. basic_offset &= 0xF;
  3453. }
  3454. /*
  3455. * Get the pointer that we need to point to
  3456. * from the direct map
  3457. */
  3458. rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
  3459. direct + 2 * basic_offset);
  3460. /* and write it to the basic map */
  3461. b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
  3462. rateptr);
  3463. }
  3464. }
  3465. static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
  3466. struct ieee80211_vif *vif,
  3467. struct ieee80211_bss_conf *conf,
  3468. u32 changed)
  3469. {
  3470. struct b43_wl *wl = hw_to_b43_wl(hw);
  3471. struct b43_wldev *dev;
  3472. mutex_lock(&wl->mutex);
  3473. dev = wl->current_dev;
  3474. if (!dev || b43_status(dev) < B43_STAT_STARTED)
  3475. goto out_unlock_mutex;
  3476. B43_WARN_ON(wl->vif != vif);
  3477. if (changed & BSS_CHANGED_BSSID) {
  3478. if (conf->bssid)
  3479. memcpy(wl->bssid, conf->bssid, ETH_ALEN);
  3480. else
  3481. memset(wl->bssid, 0, ETH_ALEN);
  3482. }
  3483. if (b43_status(dev) >= B43_STAT_INITIALIZED) {
  3484. if (changed & BSS_CHANGED_BEACON &&
  3485. (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
  3486. b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
  3487. b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
  3488. b43_update_templates(wl);
  3489. if (changed & BSS_CHANGED_BSSID)
  3490. b43_write_mac_bssid_templates(dev);
  3491. }
  3492. b43_mac_suspend(dev);
  3493. /* Update templates for AP/mesh mode. */
  3494. if (changed & BSS_CHANGED_BEACON_INT &&
  3495. (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
  3496. b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
  3497. b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) &&
  3498. conf->beacon_int)
  3499. b43_set_beacon_int(dev, conf->beacon_int);
  3500. if (changed & BSS_CHANGED_BASIC_RATES)
  3501. b43_update_basic_rates(dev, conf->basic_rates);
  3502. if (changed & BSS_CHANGED_ERP_SLOT) {
  3503. if (conf->use_short_slot)
  3504. b43_short_slot_timing_enable(dev);
  3505. else
  3506. b43_short_slot_timing_disable(dev);
  3507. }
  3508. b43_mac_enable(dev);
  3509. out_unlock_mutex:
  3510. mutex_unlock(&wl->mutex);
  3511. }
  3512. static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  3513. struct ieee80211_vif *vif, struct ieee80211_sta *sta,
  3514. struct ieee80211_key_conf *key)
  3515. {
  3516. struct b43_wl *wl = hw_to_b43_wl(hw);
  3517. struct b43_wldev *dev;
  3518. u8 algorithm;
  3519. u8 index;
  3520. int err;
  3521. static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  3522. if (modparam_nohwcrypt)
  3523. return -ENOSPC; /* User disabled HW-crypto */
  3524. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  3525. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  3526. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  3527. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  3528. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  3529. /*
  3530. * For now, disable hw crypto for the RSN IBSS group keys. This
  3531. * could be optimized in the future, but until that gets
  3532. * implemented, use of software crypto for group addressed
  3533. * frames is a acceptable to allow RSN IBSS to be used.
  3534. */
  3535. return -EOPNOTSUPP;
  3536. }
  3537. mutex_lock(&wl->mutex);
  3538. dev = wl->current_dev;
  3539. err = -ENODEV;
  3540. if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
  3541. goto out_unlock;
  3542. if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
  3543. /* We don't have firmware for the crypto engine.
  3544. * Must use software-crypto. */
  3545. err = -EOPNOTSUPP;
  3546. goto out_unlock;
  3547. }
  3548. err = -EINVAL;
  3549. switch (key->cipher) {
  3550. case WLAN_CIPHER_SUITE_WEP40:
  3551. algorithm = B43_SEC_ALGO_WEP40;
  3552. break;
  3553. case WLAN_CIPHER_SUITE_WEP104:
  3554. algorithm = B43_SEC_ALGO_WEP104;
  3555. break;
  3556. case WLAN_CIPHER_SUITE_TKIP:
  3557. algorithm = B43_SEC_ALGO_TKIP;
  3558. break;
  3559. case WLAN_CIPHER_SUITE_CCMP:
  3560. algorithm = B43_SEC_ALGO_AES;
  3561. break;
  3562. default:
  3563. B43_WARN_ON(1);
  3564. goto out_unlock;
  3565. }
  3566. index = (u8) (key->keyidx);
  3567. if (index > 3)
  3568. goto out_unlock;
  3569. switch (cmd) {
  3570. case SET_KEY:
  3571. if (algorithm == B43_SEC_ALGO_TKIP &&
  3572. (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
  3573. !modparam_hwtkip)) {
  3574. /* We support only pairwise key */
  3575. err = -EOPNOTSUPP;
  3576. goto out_unlock;
  3577. }
  3578. if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
  3579. if (WARN_ON(!sta)) {
  3580. err = -EOPNOTSUPP;
  3581. goto out_unlock;
  3582. }
  3583. /* Pairwise key with an assigned MAC address. */
  3584. err = b43_key_write(dev, -1, algorithm,
  3585. key->key, key->keylen,
  3586. sta->addr, key);
  3587. } else {
  3588. /* Group key */
  3589. err = b43_key_write(dev, index, algorithm,
  3590. key->key, key->keylen, NULL, key);
  3591. }
  3592. if (err)
  3593. goto out_unlock;
  3594. if (algorithm == B43_SEC_ALGO_WEP40 ||
  3595. algorithm == B43_SEC_ALGO_WEP104) {
  3596. b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
  3597. } else {
  3598. b43_hf_write(dev,
  3599. b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
  3600. }
  3601. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  3602. if (algorithm == B43_SEC_ALGO_TKIP)
  3603. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  3604. break;
  3605. case DISABLE_KEY: {
  3606. err = b43_key_clear(dev, key->hw_key_idx);
  3607. if (err)
  3608. goto out_unlock;
  3609. break;
  3610. }
  3611. default:
  3612. B43_WARN_ON(1);
  3613. }
  3614. out_unlock:
  3615. if (!err) {
  3616. b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
  3617. "mac: %pM\n",
  3618. cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
  3619. sta ? sta->addr : bcast_addr);
  3620. b43_dump_keymemory(dev);
  3621. }
  3622. mutex_unlock(&wl->mutex);
  3623. return err;
  3624. }
  3625. static void b43_op_configure_filter(struct ieee80211_hw *hw,
  3626. unsigned int changed, unsigned int *fflags,
  3627. u64 multicast)
  3628. {
  3629. struct b43_wl *wl = hw_to_b43_wl(hw);
  3630. struct b43_wldev *dev;
  3631. mutex_lock(&wl->mutex);
  3632. dev = wl->current_dev;
  3633. if (!dev) {
  3634. *fflags = 0;
  3635. goto out_unlock;
  3636. }
  3637. *fflags &= FIF_PROMISC_IN_BSS |
  3638. FIF_ALLMULTI |
  3639. FIF_FCSFAIL |
  3640. FIF_PLCPFAIL |
  3641. FIF_CONTROL |
  3642. FIF_OTHER_BSS |
  3643. FIF_BCN_PRBRESP_PROMISC;
  3644. changed &= FIF_PROMISC_IN_BSS |
  3645. FIF_ALLMULTI |
  3646. FIF_FCSFAIL |
  3647. FIF_PLCPFAIL |
  3648. FIF_CONTROL |
  3649. FIF_OTHER_BSS |
  3650. FIF_BCN_PRBRESP_PROMISC;
  3651. wl->filter_flags = *fflags;
  3652. if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
  3653. b43_adjust_opmode(dev);
  3654. out_unlock:
  3655. mutex_unlock(&wl->mutex);
  3656. }
  3657. /* Locking: wl->mutex
  3658. * Returns the current dev. This might be different from the passed in dev,
  3659. * because the core might be gone away while we unlocked the mutex. */
  3660. static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
  3661. {
  3662. struct b43_wl *wl;
  3663. struct b43_wldev *orig_dev;
  3664. u32 mask;
  3665. int queue_num;
  3666. if (!dev)
  3667. return NULL;
  3668. wl = dev->wl;
  3669. redo:
  3670. if (!dev || b43_status(dev) < B43_STAT_STARTED)
  3671. return dev;
  3672. /* Cancel work. Unlock to avoid deadlocks. */
  3673. mutex_unlock(&wl->mutex);
  3674. cancel_delayed_work_sync(&dev->periodic_work);
  3675. cancel_work_sync(&wl->tx_work);
  3676. mutex_lock(&wl->mutex);
  3677. dev = wl->current_dev;
  3678. if (!dev || b43_status(dev) < B43_STAT_STARTED) {
  3679. /* Whoops, aliens ate up the device while we were unlocked. */
  3680. return dev;
  3681. }
  3682. /* Disable interrupts on the device. */
  3683. b43_set_status(dev, B43_STAT_INITIALIZED);
  3684. if (b43_bus_host_is_sdio(dev->dev)) {
  3685. /* wl->mutex is locked. That is enough. */
  3686. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
  3687. b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
  3688. } else {
  3689. spin_lock_irq(&wl->hardirq_lock);
  3690. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
  3691. b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
  3692. spin_unlock_irq(&wl->hardirq_lock);
  3693. }
  3694. /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
  3695. orig_dev = dev;
  3696. mutex_unlock(&wl->mutex);
  3697. if (b43_bus_host_is_sdio(dev->dev)) {
  3698. b43_sdio_free_irq(dev);
  3699. } else {
  3700. synchronize_irq(dev->dev->irq);
  3701. free_irq(dev->dev->irq, dev);
  3702. }
  3703. mutex_lock(&wl->mutex);
  3704. dev = wl->current_dev;
  3705. if (!dev)
  3706. return dev;
  3707. if (dev != orig_dev) {
  3708. if (b43_status(dev) >= B43_STAT_STARTED)
  3709. goto redo;
  3710. return dev;
  3711. }
  3712. mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
  3713. B43_WARN_ON(mask != 0xFFFFFFFF && mask);
  3714. /* Drain all TX queues. */
  3715. for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
  3716. while (skb_queue_len(&wl->tx_queue[queue_num])) {
  3717. struct sk_buff *skb;
  3718. skb = skb_dequeue(&wl->tx_queue[queue_num]);
  3719. ieee80211_free_txskb(wl->hw, skb);
  3720. }
  3721. }
  3722. b43_mac_suspend(dev);
  3723. b43_leds_exit(dev);
  3724. b43dbg(wl, "Wireless interface stopped\n");
  3725. return dev;
  3726. }
  3727. /* Locking: wl->mutex */
  3728. static int b43_wireless_core_start(struct b43_wldev *dev)
  3729. {
  3730. int err;
  3731. B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
  3732. drain_txstatus_queue(dev);
  3733. if (b43_bus_host_is_sdio(dev->dev)) {
  3734. err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
  3735. if (err) {
  3736. b43err(dev->wl, "Cannot request SDIO IRQ\n");
  3737. goto out;
  3738. }
  3739. } else {
  3740. err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
  3741. b43_interrupt_thread_handler,
  3742. IRQF_SHARED, KBUILD_MODNAME, dev);
  3743. if (err) {
  3744. b43err(dev->wl, "Cannot request IRQ-%d\n",
  3745. dev->dev->irq);
  3746. goto out;
  3747. }
  3748. }
  3749. /* We are ready to run. */
  3750. ieee80211_wake_queues(dev->wl->hw);
  3751. b43_set_status(dev, B43_STAT_STARTED);
  3752. /* Start data flow (TX/RX). */
  3753. b43_mac_enable(dev);
  3754. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
  3755. /* Start maintenance work */
  3756. b43_periodic_tasks_setup(dev);
  3757. b43_leds_init(dev);
  3758. b43dbg(dev->wl, "Wireless interface started\n");
  3759. out:
  3760. return err;
  3761. }
  3762. static char *b43_phy_name(struct b43_wldev *dev, u8 phy_type)
  3763. {
  3764. switch (phy_type) {
  3765. case B43_PHYTYPE_A:
  3766. return "A";
  3767. case B43_PHYTYPE_B:
  3768. return "B";
  3769. case B43_PHYTYPE_G:
  3770. return "G";
  3771. case B43_PHYTYPE_N:
  3772. return "N";
  3773. case B43_PHYTYPE_LP:
  3774. return "LP";
  3775. case B43_PHYTYPE_SSLPN:
  3776. return "SSLPN";
  3777. case B43_PHYTYPE_HT:
  3778. return "HT";
  3779. case B43_PHYTYPE_LCN:
  3780. return "LCN";
  3781. case B43_PHYTYPE_LCNXN:
  3782. return "LCNXN";
  3783. case B43_PHYTYPE_LCN40:
  3784. return "LCN40";
  3785. case B43_PHYTYPE_AC:
  3786. return "AC";
  3787. }
  3788. return "UNKNOWN";
  3789. }
  3790. /* Get PHY and RADIO versioning numbers */
  3791. static int b43_phy_versioning(struct b43_wldev *dev)
  3792. {
  3793. struct b43_phy *phy = &dev->phy;
  3794. u32 tmp;
  3795. u8 analog_type;
  3796. u8 phy_type;
  3797. u8 phy_rev;
  3798. u16 radio_manuf;
  3799. u16 radio_ver;
  3800. u16 radio_rev;
  3801. int unsupported = 0;
  3802. /* Get PHY versioning */
  3803. tmp = b43_read16(dev, B43_MMIO_PHY_VER);
  3804. analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
  3805. phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
  3806. phy_rev = (tmp & B43_PHYVER_VERSION);
  3807. switch (phy_type) {
  3808. case B43_PHYTYPE_A:
  3809. if (phy_rev >= 4)
  3810. unsupported = 1;
  3811. break;
  3812. case B43_PHYTYPE_B:
  3813. if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
  3814. && phy_rev != 7)
  3815. unsupported = 1;
  3816. break;
  3817. case B43_PHYTYPE_G:
  3818. if (phy_rev > 9)
  3819. unsupported = 1;
  3820. break;
  3821. #ifdef CONFIG_B43_PHY_N
  3822. case B43_PHYTYPE_N:
  3823. if (phy_rev > 9)
  3824. unsupported = 1;
  3825. break;
  3826. #endif
  3827. #ifdef CONFIG_B43_PHY_LP
  3828. case B43_PHYTYPE_LP:
  3829. if (phy_rev > 2)
  3830. unsupported = 1;
  3831. break;
  3832. #endif
  3833. #ifdef CONFIG_B43_PHY_HT
  3834. case B43_PHYTYPE_HT:
  3835. if (phy_rev > 1)
  3836. unsupported = 1;
  3837. break;
  3838. #endif
  3839. #ifdef CONFIG_B43_PHY_LCN
  3840. case B43_PHYTYPE_LCN:
  3841. if (phy_rev > 1)
  3842. unsupported = 1;
  3843. break;
  3844. #endif
  3845. default:
  3846. unsupported = 1;
  3847. }
  3848. if (unsupported) {
  3849. b43err(dev->wl, "FOUND UNSUPPORTED PHY (Analog %u, Type %d (%s), Revision %u)\n",
  3850. analog_type, phy_type, b43_phy_name(dev, phy_type),
  3851. phy_rev);
  3852. return -EOPNOTSUPP;
  3853. }
  3854. b43info(dev->wl, "Found PHY: Analog %u, Type %d (%s), Revision %u\n",
  3855. analog_type, phy_type, b43_phy_name(dev, phy_type), phy_rev);
  3856. /* Get RADIO versioning */
  3857. if (dev->dev->core_rev >= 24) {
  3858. u16 radio24[3];
  3859. for (tmp = 0; tmp < 3; tmp++) {
  3860. b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
  3861. radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
  3862. }
  3863. /* Broadcom uses "id" for our "ver" and has separated "ver" */
  3864. /* radio_ver = (radio24[0] & 0xF0) >> 4; */
  3865. radio_manuf = 0x17F;
  3866. radio_ver = (radio24[2] << 8) | radio24[1];
  3867. radio_rev = (radio24[0] & 0xF);
  3868. } else {
  3869. if (dev->dev->chip_id == 0x4317) {
  3870. if (dev->dev->chip_rev == 0)
  3871. tmp = 0x3205017F;
  3872. else if (dev->dev->chip_rev == 1)
  3873. tmp = 0x4205017F;
  3874. else
  3875. tmp = 0x5205017F;
  3876. } else {
  3877. b43_write16(dev, B43_MMIO_RADIO_CONTROL,
  3878. B43_RADIOCTL_ID);
  3879. tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
  3880. b43_write16(dev, B43_MMIO_RADIO_CONTROL,
  3881. B43_RADIOCTL_ID);
  3882. tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
  3883. << 16;
  3884. }
  3885. radio_manuf = (tmp & 0x00000FFF);
  3886. radio_ver = (tmp & 0x0FFFF000) >> 12;
  3887. radio_rev = (tmp & 0xF0000000) >> 28;
  3888. }
  3889. if (radio_manuf != 0x17F /* Broadcom */)
  3890. unsupported = 1;
  3891. switch (phy_type) {
  3892. case B43_PHYTYPE_A:
  3893. if (radio_ver != 0x2060)
  3894. unsupported = 1;
  3895. if (radio_rev != 1)
  3896. unsupported = 1;
  3897. if (radio_manuf != 0x17F)
  3898. unsupported = 1;
  3899. break;
  3900. case B43_PHYTYPE_B:
  3901. if ((radio_ver & 0xFFF0) != 0x2050)
  3902. unsupported = 1;
  3903. break;
  3904. case B43_PHYTYPE_G:
  3905. if (radio_ver != 0x2050)
  3906. unsupported = 1;
  3907. break;
  3908. case B43_PHYTYPE_N:
  3909. if (radio_ver != 0x2055 && radio_ver != 0x2056)
  3910. unsupported = 1;
  3911. break;
  3912. case B43_PHYTYPE_LP:
  3913. if (radio_ver != 0x2062 && radio_ver != 0x2063)
  3914. unsupported = 1;
  3915. break;
  3916. case B43_PHYTYPE_HT:
  3917. if (radio_ver != 0x2059)
  3918. unsupported = 1;
  3919. break;
  3920. case B43_PHYTYPE_LCN:
  3921. if (radio_ver != 0x2064)
  3922. unsupported = 1;
  3923. break;
  3924. default:
  3925. B43_WARN_ON(1);
  3926. }
  3927. if (unsupported) {
  3928. b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
  3929. "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
  3930. radio_manuf, radio_ver, radio_rev);
  3931. return -EOPNOTSUPP;
  3932. }
  3933. b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
  3934. radio_manuf, radio_ver, radio_rev);
  3935. phy->radio_manuf = radio_manuf;
  3936. phy->radio_ver = radio_ver;
  3937. phy->radio_rev = radio_rev;
  3938. phy->analog = analog_type;
  3939. phy->type = phy_type;
  3940. phy->rev = phy_rev;
  3941. return 0;
  3942. }
  3943. static void setup_struct_phy_for_init(struct b43_wldev *dev,
  3944. struct b43_phy *phy)
  3945. {
  3946. phy->hardware_power_control = !!modparam_hwpctl;
  3947. phy->next_txpwr_check_time = jiffies;
  3948. /* PHY TX errors counter. */
  3949. atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
  3950. #if B43_DEBUG
  3951. phy->phy_locked = false;
  3952. phy->radio_locked = false;
  3953. #endif
  3954. }
  3955. static void setup_struct_wldev_for_init(struct b43_wldev *dev)
  3956. {
  3957. dev->dfq_valid = false;
  3958. /* Assume the radio is enabled. If it's not enabled, the state will
  3959. * immediately get fixed on the first periodic work run. */
  3960. dev->radio_hw_enable = true;
  3961. /* Stats */
  3962. memset(&dev->stats, 0, sizeof(dev->stats));
  3963. setup_struct_phy_for_init(dev, &dev->phy);
  3964. /* IRQ related flags */
  3965. dev->irq_reason = 0;
  3966. memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
  3967. dev->irq_mask = B43_IRQ_MASKTEMPLATE;
  3968. if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
  3969. dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
  3970. dev->mac_suspended = 1;
  3971. /* Noise calculation context */
  3972. memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
  3973. }
  3974. static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
  3975. {
  3976. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  3977. u64 hf;
  3978. if (!modparam_btcoex)
  3979. return;
  3980. if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
  3981. return;
  3982. if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
  3983. return;
  3984. hf = b43_hf_read(dev);
  3985. if (sprom->boardflags_lo & B43_BFL_BTCMOD)
  3986. hf |= B43_HF_BTCOEXALT;
  3987. else
  3988. hf |= B43_HF_BTCOEX;
  3989. b43_hf_write(dev, hf);
  3990. }
  3991. static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
  3992. {
  3993. if (!modparam_btcoex)
  3994. return;
  3995. //TODO
  3996. }
  3997. static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
  3998. {
  3999. struct ssb_bus *bus;
  4000. u32 tmp;
  4001. if (dev->dev->bus_type != B43_BUS_SSB)
  4002. return;
  4003. bus = dev->dev->sdev->bus;
  4004. if ((bus->chip_id == 0x4311 && bus->chip_rev == 2) ||
  4005. (bus->chip_id == 0x4312)) {
  4006. tmp = ssb_read32(dev->dev->sdev, SSB_IMCFGLO);
  4007. tmp &= ~SSB_IMCFGLO_REQTO;
  4008. tmp &= ~SSB_IMCFGLO_SERTO;
  4009. tmp |= 0x3;
  4010. ssb_write32(dev->dev->sdev, SSB_IMCFGLO, tmp);
  4011. ssb_commit_settings(bus);
  4012. }
  4013. }
  4014. static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
  4015. {
  4016. u16 pu_delay;
  4017. /* The time value is in microseconds. */
  4018. if (dev->phy.type == B43_PHYTYPE_A)
  4019. pu_delay = 3700;
  4020. else
  4021. pu_delay = 1050;
  4022. if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
  4023. pu_delay = 500;
  4024. if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
  4025. pu_delay = max(pu_delay, (u16)2400);
  4026. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
  4027. }
  4028. /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
  4029. static void b43_set_pretbtt(struct b43_wldev *dev)
  4030. {
  4031. u16 pretbtt;
  4032. /* The time value is in microseconds. */
  4033. if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
  4034. pretbtt = 2;
  4035. } else {
  4036. if (dev->phy.type == B43_PHYTYPE_A)
  4037. pretbtt = 120;
  4038. else
  4039. pretbtt = 250;
  4040. }
  4041. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
  4042. b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
  4043. }
  4044. /* Shutdown a wireless core */
  4045. /* Locking: wl->mutex */
  4046. static void b43_wireless_core_exit(struct b43_wldev *dev)
  4047. {
  4048. B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
  4049. if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
  4050. return;
  4051. /* Unregister HW RNG driver */
  4052. b43_rng_exit(dev->wl);
  4053. b43_set_status(dev, B43_STAT_UNINIT);
  4054. /* Stop the microcode PSM. */
  4055. b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PSM_RUN,
  4056. B43_MACCTL_PSM_JMP0);
  4057. b43_dma_free(dev);
  4058. b43_pio_free(dev);
  4059. b43_chip_exit(dev);
  4060. dev->phy.ops->switch_analog(dev, 0);
  4061. if (dev->wl->current_beacon) {
  4062. dev_kfree_skb_any(dev->wl->current_beacon);
  4063. dev->wl->current_beacon = NULL;
  4064. }
  4065. b43_device_disable(dev, 0);
  4066. b43_bus_may_powerdown(dev);
  4067. }
  4068. /* Initialize a wireless core */
  4069. static int b43_wireless_core_init(struct b43_wldev *dev)
  4070. {
  4071. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  4072. struct b43_phy *phy = &dev->phy;
  4073. int err;
  4074. u64 hf;
  4075. B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
  4076. err = b43_bus_powerup(dev, 0);
  4077. if (err)
  4078. goto out;
  4079. if (!b43_device_is_enabled(dev))
  4080. b43_wireless_core_reset(dev, phy->gmode);
  4081. /* Reset all data structures. */
  4082. setup_struct_wldev_for_init(dev);
  4083. phy->ops->prepare_structs(dev);
  4084. /* Enable IRQ routing to this device. */
  4085. switch (dev->dev->bus_type) {
  4086. #ifdef CONFIG_B43_BCMA
  4087. case B43_BUS_BCMA:
  4088. bcma_core_pci_irq_ctl(&dev->dev->bdev->bus->drv_pci[0],
  4089. dev->dev->bdev, true);
  4090. break;
  4091. #endif
  4092. #ifdef CONFIG_B43_SSB
  4093. case B43_BUS_SSB:
  4094. ssb_pcicore_dev_irqvecs_enable(&dev->dev->sdev->bus->pcicore,
  4095. dev->dev->sdev);
  4096. break;
  4097. #endif
  4098. }
  4099. b43_imcfglo_timeouts_workaround(dev);
  4100. b43_bluetooth_coext_disable(dev);
  4101. if (phy->ops->prepare_hardware) {
  4102. err = phy->ops->prepare_hardware(dev);
  4103. if (err)
  4104. goto err_busdown;
  4105. }
  4106. err = b43_chip_init(dev);
  4107. if (err)
  4108. goto err_busdown;
  4109. b43_shm_write16(dev, B43_SHM_SHARED,
  4110. B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
  4111. hf = b43_hf_read(dev);
  4112. if (phy->type == B43_PHYTYPE_G) {
  4113. hf |= B43_HF_SYMW;
  4114. if (phy->rev == 1)
  4115. hf |= B43_HF_GDCW;
  4116. if (sprom->boardflags_lo & B43_BFL_PACTRL)
  4117. hf |= B43_HF_OFDMPABOOST;
  4118. }
  4119. if (phy->radio_ver == 0x2050) {
  4120. if (phy->radio_rev == 6)
  4121. hf |= B43_HF_4318TSSI;
  4122. if (phy->radio_rev < 6)
  4123. hf |= B43_HF_VCORECALC;
  4124. }
  4125. if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
  4126. hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
  4127. #ifdef CONFIG_SSB_DRIVER_PCICORE
  4128. if (dev->dev->bus_type == B43_BUS_SSB &&
  4129. dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI &&
  4130. dev->dev->sdev->bus->pcicore.dev->id.revision <= 10)
  4131. hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
  4132. #endif
  4133. hf &= ~B43_HF_SKCFPUP;
  4134. b43_hf_write(dev, hf);
  4135. b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
  4136. B43_DEFAULT_LONG_RETRY_LIMIT);
  4137. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
  4138. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
  4139. /* Disable sending probe responses from firmware.
  4140. * Setting the MaxTime to one usec will always trigger
  4141. * a timeout, so we never send any probe resp.
  4142. * A timeout of zero is infinite. */
  4143. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
  4144. b43_rate_memory_init(dev);
  4145. b43_set_phytxctl_defaults(dev);
  4146. /* Minimum Contention Window */
  4147. if (phy->type == B43_PHYTYPE_B)
  4148. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
  4149. else
  4150. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
  4151. /* Maximum Contention Window */
  4152. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
  4153. if (b43_bus_host_is_pcmcia(dev->dev) ||
  4154. b43_bus_host_is_sdio(dev->dev)) {
  4155. dev->__using_pio_transfers = true;
  4156. err = b43_pio_init(dev);
  4157. } else if (dev->use_pio) {
  4158. b43warn(dev->wl, "Forced PIO by use_pio module parameter. "
  4159. "This should not be needed and will result in lower "
  4160. "performance.\n");
  4161. dev->__using_pio_transfers = true;
  4162. err = b43_pio_init(dev);
  4163. } else {
  4164. dev->__using_pio_transfers = false;
  4165. err = b43_dma_init(dev);
  4166. }
  4167. if (err)
  4168. goto err_chip_exit;
  4169. b43_qos_init(dev);
  4170. b43_set_synth_pu_delay(dev, 1);
  4171. b43_bluetooth_coext_enable(dev);
  4172. b43_bus_powerup(dev, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
  4173. b43_upload_card_macaddress(dev);
  4174. b43_security_init(dev);
  4175. ieee80211_wake_queues(dev->wl->hw);
  4176. b43_set_status(dev, B43_STAT_INITIALIZED);
  4177. /* Register HW RNG driver */
  4178. b43_rng_init(dev->wl);
  4179. out:
  4180. return err;
  4181. err_chip_exit:
  4182. b43_chip_exit(dev);
  4183. err_busdown:
  4184. b43_bus_may_powerdown(dev);
  4185. B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
  4186. return err;
  4187. }
  4188. static int b43_op_add_interface(struct ieee80211_hw *hw,
  4189. struct ieee80211_vif *vif)
  4190. {
  4191. struct b43_wl *wl = hw_to_b43_wl(hw);
  4192. struct b43_wldev *dev;
  4193. int err = -EOPNOTSUPP;
  4194. /* TODO: allow WDS/AP devices to coexist */
  4195. if (vif->type != NL80211_IFTYPE_AP &&
  4196. vif->type != NL80211_IFTYPE_MESH_POINT &&
  4197. vif->type != NL80211_IFTYPE_STATION &&
  4198. vif->type != NL80211_IFTYPE_WDS &&
  4199. vif->type != NL80211_IFTYPE_ADHOC)
  4200. return -EOPNOTSUPP;
  4201. mutex_lock(&wl->mutex);
  4202. if (wl->operating)
  4203. goto out_mutex_unlock;
  4204. b43dbg(wl, "Adding Interface type %d\n", vif->type);
  4205. dev = wl->current_dev;
  4206. wl->operating = true;
  4207. wl->vif = vif;
  4208. wl->if_type = vif->type;
  4209. memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
  4210. b43_adjust_opmode(dev);
  4211. b43_set_pretbtt(dev);
  4212. b43_set_synth_pu_delay(dev, 0);
  4213. b43_upload_card_macaddress(dev);
  4214. err = 0;
  4215. out_mutex_unlock:
  4216. mutex_unlock(&wl->mutex);
  4217. if (err == 0)
  4218. b43_op_bss_info_changed(hw, vif, &vif->bss_conf, ~0);
  4219. return err;
  4220. }
  4221. static void b43_op_remove_interface(struct ieee80211_hw *hw,
  4222. struct ieee80211_vif *vif)
  4223. {
  4224. struct b43_wl *wl = hw_to_b43_wl(hw);
  4225. struct b43_wldev *dev = wl->current_dev;
  4226. b43dbg(wl, "Removing Interface type %d\n", vif->type);
  4227. mutex_lock(&wl->mutex);
  4228. B43_WARN_ON(!wl->operating);
  4229. B43_WARN_ON(wl->vif != vif);
  4230. wl->vif = NULL;
  4231. wl->operating = false;
  4232. b43_adjust_opmode(dev);
  4233. memset(wl->mac_addr, 0, ETH_ALEN);
  4234. b43_upload_card_macaddress(dev);
  4235. mutex_unlock(&wl->mutex);
  4236. }
  4237. static int b43_op_start(struct ieee80211_hw *hw)
  4238. {
  4239. struct b43_wl *wl = hw_to_b43_wl(hw);
  4240. struct b43_wldev *dev = wl->current_dev;
  4241. int did_init = 0;
  4242. int err = 0;
  4243. /* Kill all old instance specific information to make sure
  4244. * the card won't use it in the short timeframe between start
  4245. * and mac80211 reconfiguring it. */
  4246. memset(wl->bssid, 0, ETH_ALEN);
  4247. memset(wl->mac_addr, 0, ETH_ALEN);
  4248. wl->filter_flags = 0;
  4249. wl->radiotap_enabled = false;
  4250. b43_qos_clear(wl);
  4251. wl->beacon0_uploaded = false;
  4252. wl->beacon1_uploaded = false;
  4253. wl->beacon_templates_virgin = true;
  4254. wl->radio_enabled = true;
  4255. mutex_lock(&wl->mutex);
  4256. if (b43_status(dev) < B43_STAT_INITIALIZED) {
  4257. err = b43_wireless_core_init(dev);
  4258. if (err)
  4259. goto out_mutex_unlock;
  4260. did_init = 1;
  4261. }
  4262. if (b43_status(dev) < B43_STAT_STARTED) {
  4263. err = b43_wireless_core_start(dev);
  4264. if (err) {
  4265. if (did_init)
  4266. b43_wireless_core_exit(dev);
  4267. goto out_mutex_unlock;
  4268. }
  4269. }
  4270. /* XXX: only do if device doesn't support rfkill irq */
  4271. wiphy_rfkill_start_polling(hw->wiphy);
  4272. out_mutex_unlock:
  4273. mutex_unlock(&wl->mutex);
  4274. /*
  4275. * Configuration may have been overwritten during initialization.
  4276. * Reload the configuration, but only if initialization was
  4277. * successful. Reloading the configuration after a failed init
  4278. * may hang the system.
  4279. */
  4280. if (!err)
  4281. b43_op_config(hw, ~0);
  4282. return err;
  4283. }
  4284. static void b43_op_stop(struct ieee80211_hw *hw)
  4285. {
  4286. struct b43_wl *wl = hw_to_b43_wl(hw);
  4287. struct b43_wldev *dev = wl->current_dev;
  4288. cancel_work_sync(&(wl->beacon_update_trigger));
  4289. if (!dev)
  4290. goto out;
  4291. mutex_lock(&wl->mutex);
  4292. if (b43_status(dev) >= B43_STAT_STARTED) {
  4293. dev = b43_wireless_core_stop(dev);
  4294. if (!dev)
  4295. goto out_unlock;
  4296. }
  4297. b43_wireless_core_exit(dev);
  4298. wl->radio_enabled = false;
  4299. out_unlock:
  4300. mutex_unlock(&wl->mutex);
  4301. out:
  4302. cancel_work_sync(&(wl->txpower_adjust_work));
  4303. }
  4304. static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
  4305. struct ieee80211_sta *sta, bool set)
  4306. {
  4307. struct b43_wl *wl = hw_to_b43_wl(hw);
  4308. /* FIXME: add locking */
  4309. b43_update_templates(wl);
  4310. return 0;
  4311. }
  4312. static void b43_op_sta_notify(struct ieee80211_hw *hw,
  4313. struct ieee80211_vif *vif,
  4314. enum sta_notify_cmd notify_cmd,
  4315. struct ieee80211_sta *sta)
  4316. {
  4317. struct b43_wl *wl = hw_to_b43_wl(hw);
  4318. B43_WARN_ON(!vif || wl->vif != vif);
  4319. }
  4320. static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
  4321. {
  4322. struct b43_wl *wl = hw_to_b43_wl(hw);
  4323. struct b43_wldev *dev;
  4324. mutex_lock(&wl->mutex);
  4325. dev = wl->current_dev;
  4326. if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
  4327. /* Disable CFP update during scan on other channels. */
  4328. b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
  4329. }
  4330. mutex_unlock(&wl->mutex);
  4331. }
  4332. static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
  4333. {
  4334. struct b43_wl *wl = hw_to_b43_wl(hw);
  4335. struct b43_wldev *dev;
  4336. mutex_lock(&wl->mutex);
  4337. dev = wl->current_dev;
  4338. if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
  4339. /* Re-enable CFP update. */
  4340. b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
  4341. }
  4342. mutex_unlock(&wl->mutex);
  4343. }
  4344. static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
  4345. struct survey_info *survey)
  4346. {
  4347. struct b43_wl *wl = hw_to_b43_wl(hw);
  4348. struct b43_wldev *dev = wl->current_dev;
  4349. struct ieee80211_conf *conf = &hw->conf;
  4350. if (idx != 0)
  4351. return -ENOENT;
  4352. survey->channel = conf->chandef.chan;
  4353. survey->filled = SURVEY_INFO_NOISE_DBM;
  4354. survey->noise = dev->stats.link_noise;
  4355. return 0;
  4356. }
  4357. static const struct ieee80211_ops b43_hw_ops = {
  4358. .tx = b43_op_tx,
  4359. .conf_tx = b43_op_conf_tx,
  4360. .add_interface = b43_op_add_interface,
  4361. .remove_interface = b43_op_remove_interface,
  4362. .config = b43_op_config,
  4363. .bss_info_changed = b43_op_bss_info_changed,
  4364. .configure_filter = b43_op_configure_filter,
  4365. .set_key = b43_op_set_key,
  4366. .update_tkip_key = b43_op_update_tkip_key,
  4367. .get_stats = b43_op_get_stats,
  4368. .get_tsf = b43_op_get_tsf,
  4369. .set_tsf = b43_op_set_tsf,
  4370. .start = b43_op_start,
  4371. .stop = b43_op_stop,
  4372. .set_tim = b43_op_beacon_set_tim,
  4373. .sta_notify = b43_op_sta_notify,
  4374. .sw_scan_start = b43_op_sw_scan_start_notifier,
  4375. .sw_scan_complete = b43_op_sw_scan_complete_notifier,
  4376. .get_survey = b43_op_get_survey,
  4377. .rfkill_poll = b43_rfkill_poll,
  4378. };
  4379. /* Hard-reset the chip. Do not call this directly.
  4380. * Use b43_controller_restart()
  4381. */
  4382. static void b43_chip_reset(struct work_struct *work)
  4383. {
  4384. struct b43_wldev *dev =
  4385. container_of(work, struct b43_wldev, restart_work);
  4386. struct b43_wl *wl = dev->wl;
  4387. int err = 0;
  4388. int prev_status;
  4389. mutex_lock(&wl->mutex);
  4390. prev_status = b43_status(dev);
  4391. /* Bring the device down... */
  4392. if (prev_status >= B43_STAT_STARTED) {
  4393. dev = b43_wireless_core_stop(dev);
  4394. if (!dev) {
  4395. err = -ENODEV;
  4396. goto out;
  4397. }
  4398. }
  4399. if (prev_status >= B43_STAT_INITIALIZED)
  4400. b43_wireless_core_exit(dev);
  4401. /* ...and up again. */
  4402. if (prev_status >= B43_STAT_INITIALIZED) {
  4403. err = b43_wireless_core_init(dev);
  4404. if (err)
  4405. goto out;
  4406. }
  4407. if (prev_status >= B43_STAT_STARTED) {
  4408. err = b43_wireless_core_start(dev);
  4409. if (err) {
  4410. b43_wireless_core_exit(dev);
  4411. goto out;
  4412. }
  4413. }
  4414. out:
  4415. if (err)
  4416. wl->current_dev = NULL; /* Failed to init the dev. */
  4417. mutex_unlock(&wl->mutex);
  4418. if (err) {
  4419. b43err(wl, "Controller restart FAILED\n");
  4420. return;
  4421. }
  4422. /* reload configuration */
  4423. b43_op_config(wl->hw, ~0);
  4424. if (wl->vif)
  4425. b43_op_bss_info_changed(wl->hw, wl->vif, &wl->vif->bss_conf, ~0);
  4426. b43info(wl, "Controller restarted\n");
  4427. }
  4428. static int b43_setup_bands(struct b43_wldev *dev,
  4429. bool have_2ghz_phy, bool have_5ghz_phy)
  4430. {
  4431. struct ieee80211_hw *hw = dev->wl->hw;
  4432. if (have_2ghz_phy)
  4433. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
  4434. if (dev->phy.type == B43_PHYTYPE_N) {
  4435. if (have_5ghz_phy)
  4436. hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
  4437. } else {
  4438. if (have_5ghz_phy)
  4439. hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
  4440. }
  4441. dev->phy.supports_2ghz = have_2ghz_phy;
  4442. dev->phy.supports_5ghz = have_5ghz_phy;
  4443. return 0;
  4444. }
  4445. static void b43_wireless_core_detach(struct b43_wldev *dev)
  4446. {
  4447. /* We release firmware that late to not be required to re-request
  4448. * is all the time when we reinit the core. */
  4449. b43_release_firmware(dev);
  4450. b43_phy_free(dev);
  4451. }
  4452. static int b43_wireless_core_attach(struct b43_wldev *dev)
  4453. {
  4454. struct b43_wl *wl = dev->wl;
  4455. struct pci_dev *pdev = NULL;
  4456. int err;
  4457. u32 tmp;
  4458. bool have_2ghz_phy = false, have_5ghz_phy = false;
  4459. /* Do NOT do any device initialization here.
  4460. * Do it in wireless_core_init() instead.
  4461. * This function is for gathering basic information about the HW, only.
  4462. * Also some structs may be set up here. But most likely you want to have
  4463. * that in core_init(), too.
  4464. */
  4465. #ifdef CONFIG_B43_SSB
  4466. if (dev->dev->bus_type == B43_BUS_SSB &&
  4467. dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI)
  4468. pdev = dev->dev->sdev->bus->host_pci;
  4469. #endif
  4470. err = b43_bus_powerup(dev, 0);
  4471. if (err) {
  4472. b43err(wl, "Bus powerup failed\n");
  4473. goto out;
  4474. }
  4475. /* Get the PHY type. */
  4476. switch (dev->dev->bus_type) {
  4477. #ifdef CONFIG_B43_BCMA
  4478. case B43_BUS_BCMA:
  4479. tmp = bcma_aread32(dev->dev->bdev, BCMA_IOST);
  4480. have_2ghz_phy = !!(tmp & B43_BCMA_IOST_2G_PHY);
  4481. have_5ghz_phy = !!(tmp & B43_BCMA_IOST_5G_PHY);
  4482. break;
  4483. #endif
  4484. #ifdef CONFIG_B43_SSB
  4485. case B43_BUS_SSB:
  4486. if (dev->dev->core_rev >= 5) {
  4487. tmp = ssb_read32(dev->dev->sdev, SSB_TMSHIGH);
  4488. have_2ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_2GHZ_PHY);
  4489. have_5ghz_phy = !!(tmp & B43_TMSHIGH_HAVE_5GHZ_PHY);
  4490. } else
  4491. B43_WARN_ON(1);
  4492. break;
  4493. #endif
  4494. }
  4495. dev->phy.gmode = have_2ghz_phy;
  4496. dev->phy.radio_on = true;
  4497. b43_wireless_core_reset(dev, dev->phy.gmode);
  4498. err = b43_phy_versioning(dev);
  4499. if (err)
  4500. goto err_powerdown;
  4501. /* Check if this device supports multiband. */
  4502. if (!pdev ||
  4503. (pdev->device != 0x4312 &&
  4504. pdev->device != 0x4319 && pdev->device != 0x4324)) {
  4505. /* No multiband support. */
  4506. have_2ghz_phy = false;
  4507. have_5ghz_phy = false;
  4508. switch (dev->phy.type) {
  4509. case B43_PHYTYPE_A:
  4510. have_5ghz_phy = true;
  4511. break;
  4512. case B43_PHYTYPE_LP: //FIXME not always!
  4513. #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
  4514. have_5ghz_phy = 1;
  4515. #endif
  4516. case B43_PHYTYPE_G:
  4517. case B43_PHYTYPE_N:
  4518. case B43_PHYTYPE_HT:
  4519. case B43_PHYTYPE_LCN:
  4520. have_2ghz_phy = true;
  4521. break;
  4522. default:
  4523. B43_WARN_ON(1);
  4524. }
  4525. }
  4526. if (dev->phy.type == B43_PHYTYPE_A) {
  4527. /* FIXME */
  4528. b43err(wl, "IEEE 802.11a devices are unsupported\n");
  4529. err = -EOPNOTSUPP;
  4530. goto err_powerdown;
  4531. }
  4532. if (1 /* disable A-PHY */) {
  4533. /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
  4534. if (dev->phy.type != B43_PHYTYPE_N &&
  4535. dev->phy.type != B43_PHYTYPE_LP) {
  4536. have_2ghz_phy = true;
  4537. have_5ghz_phy = false;
  4538. }
  4539. }
  4540. err = b43_phy_allocate(dev);
  4541. if (err)
  4542. goto err_powerdown;
  4543. dev->phy.gmode = have_2ghz_phy;
  4544. b43_wireless_core_reset(dev, dev->phy.gmode);
  4545. err = b43_validate_chipaccess(dev);
  4546. if (err)
  4547. goto err_phy_free;
  4548. err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
  4549. if (err)
  4550. goto err_phy_free;
  4551. /* Now set some default "current_dev" */
  4552. if (!wl->current_dev)
  4553. wl->current_dev = dev;
  4554. INIT_WORK(&dev->restart_work, b43_chip_reset);
  4555. dev->phy.ops->switch_analog(dev, 0);
  4556. b43_device_disable(dev, 0);
  4557. b43_bus_may_powerdown(dev);
  4558. out:
  4559. return err;
  4560. err_phy_free:
  4561. b43_phy_free(dev);
  4562. err_powerdown:
  4563. b43_bus_may_powerdown(dev);
  4564. return err;
  4565. }
  4566. static void b43_one_core_detach(struct b43_bus_dev *dev)
  4567. {
  4568. struct b43_wldev *wldev;
  4569. struct b43_wl *wl;
  4570. /* Do not cancel ieee80211-workqueue based work here.
  4571. * See comment in b43_remove(). */
  4572. wldev = b43_bus_get_wldev(dev);
  4573. wl = wldev->wl;
  4574. b43_debugfs_remove_device(wldev);
  4575. b43_wireless_core_detach(wldev);
  4576. list_del(&wldev->list);
  4577. wl->nr_devs--;
  4578. b43_bus_set_wldev(dev, NULL);
  4579. kfree(wldev);
  4580. }
  4581. static int b43_one_core_attach(struct b43_bus_dev *dev, struct b43_wl *wl)
  4582. {
  4583. struct b43_wldev *wldev;
  4584. int err = -ENOMEM;
  4585. wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
  4586. if (!wldev)
  4587. goto out;
  4588. wldev->use_pio = b43_modparam_pio;
  4589. wldev->dev = dev;
  4590. wldev->wl = wl;
  4591. b43_set_status(wldev, B43_STAT_UNINIT);
  4592. wldev->bad_frames_preempt = modparam_bad_frames_preempt;
  4593. INIT_LIST_HEAD(&wldev->list);
  4594. err = b43_wireless_core_attach(wldev);
  4595. if (err)
  4596. goto err_kfree_wldev;
  4597. list_add(&wldev->list, &wl->devlist);
  4598. wl->nr_devs++;
  4599. b43_bus_set_wldev(dev, wldev);
  4600. b43_debugfs_add_device(wldev);
  4601. out:
  4602. return err;
  4603. err_kfree_wldev:
  4604. kfree(wldev);
  4605. return err;
  4606. }
  4607. #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
  4608. (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
  4609. (pdev->device == _device) && \
  4610. (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
  4611. (pdev->subsystem_device == _subdevice) )
  4612. static void b43_sprom_fixup(struct ssb_bus *bus)
  4613. {
  4614. struct pci_dev *pdev;
  4615. /* boardflags workarounds */
  4616. if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
  4617. bus->chip_id == 0x4301 && bus->sprom.board_rev == 0x74)
  4618. bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
  4619. if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
  4620. bus->boardinfo.type == 0x4E && bus->sprom.board_rev > 0x40)
  4621. bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
  4622. if (bus->bustype == SSB_BUSTYPE_PCI) {
  4623. pdev = bus->host_pci;
  4624. if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
  4625. IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
  4626. IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
  4627. IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
  4628. IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
  4629. IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
  4630. IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
  4631. bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
  4632. }
  4633. }
  4634. static void b43_wireless_exit(struct b43_bus_dev *dev, struct b43_wl *wl)
  4635. {
  4636. struct ieee80211_hw *hw = wl->hw;
  4637. ssb_set_devtypedata(dev->sdev, NULL);
  4638. ieee80211_free_hw(hw);
  4639. }
  4640. static struct b43_wl *b43_wireless_init(struct b43_bus_dev *dev)
  4641. {
  4642. struct ssb_sprom *sprom = dev->bus_sprom;
  4643. struct ieee80211_hw *hw;
  4644. struct b43_wl *wl;
  4645. char chip_name[6];
  4646. int queue_num;
  4647. hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
  4648. if (!hw) {
  4649. b43err(NULL, "Could not allocate ieee80211 device\n");
  4650. return ERR_PTR(-ENOMEM);
  4651. }
  4652. wl = hw_to_b43_wl(hw);
  4653. /* fill hw info */
  4654. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  4655. IEEE80211_HW_SIGNAL_DBM;
  4656. hw->wiphy->interface_modes =
  4657. BIT(NL80211_IFTYPE_AP) |
  4658. BIT(NL80211_IFTYPE_MESH_POINT) |
  4659. BIT(NL80211_IFTYPE_STATION) |
  4660. BIT(NL80211_IFTYPE_WDS) |
  4661. BIT(NL80211_IFTYPE_ADHOC);
  4662. hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
  4663. wl->hw_registred = false;
  4664. hw->max_rates = 2;
  4665. SET_IEEE80211_DEV(hw, dev->dev);
  4666. if (is_valid_ether_addr(sprom->et1mac))
  4667. SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
  4668. else
  4669. SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
  4670. /* Initialize struct b43_wl */
  4671. wl->hw = hw;
  4672. mutex_init(&wl->mutex);
  4673. spin_lock_init(&wl->hardirq_lock);
  4674. INIT_LIST_HEAD(&wl->devlist);
  4675. INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
  4676. INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
  4677. INIT_WORK(&wl->tx_work, b43_tx_work);
  4678. /* Initialize queues and flags. */
  4679. for (queue_num = 0; queue_num < B43_QOS_QUEUE_NUM; queue_num++) {
  4680. skb_queue_head_init(&wl->tx_queue[queue_num]);
  4681. wl->tx_queue_stopped[queue_num] = 0;
  4682. }
  4683. snprintf(chip_name, ARRAY_SIZE(chip_name),
  4684. (dev->chip_id > 0x9999) ? "%d" : "%04X", dev->chip_id);
  4685. b43info(wl, "Broadcom %s WLAN found (core revision %u)\n", chip_name,
  4686. dev->core_rev);
  4687. return wl;
  4688. }
  4689. #ifdef CONFIG_B43_BCMA
  4690. static int b43_bcma_probe(struct bcma_device *core)
  4691. {
  4692. struct b43_bus_dev *dev;
  4693. struct b43_wl *wl;
  4694. int err;
  4695. dev = b43_bus_dev_bcma_init(core);
  4696. if (!dev)
  4697. return -ENODEV;
  4698. wl = b43_wireless_init(dev);
  4699. if (IS_ERR(wl)) {
  4700. err = PTR_ERR(wl);
  4701. goto bcma_out;
  4702. }
  4703. err = b43_one_core_attach(dev, wl);
  4704. if (err)
  4705. goto bcma_err_wireless_exit;
  4706. /* setup and start work to load firmware */
  4707. INIT_WORK(&wl->firmware_load, b43_request_firmware);
  4708. schedule_work(&wl->firmware_load);
  4709. bcma_out:
  4710. return err;
  4711. bcma_err_wireless_exit:
  4712. ieee80211_free_hw(wl->hw);
  4713. return err;
  4714. }
  4715. static void b43_bcma_remove(struct bcma_device *core)
  4716. {
  4717. struct b43_wldev *wldev = bcma_get_drvdata(core);
  4718. struct b43_wl *wl = wldev->wl;
  4719. /* We must cancel any work here before unregistering from ieee80211,
  4720. * as the ieee80211 unreg will destroy the workqueue. */
  4721. cancel_work_sync(&wldev->restart_work);
  4722. cancel_work_sync(&wl->firmware_load);
  4723. B43_WARN_ON(!wl);
  4724. if (!wldev->fw.ucode.data)
  4725. return; /* NULL if firmware never loaded */
  4726. if (wl->current_dev == wldev && wl->hw_registred) {
  4727. b43_leds_stop(wldev);
  4728. ieee80211_unregister_hw(wl->hw);
  4729. }
  4730. b43_one_core_detach(wldev->dev);
  4731. b43_leds_unregister(wl);
  4732. ieee80211_free_hw(wl->hw);
  4733. }
  4734. static struct bcma_driver b43_bcma_driver = {
  4735. .name = KBUILD_MODNAME,
  4736. .id_table = b43_bcma_tbl,
  4737. .probe = b43_bcma_probe,
  4738. .remove = b43_bcma_remove,
  4739. };
  4740. #endif
  4741. #ifdef CONFIG_B43_SSB
  4742. static
  4743. int b43_ssb_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
  4744. {
  4745. struct b43_bus_dev *dev;
  4746. struct b43_wl *wl;
  4747. int err;
  4748. int first = 0;
  4749. dev = b43_bus_dev_ssb_init(sdev);
  4750. if (!dev)
  4751. return -ENOMEM;
  4752. wl = ssb_get_devtypedata(sdev);
  4753. if (!wl) {
  4754. /* Probing the first core. Must setup common struct b43_wl */
  4755. first = 1;
  4756. b43_sprom_fixup(sdev->bus);
  4757. wl = b43_wireless_init(dev);
  4758. if (IS_ERR(wl)) {
  4759. err = PTR_ERR(wl);
  4760. goto out;
  4761. }
  4762. ssb_set_devtypedata(sdev, wl);
  4763. B43_WARN_ON(ssb_get_devtypedata(sdev) != wl);
  4764. }
  4765. err = b43_one_core_attach(dev, wl);
  4766. if (err)
  4767. goto err_wireless_exit;
  4768. /* setup and start work to load firmware */
  4769. INIT_WORK(&wl->firmware_load, b43_request_firmware);
  4770. schedule_work(&wl->firmware_load);
  4771. out:
  4772. return err;
  4773. err_wireless_exit:
  4774. if (first)
  4775. b43_wireless_exit(dev, wl);
  4776. return err;
  4777. }
  4778. static void b43_ssb_remove(struct ssb_device *sdev)
  4779. {
  4780. struct b43_wl *wl = ssb_get_devtypedata(sdev);
  4781. struct b43_wldev *wldev = ssb_get_drvdata(sdev);
  4782. struct b43_bus_dev *dev = wldev->dev;
  4783. /* We must cancel any work here before unregistering from ieee80211,
  4784. * as the ieee80211 unreg will destroy the workqueue. */
  4785. cancel_work_sync(&wldev->restart_work);
  4786. cancel_work_sync(&wl->firmware_load);
  4787. B43_WARN_ON(!wl);
  4788. if (!wldev->fw.ucode.data)
  4789. return; /* NULL if firmware never loaded */
  4790. if (wl->current_dev == wldev && wl->hw_registred) {
  4791. b43_leds_stop(wldev);
  4792. ieee80211_unregister_hw(wl->hw);
  4793. }
  4794. b43_one_core_detach(dev);
  4795. if (list_empty(&wl->devlist)) {
  4796. b43_leds_unregister(wl);
  4797. /* Last core on the chip unregistered.
  4798. * We can destroy common struct b43_wl.
  4799. */
  4800. b43_wireless_exit(dev, wl);
  4801. }
  4802. }
  4803. static struct ssb_driver b43_ssb_driver = {
  4804. .name = KBUILD_MODNAME,
  4805. .id_table = b43_ssb_tbl,
  4806. .probe = b43_ssb_probe,
  4807. .remove = b43_ssb_remove,
  4808. };
  4809. #endif /* CONFIG_B43_SSB */
  4810. /* Perform a hardware reset. This can be called from any context. */
  4811. void b43_controller_restart(struct b43_wldev *dev, const char *reason)
  4812. {
  4813. /* Must avoid requeueing, if we are in shutdown. */
  4814. if (b43_status(dev) < B43_STAT_INITIALIZED)
  4815. return;
  4816. b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
  4817. ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
  4818. }
  4819. static void b43_print_driverinfo(void)
  4820. {
  4821. const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
  4822. *feat_leds = "", *feat_sdio = "";
  4823. #ifdef CONFIG_B43_PCI_AUTOSELECT
  4824. feat_pci = "P";
  4825. #endif
  4826. #ifdef CONFIG_B43_PCMCIA
  4827. feat_pcmcia = "M";
  4828. #endif
  4829. #ifdef CONFIG_B43_PHY_N
  4830. feat_nphy = "N";
  4831. #endif
  4832. #ifdef CONFIG_B43_LEDS
  4833. feat_leds = "L";
  4834. #endif
  4835. #ifdef CONFIG_B43_SDIO
  4836. feat_sdio = "S";
  4837. #endif
  4838. printk(KERN_INFO "Broadcom 43xx driver loaded "
  4839. "[ Features: %s%s%s%s%s ]\n",
  4840. feat_pci, feat_pcmcia, feat_nphy,
  4841. feat_leds, feat_sdio);
  4842. }
  4843. static int __init b43_init(void)
  4844. {
  4845. int err;
  4846. b43_debugfs_init();
  4847. err = b43_pcmcia_init();
  4848. if (err)
  4849. goto err_dfs_exit;
  4850. err = b43_sdio_init();
  4851. if (err)
  4852. goto err_pcmcia_exit;
  4853. #ifdef CONFIG_B43_BCMA
  4854. err = bcma_driver_register(&b43_bcma_driver);
  4855. if (err)
  4856. goto err_sdio_exit;
  4857. #endif
  4858. #ifdef CONFIG_B43_SSB
  4859. err = ssb_driver_register(&b43_ssb_driver);
  4860. if (err)
  4861. goto err_bcma_driver_exit;
  4862. #endif
  4863. b43_print_driverinfo();
  4864. return err;
  4865. #ifdef CONFIG_B43_SSB
  4866. err_bcma_driver_exit:
  4867. #endif
  4868. #ifdef CONFIG_B43_BCMA
  4869. bcma_driver_unregister(&b43_bcma_driver);
  4870. err_sdio_exit:
  4871. #endif
  4872. b43_sdio_exit();
  4873. err_pcmcia_exit:
  4874. b43_pcmcia_exit();
  4875. err_dfs_exit:
  4876. b43_debugfs_exit();
  4877. return err;
  4878. }
  4879. static void __exit b43_exit(void)
  4880. {
  4881. #ifdef CONFIG_B43_SSB
  4882. ssb_driver_unregister(&b43_ssb_driver);
  4883. #endif
  4884. #ifdef CONFIG_B43_BCMA
  4885. bcma_driver_unregister(&b43_bcma_driver);
  4886. #endif
  4887. b43_sdio_exit();
  4888. b43_pcmcia_exit();
  4889. b43_debugfs_exit();
  4890. }
  4891. module_init(b43_init)
  4892. module_exit(b43_exit)