mcdi.c 32 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2008-2011 Solarflare Communications Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published
  7. * by the Free Software Foundation, incorporated herein by reference.
  8. */
  9. #include <linux/delay.h>
  10. #include "net_driver.h"
  11. #include "nic.h"
  12. #include "io.h"
  13. #include "regs.h"
  14. #include "mcdi_pcol.h"
  15. #include "phy.h"
  16. /**************************************************************************
  17. *
  18. * Management-Controller-to-Driver Interface
  19. *
  20. **************************************************************************
  21. */
  22. #define MCDI_RPC_TIMEOUT (10 * HZ)
  23. #define MCDI_PDU(efx) \
  24. (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
  25. #define MCDI_DOORBELL(efx) \
  26. (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
  27. #define MCDI_STATUS(efx) \
  28. (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
  29. /* A reboot/assertion causes the MCDI status word to be set after the
  30. * command word is set or a REBOOT event is sent. If we notice a reboot
  31. * via these mechanisms then wait 10ms for the status word to be set. */
  32. #define MCDI_STATUS_DELAY_US 100
  33. #define MCDI_STATUS_DELAY_COUNT 100
  34. #define MCDI_STATUS_SLEEP_MS \
  35. (MCDI_STATUS_DELAY_US * MCDI_STATUS_DELAY_COUNT / 1000)
  36. #define SEQ_MASK \
  37. EFX_MASK32(EFX_WIDTH(MCDI_HEADER_SEQ))
  38. static inline struct efx_mcdi_iface *efx_mcdi(struct efx_nic *efx)
  39. {
  40. struct siena_nic_data *nic_data;
  41. EFX_BUG_ON_PARANOID(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  42. nic_data = efx->nic_data;
  43. return &nic_data->mcdi;
  44. }
  45. void efx_mcdi_init(struct efx_nic *efx)
  46. {
  47. struct efx_mcdi_iface *mcdi;
  48. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  49. return;
  50. mcdi = efx_mcdi(efx);
  51. init_waitqueue_head(&mcdi->wq);
  52. spin_lock_init(&mcdi->iface_lock);
  53. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  54. mcdi->mode = MCDI_MODE_POLL;
  55. (void) efx_mcdi_poll_reboot(efx);
  56. }
  57. static void efx_mcdi_copyin(struct efx_nic *efx, unsigned cmd,
  58. const u8 *inbuf, size_t inlen)
  59. {
  60. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  61. unsigned pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  62. unsigned doorbell = FR_CZ_MC_TREG_SMEM + MCDI_DOORBELL(efx);
  63. unsigned int i;
  64. efx_dword_t hdr;
  65. u32 xflags, seqno;
  66. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  67. BUG_ON(inlen & 3 || inlen >= MC_SMEM_PDU_LEN);
  68. seqno = mcdi->seqno & SEQ_MASK;
  69. xflags = 0;
  70. if (mcdi->mode == MCDI_MODE_EVENTS)
  71. xflags |= MCDI_HEADER_XFLAGS_EVREQ;
  72. EFX_POPULATE_DWORD_6(hdr,
  73. MCDI_HEADER_RESPONSE, 0,
  74. MCDI_HEADER_RESYNC, 1,
  75. MCDI_HEADER_CODE, cmd,
  76. MCDI_HEADER_DATALEN, inlen,
  77. MCDI_HEADER_SEQ, seqno,
  78. MCDI_HEADER_XFLAGS, xflags);
  79. efx_writed(efx, &hdr, pdu);
  80. for (i = 0; i < inlen; i += 4)
  81. _efx_writed(efx, *((__le32 *)(inbuf + i)), pdu + 4 + i);
  82. /* Ensure the payload is written out before the header */
  83. wmb();
  84. /* ring the doorbell with a distinctive value */
  85. _efx_writed(efx, (__force __le32) 0x45789abc, doorbell);
  86. }
  87. static void efx_mcdi_copyout(struct efx_nic *efx, u8 *outbuf, size_t outlen)
  88. {
  89. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  90. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  91. int i;
  92. BUG_ON(atomic_read(&mcdi->state) == MCDI_STATE_QUIESCENT);
  93. BUG_ON(outlen & 3 || outlen >= MC_SMEM_PDU_LEN);
  94. for (i = 0; i < outlen; i += 4)
  95. *((__le32 *)(outbuf + i)) = _efx_readd(efx, pdu + 4 + i);
  96. }
  97. static int efx_mcdi_poll(struct efx_nic *efx)
  98. {
  99. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  100. unsigned long time, finish;
  101. unsigned int respseq, respcmd, error;
  102. unsigned int pdu = FR_CZ_MC_TREG_SMEM + MCDI_PDU(efx);
  103. unsigned int rc, spins;
  104. efx_dword_t reg;
  105. /* Check for a reboot atomically with respect to efx_mcdi_copyout() */
  106. rc = -efx_mcdi_poll_reboot(efx);
  107. if (rc)
  108. goto out;
  109. /* Poll for completion. Poll quickly (once a us) for the 1st jiffy,
  110. * because generally mcdi responses are fast. After that, back off
  111. * and poll once a jiffy (approximately)
  112. */
  113. spins = TICK_USEC;
  114. finish = jiffies + MCDI_RPC_TIMEOUT;
  115. while (1) {
  116. if (spins != 0) {
  117. --spins;
  118. udelay(1);
  119. } else {
  120. schedule_timeout_uninterruptible(1);
  121. }
  122. time = jiffies;
  123. rmb();
  124. efx_readd(efx, &reg, pdu);
  125. /* All 1's indicates that shared memory is in reset (and is
  126. * not a valid header). Wait for it to come out reset before
  127. * completing the command */
  128. if (EFX_DWORD_FIELD(reg, EFX_DWORD_0) != 0xffffffff &&
  129. EFX_DWORD_FIELD(reg, MCDI_HEADER_RESPONSE))
  130. break;
  131. if (time_after(time, finish))
  132. return -ETIMEDOUT;
  133. }
  134. mcdi->resplen = EFX_DWORD_FIELD(reg, MCDI_HEADER_DATALEN);
  135. respseq = EFX_DWORD_FIELD(reg, MCDI_HEADER_SEQ);
  136. respcmd = EFX_DWORD_FIELD(reg, MCDI_HEADER_CODE);
  137. error = EFX_DWORD_FIELD(reg, MCDI_HEADER_ERROR);
  138. if (error && mcdi->resplen == 0) {
  139. netif_err(efx, hw, efx->net_dev, "MC rebooted\n");
  140. rc = EIO;
  141. } else if ((respseq ^ mcdi->seqno) & SEQ_MASK) {
  142. netif_err(efx, hw, efx->net_dev,
  143. "MC response mismatch tx seq 0x%x rx seq 0x%x\n",
  144. respseq, mcdi->seqno);
  145. rc = EIO;
  146. } else if (error) {
  147. efx_readd(efx, &reg, pdu + 4);
  148. switch (EFX_DWORD_FIELD(reg, EFX_DWORD_0)) {
  149. #define TRANSLATE_ERROR(name) \
  150. case MC_CMD_ERR_ ## name: \
  151. rc = name; \
  152. break
  153. TRANSLATE_ERROR(ENOENT);
  154. TRANSLATE_ERROR(EINTR);
  155. TRANSLATE_ERROR(EACCES);
  156. TRANSLATE_ERROR(EBUSY);
  157. TRANSLATE_ERROR(EINVAL);
  158. TRANSLATE_ERROR(EDEADLK);
  159. TRANSLATE_ERROR(ENOSYS);
  160. TRANSLATE_ERROR(ETIME);
  161. #undef TRANSLATE_ERROR
  162. default:
  163. rc = EIO;
  164. break;
  165. }
  166. } else
  167. rc = 0;
  168. out:
  169. mcdi->resprc = rc;
  170. if (rc)
  171. mcdi->resplen = 0;
  172. /* Return rc=0 like wait_event_timeout() */
  173. return 0;
  174. }
  175. /* Test and clear MC-rebooted flag for this port/function; reset
  176. * software state as necessary.
  177. */
  178. int efx_mcdi_poll_reboot(struct efx_nic *efx)
  179. {
  180. unsigned int addr = FR_CZ_MC_TREG_SMEM + MCDI_STATUS(efx);
  181. efx_dword_t reg;
  182. uint32_t value;
  183. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  184. return false;
  185. efx_readd(efx, &reg, addr);
  186. value = EFX_DWORD_FIELD(reg, EFX_DWORD_0);
  187. if (value == 0)
  188. return 0;
  189. /* MAC statistics have been cleared on the NIC; clear our copy
  190. * so that efx_update_diff_stat() can continue to work.
  191. */
  192. memset(&efx->mac_stats, 0, sizeof(efx->mac_stats));
  193. EFX_ZERO_DWORD(reg);
  194. efx_writed(efx, &reg, addr);
  195. if (value == MC_STATUS_DWORD_ASSERT)
  196. return -EINTR;
  197. else
  198. return -EIO;
  199. }
  200. static void efx_mcdi_acquire(struct efx_mcdi_iface *mcdi)
  201. {
  202. /* Wait until the interface becomes QUIESCENT and we win the race
  203. * to mark it RUNNING. */
  204. wait_event(mcdi->wq,
  205. atomic_cmpxchg(&mcdi->state,
  206. MCDI_STATE_QUIESCENT,
  207. MCDI_STATE_RUNNING)
  208. == MCDI_STATE_QUIESCENT);
  209. }
  210. static int efx_mcdi_await_completion(struct efx_nic *efx)
  211. {
  212. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  213. if (wait_event_timeout(
  214. mcdi->wq,
  215. atomic_read(&mcdi->state) == MCDI_STATE_COMPLETED,
  216. MCDI_RPC_TIMEOUT) == 0)
  217. return -ETIMEDOUT;
  218. /* Check if efx_mcdi_set_mode() switched us back to polled completions.
  219. * In which case, poll for completions directly. If efx_mcdi_ev_cpl()
  220. * completed the request first, then we'll just end up completing the
  221. * request again, which is safe.
  222. *
  223. * We need an smp_rmb() to synchronise with efx_mcdi_mode_poll(), which
  224. * wait_event_timeout() implicitly provides.
  225. */
  226. if (mcdi->mode == MCDI_MODE_POLL)
  227. return efx_mcdi_poll(efx);
  228. return 0;
  229. }
  230. static bool efx_mcdi_complete(struct efx_mcdi_iface *mcdi)
  231. {
  232. /* If the interface is RUNNING, then move to COMPLETED and wake any
  233. * waiters. If the interface isn't in RUNNING then we've received a
  234. * duplicate completion after we've already transitioned back to
  235. * QUIESCENT. [A subsequent invocation would increment seqno, so would
  236. * have failed the seqno check].
  237. */
  238. if (atomic_cmpxchg(&mcdi->state,
  239. MCDI_STATE_RUNNING,
  240. MCDI_STATE_COMPLETED) == MCDI_STATE_RUNNING) {
  241. wake_up(&mcdi->wq);
  242. return true;
  243. }
  244. return false;
  245. }
  246. static void efx_mcdi_release(struct efx_mcdi_iface *mcdi)
  247. {
  248. atomic_set(&mcdi->state, MCDI_STATE_QUIESCENT);
  249. wake_up(&mcdi->wq);
  250. }
  251. static void efx_mcdi_ev_cpl(struct efx_nic *efx, unsigned int seqno,
  252. unsigned int datalen, unsigned int errno)
  253. {
  254. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  255. bool wake = false;
  256. spin_lock(&mcdi->iface_lock);
  257. if ((seqno ^ mcdi->seqno) & SEQ_MASK) {
  258. if (mcdi->credits)
  259. /* The request has been cancelled */
  260. --mcdi->credits;
  261. else
  262. netif_err(efx, hw, efx->net_dev,
  263. "MC response mismatch tx seq 0x%x rx "
  264. "seq 0x%x\n", seqno, mcdi->seqno);
  265. } else {
  266. mcdi->resprc = errno;
  267. mcdi->resplen = datalen;
  268. wake = true;
  269. }
  270. spin_unlock(&mcdi->iface_lock);
  271. if (wake)
  272. efx_mcdi_complete(mcdi);
  273. }
  274. int efx_mcdi_rpc(struct efx_nic *efx, unsigned cmd,
  275. const u8 *inbuf, size_t inlen, u8 *outbuf, size_t outlen,
  276. size_t *outlen_actual)
  277. {
  278. efx_mcdi_rpc_start(efx, cmd, inbuf, inlen);
  279. return efx_mcdi_rpc_finish(efx, cmd, inlen,
  280. outbuf, outlen, outlen_actual);
  281. }
  282. void efx_mcdi_rpc_start(struct efx_nic *efx, unsigned cmd, const u8 *inbuf,
  283. size_t inlen)
  284. {
  285. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  286. BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  287. efx_mcdi_acquire(mcdi);
  288. /* Serialise with efx_mcdi_ev_cpl() and efx_mcdi_ev_death() */
  289. spin_lock_bh(&mcdi->iface_lock);
  290. ++mcdi->seqno;
  291. spin_unlock_bh(&mcdi->iface_lock);
  292. efx_mcdi_copyin(efx, cmd, inbuf, inlen);
  293. }
  294. int efx_mcdi_rpc_finish(struct efx_nic *efx, unsigned cmd, size_t inlen,
  295. u8 *outbuf, size_t outlen, size_t *outlen_actual)
  296. {
  297. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  298. int rc;
  299. BUG_ON(efx_nic_rev(efx) < EFX_REV_SIENA_A0);
  300. if (mcdi->mode == MCDI_MODE_POLL)
  301. rc = efx_mcdi_poll(efx);
  302. else
  303. rc = efx_mcdi_await_completion(efx);
  304. if (rc != 0) {
  305. /* Close the race with efx_mcdi_ev_cpl() executing just too late
  306. * and completing a request we've just cancelled, by ensuring
  307. * that the seqno check therein fails.
  308. */
  309. spin_lock_bh(&mcdi->iface_lock);
  310. ++mcdi->seqno;
  311. ++mcdi->credits;
  312. spin_unlock_bh(&mcdi->iface_lock);
  313. netif_err(efx, hw, efx->net_dev,
  314. "MC command 0x%x inlen %d mode %d timed out\n",
  315. cmd, (int)inlen, mcdi->mode);
  316. } else {
  317. size_t resplen;
  318. /* At the very least we need a memory barrier here to ensure
  319. * we pick up changes from efx_mcdi_ev_cpl(). Protect against
  320. * a spurious efx_mcdi_ev_cpl() running concurrently by
  321. * acquiring the iface_lock. */
  322. spin_lock_bh(&mcdi->iface_lock);
  323. rc = -mcdi->resprc;
  324. resplen = mcdi->resplen;
  325. spin_unlock_bh(&mcdi->iface_lock);
  326. if (rc == 0) {
  327. efx_mcdi_copyout(efx, outbuf,
  328. min(outlen, mcdi->resplen + 3) & ~0x3);
  329. if (outlen_actual != NULL)
  330. *outlen_actual = resplen;
  331. } else if (cmd == MC_CMD_REBOOT && rc == -EIO)
  332. ; /* Don't reset if MC_CMD_REBOOT returns EIO */
  333. else if (rc == -EIO || rc == -EINTR) {
  334. netif_err(efx, hw, efx->net_dev, "MC fatal error %d\n",
  335. -rc);
  336. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  337. } else
  338. netif_dbg(efx, hw, efx->net_dev,
  339. "MC command 0x%x inlen %d failed rc=%d\n",
  340. cmd, (int)inlen, -rc);
  341. if (rc == -EIO || rc == -EINTR) {
  342. msleep(MCDI_STATUS_SLEEP_MS);
  343. efx_mcdi_poll_reboot(efx);
  344. }
  345. }
  346. efx_mcdi_release(mcdi);
  347. return rc;
  348. }
  349. void efx_mcdi_mode_poll(struct efx_nic *efx)
  350. {
  351. struct efx_mcdi_iface *mcdi;
  352. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  353. return;
  354. mcdi = efx_mcdi(efx);
  355. if (mcdi->mode == MCDI_MODE_POLL)
  356. return;
  357. /* We can switch from event completion to polled completion, because
  358. * mcdi requests are always completed in shared memory. We do this by
  359. * switching the mode to POLL'd then completing the request.
  360. * efx_mcdi_await_completion() will then call efx_mcdi_poll().
  361. *
  362. * We need an smp_wmb() to synchronise with efx_mcdi_await_completion(),
  363. * which efx_mcdi_complete() provides for us.
  364. */
  365. mcdi->mode = MCDI_MODE_POLL;
  366. efx_mcdi_complete(mcdi);
  367. }
  368. void efx_mcdi_mode_event(struct efx_nic *efx)
  369. {
  370. struct efx_mcdi_iface *mcdi;
  371. if (efx_nic_rev(efx) < EFX_REV_SIENA_A0)
  372. return;
  373. mcdi = efx_mcdi(efx);
  374. if (mcdi->mode == MCDI_MODE_EVENTS)
  375. return;
  376. /* We can't switch from polled to event completion in the middle of a
  377. * request, because the completion method is specified in the request.
  378. * So acquire the interface to serialise the requestors. We don't need
  379. * to acquire the iface_lock to change the mode here, but we do need a
  380. * write memory barrier ensure that efx_mcdi_rpc() sees it, which
  381. * efx_mcdi_acquire() provides.
  382. */
  383. efx_mcdi_acquire(mcdi);
  384. mcdi->mode = MCDI_MODE_EVENTS;
  385. efx_mcdi_release(mcdi);
  386. }
  387. static void efx_mcdi_ev_death(struct efx_nic *efx, int rc)
  388. {
  389. struct efx_mcdi_iface *mcdi = efx_mcdi(efx);
  390. /* If there is an outstanding MCDI request, it has been terminated
  391. * either by a BADASSERT or REBOOT event. If the mcdi interface is
  392. * in polled mode, then do nothing because the MC reboot handler will
  393. * set the header correctly. However, if the mcdi interface is waiting
  394. * for a CMDDONE event it won't receive it [and since all MCDI events
  395. * are sent to the same queue, we can't be racing with
  396. * efx_mcdi_ev_cpl()]
  397. *
  398. * There's a race here with efx_mcdi_rpc(), because we might receive
  399. * a REBOOT event *before* the request has been copied out. In polled
  400. * mode (during startup) this is irrelevant, because efx_mcdi_complete()
  401. * is ignored. In event mode, this condition is just an edge-case of
  402. * receiving a REBOOT event after posting the MCDI request. Did the mc
  403. * reboot before or after the copyout? The best we can do always is
  404. * just return failure.
  405. */
  406. spin_lock(&mcdi->iface_lock);
  407. if (efx_mcdi_complete(mcdi)) {
  408. if (mcdi->mode == MCDI_MODE_EVENTS) {
  409. mcdi->resprc = rc;
  410. mcdi->resplen = 0;
  411. ++mcdi->credits;
  412. }
  413. } else {
  414. int count;
  415. /* Nobody was waiting for an MCDI request, so trigger a reset */
  416. efx_schedule_reset(efx, RESET_TYPE_MC_FAILURE);
  417. /* Consume the status word since efx_mcdi_rpc_finish() won't */
  418. for (count = 0; count < MCDI_STATUS_DELAY_COUNT; ++count) {
  419. if (efx_mcdi_poll_reboot(efx))
  420. break;
  421. udelay(MCDI_STATUS_DELAY_US);
  422. }
  423. }
  424. spin_unlock(&mcdi->iface_lock);
  425. }
  426. static unsigned int efx_mcdi_event_link_speed[] = {
  427. [MCDI_EVENT_LINKCHANGE_SPEED_100M] = 100,
  428. [MCDI_EVENT_LINKCHANGE_SPEED_1G] = 1000,
  429. [MCDI_EVENT_LINKCHANGE_SPEED_10G] = 10000,
  430. };
  431. static void efx_mcdi_process_link_change(struct efx_nic *efx, efx_qword_t *ev)
  432. {
  433. u32 flags, fcntl, speed, lpa;
  434. speed = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_SPEED);
  435. EFX_BUG_ON_PARANOID(speed >= ARRAY_SIZE(efx_mcdi_event_link_speed));
  436. speed = efx_mcdi_event_link_speed[speed];
  437. flags = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LINK_FLAGS);
  438. fcntl = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_FCNTL);
  439. lpa = EFX_QWORD_FIELD(*ev, MCDI_EVENT_LINKCHANGE_LP_CAP);
  440. /* efx->link_state is only modified by efx_mcdi_phy_get_link(),
  441. * which is only run after flushing the event queues. Therefore, it
  442. * is safe to modify the link state outside of the mac_lock here.
  443. */
  444. efx_mcdi_phy_decode_link(efx, &efx->link_state, speed, flags, fcntl);
  445. efx_mcdi_phy_check_fcntl(efx, lpa);
  446. efx_link_status_changed(efx);
  447. }
  448. /* Called from falcon_process_eventq for MCDI events */
  449. void efx_mcdi_process_event(struct efx_channel *channel,
  450. efx_qword_t *event)
  451. {
  452. struct efx_nic *efx = channel->efx;
  453. int code = EFX_QWORD_FIELD(*event, MCDI_EVENT_CODE);
  454. u32 data = EFX_QWORD_FIELD(*event, MCDI_EVENT_DATA);
  455. switch (code) {
  456. case MCDI_EVENT_CODE_BADSSERT:
  457. netif_err(efx, hw, efx->net_dev,
  458. "MC watchdog or assertion failure at 0x%x\n", data);
  459. efx_mcdi_ev_death(efx, EINTR);
  460. break;
  461. case MCDI_EVENT_CODE_PMNOTICE:
  462. netif_info(efx, wol, efx->net_dev, "MCDI PM event.\n");
  463. break;
  464. case MCDI_EVENT_CODE_CMDDONE:
  465. efx_mcdi_ev_cpl(efx,
  466. MCDI_EVENT_FIELD(*event, CMDDONE_SEQ),
  467. MCDI_EVENT_FIELD(*event, CMDDONE_DATALEN),
  468. MCDI_EVENT_FIELD(*event, CMDDONE_ERRNO));
  469. break;
  470. case MCDI_EVENT_CODE_LINKCHANGE:
  471. efx_mcdi_process_link_change(efx, event);
  472. break;
  473. case MCDI_EVENT_CODE_SENSOREVT:
  474. efx_mcdi_sensor_event(efx, event);
  475. break;
  476. case MCDI_EVENT_CODE_SCHEDERR:
  477. netif_info(efx, hw, efx->net_dev,
  478. "MC Scheduler error address=0x%x\n", data);
  479. break;
  480. case MCDI_EVENT_CODE_REBOOT:
  481. netif_info(efx, hw, efx->net_dev, "MC Reboot\n");
  482. efx_mcdi_ev_death(efx, EIO);
  483. break;
  484. case MCDI_EVENT_CODE_MAC_STATS_DMA:
  485. /* MAC stats are gather lazily. We can ignore this. */
  486. break;
  487. case MCDI_EVENT_CODE_FLR:
  488. efx_sriov_flr(efx, MCDI_EVENT_FIELD(*event, FLR_VF));
  489. break;
  490. case MCDI_EVENT_CODE_PTP_RX:
  491. case MCDI_EVENT_CODE_PTP_FAULT:
  492. case MCDI_EVENT_CODE_PTP_PPS:
  493. efx_ptp_event(efx, event);
  494. break;
  495. default:
  496. netif_err(efx, hw, efx->net_dev, "Unknown MCDI event 0x%x\n",
  497. code);
  498. }
  499. }
  500. /**************************************************************************
  501. *
  502. * Specific request functions
  503. *
  504. **************************************************************************
  505. */
  506. void efx_mcdi_print_fwver(struct efx_nic *efx, char *buf, size_t len)
  507. {
  508. u8 outbuf[ALIGN(MC_CMD_GET_VERSION_OUT_LEN, 4)];
  509. size_t outlength;
  510. const __le16 *ver_words;
  511. int rc;
  512. BUILD_BUG_ON(MC_CMD_GET_VERSION_IN_LEN != 0);
  513. rc = efx_mcdi_rpc(efx, MC_CMD_GET_VERSION, NULL, 0,
  514. outbuf, sizeof(outbuf), &outlength);
  515. if (rc)
  516. goto fail;
  517. if (outlength < MC_CMD_GET_VERSION_OUT_LEN) {
  518. rc = -EIO;
  519. goto fail;
  520. }
  521. ver_words = (__le16 *)MCDI_PTR(outbuf, GET_VERSION_OUT_VERSION);
  522. snprintf(buf, len, "%u.%u.%u.%u",
  523. le16_to_cpu(ver_words[0]), le16_to_cpu(ver_words[1]),
  524. le16_to_cpu(ver_words[2]), le16_to_cpu(ver_words[3]));
  525. return;
  526. fail:
  527. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  528. buf[0] = 0;
  529. }
  530. int efx_mcdi_drv_attach(struct efx_nic *efx, bool driver_operating,
  531. bool *was_attached)
  532. {
  533. u8 inbuf[MC_CMD_DRV_ATTACH_IN_LEN];
  534. u8 outbuf[MC_CMD_DRV_ATTACH_OUT_LEN];
  535. size_t outlen;
  536. int rc;
  537. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_NEW_STATE,
  538. driver_operating ? 1 : 0);
  539. MCDI_SET_DWORD(inbuf, DRV_ATTACH_IN_UPDATE, 1);
  540. rc = efx_mcdi_rpc(efx, MC_CMD_DRV_ATTACH, inbuf, sizeof(inbuf),
  541. outbuf, sizeof(outbuf), &outlen);
  542. if (rc)
  543. goto fail;
  544. if (outlen < MC_CMD_DRV_ATTACH_OUT_LEN) {
  545. rc = -EIO;
  546. goto fail;
  547. }
  548. if (was_attached != NULL)
  549. *was_attached = MCDI_DWORD(outbuf, DRV_ATTACH_OUT_OLD_STATE);
  550. return 0;
  551. fail:
  552. netif_err(efx, probe, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  553. return rc;
  554. }
  555. int efx_mcdi_get_board_cfg(struct efx_nic *efx, u8 *mac_address,
  556. u16 *fw_subtype_list, u32 *capabilities)
  557. {
  558. uint8_t outbuf[MC_CMD_GET_BOARD_CFG_OUT_LENMAX];
  559. size_t outlen, offset, i;
  560. int port_num = efx_port_num(efx);
  561. int rc;
  562. BUILD_BUG_ON(MC_CMD_GET_BOARD_CFG_IN_LEN != 0);
  563. rc = efx_mcdi_rpc(efx, MC_CMD_GET_BOARD_CFG, NULL, 0,
  564. outbuf, sizeof(outbuf), &outlen);
  565. if (rc)
  566. goto fail;
  567. if (outlen < MC_CMD_GET_BOARD_CFG_OUT_LENMIN) {
  568. rc = -EIO;
  569. goto fail;
  570. }
  571. offset = (port_num)
  572. ? MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST
  573. : MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST;
  574. if (mac_address)
  575. memcpy(mac_address, outbuf + offset, ETH_ALEN);
  576. if (fw_subtype_list) {
  577. /* Byte-swap and truncate or zero-pad as necessary */
  578. offset = MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST;
  579. for (i = 0;
  580. i < MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM;
  581. i++) {
  582. fw_subtype_list[i] =
  583. (offset + 2 <= outlen) ?
  584. le16_to_cpup((__le16 *)(outbuf + offset)) : 0;
  585. offset += 2;
  586. }
  587. }
  588. if (capabilities) {
  589. if (port_num)
  590. *capabilities = MCDI_DWORD(outbuf,
  591. GET_BOARD_CFG_OUT_CAPABILITIES_PORT1);
  592. else
  593. *capabilities = MCDI_DWORD(outbuf,
  594. GET_BOARD_CFG_OUT_CAPABILITIES_PORT0);
  595. }
  596. return 0;
  597. fail:
  598. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d len=%d\n",
  599. __func__, rc, (int)outlen);
  600. return rc;
  601. }
  602. int efx_mcdi_log_ctrl(struct efx_nic *efx, bool evq, bool uart, u32 dest_evq)
  603. {
  604. u8 inbuf[MC_CMD_LOG_CTRL_IN_LEN];
  605. u32 dest = 0;
  606. int rc;
  607. if (uart)
  608. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_UART;
  609. if (evq)
  610. dest |= MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ;
  611. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST, dest);
  612. MCDI_SET_DWORD(inbuf, LOG_CTRL_IN_LOG_DEST_EVQ, dest_evq);
  613. BUILD_BUG_ON(MC_CMD_LOG_CTRL_OUT_LEN != 0);
  614. rc = efx_mcdi_rpc(efx, MC_CMD_LOG_CTRL, inbuf, sizeof(inbuf),
  615. NULL, 0, NULL);
  616. if (rc)
  617. goto fail;
  618. return 0;
  619. fail:
  620. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  621. return rc;
  622. }
  623. int efx_mcdi_nvram_types(struct efx_nic *efx, u32 *nvram_types_out)
  624. {
  625. u8 outbuf[MC_CMD_NVRAM_TYPES_OUT_LEN];
  626. size_t outlen;
  627. int rc;
  628. BUILD_BUG_ON(MC_CMD_NVRAM_TYPES_IN_LEN != 0);
  629. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TYPES, NULL, 0,
  630. outbuf, sizeof(outbuf), &outlen);
  631. if (rc)
  632. goto fail;
  633. if (outlen < MC_CMD_NVRAM_TYPES_OUT_LEN) {
  634. rc = -EIO;
  635. goto fail;
  636. }
  637. *nvram_types_out = MCDI_DWORD(outbuf, NVRAM_TYPES_OUT_TYPES);
  638. return 0;
  639. fail:
  640. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  641. __func__, rc);
  642. return rc;
  643. }
  644. int efx_mcdi_nvram_info(struct efx_nic *efx, unsigned int type,
  645. size_t *size_out, size_t *erase_size_out,
  646. bool *protected_out)
  647. {
  648. u8 inbuf[MC_CMD_NVRAM_INFO_IN_LEN];
  649. u8 outbuf[MC_CMD_NVRAM_INFO_OUT_LEN];
  650. size_t outlen;
  651. int rc;
  652. MCDI_SET_DWORD(inbuf, NVRAM_INFO_IN_TYPE, type);
  653. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_INFO, inbuf, sizeof(inbuf),
  654. outbuf, sizeof(outbuf), &outlen);
  655. if (rc)
  656. goto fail;
  657. if (outlen < MC_CMD_NVRAM_INFO_OUT_LEN) {
  658. rc = -EIO;
  659. goto fail;
  660. }
  661. *size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_SIZE);
  662. *erase_size_out = MCDI_DWORD(outbuf, NVRAM_INFO_OUT_ERASESIZE);
  663. *protected_out = !!(MCDI_DWORD(outbuf, NVRAM_INFO_OUT_FLAGS) &
  664. (1 << MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN));
  665. return 0;
  666. fail:
  667. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  668. return rc;
  669. }
  670. int efx_mcdi_nvram_update_start(struct efx_nic *efx, unsigned int type)
  671. {
  672. u8 inbuf[MC_CMD_NVRAM_UPDATE_START_IN_LEN];
  673. int rc;
  674. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_START_IN_TYPE, type);
  675. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_START_OUT_LEN != 0);
  676. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_START, inbuf, sizeof(inbuf),
  677. NULL, 0, NULL);
  678. if (rc)
  679. goto fail;
  680. return 0;
  681. fail:
  682. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  683. return rc;
  684. }
  685. int efx_mcdi_nvram_read(struct efx_nic *efx, unsigned int type,
  686. loff_t offset, u8 *buffer, size_t length)
  687. {
  688. u8 inbuf[MC_CMD_NVRAM_READ_IN_LEN];
  689. u8 outbuf[MC_CMD_NVRAM_READ_OUT_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  690. size_t outlen;
  691. int rc;
  692. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_TYPE, type);
  693. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_OFFSET, offset);
  694. MCDI_SET_DWORD(inbuf, NVRAM_READ_IN_LENGTH, length);
  695. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_READ, inbuf, sizeof(inbuf),
  696. outbuf, sizeof(outbuf), &outlen);
  697. if (rc)
  698. goto fail;
  699. memcpy(buffer, MCDI_PTR(outbuf, NVRAM_READ_OUT_READ_BUFFER), length);
  700. return 0;
  701. fail:
  702. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  703. return rc;
  704. }
  705. int efx_mcdi_nvram_write(struct efx_nic *efx, unsigned int type,
  706. loff_t offset, const u8 *buffer, size_t length)
  707. {
  708. u8 inbuf[MC_CMD_NVRAM_WRITE_IN_LEN(EFX_MCDI_NVRAM_LEN_MAX)];
  709. int rc;
  710. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_TYPE, type);
  711. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_OFFSET, offset);
  712. MCDI_SET_DWORD(inbuf, NVRAM_WRITE_IN_LENGTH, length);
  713. memcpy(MCDI_PTR(inbuf, NVRAM_WRITE_IN_WRITE_BUFFER), buffer, length);
  714. BUILD_BUG_ON(MC_CMD_NVRAM_WRITE_OUT_LEN != 0);
  715. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_WRITE, inbuf,
  716. ALIGN(MC_CMD_NVRAM_WRITE_IN_LEN(length), 4),
  717. NULL, 0, NULL);
  718. if (rc)
  719. goto fail;
  720. return 0;
  721. fail:
  722. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  723. return rc;
  724. }
  725. int efx_mcdi_nvram_erase(struct efx_nic *efx, unsigned int type,
  726. loff_t offset, size_t length)
  727. {
  728. u8 inbuf[MC_CMD_NVRAM_ERASE_IN_LEN];
  729. int rc;
  730. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_TYPE, type);
  731. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_OFFSET, offset);
  732. MCDI_SET_DWORD(inbuf, NVRAM_ERASE_IN_LENGTH, length);
  733. BUILD_BUG_ON(MC_CMD_NVRAM_ERASE_OUT_LEN != 0);
  734. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_ERASE, inbuf, sizeof(inbuf),
  735. NULL, 0, NULL);
  736. if (rc)
  737. goto fail;
  738. return 0;
  739. fail:
  740. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  741. return rc;
  742. }
  743. int efx_mcdi_nvram_update_finish(struct efx_nic *efx, unsigned int type)
  744. {
  745. u8 inbuf[MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN];
  746. int rc;
  747. MCDI_SET_DWORD(inbuf, NVRAM_UPDATE_FINISH_IN_TYPE, type);
  748. BUILD_BUG_ON(MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN != 0);
  749. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_UPDATE_FINISH, inbuf, sizeof(inbuf),
  750. NULL, 0, NULL);
  751. if (rc)
  752. goto fail;
  753. return 0;
  754. fail:
  755. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  756. return rc;
  757. }
  758. static int efx_mcdi_nvram_test(struct efx_nic *efx, unsigned int type)
  759. {
  760. u8 inbuf[MC_CMD_NVRAM_TEST_IN_LEN];
  761. u8 outbuf[MC_CMD_NVRAM_TEST_OUT_LEN];
  762. int rc;
  763. MCDI_SET_DWORD(inbuf, NVRAM_TEST_IN_TYPE, type);
  764. rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_TEST, inbuf, sizeof(inbuf),
  765. outbuf, sizeof(outbuf), NULL);
  766. if (rc)
  767. return rc;
  768. switch (MCDI_DWORD(outbuf, NVRAM_TEST_OUT_RESULT)) {
  769. case MC_CMD_NVRAM_TEST_PASS:
  770. case MC_CMD_NVRAM_TEST_NOTSUPP:
  771. return 0;
  772. default:
  773. return -EIO;
  774. }
  775. }
  776. int efx_mcdi_nvram_test_all(struct efx_nic *efx)
  777. {
  778. u32 nvram_types;
  779. unsigned int type;
  780. int rc;
  781. rc = efx_mcdi_nvram_types(efx, &nvram_types);
  782. if (rc)
  783. goto fail1;
  784. type = 0;
  785. while (nvram_types != 0) {
  786. if (nvram_types & 1) {
  787. rc = efx_mcdi_nvram_test(efx, type);
  788. if (rc)
  789. goto fail2;
  790. }
  791. type++;
  792. nvram_types >>= 1;
  793. }
  794. return 0;
  795. fail2:
  796. netif_err(efx, hw, efx->net_dev, "%s: failed type=%u\n",
  797. __func__, type);
  798. fail1:
  799. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  800. return rc;
  801. }
  802. static int efx_mcdi_read_assertion(struct efx_nic *efx)
  803. {
  804. u8 inbuf[MC_CMD_GET_ASSERTS_IN_LEN];
  805. u8 outbuf[MC_CMD_GET_ASSERTS_OUT_LEN];
  806. unsigned int flags, index, ofst;
  807. const char *reason;
  808. size_t outlen;
  809. int retry;
  810. int rc;
  811. /* Attempt to read any stored assertion state before we reboot
  812. * the mcfw out of the assertion handler. Retry twice, once
  813. * because a boot-time assertion might cause this command to fail
  814. * with EINTR. And once again because GET_ASSERTS can race with
  815. * MC_CMD_REBOOT running on the other port. */
  816. retry = 2;
  817. do {
  818. MCDI_SET_DWORD(inbuf, GET_ASSERTS_IN_CLEAR, 1);
  819. rc = efx_mcdi_rpc(efx, MC_CMD_GET_ASSERTS,
  820. inbuf, MC_CMD_GET_ASSERTS_IN_LEN,
  821. outbuf, sizeof(outbuf), &outlen);
  822. } while ((rc == -EINTR || rc == -EIO) && retry-- > 0);
  823. if (rc)
  824. return rc;
  825. if (outlen < MC_CMD_GET_ASSERTS_OUT_LEN)
  826. return -EIO;
  827. /* Print out any recorded assertion state */
  828. flags = MCDI_DWORD(outbuf, GET_ASSERTS_OUT_GLOBAL_FLAGS);
  829. if (flags == MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS)
  830. return 0;
  831. reason = (flags == MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL)
  832. ? "system-level assertion"
  833. : (flags == MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL)
  834. ? "thread-level assertion"
  835. : (flags == MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED)
  836. ? "watchdog reset"
  837. : "unknown assertion";
  838. netif_err(efx, hw, efx->net_dev,
  839. "MCPU %s at PC = 0x%.8x in thread 0x%.8x\n", reason,
  840. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_SAVED_PC_OFFS),
  841. MCDI_DWORD(outbuf, GET_ASSERTS_OUT_THREAD_OFFS));
  842. /* Print out the registers */
  843. ofst = MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST;
  844. for (index = 1; index < 32; index++) {
  845. netif_err(efx, hw, efx->net_dev, "R%.2d (?): 0x%.8x\n", index,
  846. MCDI_DWORD2(outbuf, ofst));
  847. ofst += sizeof(efx_dword_t);
  848. }
  849. return 0;
  850. }
  851. static void efx_mcdi_exit_assertion(struct efx_nic *efx)
  852. {
  853. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  854. /* If the MC is running debug firmware, it might now be
  855. * waiting for a debugger to attach, but we just want it to
  856. * reboot. We set a flag that makes the command a no-op if it
  857. * has already done so. We don't know what return code to
  858. * expect (0 or -EIO), so ignore it.
  859. */
  860. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  861. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS,
  862. MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION);
  863. (void) efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, MC_CMD_REBOOT_IN_LEN,
  864. NULL, 0, NULL);
  865. }
  866. int efx_mcdi_handle_assertion(struct efx_nic *efx)
  867. {
  868. int rc;
  869. rc = efx_mcdi_read_assertion(efx);
  870. if (rc)
  871. return rc;
  872. efx_mcdi_exit_assertion(efx);
  873. return 0;
  874. }
  875. void efx_mcdi_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
  876. {
  877. u8 inbuf[MC_CMD_SET_ID_LED_IN_LEN];
  878. int rc;
  879. BUILD_BUG_ON(EFX_LED_OFF != MC_CMD_LED_OFF);
  880. BUILD_BUG_ON(EFX_LED_ON != MC_CMD_LED_ON);
  881. BUILD_BUG_ON(EFX_LED_DEFAULT != MC_CMD_LED_DEFAULT);
  882. BUILD_BUG_ON(MC_CMD_SET_ID_LED_OUT_LEN != 0);
  883. MCDI_SET_DWORD(inbuf, SET_ID_LED_IN_STATE, mode);
  884. rc = efx_mcdi_rpc(efx, MC_CMD_SET_ID_LED, inbuf, sizeof(inbuf),
  885. NULL, 0, NULL);
  886. if (rc)
  887. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  888. __func__, rc);
  889. }
  890. int efx_mcdi_reset_port(struct efx_nic *efx)
  891. {
  892. int rc = efx_mcdi_rpc(efx, MC_CMD_ENTITY_RESET, NULL, 0, NULL, 0, NULL);
  893. if (rc)
  894. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n",
  895. __func__, rc);
  896. return rc;
  897. }
  898. int efx_mcdi_reset_mc(struct efx_nic *efx)
  899. {
  900. u8 inbuf[MC_CMD_REBOOT_IN_LEN];
  901. int rc;
  902. BUILD_BUG_ON(MC_CMD_REBOOT_OUT_LEN != 0);
  903. MCDI_SET_DWORD(inbuf, REBOOT_IN_FLAGS, 0);
  904. rc = efx_mcdi_rpc(efx, MC_CMD_REBOOT, inbuf, sizeof(inbuf),
  905. NULL, 0, NULL);
  906. /* White is black, and up is down */
  907. if (rc == -EIO)
  908. return 0;
  909. if (rc == 0)
  910. rc = -EIO;
  911. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  912. return rc;
  913. }
  914. static int efx_mcdi_wol_filter_set(struct efx_nic *efx, u32 type,
  915. const u8 *mac, int *id_out)
  916. {
  917. u8 inbuf[MC_CMD_WOL_FILTER_SET_IN_LEN];
  918. u8 outbuf[MC_CMD_WOL_FILTER_SET_OUT_LEN];
  919. size_t outlen;
  920. int rc;
  921. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_WOL_TYPE, type);
  922. MCDI_SET_DWORD(inbuf, WOL_FILTER_SET_IN_FILTER_MODE,
  923. MC_CMD_FILTER_MODE_SIMPLE);
  924. memcpy(MCDI_PTR(inbuf, WOL_FILTER_SET_IN_MAGIC_MAC), mac, ETH_ALEN);
  925. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_SET, inbuf, sizeof(inbuf),
  926. outbuf, sizeof(outbuf), &outlen);
  927. if (rc)
  928. goto fail;
  929. if (outlen < MC_CMD_WOL_FILTER_SET_OUT_LEN) {
  930. rc = -EIO;
  931. goto fail;
  932. }
  933. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_SET_OUT_FILTER_ID);
  934. return 0;
  935. fail:
  936. *id_out = -1;
  937. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  938. return rc;
  939. }
  940. int
  941. efx_mcdi_wol_filter_set_magic(struct efx_nic *efx, const u8 *mac, int *id_out)
  942. {
  943. return efx_mcdi_wol_filter_set(efx, MC_CMD_WOL_TYPE_MAGIC, mac, id_out);
  944. }
  945. int efx_mcdi_wol_filter_get_magic(struct efx_nic *efx, int *id_out)
  946. {
  947. u8 outbuf[MC_CMD_WOL_FILTER_GET_OUT_LEN];
  948. size_t outlen;
  949. int rc;
  950. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_GET, NULL, 0,
  951. outbuf, sizeof(outbuf), &outlen);
  952. if (rc)
  953. goto fail;
  954. if (outlen < MC_CMD_WOL_FILTER_GET_OUT_LEN) {
  955. rc = -EIO;
  956. goto fail;
  957. }
  958. *id_out = (int)MCDI_DWORD(outbuf, WOL_FILTER_GET_OUT_FILTER_ID);
  959. return 0;
  960. fail:
  961. *id_out = -1;
  962. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  963. return rc;
  964. }
  965. int efx_mcdi_wol_filter_remove(struct efx_nic *efx, int id)
  966. {
  967. u8 inbuf[MC_CMD_WOL_FILTER_REMOVE_IN_LEN];
  968. int rc;
  969. MCDI_SET_DWORD(inbuf, WOL_FILTER_REMOVE_IN_FILTER_ID, (u32)id);
  970. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_REMOVE, inbuf, sizeof(inbuf),
  971. NULL, 0, NULL);
  972. if (rc)
  973. goto fail;
  974. return 0;
  975. fail:
  976. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  977. return rc;
  978. }
  979. int efx_mcdi_flush_rxqs(struct efx_nic *efx)
  980. {
  981. struct efx_channel *channel;
  982. struct efx_rx_queue *rx_queue;
  983. __le32 *qid;
  984. int rc, count;
  985. BUILD_BUG_ON(EFX_MAX_CHANNELS >
  986. MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM);
  987. qid = kmalloc(EFX_MAX_CHANNELS * sizeof(*qid), GFP_KERNEL);
  988. if (qid == NULL)
  989. return -ENOMEM;
  990. count = 0;
  991. efx_for_each_channel(channel, efx) {
  992. efx_for_each_channel_rx_queue(rx_queue, channel) {
  993. if (rx_queue->flush_pending) {
  994. rx_queue->flush_pending = false;
  995. atomic_dec(&efx->rxq_flush_pending);
  996. qid[count++] = cpu_to_le32(
  997. efx_rx_queue_index(rx_queue));
  998. }
  999. }
  1000. }
  1001. rc = efx_mcdi_rpc(efx, MC_CMD_FLUSH_RX_QUEUES, (u8 *)qid,
  1002. count * sizeof(*qid), NULL, 0, NULL);
  1003. WARN_ON(rc < 0);
  1004. kfree(qid);
  1005. return rc;
  1006. }
  1007. int efx_mcdi_wol_filter_reset(struct efx_nic *efx)
  1008. {
  1009. int rc;
  1010. rc = efx_mcdi_rpc(efx, MC_CMD_WOL_FILTER_RESET, NULL, 0, NULL, 0, NULL);
  1011. if (rc)
  1012. goto fail;
  1013. return 0;
  1014. fail:
  1015. netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc);
  1016. return rc;
  1017. }