dl2k.c 45 KB

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  1. /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
  2. /*
  3. Copyright (c) 2001, 2002 by D-Link Corporation
  4. Written by Edward Peng.<edward_peng@dlink.com.tw>
  5. Created 03-May-2001, base on Linux' sundance.c.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. */
  11. #define DRV_NAME "DL2000/TC902x-based linux driver"
  12. #define DRV_VERSION "v1.19"
  13. #define DRV_RELDATE "2007/08/12"
  14. #include "dl2k.h"
  15. #include <linux/dma-mapping.h>
  16. #define dw32(reg, val) iowrite32(val, ioaddr + (reg))
  17. #define dw16(reg, val) iowrite16(val, ioaddr + (reg))
  18. #define dw8(reg, val) iowrite8(val, ioaddr + (reg))
  19. #define dr32(reg) ioread32(ioaddr + (reg))
  20. #define dr16(reg) ioread16(ioaddr + (reg))
  21. #define dr8(reg) ioread8(ioaddr + (reg))
  22. static char version[] =
  23. KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
  24. #define MAX_UNITS 8
  25. static int mtu[MAX_UNITS];
  26. static int vlan[MAX_UNITS];
  27. static int jumbo[MAX_UNITS];
  28. static char *media[MAX_UNITS];
  29. static int tx_flow=-1;
  30. static int rx_flow=-1;
  31. static int copy_thresh;
  32. static int rx_coalesce=10; /* Rx frame count each interrupt */
  33. static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
  34. static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
  35. MODULE_AUTHOR ("Edward Peng");
  36. MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
  37. MODULE_LICENSE("GPL");
  38. module_param_array(mtu, int, NULL, 0);
  39. module_param_array(media, charp, NULL, 0);
  40. module_param_array(vlan, int, NULL, 0);
  41. module_param_array(jumbo, int, NULL, 0);
  42. module_param(tx_flow, int, 0);
  43. module_param(rx_flow, int, 0);
  44. module_param(copy_thresh, int, 0);
  45. module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
  46. module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
  47. module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
  48. /* Enable the default interrupts */
  49. #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
  50. UpdateStats | LinkEvent)
  51. static void dl2k_enable_int(struct netdev_private *np)
  52. {
  53. void __iomem *ioaddr = np->ioaddr;
  54. dw16(IntEnable, DEFAULT_INTR);
  55. }
  56. static const int max_intrloop = 50;
  57. static const int multicast_filter_limit = 0x40;
  58. static int rio_open (struct net_device *dev);
  59. static void rio_timer (unsigned long data);
  60. static void rio_tx_timeout (struct net_device *dev);
  61. static void alloc_list (struct net_device *dev);
  62. static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
  63. static irqreturn_t rio_interrupt (int irq, void *dev_instance);
  64. static void rio_free_tx (struct net_device *dev, int irq);
  65. static void tx_error (struct net_device *dev, int tx_status);
  66. static int receive_packet (struct net_device *dev);
  67. static void rio_error (struct net_device *dev, int int_status);
  68. static int change_mtu (struct net_device *dev, int new_mtu);
  69. static void set_multicast (struct net_device *dev);
  70. static struct net_device_stats *get_stats (struct net_device *dev);
  71. static int clear_stats (struct net_device *dev);
  72. static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  73. static int rio_close (struct net_device *dev);
  74. static int find_miiphy (struct net_device *dev);
  75. static int parse_eeprom (struct net_device *dev);
  76. static int read_eeprom (struct netdev_private *, int eep_addr);
  77. static int mii_wait_link (struct net_device *dev, int wait);
  78. static int mii_set_media (struct net_device *dev);
  79. static int mii_get_media (struct net_device *dev);
  80. static int mii_set_media_pcs (struct net_device *dev);
  81. static int mii_get_media_pcs (struct net_device *dev);
  82. static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
  83. static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
  84. u16 data);
  85. static const struct ethtool_ops ethtool_ops;
  86. static const struct net_device_ops netdev_ops = {
  87. .ndo_open = rio_open,
  88. .ndo_start_xmit = start_xmit,
  89. .ndo_stop = rio_close,
  90. .ndo_get_stats = get_stats,
  91. .ndo_validate_addr = eth_validate_addr,
  92. .ndo_set_mac_address = eth_mac_addr,
  93. .ndo_set_rx_mode = set_multicast,
  94. .ndo_do_ioctl = rio_ioctl,
  95. .ndo_tx_timeout = rio_tx_timeout,
  96. .ndo_change_mtu = change_mtu,
  97. };
  98. static int
  99. rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
  100. {
  101. struct net_device *dev;
  102. struct netdev_private *np;
  103. static int card_idx;
  104. int chip_idx = ent->driver_data;
  105. int err, irq;
  106. void __iomem *ioaddr;
  107. static int version_printed;
  108. void *ring_space;
  109. dma_addr_t ring_dma;
  110. if (!version_printed++)
  111. printk ("%s", version);
  112. err = pci_enable_device (pdev);
  113. if (err)
  114. return err;
  115. irq = pdev->irq;
  116. err = pci_request_regions (pdev, "dl2k");
  117. if (err)
  118. goto err_out_disable;
  119. pci_set_master (pdev);
  120. err = -ENOMEM;
  121. dev = alloc_etherdev (sizeof (*np));
  122. if (!dev)
  123. goto err_out_res;
  124. SET_NETDEV_DEV(dev, &pdev->dev);
  125. np = netdev_priv(dev);
  126. /* IO registers range. */
  127. ioaddr = pci_iomap(pdev, 0, 0);
  128. if (!ioaddr)
  129. goto err_out_dev;
  130. np->eeprom_addr = ioaddr;
  131. #ifdef MEM_MAPPING
  132. /* MM registers range. */
  133. ioaddr = pci_iomap(pdev, 1, 0);
  134. if (!ioaddr)
  135. goto err_out_iounmap;
  136. #endif
  137. np->ioaddr = ioaddr;
  138. np->chip_id = chip_idx;
  139. np->pdev = pdev;
  140. spin_lock_init (&np->tx_lock);
  141. spin_lock_init (&np->rx_lock);
  142. /* Parse manual configuration */
  143. np->an_enable = 1;
  144. np->tx_coalesce = 1;
  145. if (card_idx < MAX_UNITS) {
  146. if (media[card_idx] != NULL) {
  147. np->an_enable = 0;
  148. if (strcmp (media[card_idx], "auto") == 0 ||
  149. strcmp (media[card_idx], "autosense") == 0 ||
  150. strcmp (media[card_idx], "0") == 0 ) {
  151. np->an_enable = 2;
  152. } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
  153. strcmp (media[card_idx], "4") == 0) {
  154. np->speed = 100;
  155. np->full_duplex = 1;
  156. } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
  157. strcmp (media[card_idx], "3") == 0) {
  158. np->speed = 100;
  159. np->full_duplex = 0;
  160. } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
  161. strcmp (media[card_idx], "2") == 0) {
  162. np->speed = 10;
  163. np->full_duplex = 1;
  164. } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
  165. strcmp (media[card_idx], "1") == 0) {
  166. np->speed = 10;
  167. np->full_duplex = 0;
  168. } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
  169. strcmp (media[card_idx], "6") == 0) {
  170. np->speed=1000;
  171. np->full_duplex=1;
  172. } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
  173. strcmp (media[card_idx], "5") == 0) {
  174. np->speed = 1000;
  175. np->full_duplex = 0;
  176. } else {
  177. np->an_enable = 1;
  178. }
  179. }
  180. if (jumbo[card_idx] != 0) {
  181. np->jumbo = 1;
  182. dev->mtu = MAX_JUMBO;
  183. } else {
  184. np->jumbo = 0;
  185. if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
  186. dev->mtu = mtu[card_idx];
  187. }
  188. np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
  189. vlan[card_idx] : 0;
  190. if (rx_coalesce > 0 && rx_timeout > 0) {
  191. np->rx_coalesce = rx_coalesce;
  192. np->rx_timeout = rx_timeout;
  193. np->coalesce = 1;
  194. }
  195. np->tx_flow = (tx_flow == 0) ? 0 : 1;
  196. np->rx_flow = (rx_flow == 0) ? 0 : 1;
  197. if (tx_coalesce < 1)
  198. tx_coalesce = 1;
  199. else if (tx_coalesce > TX_RING_SIZE-1)
  200. tx_coalesce = TX_RING_SIZE - 1;
  201. }
  202. dev->netdev_ops = &netdev_ops;
  203. dev->watchdog_timeo = TX_TIMEOUT;
  204. SET_ETHTOOL_OPS(dev, &ethtool_ops);
  205. #if 0
  206. dev->features = NETIF_F_IP_CSUM;
  207. #endif
  208. pci_set_drvdata (pdev, dev);
  209. ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
  210. if (!ring_space)
  211. goto err_out_iounmap;
  212. np->tx_ring = ring_space;
  213. np->tx_ring_dma = ring_dma;
  214. ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
  215. if (!ring_space)
  216. goto err_out_unmap_tx;
  217. np->rx_ring = ring_space;
  218. np->rx_ring_dma = ring_dma;
  219. /* Parse eeprom data */
  220. parse_eeprom (dev);
  221. /* Find PHY address */
  222. err = find_miiphy (dev);
  223. if (err)
  224. goto err_out_unmap_rx;
  225. /* Fiber device? */
  226. np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
  227. np->link_status = 0;
  228. /* Set media and reset PHY */
  229. if (np->phy_media) {
  230. /* default Auto-Negotiation for fiber deivices */
  231. if (np->an_enable == 2) {
  232. np->an_enable = 1;
  233. }
  234. mii_set_media_pcs (dev);
  235. } else {
  236. /* Auto-Negotiation is mandatory for 1000BASE-T,
  237. IEEE 802.3ab Annex 28D page 14 */
  238. if (np->speed == 1000)
  239. np->an_enable = 1;
  240. mii_set_media (dev);
  241. }
  242. err = register_netdev (dev);
  243. if (err)
  244. goto err_out_unmap_rx;
  245. card_idx++;
  246. printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
  247. dev->name, np->name, dev->dev_addr, irq);
  248. if (tx_coalesce > 1)
  249. printk(KERN_INFO "tx_coalesce:\t%d packets\n",
  250. tx_coalesce);
  251. if (np->coalesce)
  252. printk(KERN_INFO
  253. "rx_coalesce:\t%d packets\n"
  254. "rx_timeout: \t%d ns\n",
  255. np->rx_coalesce, np->rx_timeout*640);
  256. if (np->vlan)
  257. printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
  258. return 0;
  259. err_out_unmap_rx:
  260. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
  261. err_out_unmap_tx:
  262. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
  263. err_out_iounmap:
  264. #ifdef MEM_MAPPING
  265. pci_iounmap(pdev, np->ioaddr);
  266. #endif
  267. pci_iounmap(pdev, np->eeprom_addr);
  268. err_out_dev:
  269. free_netdev (dev);
  270. err_out_res:
  271. pci_release_regions (pdev);
  272. err_out_disable:
  273. pci_disable_device (pdev);
  274. return err;
  275. }
  276. static int
  277. find_miiphy (struct net_device *dev)
  278. {
  279. struct netdev_private *np = netdev_priv(dev);
  280. int i, phy_found = 0;
  281. np = netdev_priv(dev);
  282. np->phy_addr = 1;
  283. for (i = 31; i >= 0; i--) {
  284. int mii_status = mii_read (dev, i, 1);
  285. if (mii_status != 0xffff && mii_status != 0x0000) {
  286. np->phy_addr = i;
  287. phy_found++;
  288. }
  289. }
  290. if (!phy_found) {
  291. printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
  292. return -ENODEV;
  293. }
  294. return 0;
  295. }
  296. static int
  297. parse_eeprom (struct net_device *dev)
  298. {
  299. struct netdev_private *np = netdev_priv(dev);
  300. void __iomem *ioaddr = np->ioaddr;
  301. int i, j;
  302. u8 sromdata[256];
  303. u8 *psib;
  304. u32 crc;
  305. PSROM_t psrom = (PSROM_t) sromdata;
  306. int cid, next;
  307. for (i = 0; i < 128; i++)
  308. ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
  309. if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
  310. /* Check CRC */
  311. crc = ~ether_crc_le (256 - 4, sromdata);
  312. if (psrom->crc != cpu_to_le32(crc)) {
  313. printk (KERN_ERR "%s: EEPROM data CRC error.\n",
  314. dev->name);
  315. return -1;
  316. }
  317. }
  318. /* Set MAC address */
  319. for (i = 0; i < 6; i++)
  320. dev->dev_addr[i] = psrom->mac_addr[i];
  321. if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
  322. return 0;
  323. }
  324. /* Parse Software Information Block */
  325. i = 0x30;
  326. psib = (u8 *) sromdata;
  327. do {
  328. cid = psib[i++];
  329. next = psib[i++];
  330. if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
  331. printk (KERN_ERR "Cell data error\n");
  332. return -1;
  333. }
  334. switch (cid) {
  335. case 0: /* Format version */
  336. break;
  337. case 1: /* End of cell */
  338. return 0;
  339. case 2: /* Duplex Polarity */
  340. np->duplex_polarity = psib[i];
  341. dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
  342. break;
  343. case 3: /* Wake Polarity */
  344. np->wake_polarity = psib[i];
  345. break;
  346. case 9: /* Adapter description */
  347. j = (next - i > 255) ? 255 : next - i;
  348. memcpy (np->name, &(psib[i]), j);
  349. break;
  350. case 4:
  351. case 5:
  352. case 6:
  353. case 7:
  354. case 8: /* Reversed */
  355. break;
  356. default: /* Unknown cell */
  357. return -1;
  358. }
  359. i = next;
  360. } while (1);
  361. return 0;
  362. }
  363. static int
  364. rio_open (struct net_device *dev)
  365. {
  366. struct netdev_private *np = netdev_priv(dev);
  367. void __iomem *ioaddr = np->ioaddr;
  368. const int irq = np->pdev->irq;
  369. int i;
  370. u16 macctrl;
  371. i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
  372. if (i)
  373. return i;
  374. /* Reset all logic functions */
  375. dw16(ASICCtrl + 2,
  376. GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
  377. mdelay(10);
  378. /* DebugCtrl bit 4, 5, 9 must set */
  379. dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
  380. /* Jumbo frame */
  381. if (np->jumbo != 0)
  382. dw16(MaxFrameSize, MAX_JUMBO+14);
  383. alloc_list (dev);
  384. /* Get station address */
  385. for (i = 0; i < 6; i++)
  386. dw8(StationAddr0 + i, dev->dev_addr[i]);
  387. set_multicast (dev);
  388. if (np->coalesce) {
  389. dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
  390. }
  391. /* Set RIO to poll every N*320nsec. */
  392. dw8(RxDMAPollPeriod, 0x20);
  393. dw8(TxDMAPollPeriod, 0xff);
  394. dw8(RxDMABurstThresh, 0x30);
  395. dw8(RxDMAUrgentThresh, 0x30);
  396. dw32(RmonStatMask, 0x0007ffff);
  397. /* clear statistics */
  398. clear_stats (dev);
  399. /* VLAN supported */
  400. if (np->vlan) {
  401. /* priority field in RxDMAIntCtrl */
  402. dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
  403. /* VLANId */
  404. dw16(VLANId, np->vlan);
  405. /* Length/Type should be 0x8100 */
  406. dw32(VLANTag, 0x8100 << 16 | np->vlan);
  407. /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
  408. VLAN information tagged by TFC' VID, CFI fields. */
  409. dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
  410. }
  411. init_timer (&np->timer);
  412. np->timer.expires = jiffies + 1*HZ;
  413. np->timer.data = (unsigned long) dev;
  414. np->timer.function = rio_timer;
  415. add_timer (&np->timer);
  416. /* Start Tx/Rx */
  417. dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
  418. macctrl = 0;
  419. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  420. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  421. macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
  422. macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
  423. dw16(MACCtrl, macctrl);
  424. netif_start_queue (dev);
  425. dl2k_enable_int(np);
  426. return 0;
  427. }
  428. static void
  429. rio_timer (unsigned long data)
  430. {
  431. struct net_device *dev = (struct net_device *)data;
  432. struct netdev_private *np = netdev_priv(dev);
  433. unsigned int entry;
  434. int next_tick = 1*HZ;
  435. unsigned long flags;
  436. spin_lock_irqsave(&np->rx_lock, flags);
  437. /* Recover rx ring exhausted error */
  438. if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
  439. printk(KERN_INFO "Try to recover rx ring exhausted...\n");
  440. /* Re-allocate skbuffs to fill the descriptor ring */
  441. for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
  442. struct sk_buff *skb;
  443. entry = np->old_rx % RX_RING_SIZE;
  444. /* Dropped packets don't need to re-allocate */
  445. if (np->rx_skbuff[entry] == NULL) {
  446. skb = netdev_alloc_skb_ip_align(dev,
  447. np->rx_buf_sz);
  448. if (skb == NULL) {
  449. np->rx_ring[entry].fraginfo = 0;
  450. printk (KERN_INFO
  451. "%s: Still unable to re-allocate Rx skbuff.#%d\n",
  452. dev->name, entry);
  453. break;
  454. }
  455. np->rx_skbuff[entry] = skb;
  456. np->rx_ring[entry].fraginfo =
  457. cpu_to_le64 (pci_map_single
  458. (np->pdev, skb->data, np->rx_buf_sz,
  459. PCI_DMA_FROMDEVICE));
  460. }
  461. np->rx_ring[entry].fraginfo |=
  462. cpu_to_le64((u64)np->rx_buf_sz << 48);
  463. np->rx_ring[entry].status = 0;
  464. } /* end for */
  465. } /* end if */
  466. spin_unlock_irqrestore (&np->rx_lock, flags);
  467. np->timer.expires = jiffies + next_tick;
  468. add_timer(&np->timer);
  469. }
  470. static void
  471. rio_tx_timeout (struct net_device *dev)
  472. {
  473. struct netdev_private *np = netdev_priv(dev);
  474. void __iomem *ioaddr = np->ioaddr;
  475. printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
  476. dev->name, dr32(TxStatus));
  477. rio_free_tx(dev, 0);
  478. dev->if_port = 0;
  479. dev->trans_start = jiffies; /* prevent tx timeout */
  480. }
  481. /* allocate and initialize Tx and Rx descriptors */
  482. static void
  483. alloc_list (struct net_device *dev)
  484. {
  485. struct netdev_private *np = netdev_priv(dev);
  486. void __iomem *ioaddr = np->ioaddr;
  487. int i;
  488. np->cur_rx = np->cur_tx = 0;
  489. np->old_rx = np->old_tx = 0;
  490. np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
  491. /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
  492. for (i = 0; i < TX_RING_SIZE; i++) {
  493. np->tx_skbuff[i] = NULL;
  494. np->tx_ring[i].status = cpu_to_le64 (TFDDone);
  495. np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
  496. ((i+1)%TX_RING_SIZE) *
  497. sizeof (struct netdev_desc));
  498. }
  499. /* Initialize Rx descriptors */
  500. for (i = 0; i < RX_RING_SIZE; i++) {
  501. np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
  502. ((i + 1) % RX_RING_SIZE) *
  503. sizeof (struct netdev_desc));
  504. np->rx_ring[i].status = 0;
  505. np->rx_ring[i].fraginfo = 0;
  506. np->rx_skbuff[i] = NULL;
  507. }
  508. /* Allocate the rx buffers */
  509. for (i = 0; i < RX_RING_SIZE; i++) {
  510. /* Allocated fixed size of skbuff */
  511. struct sk_buff *skb;
  512. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  513. np->rx_skbuff[i] = skb;
  514. if (skb == NULL)
  515. break;
  516. /* Rubicon now supports 40 bits of addressing space. */
  517. np->rx_ring[i].fraginfo =
  518. cpu_to_le64 ( pci_map_single (
  519. np->pdev, skb->data, np->rx_buf_sz,
  520. PCI_DMA_FROMDEVICE));
  521. np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
  522. }
  523. /* Set RFDListPtr */
  524. dw32(RFDListPtr0, np->rx_ring_dma);
  525. dw32(RFDListPtr1, 0);
  526. }
  527. static netdev_tx_t
  528. start_xmit (struct sk_buff *skb, struct net_device *dev)
  529. {
  530. struct netdev_private *np = netdev_priv(dev);
  531. void __iomem *ioaddr = np->ioaddr;
  532. struct netdev_desc *txdesc;
  533. unsigned entry;
  534. u64 tfc_vlan_tag = 0;
  535. if (np->link_status == 0) { /* Link Down */
  536. dev_kfree_skb(skb);
  537. return NETDEV_TX_OK;
  538. }
  539. entry = np->cur_tx % TX_RING_SIZE;
  540. np->tx_skbuff[entry] = skb;
  541. txdesc = &np->tx_ring[entry];
  542. #if 0
  543. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  544. txdesc->status |=
  545. cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
  546. IPChecksumEnable);
  547. }
  548. #endif
  549. if (np->vlan) {
  550. tfc_vlan_tag = VLANTagInsert |
  551. ((u64)np->vlan << 32) |
  552. ((u64)skb->priority << 45);
  553. }
  554. txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
  555. skb->len,
  556. PCI_DMA_TODEVICE));
  557. txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
  558. /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
  559. * Work around: Always use 1 descriptor in 10Mbps mode */
  560. if (entry % np->tx_coalesce == 0 || np->speed == 10)
  561. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  562. WordAlignDisable |
  563. TxDMAIndicate |
  564. (1 << FragCountShift));
  565. else
  566. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  567. WordAlignDisable |
  568. (1 << FragCountShift));
  569. /* TxDMAPollNow */
  570. dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
  571. /* Schedule ISR */
  572. dw32(CountDown, 10000);
  573. np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
  574. if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  575. < TX_QUEUE_LEN - 1 && np->speed != 10) {
  576. /* do nothing */
  577. } else if (!netif_queue_stopped(dev)) {
  578. netif_stop_queue (dev);
  579. }
  580. /* The first TFDListPtr */
  581. if (!dr32(TFDListPtr0)) {
  582. dw32(TFDListPtr0, np->tx_ring_dma +
  583. entry * sizeof (struct netdev_desc));
  584. dw32(TFDListPtr1, 0);
  585. }
  586. return NETDEV_TX_OK;
  587. }
  588. static irqreturn_t
  589. rio_interrupt (int irq, void *dev_instance)
  590. {
  591. struct net_device *dev = dev_instance;
  592. struct netdev_private *np = netdev_priv(dev);
  593. void __iomem *ioaddr = np->ioaddr;
  594. unsigned int_status;
  595. int cnt = max_intrloop;
  596. int handled = 0;
  597. while (1) {
  598. int_status = dr16(IntStatus);
  599. dw16(IntStatus, int_status);
  600. int_status &= DEFAULT_INTR;
  601. if (int_status == 0 || --cnt < 0)
  602. break;
  603. handled = 1;
  604. /* Processing received packets */
  605. if (int_status & RxDMAComplete)
  606. receive_packet (dev);
  607. /* TxDMAComplete interrupt */
  608. if ((int_status & (TxDMAComplete|IntRequested))) {
  609. int tx_status;
  610. tx_status = dr32(TxStatus);
  611. if (tx_status & 0x01)
  612. tx_error (dev, tx_status);
  613. /* Free used tx skbuffs */
  614. rio_free_tx (dev, 1);
  615. }
  616. /* Handle uncommon events */
  617. if (int_status &
  618. (HostError | LinkEvent | UpdateStats))
  619. rio_error (dev, int_status);
  620. }
  621. if (np->cur_tx != np->old_tx)
  622. dw32(CountDown, 100);
  623. return IRQ_RETVAL(handled);
  624. }
  625. static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
  626. {
  627. return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
  628. }
  629. static void
  630. rio_free_tx (struct net_device *dev, int irq)
  631. {
  632. struct netdev_private *np = netdev_priv(dev);
  633. int entry = np->old_tx % TX_RING_SIZE;
  634. int tx_use = 0;
  635. unsigned long flag = 0;
  636. if (irq)
  637. spin_lock(&np->tx_lock);
  638. else
  639. spin_lock_irqsave(&np->tx_lock, flag);
  640. /* Free used tx skbuffs */
  641. while (entry != np->cur_tx) {
  642. struct sk_buff *skb;
  643. if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
  644. break;
  645. skb = np->tx_skbuff[entry];
  646. pci_unmap_single (np->pdev,
  647. desc_to_dma(&np->tx_ring[entry]),
  648. skb->len, PCI_DMA_TODEVICE);
  649. if (irq)
  650. dev_kfree_skb_irq (skb);
  651. else
  652. dev_kfree_skb (skb);
  653. np->tx_skbuff[entry] = NULL;
  654. entry = (entry + 1) % TX_RING_SIZE;
  655. tx_use++;
  656. }
  657. if (irq)
  658. spin_unlock(&np->tx_lock);
  659. else
  660. spin_unlock_irqrestore(&np->tx_lock, flag);
  661. np->old_tx = entry;
  662. /* If the ring is no longer full, clear tx_full and
  663. call netif_wake_queue() */
  664. if (netif_queue_stopped(dev) &&
  665. ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  666. < TX_QUEUE_LEN - 1 || np->speed == 10)) {
  667. netif_wake_queue (dev);
  668. }
  669. }
  670. static void
  671. tx_error (struct net_device *dev, int tx_status)
  672. {
  673. struct netdev_private *np = netdev_priv(dev);
  674. void __iomem *ioaddr = np->ioaddr;
  675. int frame_id;
  676. int i;
  677. frame_id = (tx_status & 0xffff0000);
  678. printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
  679. dev->name, tx_status, frame_id);
  680. np->stats.tx_errors++;
  681. /* Ttransmit Underrun */
  682. if (tx_status & 0x10) {
  683. np->stats.tx_fifo_errors++;
  684. dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
  685. /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
  686. dw16(ASICCtrl + 2,
  687. TxReset | DMAReset | FIFOReset | NetworkReset);
  688. /* Wait for ResetBusy bit clear */
  689. for (i = 50; i > 0; i--) {
  690. if (!(dr16(ASICCtrl + 2) & ResetBusy))
  691. break;
  692. mdelay (1);
  693. }
  694. rio_free_tx (dev, 1);
  695. /* Reset TFDListPtr */
  696. dw32(TFDListPtr0, np->tx_ring_dma +
  697. np->old_tx * sizeof (struct netdev_desc));
  698. dw32(TFDListPtr1, 0);
  699. /* Let TxStartThresh stay default value */
  700. }
  701. /* Late Collision */
  702. if (tx_status & 0x04) {
  703. np->stats.tx_fifo_errors++;
  704. /* TxReset and clear FIFO */
  705. dw16(ASICCtrl + 2, TxReset | FIFOReset);
  706. /* Wait reset done */
  707. for (i = 50; i > 0; i--) {
  708. if (!(dr16(ASICCtrl + 2) & ResetBusy))
  709. break;
  710. mdelay (1);
  711. }
  712. /* Let TxStartThresh stay default value */
  713. }
  714. /* Maximum Collisions */
  715. #ifdef ETHER_STATS
  716. if (tx_status & 0x08)
  717. np->stats.collisions16++;
  718. #else
  719. if (tx_status & 0x08)
  720. np->stats.collisions++;
  721. #endif
  722. /* Restart the Tx */
  723. dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
  724. }
  725. static int
  726. receive_packet (struct net_device *dev)
  727. {
  728. struct netdev_private *np = netdev_priv(dev);
  729. int entry = np->cur_rx % RX_RING_SIZE;
  730. int cnt = 30;
  731. /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
  732. while (1) {
  733. struct netdev_desc *desc = &np->rx_ring[entry];
  734. int pkt_len;
  735. u64 frame_status;
  736. if (!(desc->status & cpu_to_le64(RFDDone)) ||
  737. !(desc->status & cpu_to_le64(FrameStart)) ||
  738. !(desc->status & cpu_to_le64(FrameEnd)))
  739. break;
  740. /* Chip omits the CRC. */
  741. frame_status = le64_to_cpu(desc->status);
  742. pkt_len = frame_status & 0xffff;
  743. if (--cnt < 0)
  744. break;
  745. /* Update rx error statistics, drop packet. */
  746. if (frame_status & RFS_Errors) {
  747. np->stats.rx_errors++;
  748. if (frame_status & (RxRuntFrame | RxLengthError))
  749. np->stats.rx_length_errors++;
  750. if (frame_status & RxFCSError)
  751. np->stats.rx_crc_errors++;
  752. if (frame_status & RxAlignmentError && np->speed != 1000)
  753. np->stats.rx_frame_errors++;
  754. if (frame_status & RxFIFOOverrun)
  755. np->stats.rx_fifo_errors++;
  756. } else {
  757. struct sk_buff *skb;
  758. /* Small skbuffs for short packets */
  759. if (pkt_len > copy_thresh) {
  760. pci_unmap_single (np->pdev,
  761. desc_to_dma(desc),
  762. np->rx_buf_sz,
  763. PCI_DMA_FROMDEVICE);
  764. skb_put (skb = np->rx_skbuff[entry], pkt_len);
  765. np->rx_skbuff[entry] = NULL;
  766. } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
  767. pci_dma_sync_single_for_cpu(np->pdev,
  768. desc_to_dma(desc),
  769. np->rx_buf_sz,
  770. PCI_DMA_FROMDEVICE);
  771. skb_copy_to_linear_data (skb,
  772. np->rx_skbuff[entry]->data,
  773. pkt_len);
  774. skb_put (skb, pkt_len);
  775. pci_dma_sync_single_for_device(np->pdev,
  776. desc_to_dma(desc),
  777. np->rx_buf_sz,
  778. PCI_DMA_FROMDEVICE);
  779. }
  780. skb->protocol = eth_type_trans (skb, dev);
  781. #if 0
  782. /* Checksum done by hw, but csum value unavailable. */
  783. if (np->pdev->pci_rev_id >= 0x0c &&
  784. !(frame_status & (TCPError | UDPError | IPError))) {
  785. skb->ip_summed = CHECKSUM_UNNECESSARY;
  786. }
  787. #endif
  788. netif_rx (skb);
  789. }
  790. entry = (entry + 1) % RX_RING_SIZE;
  791. }
  792. spin_lock(&np->rx_lock);
  793. np->cur_rx = entry;
  794. /* Re-allocate skbuffs to fill the descriptor ring */
  795. entry = np->old_rx;
  796. while (entry != np->cur_rx) {
  797. struct sk_buff *skb;
  798. /* Dropped packets don't need to re-allocate */
  799. if (np->rx_skbuff[entry] == NULL) {
  800. skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
  801. if (skb == NULL) {
  802. np->rx_ring[entry].fraginfo = 0;
  803. printk (KERN_INFO
  804. "%s: receive_packet: "
  805. "Unable to re-allocate Rx skbuff.#%d\n",
  806. dev->name, entry);
  807. break;
  808. }
  809. np->rx_skbuff[entry] = skb;
  810. np->rx_ring[entry].fraginfo =
  811. cpu_to_le64 (pci_map_single
  812. (np->pdev, skb->data, np->rx_buf_sz,
  813. PCI_DMA_FROMDEVICE));
  814. }
  815. np->rx_ring[entry].fraginfo |=
  816. cpu_to_le64((u64)np->rx_buf_sz << 48);
  817. np->rx_ring[entry].status = 0;
  818. entry = (entry + 1) % RX_RING_SIZE;
  819. }
  820. np->old_rx = entry;
  821. spin_unlock(&np->rx_lock);
  822. return 0;
  823. }
  824. static void
  825. rio_error (struct net_device *dev, int int_status)
  826. {
  827. struct netdev_private *np = netdev_priv(dev);
  828. void __iomem *ioaddr = np->ioaddr;
  829. u16 macctrl;
  830. /* Link change event */
  831. if (int_status & LinkEvent) {
  832. if (mii_wait_link (dev, 10) == 0) {
  833. printk (KERN_INFO "%s: Link up\n", dev->name);
  834. if (np->phy_media)
  835. mii_get_media_pcs (dev);
  836. else
  837. mii_get_media (dev);
  838. if (np->speed == 1000)
  839. np->tx_coalesce = tx_coalesce;
  840. else
  841. np->tx_coalesce = 1;
  842. macctrl = 0;
  843. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  844. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  845. macctrl |= (np->tx_flow) ?
  846. TxFlowControlEnable : 0;
  847. macctrl |= (np->rx_flow) ?
  848. RxFlowControlEnable : 0;
  849. dw16(MACCtrl, macctrl);
  850. np->link_status = 1;
  851. netif_carrier_on(dev);
  852. } else {
  853. printk (KERN_INFO "%s: Link off\n", dev->name);
  854. np->link_status = 0;
  855. netif_carrier_off(dev);
  856. }
  857. }
  858. /* UpdateStats statistics registers */
  859. if (int_status & UpdateStats) {
  860. get_stats (dev);
  861. }
  862. /* PCI Error, a catastronphic error related to the bus interface
  863. occurs, set GlobalReset and HostReset to reset. */
  864. if (int_status & HostError) {
  865. printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
  866. dev->name, int_status);
  867. dw16(ASICCtrl + 2, GlobalReset | HostReset);
  868. mdelay (500);
  869. }
  870. }
  871. static struct net_device_stats *
  872. get_stats (struct net_device *dev)
  873. {
  874. struct netdev_private *np = netdev_priv(dev);
  875. void __iomem *ioaddr = np->ioaddr;
  876. #ifdef MEM_MAPPING
  877. int i;
  878. #endif
  879. unsigned int stat_reg;
  880. /* All statistics registers need to be acknowledged,
  881. else statistic overflow could cause problems */
  882. np->stats.rx_packets += dr32(FramesRcvOk);
  883. np->stats.tx_packets += dr32(FramesXmtOk);
  884. np->stats.rx_bytes += dr32(OctetRcvOk);
  885. np->stats.tx_bytes += dr32(OctetXmtOk);
  886. np->stats.multicast = dr32(McstFramesRcvdOk);
  887. np->stats.collisions += dr32(SingleColFrames)
  888. + dr32(MultiColFrames);
  889. /* detailed tx errors */
  890. stat_reg = dr16(FramesAbortXSColls);
  891. np->stats.tx_aborted_errors += stat_reg;
  892. np->stats.tx_errors += stat_reg;
  893. stat_reg = dr16(CarrierSenseErrors);
  894. np->stats.tx_carrier_errors += stat_reg;
  895. np->stats.tx_errors += stat_reg;
  896. /* Clear all other statistic register. */
  897. dr32(McstOctetXmtOk);
  898. dr16(BcstFramesXmtdOk);
  899. dr32(McstFramesXmtdOk);
  900. dr16(BcstFramesRcvdOk);
  901. dr16(MacControlFramesRcvd);
  902. dr16(FrameTooLongErrors);
  903. dr16(InRangeLengthErrors);
  904. dr16(FramesCheckSeqErrors);
  905. dr16(FramesLostRxErrors);
  906. dr32(McstOctetXmtOk);
  907. dr32(BcstOctetXmtOk);
  908. dr32(McstFramesXmtdOk);
  909. dr32(FramesWDeferredXmt);
  910. dr32(LateCollisions);
  911. dr16(BcstFramesXmtdOk);
  912. dr16(MacControlFramesXmtd);
  913. dr16(FramesWEXDeferal);
  914. #ifdef MEM_MAPPING
  915. for (i = 0x100; i <= 0x150; i += 4)
  916. dr32(i);
  917. #endif
  918. dr16(TxJumboFrames);
  919. dr16(RxJumboFrames);
  920. dr16(TCPCheckSumErrors);
  921. dr16(UDPCheckSumErrors);
  922. dr16(IPCheckSumErrors);
  923. return &np->stats;
  924. }
  925. static int
  926. clear_stats (struct net_device *dev)
  927. {
  928. struct netdev_private *np = netdev_priv(dev);
  929. void __iomem *ioaddr = np->ioaddr;
  930. #ifdef MEM_MAPPING
  931. int i;
  932. #endif
  933. /* All statistics registers need to be acknowledged,
  934. else statistic overflow could cause problems */
  935. dr32(FramesRcvOk);
  936. dr32(FramesXmtOk);
  937. dr32(OctetRcvOk);
  938. dr32(OctetXmtOk);
  939. dr32(McstFramesRcvdOk);
  940. dr32(SingleColFrames);
  941. dr32(MultiColFrames);
  942. dr32(LateCollisions);
  943. /* detailed rx errors */
  944. dr16(FrameTooLongErrors);
  945. dr16(InRangeLengthErrors);
  946. dr16(FramesCheckSeqErrors);
  947. dr16(FramesLostRxErrors);
  948. /* detailed tx errors */
  949. dr16(FramesAbortXSColls);
  950. dr16(CarrierSenseErrors);
  951. /* Clear all other statistic register. */
  952. dr32(McstOctetXmtOk);
  953. dr16(BcstFramesXmtdOk);
  954. dr32(McstFramesXmtdOk);
  955. dr16(BcstFramesRcvdOk);
  956. dr16(MacControlFramesRcvd);
  957. dr32(McstOctetXmtOk);
  958. dr32(BcstOctetXmtOk);
  959. dr32(McstFramesXmtdOk);
  960. dr32(FramesWDeferredXmt);
  961. dr16(BcstFramesXmtdOk);
  962. dr16(MacControlFramesXmtd);
  963. dr16(FramesWEXDeferal);
  964. #ifdef MEM_MAPPING
  965. for (i = 0x100; i <= 0x150; i += 4)
  966. dr32(i);
  967. #endif
  968. dr16(TxJumboFrames);
  969. dr16(RxJumboFrames);
  970. dr16(TCPCheckSumErrors);
  971. dr16(UDPCheckSumErrors);
  972. dr16(IPCheckSumErrors);
  973. return 0;
  974. }
  975. static int
  976. change_mtu (struct net_device *dev, int new_mtu)
  977. {
  978. struct netdev_private *np = netdev_priv(dev);
  979. int max = (np->jumbo) ? MAX_JUMBO : 1536;
  980. if ((new_mtu < 68) || (new_mtu > max)) {
  981. return -EINVAL;
  982. }
  983. dev->mtu = new_mtu;
  984. return 0;
  985. }
  986. static void
  987. set_multicast (struct net_device *dev)
  988. {
  989. struct netdev_private *np = netdev_priv(dev);
  990. void __iomem *ioaddr = np->ioaddr;
  991. u32 hash_table[2];
  992. u16 rx_mode = 0;
  993. hash_table[0] = hash_table[1] = 0;
  994. /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
  995. hash_table[1] |= 0x02000000;
  996. if (dev->flags & IFF_PROMISC) {
  997. /* Receive all frames promiscuously. */
  998. rx_mode = ReceiveAllFrames;
  999. } else if ((dev->flags & IFF_ALLMULTI) ||
  1000. (netdev_mc_count(dev) > multicast_filter_limit)) {
  1001. /* Receive broadcast and multicast frames */
  1002. rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
  1003. } else if (!netdev_mc_empty(dev)) {
  1004. struct netdev_hw_addr *ha;
  1005. /* Receive broadcast frames and multicast frames filtering
  1006. by Hashtable */
  1007. rx_mode =
  1008. ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
  1009. netdev_for_each_mc_addr(ha, dev) {
  1010. int bit, index = 0;
  1011. int crc = ether_crc_le(ETH_ALEN, ha->addr);
  1012. /* The inverted high significant 6 bits of CRC are
  1013. used as an index to hashtable */
  1014. for (bit = 0; bit < 6; bit++)
  1015. if (crc & (1 << (31 - bit)))
  1016. index |= (1 << bit);
  1017. hash_table[index / 32] |= (1 << (index % 32));
  1018. }
  1019. } else {
  1020. rx_mode = ReceiveBroadcast | ReceiveUnicast;
  1021. }
  1022. if (np->vlan) {
  1023. /* ReceiveVLANMatch field in ReceiveMode */
  1024. rx_mode |= ReceiveVLANMatch;
  1025. }
  1026. dw32(HashTable0, hash_table[0]);
  1027. dw32(HashTable1, hash_table[1]);
  1028. dw16(ReceiveMode, rx_mode);
  1029. }
  1030. static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1031. {
  1032. struct netdev_private *np = netdev_priv(dev);
  1033. strlcpy(info->driver, "dl2k", sizeof(info->driver));
  1034. strlcpy(info->version, DRV_VERSION, sizeof(info->version));
  1035. strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
  1036. }
  1037. static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1038. {
  1039. struct netdev_private *np = netdev_priv(dev);
  1040. if (np->phy_media) {
  1041. /* fiber device */
  1042. cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1043. cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
  1044. cmd->port = PORT_FIBRE;
  1045. cmd->transceiver = XCVR_INTERNAL;
  1046. } else {
  1047. /* copper device */
  1048. cmd->supported = SUPPORTED_10baseT_Half |
  1049. SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
  1050. | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
  1051. SUPPORTED_Autoneg | SUPPORTED_MII;
  1052. cmd->advertising = ADVERTISED_10baseT_Half |
  1053. ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
  1054. ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
  1055. ADVERTISED_Autoneg | ADVERTISED_MII;
  1056. cmd->port = PORT_MII;
  1057. cmd->transceiver = XCVR_INTERNAL;
  1058. }
  1059. if ( np->link_status ) {
  1060. ethtool_cmd_speed_set(cmd, np->speed);
  1061. cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1062. } else {
  1063. ethtool_cmd_speed_set(cmd, -1);
  1064. cmd->duplex = -1;
  1065. }
  1066. if ( np->an_enable)
  1067. cmd->autoneg = AUTONEG_ENABLE;
  1068. else
  1069. cmd->autoneg = AUTONEG_DISABLE;
  1070. cmd->phy_address = np->phy_addr;
  1071. return 0;
  1072. }
  1073. static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1074. {
  1075. struct netdev_private *np = netdev_priv(dev);
  1076. netif_carrier_off(dev);
  1077. if (cmd->autoneg == AUTONEG_ENABLE) {
  1078. if (np->an_enable)
  1079. return 0;
  1080. else {
  1081. np->an_enable = 1;
  1082. mii_set_media(dev);
  1083. return 0;
  1084. }
  1085. } else {
  1086. np->an_enable = 0;
  1087. if (np->speed == 1000) {
  1088. ethtool_cmd_speed_set(cmd, SPEED_100);
  1089. cmd->duplex = DUPLEX_FULL;
  1090. printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
  1091. }
  1092. switch (ethtool_cmd_speed(cmd)) {
  1093. case SPEED_10:
  1094. np->speed = 10;
  1095. np->full_duplex = (cmd->duplex == DUPLEX_FULL);
  1096. break;
  1097. case SPEED_100:
  1098. np->speed = 100;
  1099. np->full_duplex = (cmd->duplex == DUPLEX_FULL);
  1100. break;
  1101. case SPEED_1000: /* not supported */
  1102. default:
  1103. return -EINVAL;
  1104. }
  1105. mii_set_media(dev);
  1106. }
  1107. return 0;
  1108. }
  1109. static u32 rio_get_link(struct net_device *dev)
  1110. {
  1111. struct netdev_private *np = netdev_priv(dev);
  1112. return np->link_status;
  1113. }
  1114. static const struct ethtool_ops ethtool_ops = {
  1115. .get_drvinfo = rio_get_drvinfo,
  1116. .get_settings = rio_get_settings,
  1117. .set_settings = rio_set_settings,
  1118. .get_link = rio_get_link,
  1119. };
  1120. static int
  1121. rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
  1122. {
  1123. int phy_addr;
  1124. struct netdev_private *np = netdev_priv(dev);
  1125. struct mii_ioctl_data *miidata = if_mii(rq);
  1126. phy_addr = np->phy_addr;
  1127. switch (cmd) {
  1128. case SIOCGMIIPHY:
  1129. miidata->phy_id = phy_addr;
  1130. break;
  1131. case SIOCGMIIREG:
  1132. miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
  1133. break;
  1134. case SIOCSMIIREG:
  1135. if (!capable(CAP_NET_ADMIN))
  1136. return -EPERM;
  1137. mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
  1138. break;
  1139. default:
  1140. return -EOPNOTSUPP;
  1141. }
  1142. return 0;
  1143. }
  1144. #define EEP_READ 0x0200
  1145. #define EEP_BUSY 0x8000
  1146. /* Read the EEPROM word */
  1147. /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
  1148. static int read_eeprom(struct netdev_private *np, int eep_addr)
  1149. {
  1150. void __iomem *ioaddr = np->eeprom_addr;
  1151. int i = 1000;
  1152. dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
  1153. while (i-- > 0) {
  1154. if (!(dr16(EepromCtrl) & EEP_BUSY))
  1155. return dr16(EepromData);
  1156. }
  1157. return 0;
  1158. }
  1159. enum phy_ctrl_bits {
  1160. MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
  1161. MII_DUPLEX = 0x08,
  1162. };
  1163. #define mii_delay() dr8(PhyCtrl)
  1164. static void
  1165. mii_sendbit (struct net_device *dev, u32 data)
  1166. {
  1167. struct netdev_private *np = netdev_priv(dev);
  1168. void __iomem *ioaddr = np->ioaddr;
  1169. data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
  1170. dw8(PhyCtrl, data);
  1171. mii_delay ();
  1172. dw8(PhyCtrl, data | MII_CLK);
  1173. mii_delay ();
  1174. }
  1175. static int
  1176. mii_getbit (struct net_device *dev)
  1177. {
  1178. struct netdev_private *np = netdev_priv(dev);
  1179. void __iomem *ioaddr = np->ioaddr;
  1180. u8 data;
  1181. data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
  1182. dw8(PhyCtrl, data);
  1183. mii_delay ();
  1184. dw8(PhyCtrl, data | MII_CLK);
  1185. mii_delay ();
  1186. return (dr8(PhyCtrl) >> 1) & 1;
  1187. }
  1188. static void
  1189. mii_send_bits (struct net_device *dev, u32 data, int len)
  1190. {
  1191. int i;
  1192. for (i = len - 1; i >= 0; i--) {
  1193. mii_sendbit (dev, data & (1 << i));
  1194. }
  1195. }
  1196. static int
  1197. mii_read (struct net_device *dev, int phy_addr, int reg_num)
  1198. {
  1199. u32 cmd;
  1200. int i;
  1201. u32 retval = 0;
  1202. /* Preamble */
  1203. mii_send_bits (dev, 0xffffffff, 32);
  1204. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1205. /* ST,OP = 0110'b for read operation */
  1206. cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
  1207. mii_send_bits (dev, cmd, 14);
  1208. /* Turnaround */
  1209. if (mii_getbit (dev))
  1210. goto err_out;
  1211. /* Read data */
  1212. for (i = 0; i < 16; i++) {
  1213. retval |= mii_getbit (dev);
  1214. retval <<= 1;
  1215. }
  1216. /* End cycle */
  1217. mii_getbit (dev);
  1218. return (retval >> 1) & 0xffff;
  1219. err_out:
  1220. return 0;
  1221. }
  1222. static int
  1223. mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
  1224. {
  1225. u32 cmd;
  1226. /* Preamble */
  1227. mii_send_bits (dev, 0xffffffff, 32);
  1228. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1229. /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
  1230. cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
  1231. mii_send_bits (dev, cmd, 32);
  1232. /* End cycle */
  1233. mii_getbit (dev);
  1234. return 0;
  1235. }
  1236. static int
  1237. mii_wait_link (struct net_device *dev, int wait)
  1238. {
  1239. __u16 bmsr;
  1240. int phy_addr;
  1241. struct netdev_private *np;
  1242. np = netdev_priv(dev);
  1243. phy_addr = np->phy_addr;
  1244. do {
  1245. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1246. if (bmsr & BMSR_LSTATUS)
  1247. return 0;
  1248. mdelay (1);
  1249. } while (--wait > 0);
  1250. return -1;
  1251. }
  1252. static int
  1253. mii_get_media (struct net_device *dev)
  1254. {
  1255. __u16 negotiate;
  1256. __u16 bmsr;
  1257. __u16 mscr;
  1258. __u16 mssr;
  1259. int phy_addr;
  1260. struct netdev_private *np;
  1261. np = netdev_priv(dev);
  1262. phy_addr = np->phy_addr;
  1263. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1264. if (np->an_enable) {
  1265. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1266. /* Auto-Negotiation not completed */
  1267. return -1;
  1268. }
  1269. negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1270. mii_read (dev, phy_addr, MII_LPA);
  1271. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1272. mssr = mii_read (dev, phy_addr, MII_STAT1000);
  1273. if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
  1274. np->speed = 1000;
  1275. np->full_duplex = 1;
  1276. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1277. } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
  1278. np->speed = 1000;
  1279. np->full_duplex = 0;
  1280. printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
  1281. } else if (negotiate & ADVERTISE_100FULL) {
  1282. np->speed = 100;
  1283. np->full_duplex = 1;
  1284. printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
  1285. } else if (negotiate & ADVERTISE_100HALF) {
  1286. np->speed = 100;
  1287. np->full_duplex = 0;
  1288. printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
  1289. } else if (negotiate & ADVERTISE_10FULL) {
  1290. np->speed = 10;
  1291. np->full_duplex = 1;
  1292. printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
  1293. } else if (negotiate & ADVERTISE_10HALF) {
  1294. np->speed = 10;
  1295. np->full_duplex = 0;
  1296. printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
  1297. }
  1298. if (negotiate & ADVERTISE_PAUSE_CAP) {
  1299. np->tx_flow &= 1;
  1300. np->rx_flow &= 1;
  1301. } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
  1302. np->tx_flow = 0;
  1303. np->rx_flow &= 1;
  1304. }
  1305. /* else tx_flow, rx_flow = user select */
  1306. } else {
  1307. __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1308. switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
  1309. case BMCR_SPEED1000:
  1310. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1311. break;
  1312. case BMCR_SPEED100:
  1313. printk (KERN_INFO "Operating at 100 Mbps, ");
  1314. break;
  1315. case 0:
  1316. printk (KERN_INFO "Operating at 10 Mbps, ");
  1317. }
  1318. if (bmcr & BMCR_FULLDPLX) {
  1319. printk (KERN_CONT "Full duplex\n");
  1320. } else {
  1321. printk (KERN_CONT "Half duplex\n");
  1322. }
  1323. }
  1324. if (np->tx_flow)
  1325. printk(KERN_INFO "Enable Tx Flow Control\n");
  1326. else
  1327. printk(KERN_INFO "Disable Tx Flow Control\n");
  1328. if (np->rx_flow)
  1329. printk(KERN_INFO "Enable Rx Flow Control\n");
  1330. else
  1331. printk(KERN_INFO "Disable Rx Flow Control\n");
  1332. return 0;
  1333. }
  1334. static int
  1335. mii_set_media (struct net_device *dev)
  1336. {
  1337. __u16 pscr;
  1338. __u16 bmcr;
  1339. __u16 bmsr;
  1340. __u16 anar;
  1341. int phy_addr;
  1342. struct netdev_private *np;
  1343. np = netdev_priv(dev);
  1344. phy_addr = np->phy_addr;
  1345. /* Does user set speed? */
  1346. if (np->an_enable) {
  1347. /* Advertise capabilities */
  1348. bmsr = mii_read (dev, phy_addr, MII_BMSR);
  1349. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1350. ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
  1351. ADVERTISE_100HALF | ADVERTISE_10HALF |
  1352. ADVERTISE_100BASE4);
  1353. if (bmsr & BMSR_100FULL)
  1354. anar |= ADVERTISE_100FULL;
  1355. if (bmsr & BMSR_100HALF)
  1356. anar |= ADVERTISE_100HALF;
  1357. if (bmsr & BMSR_100BASE4)
  1358. anar |= ADVERTISE_100BASE4;
  1359. if (bmsr & BMSR_10FULL)
  1360. anar |= ADVERTISE_10FULL;
  1361. if (bmsr & BMSR_10HALF)
  1362. anar |= ADVERTISE_10HALF;
  1363. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  1364. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1365. /* Enable Auto crossover */
  1366. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1367. pscr |= 3 << 5; /* 11'b */
  1368. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1369. /* Soft reset PHY */
  1370. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1371. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1372. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1373. mdelay(1);
  1374. } else {
  1375. /* Force speed setting */
  1376. /* 1) Disable Auto crossover */
  1377. pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
  1378. pscr &= ~(3 << 5);
  1379. mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
  1380. /* 2) PHY Reset */
  1381. bmcr = mii_read (dev, phy_addr, MII_BMCR);
  1382. bmcr |= BMCR_RESET;
  1383. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1384. /* 3) Power Down */
  1385. bmcr = 0x1940; /* must be 0x1940 */
  1386. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1387. mdelay (100); /* wait a certain time */
  1388. /* 4) Advertise nothing */
  1389. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1390. /* 5) Set media and Power Up */
  1391. bmcr = BMCR_PDOWN;
  1392. if (np->speed == 100) {
  1393. bmcr |= BMCR_SPEED100;
  1394. printk (KERN_INFO "Manual 100 Mbps, ");
  1395. } else if (np->speed == 10) {
  1396. printk (KERN_INFO "Manual 10 Mbps, ");
  1397. }
  1398. if (np->full_duplex) {
  1399. bmcr |= BMCR_FULLDPLX;
  1400. printk (KERN_CONT "Full duplex\n");
  1401. } else {
  1402. printk (KERN_CONT "Half duplex\n");
  1403. }
  1404. #if 0
  1405. /* Set 1000BaseT Master/Slave setting */
  1406. mscr = mii_read (dev, phy_addr, MII_CTRL1000);
  1407. mscr |= MII_MSCR_CFG_ENABLE;
  1408. mscr &= ~MII_MSCR_CFG_VALUE = 0;
  1409. #endif
  1410. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1411. mdelay(10);
  1412. }
  1413. return 0;
  1414. }
  1415. static int
  1416. mii_get_media_pcs (struct net_device *dev)
  1417. {
  1418. __u16 negotiate;
  1419. __u16 bmsr;
  1420. int phy_addr;
  1421. struct netdev_private *np;
  1422. np = netdev_priv(dev);
  1423. phy_addr = np->phy_addr;
  1424. bmsr = mii_read (dev, phy_addr, PCS_BMSR);
  1425. if (np->an_enable) {
  1426. if (!(bmsr & BMSR_ANEGCOMPLETE)) {
  1427. /* Auto-Negotiation not completed */
  1428. return -1;
  1429. }
  1430. negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
  1431. mii_read (dev, phy_addr, PCS_ANLPAR);
  1432. np->speed = 1000;
  1433. if (negotiate & PCS_ANAR_FULL_DUPLEX) {
  1434. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1435. np->full_duplex = 1;
  1436. } else {
  1437. printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
  1438. np->full_duplex = 0;
  1439. }
  1440. if (negotiate & PCS_ANAR_PAUSE) {
  1441. np->tx_flow &= 1;
  1442. np->rx_flow &= 1;
  1443. } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
  1444. np->tx_flow = 0;
  1445. np->rx_flow &= 1;
  1446. }
  1447. /* else tx_flow, rx_flow = user select */
  1448. } else {
  1449. __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
  1450. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1451. if (bmcr & BMCR_FULLDPLX) {
  1452. printk (KERN_CONT "Full duplex\n");
  1453. } else {
  1454. printk (KERN_CONT "Half duplex\n");
  1455. }
  1456. }
  1457. if (np->tx_flow)
  1458. printk(KERN_INFO "Enable Tx Flow Control\n");
  1459. else
  1460. printk(KERN_INFO "Disable Tx Flow Control\n");
  1461. if (np->rx_flow)
  1462. printk(KERN_INFO "Enable Rx Flow Control\n");
  1463. else
  1464. printk(KERN_INFO "Disable Rx Flow Control\n");
  1465. return 0;
  1466. }
  1467. static int
  1468. mii_set_media_pcs (struct net_device *dev)
  1469. {
  1470. __u16 bmcr;
  1471. __u16 esr;
  1472. __u16 anar;
  1473. int phy_addr;
  1474. struct netdev_private *np;
  1475. np = netdev_priv(dev);
  1476. phy_addr = np->phy_addr;
  1477. /* Auto-Negotiation? */
  1478. if (np->an_enable) {
  1479. /* Advertise capabilities */
  1480. esr = mii_read (dev, phy_addr, PCS_ESR);
  1481. anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
  1482. ~PCS_ANAR_HALF_DUPLEX &
  1483. ~PCS_ANAR_FULL_DUPLEX;
  1484. if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
  1485. anar |= PCS_ANAR_HALF_DUPLEX;
  1486. if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
  1487. anar |= PCS_ANAR_FULL_DUPLEX;
  1488. anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
  1489. mii_write (dev, phy_addr, MII_ADVERTISE, anar);
  1490. /* Soft reset PHY */
  1491. mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
  1492. bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
  1493. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1494. mdelay(1);
  1495. } else {
  1496. /* Force speed setting */
  1497. /* PHY Reset */
  1498. bmcr = BMCR_RESET;
  1499. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1500. mdelay(10);
  1501. if (np->full_duplex) {
  1502. bmcr = BMCR_FULLDPLX;
  1503. printk (KERN_INFO "Manual full duplex\n");
  1504. } else {
  1505. bmcr = 0;
  1506. printk (KERN_INFO "Manual half duplex\n");
  1507. }
  1508. mii_write (dev, phy_addr, MII_BMCR, bmcr);
  1509. mdelay(10);
  1510. /* Advertise nothing */
  1511. mii_write (dev, phy_addr, MII_ADVERTISE, 0);
  1512. }
  1513. return 0;
  1514. }
  1515. static int
  1516. rio_close (struct net_device *dev)
  1517. {
  1518. struct netdev_private *np = netdev_priv(dev);
  1519. void __iomem *ioaddr = np->ioaddr;
  1520. struct pci_dev *pdev = np->pdev;
  1521. struct sk_buff *skb;
  1522. int i;
  1523. netif_stop_queue (dev);
  1524. /* Disable interrupts */
  1525. dw16(IntEnable, 0);
  1526. /* Stop Tx and Rx logics */
  1527. dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
  1528. free_irq(pdev->irq, dev);
  1529. del_timer_sync (&np->timer);
  1530. /* Free all the skbuffs in the queue. */
  1531. for (i = 0; i < RX_RING_SIZE; i++) {
  1532. skb = np->rx_skbuff[i];
  1533. if (skb) {
  1534. pci_unmap_single(pdev, desc_to_dma(&np->rx_ring[i]),
  1535. skb->len, PCI_DMA_FROMDEVICE);
  1536. dev_kfree_skb (skb);
  1537. np->rx_skbuff[i] = NULL;
  1538. }
  1539. np->rx_ring[i].status = 0;
  1540. np->rx_ring[i].fraginfo = 0;
  1541. }
  1542. for (i = 0; i < TX_RING_SIZE; i++) {
  1543. skb = np->tx_skbuff[i];
  1544. if (skb) {
  1545. pci_unmap_single(pdev, desc_to_dma(&np->tx_ring[i]),
  1546. skb->len, PCI_DMA_TODEVICE);
  1547. dev_kfree_skb (skb);
  1548. np->tx_skbuff[i] = NULL;
  1549. }
  1550. }
  1551. return 0;
  1552. }
  1553. static void
  1554. rio_remove1 (struct pci_dev *pdev)
  1555. {
  1556. struct net_device *dev = pci_get_drvdata (pdev);
  1557. if (dev) {
  1558. struct netdev_private *np = netdev_priv(dev);
  1559. unregister_netdev (dev);
  1560. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
  1561. np->rx_ring_dma);
  1562. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
  1563. np->tx_ring_dma);
  1564. #ifdef MEM_MAPPING
  1565. pci_iounmap(pdev, np->ioaddr);
  1566. #endif
  1567. pci_iounmap(pdev, np->eeprom_addr);
  1568. free_netdev (dev);
  1569. pci_release_regions (pdev);
  1570. pci_disable_device (pdev);
  1571. }
  1572. pci_set_drvdata (pdev, NULL);
  1573. }
  1574. static struct pci_driver rio_driver = {
  1575. .name = "dl2k",
  1576. .id_table = rio_pci_tbl,
  1577. .probe = rio_probe1,
  1578. .remove = rio_remove1,
  1579. };
  1580. module_pci_driver(rio_driver);
  1581. /*
  1582. Compile command:
  1583. gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
  1584. Read Documentation/networking/dl2k.txt for details.
  1585. */