qeth_core_main.c 130 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394239523962397239823992400240124022403240424052406240724082409241024112412241324142415241624172418241924202421242224232424242524262427242824292430243124322433243424352436243724382439244024412442244324442445244624472448244924502451245224532454245524562457245824592460246124622463246424652466246724682469247024712472247324742475247624772478247924802481248224832484248524862487248824892490249124922493249424952496249724982499250025012502250325042505250625072508250925102511251225132514251525162517251825192520252125222523252425252526252725282529253025312532253325342535253625372538253925402541254225432544254525462547254825492550255125522553255425552556255725582559256025612562256325642565256625672568256925702571257225732574257525762577257825792580258125822583258425852586258725882589259025912592259325942595259625972598259926002601260226032604260526062607260826092610261126122613261426152616261726182619262026212622262326242625262626272628262926302631263226332634263526362637263826392640264126422643264426452646264726482649265026512652265326542655265626572658265926602661266226632664266526662667266826692670267126722673267426752676267726782679268026812682268326842685268626872688268926902691269226932694269526962697269826992700270127022703270427052706270727082709271027112712271327142715271627172718271927202721272227232724272527262727272827292730273127322733273427352736273727382739274027412742274327442745274627472748274927502751275227532754275527562757275827592760276127622763276427652766276727682769277027712772277327742775277627772778277927802781278227832784278527862787278827892790279127922793279427952796279727982799280028012802280328042805280628072808280928102811281228132814281528162817281828192820282128222823282428252826282728282829283028312832283328342835283628372838283928402841284228432844284528462847284828492850285128522853285428552856285728582859286028612862286328642865286628672868286928702871287228732874287528762877287828792880288128822883288428852886288728882889289028912892289328942895289628972898289929002901290229032904290529062907290829092910291129122913291429152916291729182919292029212922292329242925292629272928292929302931293229332934293529362937293829392940294129422943294429452946294729482949295029512952295329542955295629572958295929602961296229632964296529662967296829692970297129722973297429752976297729782979298029812982298329842985298629872988298929902991299229932994299529962997299829993000300130023003300430053006300730083009301030113012301330143015301630173018301930203021302230233024302530263027302830293030303130323033303430353036303730383039304030413042304330443045304630473048304930503051305230533054305530563057305830593060306130623063306430653066306730683069307030713072307330743075307630773078307930803081308230833084308530863087308830893090309130923093309430953096309730983099310031013102310331043105310631073108310931103111311231133114311531163117311831193120312131223123312431253126312731283129313031313132313331343135313631373138313931403141314231433144314531463147314831493150315131523153315431553156315731583159316031613162316331643165316631673168316931703171317231733174317531763177317831793180318131823183318431853186318731883189319031913192319331943195319631973198319932003201320232033204320532063207320832093210321132123213321432153216321732183219322032213222322332243225322632273228322932303231323232333234323532363237323832393240324132423243324432453246324732483249325032513252325332543255325632573258325932603261326232633264326532663267326832693270327132723273327432753276327732783279328032813282328332843285328632873288328932903291329232933294329532963297329832993300330133023303330433053306330733083309331033113312331333143315331633173318331933203321332233233324332533263327332833293330333133323333333433353336333733383339334033413342334333443345334633473348334933503351335233533354335533563357335833593360336133623363336433653366336733683369337033713372337333743375337633773378337933803381338233833384338533863387338833893390339133923393339433953396339733983399340034013402340334043405340634073408340934103411341234133414341534163417341834193420342134223423342434253426342734283429343034313432343334343435343634373438343934403441344234433444344534463447344834493450345134523453345434553456345734583459346034613462346334643465346634673468346934703471347234733474347534763477347834793480348134823483348434853486348734883489349034913492349334943495349634973498349935003501350235033504350535063507350835093510351135123513351435153516351735183519352035213522352335243525352635273528352935303531353235333534353535363537353835393540354135423543354435453546354735483549355035513552355335543555355635573558355935603561356235633564356535663567356835693570357135723573357435753576357735783579358035813582358335843585358635873588358935903591359235933594359535963597359835993600360136023603360436053606360736083609361036113612361336143615361636173618361936203621362236233624362536263627362836293630363136323633363436353636363736383639364036413642364336443645364636473648364936503651365236533654365536563657365836593660366136623663366436653666366736683669367036713672367336743675367636773678367936803681368236833684368536863687368836893690369136923693369436953696369736983699370037013702370337043705370637073708370937103711371237133714371537163717371837193720372137223723372437253726372737283729373037313732373337343735373637373738373937403741374237433744374537463747374837493750375137523753375437553756375737583759376037613762376337643765376637673768376937703771377237733774377537763777377837793780378137823783378437853786378737883789379037913792379337943795379637973798379938003801380238033804380538063807380838093810381138123813381438153816381738183819382038213822382338243825382638273828382938303831383238333834383538363837383838393840384138423843384438453846384738483849385038513852385338543855385638573858385938603861386238633864386538663867386838693870387138723873387438753876387738783879388038813882388338843885388638873888388938903891389238933894389538963897389838993900390139023903390439053906390739083909391039113912391339143915391639173918391939203921392239233924392539263927392839293930393139323933393439353936393739383939394039413942394339443945394639473948394939503951395239533954395539563957395839593960396139623963396439653966396739683969397039713972397339743975397639773978397939803981398239833984398539863987398839893990399139923993399439953996399739983999400040014002400340044005400640074008400940104011401240134014401540164017401840194020402140224023402440254026402740284029403040314032403340344035403640374038403940404041404240434044404540464047404840494050405140524053405440554056405740584059406040614062406340644065406640674068406940704071407240734074407540764077407840794080408140824083408440854086408740884089409040914092409340944095409640974098409941004101410241034104410541064107410841094110411141124113411441154116411741184119412041214122412341244125412641274128412941304131413241334134413541364137413841394140414141424143414441454146414741484149415041514152415341544155415641574158415941604161416241634164416541664167416841694170417141724173417441754176417741784179418041814182418341844185418641874188418941904191419241934194419541964197419841994200420142024203420442054206420742084209421042114212421342144215421642174218421942204221422242234224422542264227422842294230423142324233423442354236423742384239424042414242424342444245424642474248424942504251425242534254425542564257425842594260426142624263426442654266426742684269427042714272427342744275427642774278427942804281428242834284428542864287428842894290429142924293429442954296429742984299430043014302430343044305430643074308430943104311431243134314431543164317431843194320432143224323432443254326432743284329433043314332433343344335433643374338433943404341434243434344434543464347434843494350435143524353435443554356435743584359436043614362436343644365436643674368436943704371437243734374437543764377437843794380438143824383438443854386438743884389439043914392439343944395439643974398439944004401440244034404440544064407440844094410441144124413441444154416441744184419442044214422442344244425442644274428442944304431443244334434443544364437443844394440444144424443444444454446444744484449445044514452445344544455445644574458445944604461446244634464446544664467446844694470447144724473447444754476447744784479448044814482448344844485448644874488448944904491449244934494449544964497449844994500450145024503450445054506450745084509451045114512451345144515451645174518451945204521452245234524452545264527452845294530453145324533453445354536453745384539454045414542454345444545454645474548454945504551455245534554455545564557455845594560456145624563456445654566456745684569457045714572457345744575457645774578457945804581458245834584458545864587458845894590459145924593459445954596459745984599460046014602460346044605460646074608460946104611461246134614461546164617461846194620462146224623462446254626462746284629463046314632463346344635463646374638463946404641464246434644464546464647464846494650465146524653465446554656465746584659466046614662466346644665466646674668466946704671467246734674467546764677467846794680468146824683468446854686468746884689469046914692469346944695469646974698469947004701470247034704470547064707470847094710471147124713471447154716471747184719472047214722472347244725472647274728472947304731473247334734473547364737473847394740474147424743474447454746474747484749
  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <asm/ebcdic.h>
  23. #include <asm/io.h>
  24. #include "qeth_core.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_MSG] = {"qeth_msg",
  31. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  32. [QETH_DBF_CTRL] = {"qeth_control",
  33. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  34. };
  35. EXPORT_SYMBOL_GPL(qeth_dbf);
  36. struct qeth_card_list_struct qeth_core_card_list;
  37. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  38. struct kmem_cache *qeth_core_header_cache;
  39. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  40. static struct device *qeth_core_root_dev;
  41. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  42. static struct lock_class_key qdio_out_skb_queue_key;
  43. static void qeth_send_control_data_cb(struct qeth_channel *,
  44. struct qeth_cmd_buffer *);
  45. static int qeth_issue_next_read(struct qeth_card *);
  46. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  47. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  48. static void qeth_free_buffer_pool(struct qeth_card *);
  49. static int qeth_qdio_establish(struct qeth_card *);
  50. static inline const char *qeth_get_cardname(struct qeth_card *card)
  51. {
  52. if (card->info.guestlan) {
  53. switch (card->info.type) {
  54. case QETH_CARD_TYPE_OSD:
  55. return " Guest LAN QDIO";
  56. case QETH_CARD_TYPE_IQD:
  57. return " Guest LAN Hiper";
  58. case QETH_CARD_TYPE_OSM:
  59. return " Guest LAN QDIO - OSM";
  60. case QETH_CARD_TYPE_OSX:
  61. return " Guest LAN QDIO - OSX";
  62. default:
  63. return " unknown";
  64. }
  65. } else {
  66. switch (card->info.type) {
  67. case QETH_CARD_TYPE_OSD:
  68. return " OSD Express";
  69. case QETH_CARD_TYPE_IQD:
  70. return " HiperSockets";
  71. case QETH_CARD_TYPE_OSN:
  72. return " OSN QDIO";
  73. case QETH_CARD_TYPE_OSM:
  74. return " OSM QDIO";
  75. case QETH_CARD_TYPE_OSX:
  76. return " OSX QDIO";
  77. default:
  78. return " unknown";
  79. }
  80. }
  81. return " n/a";
  82. }
  83. /* max length to be returned: 14 */
  84. const char *qeth_get_cardname_short(struct qeth_card *card)
  85. {
  86. if (card->info.guestlan) {
  87. switch (card->info.type) {
  88. case QETH_CARD_TYPE_OSD:
  89. return "GuestLAN QDIO";
  90. case QETH_CARD_TYPE_IQD:
  91. return "GuestLAN Hiper";
  92. case QETH_CARD_TYPE_OSM:
  93. return "GuestLAN OSM";
  94. case QETH_CARD_TYPE_OSX:
  95. return "GuestLAN OSX";
  96. default:
  97. return "unknown";
  98. }
  99. } else {
  100. switch (card->info.type) {
  101. case QETH_CARD_TYPE_OSD:
  102. switch (card->info.link_type) {
  103. case QETH_LINK_TYPE_FAST_ETH:
  104. return "OSD_100";
  105. case QETH_LINK_TYPE_HSTR:
  106. return "HSTR";
  107. case QETH_LINK_TYPE_GBIT_ETH:
  108. return "OSD_1000";
  109. case QETH_LINK_TYPE_10GBIT_ETH:
  110. return "OSD_10GIG";
  111. case QETH_LINK_TYPE_LANE_ETH100:
  112. return "OSD_FE_LANE";
  113. case QETH_LINK_TYPE_LANE_TR:
  114. return "OSD_TR_LANE";
  115. case QETH_LINK_TYPE_LANE_ETH1000:
  116. return "OSD_GbE_LANE";
  117. case QETH_LINK_TYPE_LANE:
  118. return "OSD_ATM_LANE";
  119. default:
  120. return "OSD_Express";
  121. }
  122. case QETH_CARD_TYPE_IQD:
  123. return "HiperSockets";
  124. case QETH_CARD_TYPE_OSN:
  125. return "OSN";
  126. case QETH_CARD_TYPE_OSM:
  127. return "OSM_1000";
  128. case QETH_CARD_TYPE_OSX:
  129. return "OSX_10GIG";
  130. default:
  131. return "unknown";
  132. }
  133. }
  134. return "n/a";
  135. }
  136. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  137. int clear_start_mask)
  138. {
  139. unsigned long flags;
  140. spin_lock_irqsave(&card->thread_mask_lock, flags);
  141. card->thread_allowed_mask = threads;
  142. if (clear_start_mask)
  143. card->thread_start_mask &= threads;
  144. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  145. wake_up(&card->wait_q);
  146. }
  147. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  148. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  149. {
  150. unsigned long flags;
  151. int rc = 0;
  152. spin_lock_irqsave(&card->thread_mask_lock, flags);
  153. rc = (card->thread_running_mask & threads);
  154. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  155. return rc;
  156. }
  157. EXPORT_SYMBOL_GPL(qeth_threads_running);
  158. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  159. {
  160. return wait_event_interruptible(card->wait_q,
  161. qeth_threads_running(card, threads) == 0);
  162. }
  163. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  164. void qeth_clear_working_pool_list(struct qeth_card *card)
  165. {
  166. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  167. QETH_CARD_TEXT(card, 5, "clwrklst");
  168. list_for_each_entry_safe(pool_entry, tmp,
  169. &card->qdio.in_buf_pool.entry_list, list){
  170. list_del(&pool_entry->list);
  171. }
  172. }
  173. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  174. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  175. {
  176. struct qeth_buffer_pool_entry *pool_entry;
  177. void *ptr;
  178. int i, j;
  179. QETH_CARD_TEXT(card, 5, "alocpool");
  180. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  181. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  182. if (!pool_entry) {
  183. qeth_free_buffer_pool(card);
  184. return -ENOMEM;
  185. }
  186. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  187. ptr = (void *) __get_free_page(GFP_KERNEL);
  188. if (!ptr) {
  189. while (j > 0)
  190. free_page((unsigned long)
  191. pool_entry->elements[--j]);
  192. kfree(pool_entry);
  193. qeth_free_buffer_pool(card);
  194. return -ENOMEM;
  195. }
  196. pool_entry->elements[j] = ptr;
  197. }
  198. list_add(&pool_entry->init_list,
  199. &card->qdio.init_pool.entry_list);
  200. }
  201. return 0;
  202. }
  203. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  204. {
  205. QETH_CARD_TEXT(card, 2, "realcbp");
  206. if ((card->state != CARD_STATE_DOWN) &&
  207. (card->state != CARD_STATE_RECOVER))
  208. return -EPERM;
  209. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  210. qeth_clear_working_pool_list(card);
  211. qeth_free_buffer_pool(card);
  212. card->qdio.in_buf_pool.buf_count = bufcnt;
  213. card->qdio.init_pool.buf_count = bufcnt;
  214. return qeth_alloc_buffer_pool(card);
  215. }
  216. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  217. static int qeth_issue_next_read(struct qeth_card *card)
  218. {
  219. int rc;
  220. struct qeth_cmd_buffer *iob;
  221. QETH_CARD_TEXT(card, 5, "issnxrd");
  222. if (card->read.state != CH_STATE_UP)
  223. return -EIO;
  224. iob = qeth_get_buffer(&card->read);
  225. if (!iob) {
  226. dev_warn(&card->gdev->dev, "The qeth device driver "
  227. "failed to recover an error on the device\n");
  228. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  229. "available\n", dev_name(&card->gdev->dev));
  230. return -ENOMEM;
  231. }
  232. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  233. QETH_CARD_TEXT(card, 6, "noirqpnd");
  234. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  235. (addr_t) iob, 0, 0);
  236. if (rc) {
  237. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  238. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  239. atomic_set(&card->read.irq_pending, 0);
  240. card->read_or_write_problem = 1;
  241. qeth_schedule_recovery(card);
  242. wake_up(&card->wait_q);
  243. }
  244. return rc;
  245. }
  246. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  247. {
  248. struct qeth_reply *reply;
  249. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  250. if (reply) {
  251. atomic_set(&reply->refcnt, 1);
  252. atomic_set(&reply->received, 0);
  253. reply->card = card;
  254. };
  255. return reply;
  256. }
  257. static void qeth_get_reply(struct qeth_reply *reply)
  258. {
  259. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  260. atomic_inc(&reply->refcnt);
  261. }
  262. static void qeth_put_reply(struct qeth_reply *reply)
  263. {
  264. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  265. if (atomic_dec_and_test(&reply->refcnt))
  266. kfree(reply);
  267. }
  268. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  269. struct qeth_card *card)
  270. {
  271. char *ipa_name;
  272. int com = cmd->hdr.command;
  273. ipa_name = qeth_get_ipa_cmd_name(com);
  274. if (rc)
  275. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  276. "x%X \"%s\"\n",
  277. ipa_name, com, dev_name(&card->gdev->dev),
  278. QETH_CARD_IFNAME(card), rc,
  279. qeth_get_ipa_msg(rc));
  280. else
  281. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  282. ipa_name, com, dev_name(&card->gdev->dev),
  283. QETH_CARD_IFNAME(card));
  284. }
  285. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  286. struct qeth_cmd_buffer *iob)
  287. {
  288. struct qeth_ipa_cmd *cmd = NULL;
  289. QETH_CARD_TEXT(card, 5, "chkipad");
  290. if (IS_IPA(iob->data)) {
  291. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  292. if (IS_IPA_REPLY(cmd)) {
  293. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  294. cmd->hdr.command != IPA_CMD_DELCCID &&
  295. cmd->hdr.command != IPA_CMD_MODCCID &&
  296. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  297. qeth_issue_ipa_msg(cmd,
  298. cmd->hdr.return_code, card);
  299. return cmd;
  300. } else {
  301. switch (cmd->hdr.command) {
  302. case IPA_CMD_STOPLAN:
  303. dev_warn(&card->gdev->dev,
  304. "The link for interface %s on CHPID"
  305. " 0x%X failed\n",
  306. QETH_CARD_IFNAME(card),
  307. card->info.chpid);
  308. card->lan_online = 0;
  309. if (card->dev && netif_carrier_ok(card->dev))
  310. netif_carrier_off(card->dev);
  311. return NULL;
  312. case IPA_CMD_STARTLAN:
  313. dev_info(&card->gdev->dev,
  314. "The link for %s on CHPID 0x%X has"
  315. " been restored\n",
  316. QETH_CARD_IFNAME(card),
  317. card->info.chpid);
  318. netif_carrier_on(card->dev);
  319. card->lan_online = 1;
  320. qeth_schedule_recovery(card);
  321. return NULL;
  322. case IPA_CMD_MODCCID:
  323. return cmd;
  324. case IPA_CMD_REGISTER_LOCAL_ADDR:
  325. QETH_CARD_TEXT(card, 3, "irla");
  326. break;
  327. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  328. QETH_CARD_TEXT(card, 3, "urla");
  329. break;
  330. default:
  331. QETH_DBF_MESSAGE(2, "Received data is IPA "
  332. "but not a reply!\n");
  333. break;
  334. }
  335. }
  336. }
  337. return cmd;
  338. }
  339. void qeth_clear_ipacmd_list(struct qeth_card *card)
  340. {
  341. struct qeth_reply *reply, *r;
  342. unsigned long flags;
  343. QETH_CARD_TEXT(card, 4, "clipalst");
  344. spin_lock_irqsave(&card->lock, flags);
  345. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  346. qeth_get_reply(reply);
  347. reply->rc = -EIO;
  348. atomic_inc(&reply->received);
  349. list_del_init(&reply->list);
  350. wake_up(&reply->wait_q);
  351. qeth_put_reply(reply);
  352. }
  353. spin_unlock_irqrestore(&card->lock, flags);
  354. atomic_set(&card->write.irq_pending, 0);
  355. }
  356. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  357. static int qeth_check_idx_response(struct qeth_card *card,
  358. unsigned char *buffer)
  359. {
  360. if (!buffer)
  361. return 0;
  362. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  363. if ((buffer[2] & 0xc0) == 0xc0) {
  364. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  365. "with cause code 0x%02x%s\n",
  366. buffer[4],
  367. ((buffer[4] == 0x22) ?
  368. " -- try another portname" : ""));
  369. QETH_CARD_TEXT(card, 2, "ckidxres");
  370. QETH_CARD_TEXT(card, 2, " idxterm");
  371. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  372. if (buffer[4] == 0xf6) {
  373. dev_err(&card->gdev->dev,
  374. "The qeth device is not configured "
  375. "for the OSI layer required by z/VM\n");
  376. return -EPERM;
  377. }
  378. return -EIO;
  379. }
  380. return 0;
  381. }
  382. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  383. __u32 len)
  384. {
  385. struct qeth_card *card;
  386. card = CARD_FROM_CDEV(channel->ccwdev);
  387. QETH_CARD_TEXT(card, 4, "setupccw");
  388. if (channel == &card->read)
  389. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  390. else
  391. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  392. channel->ccw.count = len;
  393. channel->ccw.cda = (__u32) __pa(iob);
  394. }
  395. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  396. {
  397. __u8 index;
  398. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  399. index = channel->io_buf_no;
  400. do {
  401. if (channel->iob[index].state == BUF_STATE_FREE) {
  402. channel->iob[index].state = BUF_STATE_LOCKED;
  403. channel->io_buf_no = (channel->io_buf_no + 1) %
  404. QETH_CMD_BUFFER_NO;
  405. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  406. return channel->iob + index;
  407. }
  408. index = (index + 1) % QETH_CMD_BUFFER_NO;
  409. } while (index != channel->io_buf_no);
  410. return NULL;
  411. }
  412. void qeth_release_buffer(struct qeth_channel *channel,
  413. struct qeth_cmd_buffer *iob)
  414. {
  415. unsigned long flags;
  416. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  417. spin_lock_irqsave(&channel->iob_lock, flags);
  418. memset(iob->data, 0, QETH_BUFSIZE);
  419. iob->state = BUF_STATE_FREE;
  420. iob->callback = qeth_send_control_data_cb;
  421. iob->rc = 0;
  422. spin_unlock_irqrestore(&channel->iob_lock, flags);
  423. }
  424. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  425. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  426. {
  427. struct qeth_cmd_buffer *buffer = NULL;
  428. unsigned long flags;
  429. spin_lock_irqsave(&channel->iob_lock, flags);
  430. buffer = __qeth_get_buffer(channel);
  431. spin_unlock_irqrestore(&channel->iob_lock, flags);
  432. return buffer;
  433. }
  434. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  435. {
  436. struct qeth_cmd_buffer *buffer;
  437. wait_event(channel->wait_q,
  438. ((buffer = qeth_get_buffer(channel)) != NULL));
  439. return buffer;
  440. }
  441. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  442. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  443. {
  444. int cnt;
  445. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  446. qeth_release_buffer(channel, &channel->iob[cnt]);
  447. channel->buf_no = 0;
  448. channel->io_buf_no = 0;
  449. }
  450. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  451. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  452. struct qeth_cmd_buffer *iob)
  453. {
  454. struct qeth_card *card;
  455. struct qeth_reply *reply, *r;
  456. struct qeth_ipa_cmd *cmd;
  457. unsigned long flags;
  458. int keep_reply;
  459. int rc = 0;
  460. card = CARD_FROM_CDEV(channel->ccwdev);
  461. QETH_CARD_TEXT(card, 4, "sndctlcb");
  462. rc = qeth_check_idx_response(card, iob->data);
  463. switch (rc) {
  464. case 0:
  465. break;
  466. case -EIO:
  467. qeth_clear_ipacmd_list(card);
  468. qeth_schedule_recovery(card);
  469. /* fall through */
  470. default:
  471. goto out;
  472. }
  473. cmd = qeth_check_ipa_data(card, iob);
  474. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  475. goto out;
  476. /*in case of OSN : check if cmd is set */
  477. if (card->info.type == QETH_CARD_TYPE_OSN &&
  478. cmd &&
  479. cmd->hdr.command != IPA_CMD_STARTLAN &&
  480. card->osn_info.assist_cb != NULL) {
  481. card->osn_info.assist_cb(card->dev, cmd);
  482. goto out;
  483. }
  484. spin_lock_irqsave(&card->lock, flags);
  485. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  486. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  487. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  488. qeth_get_reply(reply);
  489. list_del_init(&reply->list);
  490. spin_unlock_irqrestore(&card->lock, flags);
  491. keep_reply = 0;
  492. if (reply->callback != NULL) {
  493. if (cmd) {
  494. reply->offset = (__u16)((char *)cmd -
  495. (char *)iob->data);
  496. keep_reply = reply->callback(card,
  497. reply,
  498. (unsigned long)cmd);
  499. } else
  500. keep_reply = reply->callback(card,
  501. reply,
  502. (unsigned long)iob);
  503. }
  504. if (cmd)
  505. reply->rc = (u16) cmd->hdr.return_code;
  506. else if (iob->rc)
  507. reply->rc = iob->rc;
  508. if (keep_reply) {
  509. spin_lock_irqsave(&card->lock, flags);
  510. list_add_tail(&reply->list,
  511. &card->cmd_waiter_list);
  512. spin_unlock_irqrestore(&card->lock, flags);
  513. } else {
  514. atomic_inc(&reply->received);
  515. wake_up(&reply->wait_q);
  516. }
  517. qeth_put_reply(reply);
  518. goto out;
  519. }
  520. }
  521. spin_unlock_irqrestore(&card->lock, flags);
  522. out:
  523. memcpy(&card->seqno.pdu_hdr_ack,
  524. QETH_PDU_HEADER_SEQ_NO(iob->data),
  525. QETH_SEQ_NO_LENGTH);
  526. qeth_release_buffer(channel, iob);
  527. }
  528. static int qeth_setup_channel(struct qeth_channel *channel)
  529. {
  530. int cnt;
  531. QETH_DBF_TEXT(SETUP, 2, "setupch");
  532. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  533. channel->iob[cnt].data =
  534. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  535. if (channel->iob[cnt].data == NULL)
  536. break;
  537. channel->iob[cnt].state = BUF_STATE_FREE;
  538. channel->iob[cnt].channel = channel;
  539. channel->iob[cnt].callback = qeth_send_control_data_cb;
  540. channel->iob[cnt].rc = 0;
  541. }
  542. if (cnt < QETH_CMD_BUFFER_NO) {
  543. while (cnt-- > 0)
  544. kfree(channel->iob[cnt].data);
  545. return -ENOMEM;
  546. }
  547. channel->buf_no = 0;
  548. channel->io_buf_no = 0;
  549. atomic_set(&channel->irq_pending, 0);
  550. spin_lock_init(&channel->iob_lock);
  551. init_waitqueue_head(&channel->wait_q);
  552. return 0;
  553. }
  554. static int qeth_set_thread_start_bit(struct qeth_card *card,
  555. unsigned long thread)
  556. {
  557. unsigned long flags;
  558. spin_lock_irqsave(&card->thread_mask_lock, flags);
  559. if (!(card->thread_allowed_mask & thread) ||
  560. (card->thread_start_mask & thread)) {
  561. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  562. return -EPERM;
  563. }
  564. card->thread_start_mask |= thread;
  565. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  566. return 0;
  567. }
  568. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  569. {
  570. unsigned long flags;
  571. spin_lock_irqsave(&card->thread_mask_lock, flags);
  572. card->thread_start_mask &= ~thread;
  573. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  574. wake_up(&card->wait_q);
  575. }
  576. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  577. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  578. {
  579. unsigned long flags;
  580. spin_lock_irqsave(&card->thread_mask_lock, flags);
  581. card->thread_running_mask &= ~thread;
  582. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  583. wake_up(&card->wait_q);
  584. }
  585. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  586. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  587. {
  588. unsigned long flags;
  589. int rc = 0;
  590. spin_lock_irqsave(&card->thread_mask_lock, flags);
  591. if (card->thread_start_mask & thread) {
  592. if ((card->thread_allowed_mask & thread) &&
  593. !(card->thread_running_mask & thread)) {
  594. rc = 1;
  595. card->thread_start_mask &= ~thread;
  596. card->thread_running_mask |= thread;
  597. } else
  598. rc = -EPERM;
  599. }
  600. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  601. return rc;
  602. }
  603. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  604. {
  605. int rc = 0;
  606. wait_event(card->wait_q,
  607. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  608. return rc;
  609. }
  610. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  611. void qeth_schedule_recovery(struct qeth_card *card)
  612. {
  613. QETH_CARD_TEXT(card, 2, "startrec");
  614. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  615. schedule_work(&card->kernel_thread_starter);
  616. }
  617. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  618. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  619. {
  620. int dstat, cstat;
  621. char *sense;
  622. struct qeth_card *card;
  623. sense = (char *) irb->ecw;
  624. cstat = irb->scsw.cmd.cstat;
  625. dstat = irb->scsw.cmd.dstat;
  626. card = CARD_FROM_CDEV(cdev);
  627. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  628. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  629. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  630. QETH_CARD_TEXT(card, 2, "CGENCHK");
  631. dev_warn(&cdev->dev, "The qeth device driver "
  632. "failed to recover an error on the device\n");
  633. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  634. dev_name(&cdev->dev), dstat, cstat);
  635. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  636. 16, 1, irb, 64, 1);
  637. return 1;
  638. }
  639. if (dstat & DEV_STAT_UNIT_CHECK) {
  640. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  641. SENSE_RESETTING_EVENT_FLAG) {
  642. QETH_CARD_TEXT(card, 2, "REVIND");
  643. return 1;
  644. }
  645. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  646. SENSE_COMMAND_REJECT_FLAG) {
  647. QETH_CARD_TEXT(card, 2, "CMDREJi");
  648. return 1;
  649. }
  650. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  651. QETH_CARD_TEXT(card, 2, "AFFE");
  652. return 1;
  653. }
  654. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  655. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  656. return 0;
  657. }
  658. QETH_CARD_TEXT(card, 2, "DGENCHK");
  659. return 1;
  660. }
  661. return 0;
  662. }
  663. static long __qeth_check_irb_error(struct ccw_device *cdev,
  664. unsigned long intparm, struct irb *irb)
  665. {
  666. struct qeth_card *card;
  667. card = CARD_FROM_CDEV(cdev);
  668. if (!IS_ERR(irb))
  669. return 0;
  670. switch (PTR_ERR(irb)) {
  671. case -EIO:
  672. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  673. dev_name(&cdev->dev));
  674. QETH_CARD_TEXT(card, 2, "ckirberr");
  675. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  676. break;
  677. case -ETIMEDOUT:
  678. dev_warn(&cdev->dev, "A hardware operation timed out"
  679. " on the device\n");
  680. QETH_CARD_TEXT(card, 2, "ckirberr");
  681. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  682. if (intparm == QETH_RCD_PARM) {
  683. if (card && (card->data.ccwdev == cdev)) {
  684. card->data.state = CH_STATE_DOWN;
  685. wake_up(&card->wait_q);
  686. }
  687. }
  688. break;
  689. default:
  690. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  691. dev_name(&cdev->dev), PTR_ERR(irb));
  692. QETH_CARD_TEXT(card, 2, "ckirberr");
  693. QETH_CARD_TEXT(card, 2, " rc???");
  694. }
  695. return PTR_ERR(irb);
  696. }
  697. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  698. struct irb *irb)
  699. {
  700. int rc;
  701. int cstat, dstat;
  702. struct qeth_cmd_buffer *buffer;
  703. struct qeth_channel *channel;
  704. struct qeth_card *card;
  705. struct qeth_cmd_buffer *iob;
  706. __u8 index;
  707. if (__qeth_check_irb_error(cdev, intparm, irb))
  708. return;
  709. cstat = irb->scsw.cmd.cstat;
  710. dstat = irb->scsw.cmd.dstat;
  711. card = CARD_FROM_CDEV(cdev);
  712. if (!card)
  713. return;
  714. QETH_CARD_TEXT(card, 5, "irq");
  715. if (card->read.ccwdev == cdev) {
  716. channel = &card->read;
  717. QETH_CARD_TEXT(card, 5, "read");
  718. } else if (card->write.ccwdev == cdev) {
  719. channel = &card->write;
  720. QETH_CARD_TEXT(card, 5, "write");
  721. } else {
  722. channel = &card->data;
  723. QETH_CARD_TEXT(card, 5, "data");
  724. }
  725. atomic_set(&channel->irq_pending, 0);
  726. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  727. channel->state = CH_STATE_STOPPED;
  728. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  729. channel->state = CH_STATE_HALTED;
  730. /*let's wake up immediately on data channel*/
  731. if ((channel == &card->data) && (intparm != 0) &&
  732. (intparm != QETH_RCD_PARM))
  733. goto out;
  734. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  735. QETH_CARD_TEXT(card, 6, "clrchpar");
  736. /* we don't have to handle this further */
  737. intparm = 0;
  738. }
  739. if (intparm == QETH_HALT_CHANNEL_PARM) {
  740. QETH_CARD_TEXT(card, 6, "hltchpar");
  741. /* we don't have to handle this further */
  742. intparm = 0;
  743. }
  744. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  745. (dstat & DEV_STAT_UNIT_CHECK) ||
  746. (cstat)) {
  747. if (irb->esw.esw0.erw.cons) {
  748. dev_warn(&channel->ccwdev->dev,
  749. "The qeth device driver failed to recover "
  750. "an error on the device\n");
  751. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  752. "0x%X dstat 0x%X\n",
  753. dev_name(&channel->ccwdev->dev), cstat, dstat);
  754. print_hex_dump(KERN_WARNING, "qeth: irb ",
  755. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  756. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  757. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  758. }
  759. if (intparm == QETH_RCD_PARM) {
  760. channel->state = CH_STATE_DOWN;
  761. goto out;
  762. }
  763. rc = qeth_get_problem(cdev, irb);
  764. if (rc) {
  765. qeth_clear_ipacmd_list(card);
  766. qeth_schedule_recovery(card);
  767. goto out;
  768. }
  769. }
  770. if (intparm == QETH_RCD_PARM) {
  771. channel->state = CH_STATE_RCD_DONE;
  772. goto out;
  773. }
  774. if (intparm) {
  775. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  776. buffer->state = BUF_STATE_PROCESSED;
  777. }
  778. if (channel == &card->data)
  779. return;
  780. if (channel == &card->read &&
  781. channel->state == CH_STATE_UP)
  782. qeth_issue_next_read(card);
  783. iob = channel->iob;
  784. index = channel->buf_no;
  785. while (iob[index].state == BUF_STATE_PROCESSED) {
  786. if (iob[index].callback != NULL)
  787. iob[index].callback(channel, iob + index);
  788. index = (index + 1) % QETH_CMD_BUFFER_NO;
  789. }
  790. channel->buf_no = index;
  791. out:
  792. wake_up(&card->wait_q);
  793. return;
  794. }
  795. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  796. struct qeth_qdio_out_buffer *buf)
  797. {
  798. int i;
  799. struct sk_buff *skb;
  800. /* is PCI flag set on buffer? */
  801. if (buf->buffer->element[0].flags & 0x40)
  802. atomic_dec(&queue->set_pci_flags_count);
  803. skb = skb_dequeue(&buf->skb_list);
  804. while (skb) {
  805. atomic_dec(&skb->users);
  806. dev_kfree_skb_any(skb);
  807. skb = skb_dequeue(&buf->skb_list);
  808. }
  809. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  810. if (buf->buffer->element[i].addr && buf->is_header[i])
  811. kmem_cache_free(qeth_core_header_cache,
  812. buf->buffer->element[i].addr);
  813. buf->is_header[i] = 0;
  814. buf->buffer->element[i].length = 0;
  815. buf->buffer->element[i].addr = NULL;
  816. buf->buffer->element[i].flags = 0;
  817. }
  818. buf->buffer->element[15].flags = 0;
  819. buf->next_element_to_fill = 0;
  820. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  821. }
  822. void qeth_clear_qdio_buffers(struct qeth_card *card)
  823. {
  824. int i, j;
  825. QETH_CARD_TEXT(card, 2, "clearqdbf");
  826. /* clear outbound buffers to free skbs */
  827. for (i = 0; i < card->qdio.no_out_queues; ++i)
  828. if (card->qdio.out_qs[i]) {
  829. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  830. qeth_clear_output_buffer(card->qdio.out_qs[i],
  831. &card->qdio.out_qs[i]->bufs[j]);
  832. }
  833. }
  834. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  835. static void qeth_free_buffer_pool(struct qeth_card *card)
  836. {
  837. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  838. int i = 0;
  839. list_for_each_entry_safe(pool_entry, tmp,
  840. &card->qdio.init_pool.entry_list, init_list){
  841. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  842. free_page((unsigned long)pool_entry->elements[i]);
  843. list_del(&pool_entry->init_list);
  844. kfree(pool_entry);
  845. }
  846. }
  847. static void qeth_free_qdio_buffers(struct qeth_card *card)
  848. {
  849. int i, j;
  850. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  851. QETH_QDIO_UNINITIALIZED)
  852. return;
  853. kfree(card->qdio.in_q);
  854. card->qdio.in_q = NULL;
  855. /* inbound buffer pool */
  856. qeth_free_buffer_pool(card);
  857. /* free outbound qdio_qs */
  858. if (card->qdio.out_qs) {
  859. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  860. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  861. qeth_clear_output_buffer(card->qdio.out_qs[i],
  862. &card->qdio.out_qs[i]->bufs[j]);
  863. kfree(card->qdio.out_qs[i]);
  864. }
  865. kfree(card->qdio.out_qs);
  866. card->qdio.out_qs = NULL;
  867. }
  868. }
  869. static void qeth_clean_channel(struct qeth_channel *channel)
  870. {
  871. int cnt;
  872. QETH_DBF_TEXT(SETUP, 2, "freech");
  873. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  874. kfree(channel->iob[cnt].data);
  875. }
  876. static void qeth_get_channel_path_desc(struct qeth_card *card)
  877. {
  878. struct ccw_device *ccwdev;
  879. struct channelPath_dsc {
  880. u8 flags;
  881. u8 lsn;
  882. u8 desc;
  883. u8 chpid;
  884. u8 swla;
  885. u8 zeroes;
  886. u8 chla;
  887. u8 chpp;
  888. } *chp_dsc;
  889. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  890. ccwdev = card->data.ccwdev;
  891. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  892. if (chp_dsc != NULL) {
  893. /* CHPP field bit 6 == 1 -> single queue */
  894. if ((chp_dsc->chpp & 0x02) == 0x02) {
  895. if ((atomic_read(&card->qdio.state) !=
  896. QETH_QDIO_UNINITIALIZED) &&
  897. (card->qdio.no_out_queues == 4))
  898. /* change from 4 to 1 outbound queues */
  899. qeth_free_qdio_buffers(card);
  900. card->qdio.no_out_queues = 1;
  901. if (card->qdio.default_out_queue != 0)
  902. dev_info(&card->gdev->dev,
  903. "Priority Queueing not supported\n");
  904. card->qdio.default_out_queue = 0;
  905. } else {
  906. if ((atomic_read(&card->qdio.state) !=
  907. QETH_QDIO_UNINITIALIZED) &&
  908. (card->qdio.no_out_queues == 1)) {
  909. /* change from 1 to 4 outbound queues */
  910. qeth_free_qdio_buffers(card);
  911. card->qdio.default_out_queue = 2;
  912. }
  913. card->qdio.no_out_queues = 4;
  914. }
  915. card->info.func_level = 0x4100 + chp_dsc->desc;
  916. kfree(chp_dsc);
  917. }
  918. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  919. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  920. return;
  921. }
  922. static void qeth_init_qdio_info(struct qeth_card *card)
  923. {
  924. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  925. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  926. /* inbound */
  927. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  928. if (card->info.type == QETH_CARD_TYPE_IQD)
  929. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_HSDEFAULT;
  930. else
  931. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  932. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  933. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  934. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  935. }
  936. static void qeth_set_intial_options(struct qeth_card *card)
  937. {
  938. card->options.route4.type = NO_ROUTER;
  939. card->options.route6.type = NO_ROUTER;
  940. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  941. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  942. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  943. card->options.fake_broadcast = 0;
  944. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  945. card->options.performance_stats = 0;
  946. card->options.rx_sg_cb = QETH_RX_SG_CB;
  947. card->options.isolation = ISOLATION_MODE_NONE;
  948. }
  949. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  950. {
  951. unsigned long flags;
  952. int rc = 0;
  953. spin_lock_irqsave(&card->thread_mask_lock, flags);
  954. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  955. (u8) card->thread_start_mask,
  956. (u8) card->thread_allowed_mask,
  957. (u8) card->thread_running_mask);
  958. rc = (card->thread_start_mask & thread);
  959. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  960. return rc;
  961. }
  962. static void qeth_start_kernel_thread(struct work_struct *work)
  963. {
  964. struct qeth_card *card = container_of(work, struct qeth_card,
  965. kernel_thread_starter);
  966. QETH_CARD_TEXT(card , 2, "strthrd");
  967. if (card->read.state != CH_STATE_UP &&
  968. card->write.state != CH_STATE_UP)
  969. return;
  970. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  971. kthread_run(card->discipline.recover, (void *) card,
  972. "qeth_recover");
  973. }
  974. static int qeth_setup_card(struct qeth_card *card)
  975. {
  976. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  977. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  978. card->read.state = CH_STATE_DOWN;
  979. card->write.state = CH_STATE_DOWN;
  980. card->data.state = CH_STATE_DOWN;
  981. card->state = CARD_STATE_DOWN;
  982. card->lan_online = 0;
  983. card->read_or_write_problem = 0;
  984. card->dev = NULL;
  985. spin_lock_init(&card->vlanlock);
  986. spin_lock_init(&card->mclock);
  987. card->vlangrp = NULL;
  988. spin_lock_init(&card->lock);
  989. spin_lock_init(&card->ip_lock);
  990. spin_lock_init(&card->thread_mask_lock);
  991. mutex_init(&card->conf_mutex);
  992. mutex_init(&card->discipline_mutex);
  993. card->thread_start_mask = 0;
  994. card->thread_allowed_mask = 0;
  995. card->thread_running_mask = 0;
  996. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  997. INIT_LIST_HEAD(&card->ip_list);
  998. INIT_LIST_HEAD(card->ip_tbd_list);
  999. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1000. init_waitqueue_head(&card->wait_q);
  1001. /* intial options */
  1002. qeth_set_intial_options(card);
  1003. /* IP address takeover */
  1004. INIT_LIST_HEAD(&card->ipato.entries);
  1005. card->ipato.enabled = 0;
  1006. card->ipato.invert4 = 0;
  1007. card->ipato.invert6 = 0;
  1008. /* init QDIO stuff */
  1009. qeth_init_qdio_info(card);
  1010. return 0;
  1011. }
  1012. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1013. {
  1014. struct qeth_card *card = container_of(slr, struct qeth_card,
  1015. qeth_service_level);
  1016. if (card->info.mcl_level[0])
  1017. seq_printf(m, "qeth: %s firmware level %s\n",
  1018. CARD_BUS_ID(card), card->info.mcl_level);
  1019. }
  1020. static struct qeth_card *qeth_alloc_card(void)
  1021. {
  1022. struct qeth_card *card;
  1023. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1024. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1025. if (!card)
  1026. goto out;
  1027. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1028. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1029. if (!card->ip_tbd_list) {
  1030. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1031. goto out_card;
  1032. }
  1033. if (qeth_setup_channel(&card->read))
  1034. goto out_ip;
  1035. if (qeth_setup_channel(&card->write))
  1036. goto out_channel;
  1037. card->options.layer2 = -1;
  1038. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1039. register_service_level(&card->qeth_service_level);
  1040. return card;
  1041. out_channel:
  1042. qeth_clean_channel(&card->read);
  1043. out_ip:
  1044. kfree(card->ip_tbd_list);
  1045. out_card:
  1046. kfree(card);
  1047. out:
  1048. return NULL;
  1049. }
  1050. static int qeth_determine_card_type(struct qeth_card *card)
  1051. {
  1052. int i = 0;
  1053. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1054. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1055. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1056. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1057. if ((CARD_RDEV(card)->id.dev_type ==
  1058. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1059. (CARD_RDEV(card)->id.dev_model ==
  1060. known_devices[i][QETH_DEV_MODEL_IND])) {
  1061. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1062. card->qdio.no_out_queues =
  1063. known_devices[i][QETH_QUEUE_NO_IND];
  1064. card->info.is_multicast_different =
  1065. known_devices[i][QETH_MULTICAST_IND];
  1066. qeth_get_channel_path_desc(card);
  1067. return 0;
  1068. }
  1069. i++;
  1070. }
  1071. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1072. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1073. "unknown type\n");
  1074. return -ENOENT;
  1075. }
  1076. static int qeth_clear_channel(struct qeth_channel *channel)
  1077. {
  1078. unsigned long flags;
  1079. struct qeth_card *card;
  1080. int rc;
  1081. card = CARD_FROM_CDEV(channel->ccwdev);
  1082. QETH_CARD_TEXT(card, 3, "clearch");
  1083. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1084. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1085. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1086. if (rc)
  1087. return rc;
  1088. rc = wait_event_interruptible_timeout(card->wait_q,
  1089. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1090. if (rc == -ERESTARTSYS)
  1091. return rc;
  1092. if (channel->state != CH_STATE_STOPPED)
  1093. return -ETIME;
  1094. channel->state = CH_STATE_DOWN;
  1095. return 0;
  1096. }
  1097. static int qeth_halt_channel(struct qeth_channel *channel)
  1098. {
  1099. unsigned long flags;
  1100. struct qeth_card *card;
  1101. int rc;
  1102. card = CARD_FROM_CDEV(channel->ccwdev);
  1103. QETH_CARD_TEXT(card, 3, "haltch");
  1104. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1105. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1106. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1107. if (rc)
  1108. return rc;
  1109. rc = wait_event_interruptible_timeout(card->wait_q,
  1110. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1111. if (rc == -ERESTARTSYS)
  1112. return rc;
  1113. if (channel->state != CH_STATE_HALTED)
  1114. return -ETIME;
  1115. return 0;
  1116. }
  1117. static int qeth_halt_channels(struct qeth_card *card)
  1118. {
  1119. int rc1 = 0, rc2 = 0, rc3 = 0;
  1120. QETH_CARD_TEXT(card, 3, "haltchs");
  1121. rc1 = qeth_halt_channel(&card->read);
  1122. rc2 = qeth_halt_channel(&card->write);
  1123. rc3 = qeth_halt_channel(&card->data);
  1124. if (rc1)
  1125. return rc1;
  1126. if (rc2)
  1127. return rc2;
  1128. return rc3;
  1129. }
  1130. static int qeth_clear_channels(struct qeth_card *card)
  1131. {
  1132. int rc1 = 0, rc2 = 0, rc3 = 0;
  1133. QETH_CARD_TEXT(card, 3, "clearchs");
  1134. rc1 = qeth_clear_channel(&card->read);
  1135. rc2 = qeth_clear_channel(&card->write);
  1136. rc3 = qeth_clear_channel(&card->data);
  1137. if (rc1)
  1138. return rc1;
  1139. if (rc2)
  1140. return rc2;
  1141. return rc3;
  1142. }
  1143. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1144. {
  1145. int rc = 0;
  1146. QETH_CARD_TEXT(card, 3, "clhacrd");
  1147. if (halt)
  1148. rc = qeth_halt_channels(card);
  1149. if (rc)
  1150. return rc;
  1151. return qeth_clear_channels(card);
  1152. }
  1153. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1154. {
  1155. int rc = 0;
  1156. QETH_CARD_TEXT(card, 3, "qdioclr");
  1157. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1158. QETH_QDIO_CLEANING)) {
  1159. case QETH_QDIO_ESTABLISHED:
  1160. if (card->info.type == QETH_CARD_TYPE_IQD)
  1161. rc = qdio_shutdown(CARD_DDEV(card),
  1162. QDIO_FLAG_CLEANUP_USING_HALT);
  1163. else
  1164. rc = qdio_shutdown(CARD_DDEV(card),
  1165. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1166. if (rc)
  1167. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1168. qdio_free(CARD_DDEV(card));
  1169. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1170. break;
  1171. case QETH_QDIO_CLEANING:
  1172. return rc;
  1173. default:
  1174. break;
  1175. }
  1176. rc = qeth_clear_halt_card(card, use_halt);
  1177. if (rc)
  1178. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1179. card->state = CARD_STATE_DOWN;
  1180. return rc;
  1181. }
  1182. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1183. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1184. int *length)
  1185. {
  1186. struct ciw *ciw;
  1187. char *rcd_buf;
  1188. int ret;
  1189. struct qeth_channel *channel = &card->data;
  1190. unsigned long flags;
  1191. /*
  1192. * scan for RCD command in extended SenseID data
  1193. */
  1194. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1195. if (!ciw || ciw->cmd == 0)
  1196. return -EOPNOTSUPP;
  1197. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1198. if (!rcd_buf)
  1199. return -ENOMEM;
  1200. channel->ccw.cmd_code = ciw->cmd;
  1201. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1202. channel->ccw.count = ciw->count;
  1203. channel->ccw.flags = CCW_FLAG_SLI;
  1204. channel->state = CH_STATE_RCD;
  1205. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1206. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1207. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1208. QETH_RCD_TIMEOUT);
  1209. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1210. if (!ret)
  1211. wait_event(card->wait_q,
  1212. (channel->state == CH_STATE_RCD_DONE ||
  1213. channel->state == CH_STATE_DOWN));
  1214. if (channel->state == CH_STATE_DOWN)
  1215. ret = -EIO;
  1216. else
  1217. channel->state = CH_STATE_DOWN;
  1218. if (ret) {
  1219. kfree(rcd_buf);
  1220. *buffer = NULL;
  1221. *length = 0;
  1222. } else {
  1223. *length = ciw->count;
  1224. *buffer = rcd_buf;
  1225. }
  1226. return ret;
  1227. }
  1228. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1229. {
  1230. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1231. card->info.chpid = prcd[30];
  1232. card->info.unit_addr2 = prcd[31];
  1233. card->info.cula = prcd[63];
  1234. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1235. (prcd[0x11] == _ascebc['M']));
  1236. }
  1237. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1238. {
  1239. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1240. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1241. card->info.blkt.time_total = 250;
  1242. card->info.blkt.inter_packet = 5;
  1243. card->info.blkt.inter_packet_jumbo = 15;
  1244. } else {
  1245. card->info.blkt.time_total = 0;
  1246. card->info.blkt.inter_packet = 0;
  1247. card->info.blkt.inter_packet_jumbo = 0;
  1248. }
  1249. }
  1250. static void qeth_init_tokens(struct qeth_card *card)
  1251. {
  1252. card->token.issuer_rm_w = 0x00010103UL;
  1253. card->token.cm_filter_w = 0x00010108UL;
  1254. card->token.cm_connection_w = 0x0001010aUL;
  1255. card->token.ulp_filter_w = 0x0001010bUL;
  1256. card->token.ulp_connection_w = 0x0001010dUL;
  1257. }
  1258. static void qeth_init_func_level(struct qeth_card *card)
  1259. {
  1260. switch (card->info.type) {
  1261. case QETH_CARD_TYPE_IQD:
  1262. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1263. break;
  1264. case QETH_CARD_TYPE_OSD:
  1265. case QETH_CARD_TYPE_OSN:
  1266. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1267. break;
  1268. default:
  1269. break;
  1270. }
  1271. }
  1272. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1273. void (*idx_reply_cb)(struct qeth_channel *,
  1274. struct qeth_cmd_buffer *))
  1275. {
  1276. struct qeth_cmd_buffer *iob;
  1277. unsigned long flags;
  1278. int rc;
  1279. struct qeth_card *card;
  1280. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1281. card = CARD_FROM_CDEV(channel->ccwdev);
  1282. iob = qeth_get_buffer(channel);
  1283. iob->callback = idx_reply_cb;
  1284. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1285. channel->ccw.count = QETH_BUFSIZE;
  1286. channel->ccw.cda = (__u32) __pa(iob->data);
  1287. wait_event(card->wait_q,
  1288. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1289. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1290. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1291. rc = ccw_device_start(channel->ccwdev,
  1292. &channel->ccw, (addr_t) iob, 0, 0);
  1293. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1294. if (rc) {
  1295. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1296. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1297. atomic_set(&channel->irq_pending, 0);
  1298. wake_up(&card->wait_q);
  1299. return rc;
  1300. }
  1301. rc = wait_event_interruptible_timeout(card->wait_q,
  1302. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1303. if (rc == -ERESTARTSYS)
  1304. return rc;
  1305. if (channel->state != CH_STATE_UP) {
  1306. rc = -ETIME;
  1307. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1308. qeth_clear_cmd_buffers(channel);
  1309. } else
  1310. rc = 0;
  1311. return rc;
  1312. }
  1313. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1314. void (*idx_reply_cb)(struct qeth_channel *,
  1315. struct qeth_cmd_buffer *))
  1316. {
  1317. struct qeth_card *card;
  1318. struct qeth_cmd_buffer *iob;
  1319. unsigned long flags;
  1320. __u16 temp;
  1321. __u8 tmp;
  1322. int rc;
  1323. struct ccw_dev_id temp_devid;
  1324. card = CARD_FROM_CDEV(channel->ccwdev);
  1325. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1326. iob = qeth_get_buffer(channel);
  1327. iob->callback = idx_reply_cb;
  1328. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1329. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1330. channel->ccw.cda = (__u32) __pa(iob->data);
  1331. if (channel == &card->write) {
  1332. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1333. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1334. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1335. card->seqno.trans_hdr++;
  1336. } else {
  1337. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1338. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1339. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1340. }
  1341. tmp = ((__u8)card->info.portno) | 0x80;
  1342. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1343. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1344. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1345. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1346. &card->info.func_level, sizeof(__u16));
  1347. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1348. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1349. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1350. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1351. wait_event(card->wait_q,
  1352. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1353. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1354. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1355. rc = ccw_device_start(channel->ccwdev,
  1356. &channel->ccw, (addr_t) iob, 0, 0);
  1357. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1358. if (rc) {
  1359. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1360. rc);
  1361. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1362. atomic_set(&channel->irq_pending, 0);
  1363. wake_up(&card->wait_q);
  1364. return rc;
  1365. }
  1366. rc = wait_event_interruptible_timeout(card->wait_q,
  1367. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1368. if (rc == -ERESTARTSYS)
  1369. return rc;
  1370. if (channel->state != CH_STATE_ACTIVATING) {
  1371. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1372. " failed to recover an error on the device\n");
  1373. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1374. dev_name(&channel->ccwdev->dev));
  1375. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1376. qeth_clear_cmd_buffers(channel);
  1377. return -ETIME;
  1378. }
  1379. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1380. }
  1381. static int qeth_peer_func_level(int level)
  1382. {
  1383. if ((level & 0xff) == 8)
  1384. return (level & 0xff) + 0x400;
  1385. if (((level >> 8) & 3) == 1)
  1386. return (level & 0xff) + 0x200;
  1387. return level;
  1388. }
  1389. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1390. struct qeth_cmd_buffer *iob)
  1391. {
  1392. struct qeth_card *card;
  1393. __u16 temp;
  1394. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1395. if (channel->state == CH_STATE_DOWN) {
  1396. channel->state = CH_STATE_ACTIVATING;
  1397. goto out;
  1398. }
  1399. card = CARD_FROM_CDEV(channel->ccwdev);
  1400. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1401. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1402. dev_err(&card->write.ccwdev->dev,
  1403. "The adapter is used exclusively by another "
  1404. "host\n");
  1405. else
  1406. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1407. " negative reply\n",
  1408. dev_name(&card->write.ccwdev->dev));
  1409. goto out;
  1410. }
  1411. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1412. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1413. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1414. "function level mismatch (sent: 0x%x, received: "
  1415. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1416. card->info.func_level, temp);
  1417. goto out;
  1418. }
  1419. channel->state = CH_STATE_UP;
  1420. out:
  1421. qeth_release_buffer(channel, iob);
  1422. }
  1423. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1424. struct qeth_cmd_buffer *iob)
  1425. {
  1426. struct qeth_card *card;
  1427. __u16 temp;
  1428. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1429. if (channel->state == CH_STATE_DOWN) {
  1430. channel->state = CH_STATE_ACTIVATING;
  1431. goto out;
  1432. }
  1433. card = CARD_FROM_CDEV(channel->ccwdev);
  1434. if (qeth_check_idx_response(card, iob->data))
  1435. goto out;
  1436. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1437. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1438. case QETH_IDX_ACT_ERR_EXCL:
  1439. dev_err(&card->write.ccwdev->dev,
  1440. "The adapter is used exclusively by another "
  1441. "host\n");
  1442. break;
  1443. case QETH_IDX_ACT_ERR_AUTH:
  1444. case QETH_IDX_ACT_ERR_AUTH_USER:
  1445. dev_err(&card->read.ccwdev->dev,
  1446. "Setting the device online failed because of "
  1447. "insufficient authorization\n");
  1448. break;
  1449. default:
  1450. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1451. " negative reply\n",
  1452. dev_name(&card->read.ccwdev->dev));
  1453. }
  1454. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1455. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1456. goto out;
  1457. }
  1458. /**
  1459. * * temporary fix for microcode bug
  1460. * * to revert it,replace OR by AND
  1461. * */
  1462. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1463. (card->info.type == QETH_CARD_TYPE_OSD))
  1464. card->info.portname_required = 1;
  1465. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1466. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1467. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1468. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1469. dev_name(&card->read.ccwdev->dev),
  1470. card->info.func_level, temp);
  1471. goto out;
  1472. }
  1473. memcpy(&card->token.issuer_rm_r,
  1474. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1475. QETH_MPC_TOKEN_LENGTH);
  1476. memcpy(&card->info.mcl_level[0],
  1477. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1478. channel->state = CH_STATE_UP;
  1479. out:
  1480. qeth_release_buffer(channel, iob);
  1481. }
  1482. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1483. struct qeth_cmd_buffer *iob)
  1484. {
  1485. qeth_setup_ccw(&card->write, iob->data, len);
  1486. iob->callback = qeth_release_buffer;
  1487. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1488. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1489. card->seqno.trans_hdr++;
  1490. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1491. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1492. card->seqno.pdu_hdr++;
  1493. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1494. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1495. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1496. }
  1497. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1498. int qeth_send_control_data(struct qeth_card *card, int len,
  1499. struct qeth_cmd_buffer *iob,
  1500. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1501. unsigned long),
  1502. void *reply_param)
  1503. {
  1504. int rc;
  1505. unsigned long flags;
  1506. struct qeth_reply *reply = NULL;
  1507. unsigned long timeout, event_timeout;
  1508. struct qeth_ipa_cmd *cmd;
  1509. QETH_CARD_TEXT(card, 2, "sendctl");
  1510. if (card->read_or_write_problem) {
  1511. qeth_release_buffer(iob->channel, iob);
  1512. return -EIO;
  1513. }
  1514. reply = qeth_alloc_reply(card);
  1515. if (!reply) {
  1516. return -ENOMEM;
  1517. }
  1518. reply->callback = reply_cb;
  1519. reply->param = reply_param;
  1520. if (card->state == CARD_STATE_DOWN)
  1521. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1522. else
  1523. reply->seqno = card->seqno.ipa++;
  1524. init_waitqueue_head(&reply->wait_q);
  1525. spin_lock_irqsave(&card->lock, flags);
  1526. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1527. spin_unlock_irqrestore(&card->lock, flags);
  1528. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1529. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1530. qeth_prepare_control_data(card, len, iob);
  1531. if (IS_IPA(iob->data))
  1532. event_timeout = QETH_IPA_TIMEOUT;
  1533. else
  1534. event_timeout = QETH_TIMEOUT;
  1535. timeout = jiffies + event_timeout;
  1536. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1537. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1538. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1539. (addr_t) iob, 0, 0);
  1540. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1541. if (rc) {
  1542. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1543. "ccw_device_start rc = %i\n",
  1544. dev_name(&card->write.ccwdev->dev), rc);
  1545. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1546. spin_lock_irqsave(&card->lock, flags);
  1547. list_del_init(&reply->list);
  1548. qeth_put_reply(reply);
  1549. spin_unlock_irqrestore(&card->lock, flags);
  1550. qeth_release_buffer(iob->channel, iob);
  1551. atomic_set(&card->write.irq_pending, 0);
  1552. wake_up(&card->wait_q);
  1553. return rc;
  1554. }
  1555. /* we have only one long running ipassist, since we can ensure
  1556. process context of this command we can sleep */
  1557. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1558. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1559. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1560. if (!wait_event_timeout(reply->wait_q,
  1561. atomic_read(&reply->received), event_timeout))
  1562. goto time_err;
  1563. } else {
  1564. while (!atomic_read(&reply->received)) {
  1565. if (time_after(jiffies, timeout))
  1566. goto time_err;
  1567. cpu_relax();
  1568. };
  1569. }
  1570. if (reply->rc == -EIO)
  1571. goto error;
  1572. rc = reply->rc;
  1573. qeth_put_reply(reply);
  1574. return rc;
  1575. time_err:
  1576. reply->rc = -ETIME;
  1577. spin_lock_irqsave(&reply->card->lock, flags);
  1578. list_del_init(&reply->list);
  1579. spin_unlock_irqrestore(&reply->card->lock, flags);
  1580. atomic_inc(&reply->received);
  1581. error:
  1582. atomic_set(&card->write.irq_pending, 0);
  1583. qeth_release_buffer(iob->channel, iob);
  1584. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1585. rc = reply->rc;
  1586. qeth_put_reply(reply);
  1587. return rc;
  1588. }
  1589. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1590. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1591. unsigned long data)
  1592. {
  1593. struct qeth_cmd_buffer *iob;
  1594. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1595. iob = (struct qeth_cmd_buffer *) data;
  1596. memcpy(&card->token.cm_filter_r,
  1597. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1598. QETH_MPC_TOKEN_LENGTH);
  1599. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1600. return 0;
  1601. }
  1602. static int qeth_cm_enable(struct qeth_card *card)
  1603. {
  1604. int rc;
  1605. struct qeth_cmd_buffer *iob;
  1606. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1607. iob = qeth_wait_for_buffer(&card->write);
  1608. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1609. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1610. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1611. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1612. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1613. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1614. qeth_cm_enable_cb, NULL);
  1615. return rc;
  1616. }
  1617. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1618. unsigned long data)
  1619. {
  1620. struct qeth_cmd_buffer *iob;
  1621. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1622. iob = (struct qeth_cmd_buffer *) data;
  1623. memcpy(&card->token.cm_connection_r,
  1624. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1625. QETH_MPC_TOKEN_LENGTH);
  1626. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1627. return 0;
  1628. }
  1629. static int qeth_cm_setup(struct qeth_card *card)
  1630. {
  1631. int rc;
  1632. struct qeth_cmd_buffer *iob;
  1633. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1634. iob = qeth_wait_for_buffer(&card->write);
  1635. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1636. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1637. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1638. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1639. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1640. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1641. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1642. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1643. qeth_cm_setup_cb, NULL);
  1644. return rc;
  1645. }
  1646. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1647. {
  1648. switch (card->info.type) {
  1649. case QETH_CARD_TYPE_UNKNOWN:
  1650. return 1500;
  1651. case QETH_CARD_TYPE_IQD:
  1652. return card->info.max_mtu;
  1653. case QETH_CARD_TYPE_OSD:
  1654. switch (card->info.link_type) {
  1655. case QETH_LINK_TYPE_HSTR:
  1656. case QETH_LINK_TYPE_LANE_TR:
  1657. return 2000;
  1658. default:
  1659. return 1492;
  1660. }
  1661. case QETH_CARD_TYPE_OSM:
  1662. case QETH_CARD_TYPE_OSX:
  1663. return 1492;
  1664. default:
  1665. return 1500;
  1666. }
  1667. }
  1668. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1669. {
  1670. switch (framesize) {
  1671. case 0x4000:
  1672. return 8192;
  1673. case 0x6000:
  1674. return 16384;
  1675. case 0xa000:
  1676. return 32768;
  1677. case 0xffff:
  1678. return 57344;
  1679. default:
  1680. return 0;
  1681. }
  1682. }
  1683. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1684. {
  1685. switch (card->info.type) {
  1686. case QETH_CARD_TYPE_OSD:
  1687. case QETH_CARD_TYPE_OSM:
  1688. case QETH_CARD_TYPE_OSX:
  1689. case QETH_CARD_TYPE_IQD:
  1690. return ((mtu >= 576) &&
  1691. (mtu <= card->info.max_mtu));
  1692. case QETH_CARD_TYPE_OSN:
  1693. case QETH_CARD_TYPE_UNKNOWN:
  1694. default:
  1695. return 1;
  1696. }
  1697. }
  1698. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1699. unsigned long data)
  1700. {
  1701. __u16 mtu, framesize;
  1702. __u16 len;
  1703. __u8 link_type;
  1704. struct qeth_cmd_buffer *iob;
  1705. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1706. iob = (struct qeth_cmd_buffer *) data;
  1707. memcpy(&card->token.ulp_filter_r,
  1708. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1709. QETH_MPC_TOKEN_LENGTH);
  1710. if (card->info.type == QETH_CARD_TYPE_IQD) {
  1711. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1712. mtu = qeth_get_mtu_outof_framesize(framesize);
  1713. if (!mtu) {
  1714. iob->rc = -EINVAL;
  1715. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1716. return 0;
  1717. }
  1718. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  1719. /* frame size has changed */
  1720. if (card->dev &&
  1721. ((card->dev->mtu == card->info.initial_mtu) ||
  1722. (card->dev->mtu > mtu)))
  1723. card->dev->mtu = mtu;
  1724. qeth_free_qdio_buffers(card);
  1725. }
  1726. card->info.initial_mtu = mtu;
  1727. card->info.max_mtu = mtu;
  1728. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1729. } else {
  1730. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1731. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  1732. iob->data);
  1733. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1734. }
  1735. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1736. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1737. memcpy(&link_type,
  1738. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1739. card->info.link_type = link_type;
  1740. } else
  1741. card->info.link_type = 0;
  1742. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  1743. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1744. return 0;
  1745. }
  1746. static int qeth_ulp_enable(struct qeth_card *card)
  1747. {
  1748. int rc;
  1749. char prot_type;
  1750. struct qeth_cmd_buffer *iob;
  1751. /*FIXME: trace view callbacks*/
  1752. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1753. iob = qeth_wait_for_buffer(&card->write);
  1754. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1755. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1756. (__u8) card->info.portno;
  1757. if (card->options.layer2)
  1758. if (card->info.type == QETH_CARD_TYPE_OSN)
  1759. prot_type = QETH_PROT_OSN2;
  1760. else
  1761. prot_type = QETH_PROT_LAYER2;
  1762. else
  1763. prot_type = QETH_PROT_TCPIP;
  1764. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1765. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1766. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1767. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1768. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1769. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1770. card->info.portname, 9);
  1771. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1772. qeth_ulp_enable_cb, NULL);
  1773. return rc;
  1774. }
  1775. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1776. unsigned long data)
  1777. {
  1778. struct qeth_cmd_buffer *iob;
  1779. int rc = 0;
  1780. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1781. iob = (struct qeth_cmd_buffer *) data;
  1782. memcpy(&card->token.ulp_connection_r,
  1783. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1784. QETH_MPC_TOKEN_LENGTH);
  1785. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1786. 3)) {
  1787. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  1788. dev_err(&card->gdev->dev, "A connection could not be "
  1789. "established because of an OLM limit\n");
  1790. iob->rc = -EMLINK;
  1791. }
  1792. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1793. return rc;
  1794. }
  1795. static int qeth_ulp_setup(struct qeth_card *card)
  1796. {
  1797. int rc;
  1798. __u16 temp;
  1799. struct qeth_cmd_buffer *iob;
  1800. struct ccw_dev_id dev_id;
  1801. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1802. iob = qeth_wait_for_buffer(&card->write);
  1803. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1804. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1805. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1806. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1807. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1808. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1809. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1810. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1811. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1812. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1813. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1814. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1815. qeth_ulp_setup_cb, NULL);
  1816. return rc;
  1817. }
  1818. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1819. {
  1820. int i, j;
  1821. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1822. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1823. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1824. return 0;
  1825. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1826. GFP_KERNEL);
  1827. if (!card->qdio.in_q)
  1828. goto out_nomem;
  1829. QETH_DBF_TEXT(SETUP, 2, "inq");
  1830. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1831. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1832. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1833. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1834. card->qdio.in_q->bufs[i].buffer =
  1835. &card->qdio.in_q->qdio_bufs[i];
  1836. /* inbound buffer pool */
  1837. if (qeth_alloc_buffer_pool(card))
  1838. goto out_freeinq;
  1839. /* outbound */
  1840. card->qdio.out_qs =
  1841. kmalloc(card->qdio.no_out_queues *
  1842. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1843. if (!card->qdio.out_qs)
  1844. goto out_freepool;
  1845. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1846. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1847. GFP_KERNEL);
  1848. if (!card->qdio.out_qs[i])
  1849. goto out_freeoutq;
  1850. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1851. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1852. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1853. card->qdio.out_qs[i]->queue_no = i;
  1854. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1855. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1856. card->qdio.out_qs[i]->bufs[j].buffer =
  1857. &card->qdio.out_qs[i]->qdio_bufs[j];
  1858. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1859. skb_list);
  1860. lockdep_set_class(
  1861. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1862. &qdio_out_skb_queue_key);
  1863. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1864. }
  1865. }
  1866. return 0;
  1867. out_freeoutq:
  1868. while (i > 0)
  1869. kfree(card->qdio.out_qs[--i]);
  1870. kfree(card->qdio.out_qs);
  1871. card->qdio.out_qs = NULL;
  1872. out_freepool:
  1873. qeth_free_buffer_pool(card);
  1874. out_freeinq:
  1875. kfree(card->qdio.in_q);
  1876. card->qdio.in_q = NULL;
  1877. out_nomem:
  1878. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1879. return -ENOMEM;
  1880. }
  1881. static void qeth_create_qib_param_field(struct qeth_card *card,
  1882. char *param_field)
  1883. {
  1884. param_field[0] = _ascebc['P'];
  1885. param_field[1] = _ascebc['C'];
  1886. param_field[2] = _ascebc['I'];
  1887. param_field[3] = _ascebc['T'];
  1888. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1889. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1890. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1891. }
  1892. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1893. char *param_field)
  1894. {
  1895. param_field[16] = _ascebc['B'];
  1896. param_field[17] = _ascebc['L'];
  1897. param_field[18] = _ascebc['K'];
  1898. param_field[19] = _ascebc['T'];
  1899. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1900. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1901. *((unsigned int *) (&param_field[28])) =
  1902. card->info.blkt.inter_packet_jumbo;
  1903. }
  1904. static int qeth_qdio_activate(struct qeth_card *card)
  1905. {
  1906. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1907. return qdio_activate(CARD_DDEV(card));
  1908. }
  1909. static int qeth_dm_act(struct qeth_card *card)
  1910. {
  1911. int rc;
  1912. struct qeth_cmd_buffer *iob;
  1913. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1914. iob = qeth_wait_for_buffer(&card->write);
  1915. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1916. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1917. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1918. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1919. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1920. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1921. return rc;
  1922. }
  1923. static int qeth_mpc_initialize(struct qeth_card *card)
  1924. {
  1925. int rc;
  1926. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1927. rc = qeth_issue_next_read(card);
  1928. if (rc) {
  1929. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1930. return rc;
  1931. }
  1932. rc = qeth_cm_enable(card);
  1933. if (rc) {
  1934. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1935. goto out_qdio;
  1936. }
  1937. rc = qeth_cm_setup(card);
  1938. if (rc) {
  1939. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1940. goto out_qdio;
  1941. }
  1942. rc = qeth_ulp_enable(card);
  1943. if (rc) {
  1944. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1945. goto out_qdio;
  1946. }
  1947. rc = qeth_ulp_setup(card);
  1948. if (rc) {
  1949. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1950. goto out_qdio;
  1951. }
  1952. rc = qeth_alloc_qdio_buffers(card);
  1953. if (rc) {
  1954. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1955. goto out_qdio;
  1956. }
  1957. rc = qeth_qdio_establish(card);
  1958. if (rc) {
  1959. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1960. qeth_free_qdio_buffers(card);
  1961. goto out_qdio;
  1962. }
  1963. rc = qeth_qdio_activate(card);
  1964. if (rc) {
  1965. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1966. goto out_qdio;
  1967. }
  1968. rc = qeth_dm_act(card);
  1969. if (rc) {
  1970. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1971. goto out_qdio;
  1972. }
  1973. return 0;
  1974. out_qdio:
  1975. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1976. return rc;
  1977. }
  1978. static void qeth_print_status_with_portname(struct qeth_card *card)
  1979. {
  1980. char dbf_text[15];
  1981. int i;
  1982. sprintf(dbf_text, "%s", card->info.portname + 1);
  1983. for (i = 0; i < 8; i++)
  1984. dbf_text[i] =
  1985. (char) _ebcasc[(__u8) dbf_text[i]];
  1986. dbf_text[8] = 0;
  1987. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  1988. "with link type %s (portname: %s)\n",
  1989. qeth_get_cardname(card),
  1990. (card->info.mcl_level[0]) ? " (level: " : "",
  1991. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1992. (card->info.mcl_level[0]) ? ")" : "",
  1993. qeth_get_cardname_short(card),
  1994. dbf_text);
  1995. }
  1996. static void qeth_print_status_no_portname(struct qeth_card *card)
  1997. {
  1998. if (card->info.portname[0])
  1999. dev_info(&card->gdev->dev, "Device is a%s "
  2000. "card%s%s%s\nwith link type %s "
  2001. "(no portname needed by interface).\n",
  2002. qeth_get_cardname(card),
  2003. (card->info.mcl_level[0]) ? " (level: " : "",
  2004. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2005. (card->info.mcl_level[0]) ? ")" : "",
  2006. qeth_get_cardname_short(card));
  2007. else
  2008. dev_info(&card->gdev->dev, "Device is a%s "
  2009. "card%s%s%s\nwith link type %s.\n",
  2010. qeth_get_cardname(card),
  2011. (card->info.mcl_level[0]) ? " (level: " : "",
  2012. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2013. (card->info.mcl_level[0]) ? ")" : "",
  2014. qeth_get_cardname_short(card));
  2015. }
  2016. void qeth_print_status_message(struct qeth_card *card)
  2017. {
  2018. switch (card->info.type) {
  2019. case QETH_CARD_TYPE_OSD:
  2020. case QETH_CARD_TYPE_OSM:
  2021. case QETH_CARD_TYPE_OSX:
  2022. /* VM will use a non-zero first character
  2023. * to indicate a HiperSockets like reporting
  2024. * of the level OSA sets the first character to zero
  2025. * */
  2026. if (!card->info.mcl_level[0]) {
  2027. sprintf(card->info.mcl_level, "%02x%02x",
  2028. card->info.mcl_level[2],
  2029. card->info.mcl_level[3]);
  2030. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2031. break;
  2032. }
  2033. /* fallthrough */
  2034. case QETH_CARD_TYPE_IQD:
  2035. if ((card->info.guestlan) ||
  2036. (card->info.mcl_level[0] & 0x80)) {
  2037. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2038. card->info.mcl_level[0]];
  2039. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2040. card->info.mcl_level[1]];
  2041. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2042. card->info.mcl_level[2]];
  2043. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2044. card->info.mcl_level[3]];
  2045. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2046. }
  2047. break;
  2048. default:
  2049. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2050. }
  2051. if (card->info.portname_required)
  2052. qeth_print_status_with_portname(card);
  2053. else
  2054. qeth_print_status_no_portname(card);
  2055. }
  2056. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2057. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2058. {
  2059. struct qeth_buffer_pool_entry *entry;
  2060. QETH_CARD_TEXT(card, 5, "inwrklst");
  2061. list_for_each_entry(entry,
  2062. &card->qdio.init_pool.entry_list, init_list) {
  2063. qeth_put_buffer_pool_entry(card, entry);
  2064. }
  2065. }
  2066. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2067. struct qeth_card *card)
  2068. {
  2069. struct list_head *plh;
  2070. struct qeth_buffer_pool_entry *entry;
  2071. int i, free;
  2072. struct page *page;
  2073. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2074. return NULL;
  2075. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2076. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2077. free = 1;
  2078. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2079. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2080. free = 0;
  2081. break;
  2082. }
  2083. }
  2084. if (free) {
  2085. list_del_init(&entry->list);
  2086. return entry;
  2087. }
  2088. }
  2089. /* no free buffer in pool so take first one and swap pages */
  2090. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2091. struct qeth_buffer_pool_entry, list);
  2092. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2093. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2094. page = alloc_page(GFP_ATOMIC);
  2095. if (!page) {
  2096. return NULL;
  2097. } else {
  2098. free_page((unsigned long)entry->elements[i]);
  2099. entry->elements[i] = page_address(page);
  2100. if (card->options.performance_stats)
  2101. card->perf_stats.sg_alloc_page_rx++;
  2102. }
  2103. }
  2104. }
  2105. list_del_init(&entry->list);
  2106. return entry;
  2107. }
  2108. static int qeth_init_input_buffer(struct qeth_card *card,
  2109. struct qeth_qdio_buffer *buf)
  2110. {
  2111. struct qeth_buffer_pool_entry *pool_entry;
  2112. int i;
  2113. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2114. if (!pool_entry)
  2115. return 1;
  2116. /*
  2117. * since the buffer is accessed only from the input_tasklet
  2118. * there shouldn't be a need to synchronize; also, since we use
  2119. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2120. * buffers
  2121. */
  2122. buf->pool_entry = pool_entry;
  2123. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2124. buf->buffer->element[i].length = PAGE_SIZE;
  2125. buf->buffer->element[i].addr = pool_entry->elements[i];
  2126. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2127. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2128. else
  2129. buf->buffer->element[i].flags = 0;
  2130. }
  2131. return 0;
  2132. }
  2133. int qeth_init_qdio_queues(struct qeth_card *card)
  2134. {
  2135. int i, j;
  2136. int rc;
  2137. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2138. /* inbound queue */
  2139. memset(card->qdio.in_q->qdio_bufs, 0,
  2140. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2141. qeth_initialize_working_pool_list(card);
  2142. /*give only as many buffers to hardware as we have buffer pool entries*/
  2143. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2144. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2145. card->qdio.in_q->next_buf_to_init =
  2146. card->qdio.in_buf_pool.buf_count - 1;
  2147. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2148. card->qdio.in_buf_pool.buf_count - 1);
  2149. if (rc) {
  2150. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2151. return rc;
  2152. }
  2153. /* outbound queue */
  2154. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2155. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2156. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2157. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2158. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2159. &card->qdio.out_qs[i]->bufs[j]);
  2160. }
  2161. card->qdio.out_qs[i]->card = card;
  2162. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2163. card->qdio.out_qs[i]->do_pack = 0;
  2164. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2165. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2166. atomic_set(&card->qdio.out_qs[i]->state,
  2167. QETH_OUT_Q_UNLOCKED);
  2168. }
  2169. return 0;
  2170. }
  2171. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2172. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2173. {
  2174. switch (link_type) {
  2175. case QETH_LINK_TYPE_HSTR:
  2176. return 2;
  2177. default:
  2178. return 1;
  2179. }
  2180. }
  2181. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2182. struct qeth_ipa_cmd *cmd, __u8 command,
  2183. enum qeth_prot_versions prot)
  2184. {
  2185. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2186. cmd->hdr.command = command;
  2187. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2188. cmd->hdr.seqno = card->seqno.ipa;
  2189. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2190. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2191. if (card->options.layer2)
  2192. cmd->hdr.prim_version_no = 2;
  2193. else
  2194. cmd->hdr.prim_version_no = 1;
  2195. cmd->hdr.param_count = 1;
  2196. cmd->hdr.prot_version = prot;
  2197. cmd->hdr.ipa_supported = 0;
  2198. cmd->hdr.ipa_enabled = 0;
  2199. }
  2200. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2201. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2202. {
  2203. struct qeth_cmd_buffer *iob;
  2204. struct qeth_ipa_cmd *cmd;
  2205. iob = qeth_wait_for_buffer(&card->write);
  2206. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2207. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2208. return iob;
  2209. }
  2210. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2211. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2212. char prot_type)
  2213. {
  2214. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2215. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2216. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2217. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2218. }
  2219. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2220. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2221. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2222. unsigned long),
  2223. void *reply_param)
  2224. {
  2225. int rc;
  2226. char prot_type;
  2227. QETH_CARD_TEXT(card, 4, "sendipa");
  2228. if (card->options.layer2)
  2229. if (card->info.type == QETH_CARD_TYPE_OSN)
  2230. prot_type = QETH_PROT_OSN2;
  2231. else
  2232. prot_type = QETH_PROT_LAYER2;
  2233. else
  2234. prot_type = QETH_PROT_TCPIP;
  2235. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2236. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2237. iob, reply_cb, reply_param);
  2238. if (rc == -ETIME) {
  2239. qeth_clear_ipacmd_list(card);
  2240. qeth_schedule_recovery(card);
  2241. }
  2242. return rc;
  2243. }
  2244. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2245. int qeth_send_startlan(struct qeth_card *card)
  2246. {
  2247. int rc;
  2248. struct qeth_cmd_buffer *iob;
  2249. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2250. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2251. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2252. return rc;
  2253. }
  2254. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2255. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2256. struct qeth_reply *reply, unsigned long data)
  2257. {
  2258. struct qeth_ipa_cmd *cmd;
  2259. QETH_CARD_TEXT(card, 4, "defadpcb");
  2260. cmd = (struct qeth_ipa_cmd *) data;
  2261. if (cmd->hdr.return_code == 0)
  2262. cmd->hdr.return_code =
  2263. cmd->data.setadapterparms.hdr.return_code;
  2264. return 0;
  2265. }
  2266. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2267. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2268. struct qeth_reply *reply, unsigned long data)
  2269. {
  2270. struct qeth_ipa_cmd *cmd;
  2271. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2272. cmd = (struct qeth_ipa_cmd *) data;
  2273. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2274. card->info.link_type =
  2275. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2276. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2277. }
  2278. card->options.adp.supported_funcs =
  2279. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2280. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2281. }
  2282. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2283. __u32 command, __u32 cmdlen)
  2284. {
  2285. struct qeth_cmd_buffer *iob;
  2286. struct qeth_ipa_cmd *cmd;
  2287. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2288. QETH_PROT_IPV4);
  2289. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2290. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2291. cmd->data.setadapterparms.hdr.command_code = command;
  2292. cmd->data.setadapterparms.hdr.used_total = 1;
  2293. cmd->data.setadapterparms.hdr.seq_no = 1;
  2294. return iob;
  2295. }
  2296. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2297. int qeth_query_setadapterparms(struct qeth_card *card)
  2298. {
  2299. int rc;
  2300. struct qeth_cmd_buffer *iob;
  2301. QETH_CARD_TEXT(card, 3, "queryadp");
  2302. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2303. sizeof(struct qeth_ipacmd_setadpparms));
  2304. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2305. return rc;
  2306. }
  2307. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2308. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2309. unsigned int qdio_error, const char *dbftext)
  2310. {
  2311. if (qdio_error) {
  2312. QETH_CARD_TEXT(card, 2, dbftext);
  2313. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2314. buf->element[15].flags & 0xff);
  2315. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2316. buf->element[14].flags & 0xff);
  2317. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2318. if ((buf->element[15].flags & 0xff) == 0x12) {
  2319. card->stats.rx_dropped++;
  2320. return 0;
  2321. } else
  2322. return 1;
  2323. }
  2324. return 0;
  2325. }
  2326. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2327. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2328. {
  2329. struct qeth_qdio_q *queue = card->qdio.in_q;
  2330. int count;
  2331. int i;
  2332. int rc;
  2333. int newcount = 0;
  2334. count = (index < queue->next_buf_to_init)?
  2335. card->qdio.in_buf_pool.buf_count -
  2336. (queue->next_buf_to_init - index) :
  2337. card->qdio.in_buf_pool.buf_count -
  2338. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2339. /* only requeue at a certain threshold to avoid SIGAs */
  2340. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2341. for (i = queue->next_buf_to_init;
  2342. i < queue->next_buf_to_init + count; ++i) {
  2343. if (qeth_init_input_buffer(card,
  2344. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2345. break;
  2346. } else {
  2347. newcount++;
  2348. }
  2349. }
  2350. if (newcount < count) {
  2351. /* we are in memory shortage so we switch back to
  2352. traditional skb allocation and drop packages */
  2353. atomic_set(&card->force_alloc_skb, 3);
  2354. count = newcount;
  2355. } else {
  2356. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2357. }
  2358. /*
  2359. * according to old code it should be avoided to requeue all
  2360. * 128 buffers in order to benefit from PCI avoidance.
  2361. * this function keeps at least one buffer (the buffer at
  2362. * 'index') un-requeued -> this buffer is the first buffer that
  2363. * will be requeued the next time
  2364. */
  2365. if (card->options.performance_stats) {
  2366. card->perf_stats.inbound_do_qdio_cnt++;
  2367. card->perf_stats.inbound_do_qdio_start_time =
  2368. qeth_get_micros();
  2369. }
  2370. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2371. queue->next_buf_to_init, count);
  2372. if (card->options.performance_stats)
  2373. card->perf_stats.inbound_do_qdio_time +=
  2374. qeth_get_micros() -
  2375. card->perf_stats.inbound_do_qdio_start_time;
  2376. if (rc) {
  2377. dev_warn(&card->gdev->dev,
  2378. "QDIO reported an error, rc=%i\n", rc);
  2379. QETH_CARD_TEXT(card, 2, "qinberr");
  2380. }
  2381. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2382. QDIO_MAX_BUFFERS_PER_Q;
  2383. }
  2384. }
  2385. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2386. static int qeth_handle_send_error(struct qeth_card *card,
  2387. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2388. {
  2389. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2390. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2391. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2392. if (sbalf15 == 0) {
  2393. qdio_err = 0;
  2394. } else {
  2395. qdio_err = 1;
  2396. }
  2397. }
  2398. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2399. if (!qdio_err)
  2400. return QETH_SEND_ERROR_NONE;
  2401. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2402. return QETH_SEND_ERROR_RETRY;
  2403. QETH_CARD_TEXT(card, 1, "lnkfail");
  2404. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2405. (u16)qdio_err, (u8)sbalf15);
  2406. return QETH_SEND_ERROR_LINK_FAILURE;
  2407. }
  2408. /*
  2409. * Switched to packing state if the number of used buffers on a queue
  2410. * reaches a certain limit.
  2411. */
  2412. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2413. {
  2414. if (!queue->do_pack) {
  2415. if (atomic_read(&queue->used_buffers)
  2416. >= QETH_HIGH_WATERMARK_PACK){
  2417. /* switch non-PACKING -> PACKING */
  2418. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2419. if (queue->card->options.performance_stats)
  2420. queue->card->perf_stats.sc_dp_p++;
  2421. queue->do_pack = 1;
  2422. }
  2423. }
  2424. }
  2425. /*
  2426. * Switches from packing to non-packing mode. If there is a packing
  2427. * buffer on the queue this buffer will be prepared to be flushed.
  2428. * In that case 1 is returned to inform the caller. If no buffer
  2429. * has to be flushed, zero is returned.
  2430. */
  2431. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2432. {
  2433. struct qeth_qdio_out_buffer *buffer;
  2434. int flush_count = 0;
  2435. if (queue->do_pack) {
  2436. if (atomic_read(&queue->used_buffers)
  2437. <= QETH_LOW_WATERMARK_PACK) {
  2438. /* switch PACKING -> non-PACKING */
  2439. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2440. if (queue->card->options.performance_stats)
  2441. queue->card->perf_stats.sc_p_dp++;
  2442. queue->do_pack = 0;
  2443. /* flush packing buffers */
  2444. buffer = &queue->bufs[queue->next_buf_to_fill];
  2445. if ((atomic_read(&buffer->state) ==
  2446. QETH_QDIO_BUF_EMPTY) &&
  2447. (buffer->next_element_to_fill > 0)) {
  2448. atomic_set(&buffer->state,
  2449. QETH_QDIO_BUF_PRIMED);
  2450. flush_count++;
  2451. queue->next_buf_to_fill =
  2452. (queue->next_buf_to_fill + 1) %
  2453. QDIO_MAX_BUFFERS_PER_Q;
  2454. }
  2455. }
  2456. }
  2457. return flush_count;
  2458. }
  2459. /*
  2460. * Called to flush a packing buffer if no more pci flags are on the queue.
  2461. * Checks if there is a packing buffer and prepares it to be flushed.
  2462. * In that case returns 1, otherwise zero.
  2463. */
  2464. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2465. {
  2466. struct qeth_qdio_out_buffer *buffer;
  2467. buffer = &queue->bufs[queue->next_buf_to_fill];
  2468. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2469. (buffer->next_element_to_fill > 0)) {
  2470. /* it's a packing buffer */
  2471. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2472. queue->next_buf_to_fill =
  2473. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2474. return 1;
  2475. }
  2476. return 0;
  2477. }
  2478. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2479. int count)
  2480. {
  2481. struct qeth_qdio_out_buffer *buf;
  2482. int rc;
  2483. int i;
  2484. unsigned int qdio_flags;
  2485. for (i = index; i < index + count; ++i) {
  2486. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2487. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2488. SBAL_FLAGS_LAST_ENTRY;
  2489. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2490. continue;
  2491. if (!queue->do_pack) {
  2492. if ((atomic_read(&queue->used_buffers) >=
  2493. (QETH_HIGH_WATERMARK_PACK -
  2494. QETH_WATERMARK_PACK_FUZZ)) &&
  2495. !atomic_read(&queue->set_pci_flags_count)) {
  2496. /* it's likely that we'll go to packing
  2497. * mode soon */
  2498. atomic_inc(&queue->set_pci_flags_count);
  2499. buf->buffer->element[0].flags |= 0x40;
  2500. }
  2501. } else {
  2502. if (!atomic_read(&queue->set_pci_flags_count)) {
  2503. /*
  2504. * there's no outstanding PCI any more, so we
  2505. * have to request a PCI to be sure the the PCI
  2506. * will wake at some time in the future then we
  2507. * can flush packed buffers that might still be
  2508. * hanging around, which can happen if no
  2509. * further send was requested by the stack
  2510. */
  2511. atomic_inc(&queue->set_pci_flags_count);
  2512. buf->buffer->element[0].flags |= 0x40;
  2513. }
  2514. }
  2515. }
  2516. queue->card->dev->trans_start = jiffies;
  2517. if (queue->card->options.performance_stats) {
  2518. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2519. queue->card->perf_stats.outbound_do_qdio_start_time =
  2520. qeth_get_micros();
  2521. }
  2522. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2523. if (atomic_read(&queue->set_pci_flags_count))
  2524. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2525. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2526. queue->queue_no, index, count);
  2527. if (queue->card->options.performance_stats)
  2528. queue->card->perf_stats.outbound_do_qdio_time +=
  2529. qeth_get_micros() -
  2530. queue->card->perf_stats.outbound_do_qdio_start_time;
  2531. atomic_add(count, &queue->used_buffers);
  2532. if (rc) {
  2533. queue->card->stats.tx_errors += count;
  2534. /* ignore temporary SIGA errors without busy condition */
  2535. if (rc == QDIO_ERROR_SIGA_TARGET)
  2536. return;
  2537. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2538. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  2539. /* this must not happen under normal circumstances. if it
  2540. * happens something is really wrong -> recover */
  2541. qeth_schedule_recovery(queue->card);
  2542. return;
  2543. }
  2544. if (queue->card->options.performance_stats)
  2545. queue->card->perf_stats.bufs_sent += count;
  2546. }
  2547. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2548. {
  2549. int index;
  2550. int flush_cnt = 0;
  2551. int q_was_packing = 0;
  2552. /*
  2553. * check if weed have to switch to non-packing mode or if
  2554. * we have to get a pci flag out on the queue
  2555. */
  2556. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2557. !atomic_read(&queue->set_pci_flags_count)) {
  2558. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2559. QETH_OUT_Q_UNLOCKED) {
  2560. /*
  2561. * If we get in here, there was no action in
  2562. * do_send_packet. So, we check if there is a
  2563. * packing buffer to be flushed here.
  2564. */
  2565. netif_stop_queue(queue->card->dev);
  2566. index = queue->next_buf_to_fill;
  2567. q_was_packing = queue->do_pack;
  2568. /* queue->do_pack may change */
  2569. barrier();
  2570. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2571. if (!flush_cnt &&
  2572. !atomic_read(&queue->set_pci_flags_count))
  2573. flush_cnt +=
  2574. qeth_flush_buffers_on_no_pci(queue);
  2575. if (queue->card->options.performance_stats &&
  2576. q_was_packing)
  2577. queue->card->perf_stats.bufs_sent_pack +=
  2578. flush_cnt;
  2579. if (flush_cnt)
  2580. qeth_flush_buffers(queue, index, flush_cnt);
  2581. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2582. }
  2583. }
  2584. }
  2585. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  2586. unsigned long card_ptr)
  2587. {
  2588. struct qeth_card *card = (struct qeth_card *)card_ptr;
  2589. if (card->dev && (card->dev->flags & IFF_UP))
  2590. napi_schedule(&card->napi);
  2591. }
  2592. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  2593. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  2594. unsigned int queue, int first_element, int count,
  2595. unsigned long card_ptr)
  2596. {
  2597. struct qeth_card *card = (struct qeth_card *)card_ptr;
  2598. if (qdio_err)
  2599. qeth_schedule_recovery(card);
  2600. }
  2601. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  2602. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2603. unsigned int qdio_error, int __queue, int first_element,
  2604. int count, unsigned long card_ptr)
  2605. {
  2606. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2607. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2608. struct qeth_qdio_out_buffer *buffer;
  2609. int i;
  2610. QETH_CARD_TEXT(card, 6, "qdouhdl");
  2611. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2612. QETH_CARD_TEXT(card, 2, "achkcond");
  2613. netif_stop_queue(card->dev);
  2614. qeth_schedule_recovery(card);
  2615. return;
  2616. }
  2617. if (card->options.performance_stats) {
  2618. card->perf_stats.outbound_handler_cnt++;
  2619. card->perf_stats.outbound_handler_start_time =
  2620. qeth_get_micros();
  2621. }
  2622. for (i = first_element; i < (first_element + count); ++i) {
  2623. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2624. qeth_handle_send_error(card, buffer, qdio_error);
  2625. qeth_clear_output_buffer(queue, buffer);
  2626. }
  2627. atomic_sub(count, &queue->used_buffers);
  2628. /* check if we need to do something on this outbound queue */
  2629. if (card->info.type != QETH_CARD_TYPE_IQD)
  2630. qeth_check_outbound_queue(queue);
  2631. netif_wake_queue(queue->card->dev);
  2632. if (card->options.performance_stats)
  2633. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2634. card->perf_stats.outbound_handler_start_time;
  2635. }
  2636. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2637. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2638. int ipv, int cast_type)
  2639. {
  2640. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  2641. card->info.type == QETH_CARD_TYPE_OSX))
  2642. return card->qdio.default_out_queue;
  2643. switch (card->qdio.no_out_queues) {
  2644. case 4:
  2645. if (cast_type && card->info.is_multicast_different)
  2646. return card->info.is_multicast_different &
  2647. (card->qdio.no_out_queues - 1);
  2648. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2649. const u8 tos = ip_hdr(skb)->tos;
  2650. if (card->qdio.do_prio_queueing ==
  2651. QETH_PRIO_Q_ING_TOS) {
  2652. if (tos & IP_TOS_NOTIMPORTANT)
  2653. return 3;
  2654. if (tos & IP_TOS_HIGHRELIABILITY)
  2655. return 2;
  2656. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2657. return 1;
  2658. if (tos & IP_TOS_LOWDELAY)
  2659. return 0;
  2660. }
  2661. if (card->qdio.do_prio_queueing ==
  2662. QETH_PRIO_Q_ING_PREC)
  2663. return 3 - (tos >> 6);
  2664. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2665. /* TODO: IPv6!!! */
  2666. }
  2667. return card->qdio.default_out_queue;
  2668. case 1: /* fallthrough for single-out-queue 1920-device */
  2669. default:
  2670. return card->qdio.default_out_queue;
  2671. }
  2672. }
  2673. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2674. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2675. struct sk_buff *skb, int elems)
  2676. {
  2677. int dlen = skb->len - skb->data_len;
  2678. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  2679. PFN_DOWN((unsigned long)skb->data);
  2680. elements_needed += skb_shinfo(skb)->nr_frags;
  2681. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2682. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2683. "(Number=%d / Length=%d). Discarded.\n",
  2684. (elements_needed+elems), skb->len);
  2685. return 0;
  2686. }
  2687. return elements_needed;
  2688. }
  2689. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2690. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  2691. {
  2692. int hroom, inpage, rest;
  2693. if (((unsigned long)skb->data & PAGE_MASK) !=
  2694. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  2695. hroom = skb_headroom(skb);
  2696. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  2697. rest = len - inpage;
  2698. if (rest > hroom)
  2699. return 1;
  2700. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  2701. skb->data -= rest;
  2702. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  2703. }
  2704. return 0;
  2705. }
  2706. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  2707. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2708. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2709. int offset)
  2710. {
  2711. int length = skb->len - skb->data_len;
  2712. int length_here;
  2713. int element;
  2714. char *data;
  2715. int first_lap, cnt;
  2716. struct skb_frag_struct *frag;
  2717. element = *next_element_to_fill;
  2718. data = skb->data;
  2719. first_lap = (is_tso == 0 ? 1 : 0);
  2720. if (offset >= 0) {
  2721. data = skb->data + offset;
  2722. length -= offset;
  2723. first_lap = 0;
  2724. }
  2725. while (length > 0) {
  2726. /* length_here is the remaining amount of data in this page */
  2727. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2728. if (length < length_here)
  2729. length_here = length;
  2730. buffer->element[element].addr = data;
  2731. buffer->element[element].length = length_here;
  2732. length -= length_here;
  2733. if (!length) {
  2734. if (first_lap)
  2735. if (skb_shinfo(skb)->nr_frags)
  2736. buffer->element[element].flags =
  2737. SBAL_FLAGS_FIRST_FRAG;
  2738. else
  2739. buffer->element[element].flags = 0;
  2740. else
  2741. buffer->element[element].flags =
  2742. SBAL_FLAGS_MIDDLE_FRAG;
  2743. } else {
  2744. if (first_lap)
  2745. buffer->element[element].flags =
  2746. SBAL_FLAGS_FIRST_FRAG;
  2747. else
  2748. buffer->element[element].flags =
  2749. SBAL_FLAGS_MIDDLE_FRAG;
  2750. }
  2751. data += length_here;
  2752. element++;
  2753. first_lap = 0;
  2754. }
  2755. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  2756. frag = &skb_shinfo(skb)->frags[cnt];
  2757. buffer->element[element].addr = (char *)page_to_phys(frag->page)
  2758. + frag->page_offset;
  2759. buffer->element[element].length = frag->size;
  2760. buffer->element[element].flags = SBAL_FLAGS_MIDDLE_FRAG;
  2761. element++;
  2762. }
  2763. if (buffer->element[element - 1].flags)
  2764. buffer->element[element - 1].flags = SBAL_FLAGS_LAST_FRAG;
  2765. *next_element_to_fill = element;
  2766. }
  2767. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2768. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2769. struct qeth_hdr *hdr, int offset, int hd_len)
  2770. {
  2771. struct qdio_buffer *buffer;
  2772. int flush_cnt = 0, hdr_len, large_send = 0;
  2773. buffer = buf->buffer;
  2774. atomic_inc(&skb->users);
  2775. skb_queue_tail(&buf->skb_list, skb);
  2776. /*check first on TSO ....*/
  2777. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2778. int element = buf->next_element_to_fill;
  2779. hdr_len = sizeof(struct qeth_hdr_tso) +
  2780. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2781. /*fill first buffer entry only with header information */
  2782. buffer->element[element].addr = skb->data;
  2783. buffer->element[element].length = hdr_len;
  2784. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2785. buf->next_element_to_fill++;
  2786. skb->data += hdr_len;
  2787. skb->len -= hdr_len;
  2788. large_send = 1;
  2789. }
  2790. if (offset >= 0) {
  2791. int element = buf->next_element_to_fill;
  2792. buffer->element[element].addr = hdr;
  2793. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2794. hd_len;
  2795. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2796. buf->is_header[element] = 1;
  2797. buf->next_element_to_fill++;
  2798. }
  2799. __qeth_fill_buffer(skb, buffer, large_send,
  2800. (int *)&buf->next_element_to_fill, offset);
  2801. if (!queue->do_pack) {
  2802. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  2803. /* set state to PRIMED -> will be flushed */
  2804. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2805. flush_cnt = 1;
  2806. } else {
  2807. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  2808. if (queue->card->options.performance_stats)
  2809. queue->card->perf_stats.skbs_sent_pack++;
  2810. if (buf->next_element_to_fill >=
  2811. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2812. /*
  2813. * packed buffer if full -> set state PRIMED
  2814. * -> will be flushed
  2815. */
  2816. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2817. flush_cnt = 1;
  2818. }
  2819. }
  2820. return flush_cnt;
  2821. }
  2822. int qeth_do_send_packet_fast(struct qeth_card *card,
  2823. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2824. struct qeth_hdr *hdr, int elements_needed,
  2825. int offset, int hd_len)
  2826. {
  2827. struct qeth_qdio_out_buffer *buffer;
  2828. int index;
  2829. /* spin until we get the queue ... */
  2830. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2831. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2832. /* ... now we've got the queue */
  2833. index = queue->next_buf_to_fill;
  2834. buffer = &queue->bufs[queue->next_buf_to_fill];
  2835. /*
  2836. * check if buffer is empty to make sure that we do not 'overtake'
  2837. * ourselves and try to fill a buffer that is already primed
  2838. */
  2839. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2840. goto out;
  2841. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2842. QDIO_MAX_BUFFERS_PER_Q;
  2843. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2844. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2845. qeth_flush_buffers(queue, index, 1);
  2846. return 0;
  2847. out:
  2848. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2849. return -EBUSY;
  2850. }
  2851. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2852. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2853. struct sk_buff *skb, struct qeth_hdr *hdr,
  2854. int elements_needed)
  2855. {
  2856. struct qeth_qdio_out_buffer *buffer;
  2857. int start_index;
  2858. int flush_count = 0;
  2859. int do_pack = 0;
  2860. int tmp;
  2861. int rc = 0;
  2862. /* spin until we get the queue ... */
  2863. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2864. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2865. start_index = queue->next_buf_to_fill;
  2866. buffer = &queue->bufs[queue->next_buf_to_fill];
  2867. /*
  2868. * check if buffer is empty to make sure that we do not 'overtake'
  2869. * ourselves and try to fill a buffer that is already primed
  2870. */
  2871. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2872. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2873. return -EBUSY;
  2874. }
  2875. /* check if we need to switch packing state of this queue */
  2876. qeth_switch_to_packing_if_needed(queue);
  2877. if (queue->do_pack) {
  2878. do_pack = 1;
  2879. /* does packet fit in current buffer? */
  2880. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2881. buffer->next_element_to_fill) < elements_needed) {
  2882. /* ... no -> set state PRIMED */
  2883. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2884. flush_count++;
  2885. queue->next_buf_to_fill =
  2886. (queue->next_buf_to_fill + 1) %
  2887. QDIO_MAX_BUFFERS_PER_Q;
  2888. buffer = &queue->bufs[queue->next_buf_to_fill];
  2889. /* we did a step forward, so check buffer state
  2890. * again */
  2891. if (atomic_read(&buffer->state) !=
  2892. QETH_QDIO_BUF_EMPTY) {
  2893. qeth_flush_buffers(queue, start_index,
  2894. flush_count);
  2895. atomic_set(&queue->state,
  2896. QETH_OUT_Q_UNLOCKED);
  2897. return -EBUSY;
  2898. }
  2899. }
  2900. }
  2901. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2902. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2903. QDIO_MAX_BUFFERS_PER_Q;
  2904. flush_count += tmp;
  2905. if (flush_count)
  2906. qeth_flush_buffers(queue, start_index, flush_count);
  2907. else if (!atomic_read(&queue->set_pci_flags_count))
  2908. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2909. /*
  2910. * queue->state will go from LOCKED -> UNLOCKED or from
  2911. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2912. * (switch packing state or flush buffer to get another pci flag out).
  2913. * In that case we will enter this loop
  2914. */
  2915. while (atomic_dec_return(&queue->state)) {
  2916. flush_count = 0;
  2917. start_index = queue->next_buf_to_fill;
  2918. /* check if we can go back to non-packing state */
  2919. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2920. /*
  2921. * check if we need to flush a packing buffer to get a pci
  2922. * flag out on the queue
  2923. */
  2924. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2925. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2926. if (flush_count)
  2927. qeth_flush_buffers(queue, start_index, flush_count);
  2928. }
  2929. /* at this point the queue is UNLOCKED again */
  2930. if (queue->card->options.performance_stats && do_pack)
  2931. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2932. return rc;
  2933. }
  2934. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2935. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2936. struct qeth_reply *reply, unsigned long data)
  2937. {
  2938. struct qeth_ipa_cmd *cmd;
  2939. struct qeth_ipacmd_setadpparms *setparms;
  2940. QETH_CARD_TEXT(card, 4, "prmadpcb");
  2941. cmd = (struct qeth_ipa_cmd *) data;
  2942. setparms = &(cmd->data.setadapterparms);
  2943. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2944. if (cmd->hdr.return_code) {
  2945. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2946. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2947. }
  2948. card->info.promisc_mode = setparms->data.mode;
  2949. return 0;
  2950. }
  2951. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2952. {
  2953. enum qeth_ipa_promisc_modes mode;
  2954. struct net_device *dev = card->dev;
  2955. struct qeth_cmd_buffer *iob;
  2956. struct qeth_ipa_cmd *cmd;
  2957. QETH_CARD_TEXT(card, 4, "setprom");
  2958. if (((dev->flags & IFF_PROMISC) &&
  2959. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2960. (!(dev->flags & IFF_PROMISC) &&
  2961. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  2962. return;
  2963. mode = SET_PROMISC_MODE_OFF;
  2964. if (dev->flags & IFF_PROMISC)
  2965. mode = SET_PROMISC_MODE_ON;
  2966. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  2967. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  2968. sizeof(struct qeth_ipacmd_setadpparms));
  2969. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  2970. cmd->data.setadapterparms.data.mode = mode;
  2971. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  2972. }
  2973. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  2974. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  2975. {
  2976. struct qeth_card *card;
  2977. char dbf_text[15];
  2978. card = dev->ml_priv;
  2979. QETH_CARD_TEXT(card, 4, "chgmtu");
  2980. sprintf(dbf_text, "%8x", new_mtu);
  2981. QETH_CARD_TEXT(card, 4, dbf_text);
  2982. if (new_mtu < 64)
  2983. return -EINVAL;
  2984. if (new_mtu > 65535)
  2985. return -EINVAL;
  2986. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  2987. (!qeth_mtu_is_valid(card, new_mtu)))
  2988. return -EINVAL;
  2989. dev->mtu = new_mtu;
  2990. return 0;
  2991. }
  2992. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  2993. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  2994. {
  2995. struct qeth_card *card;
  2996. card = dev->ml_priv;
  2997. QETH_CARD_TEXT(card, 5, "getstat");
  2998. return &card->stats;
  2999. }
  3000. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3001. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3002. struct qeth_reply *reply, unsigned long data)
  3003. {
  3004. struct qeth_ipa_cmd *cmd;
  3005. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3006. cmd = (struct qeth_ipa_cmd *) data;
  3007. if (!card->options.layer2 ||
  3008. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3009. memcpy(card->dev->dev_addr,
  3010. &cmd->data.setadapterparms.data.change_addr.addr,
  3011. OSA_ADDR_LEN);
  3012. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3013. }
  3014. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3015. return 0;
  3016. }
  3017. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3018. {
  3019. int rc;
  3020. struct qeth_cmd_buffer *iob;
  3021. struct qeth_ipa_cmd *cmd;
  3022. QETH_CARD_TEXT(card, 4, "chgmac");
  3023. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3024. sizeof(struct qeth_ipacmd_setadpparms));
  3025. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3026. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3027. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3028. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3029. card->dev->dev_addr, OSA_ADDR_LEN);
  3030. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3031. NULL);
  3032. return rc;
  3033. }
  3034. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3035. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3036. struct qeth_reply *reply, unsigned long data)
  3037. {
  3038. struct qeth_ipa_cmd *cmd;
  3039. struct qeth_set_access_ctrl *access_ctrl_req;
  3040. QETH_CARD_TEXT(card, 4, "setaccb");
  3041. cmd = (struct qeth_ipa_cmd *) data;
  3042. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3043. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3044. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3045. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3046. cmd->data.setadapterparms.hdr.return_code);
  3047. switch (cmd->data.setadapterparms.hdr.return_code) {
  3048. case SET_ACCESS_CTRL_RC_SUCCESS:
  3049. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3050. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3051. {
  3052. card->options.isolation = access_ctrl_req->subcmd_code;
  3053. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3054. dev_info(&card->gdev->dev,
  3055. "QDIO data connection isolation is deactivated\n");
  3056. } else {
  3057. dev_info(&card->gdev->dev,
  3058. "QDIO data connection isolation is activated\n");
  3059. }
  3060. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3061. card->gdev->dev.kobj.name,
  3062. access_ctrl_req->subcmd_code,
  3063. cmd->data.setadapterparms.hdr.return_code);
  3064. break;
  3065. }
  3066. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3067. {
  3068. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3069. card->gdev->dev.kobj.name,
  3070. access_ctrl_req->subcmd_code,
  3071. cmd->data.setadapterparms.hdr.return_code);
  3072. dev_err(&card->gdev->dev, "Adapter does not "
  3073. "support QDIO data connection isolation\n");
  3074. /* ensure isolation mode is "none" */
  3075. card->options.isolation = ISOLATION_MODE_NONE;
  3076. break;
  3077. }
  3078. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3079. {
  3080. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3081. card->gdev->dev.kobj.name,
  3082. access_ctrl_req->subcmd_code,
  3083. cmd->data.setadapterparms.hdr.return_code);
  3084. dev_err(&card->gdev->dev,
  3085. "Adapter is dedicated. "
  3086. "QDIO data connection isolation not supported\n");
  3087. /* ensure isolation mode is "none" */
  3088. card->options.isolation = ISOLATION_MODE_NONE;
  3089. break;
  3090. }
  3091. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3092. {
  3093. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3094. card->gdev->dev.kobj.name,
  3095. access_ctrl_req->subcmd_code,
  3096. cmd->data.setadapterparms.hdr.return_code);
  3097. dev_err(&card->gdev->dev,
  3098. "TSO does not permit QDIO data connection isolation\n");
  3099. /* ensure isolation mode is "none" */
  3100. card->options.isolation = ISOLATION_MODE_NONE;
  3101. break;
  3102. }
  3103. default:
  3104. {
  3105. /* this should never happen */
  3106. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3107. "==UNKNOWN\n",
  3108. card->gdev->dev.kobj.name,
  3109. access_ctrl_req->subcmd_code,
  3110. cmd->data.setadapterparms.hdr.return_code);
  3111. /* ensure isolation mode is "none" */
  3112. card->options.isolation = ISOLATION_MODE_NONE;
  3113. break;
  3114. }
  3115. }
  3116. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3117. return 0;
  3118. }
  3119. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3120. enum qeth_ipa_isolation_modes isolation)
  3121. {
  3122. int rc;
  3123. struct qeth_cmd_buffer *iob;
  3124. struct qeth_ipa_cmd *cmd;
  3125. struct qeth_set_access_ctrl *access_ctrl_req;
  3126. QETH_CARD_TEXT(card, 4, "setacctl");
  3127. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3128. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3129. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3130. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3131. sizeof(struct qeth_set_access_ctrl));
  3132. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3133. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3134. access_ctrl_req->subcmd_code = isolation;
  3135. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3136. NULL);
  3137. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3138. return rc;
  3139. }
  3140. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3141. {
  3142. int rc = 0;
  3143. QETH_CARD_TEXT(card, 4, "setactlo");
  3144. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3145. card->info.type == QETH_CARD_TYPE_OSX) &&
  3146. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3147. rc = qeth_setadpparms_set_access_ctrl(card,
  3148. card->options.isolation);
  3149. if (rc) {
  3150. QETH_DBF_MESSAGE(3,
  3151. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3152. card->gdev->dev.kobj.name,
  3153. rc);
  3154. }
  3155. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3156. card->options.isolation = ISOLATION_MODE_NONE;
  3157. dev_err(&card->gdev->dev, "Adapter does not "
  3158. "support QDIO data connection isolation\n");
  3159. rc = -EOPNOTSUPP;
  3160. }
  3161. return rc;
  3162. }
  3163. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3164. void qeth_tx_timeout(struct net_device *dev)
  3165. {
  3166. struct qeth_card *card;
  3167. card = dev->ml_priv;
  3168. QETH_CARD_TEXT(card, 4, "txtimeo");
  3169. card->stats.tx_errors++;
  3170. qeth_schedule_recovery(card);
  3171. }
  3172. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3173. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3174. {
  3175. struct qeth_card *card = dev->ml_priv;
  3176. int rc = 0;
  3177. switch (regnum) {
  3178. case MII_BMCR: /* Basic mode control register */
  3179. rc = BMCR_FULLDPLX;
  3180. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3181. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3182. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3183. rc |= BMCR_SPEED100;
  3184. break;
  3185. case MII_BMSR: /* Basic mode status register */
  3186. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3187. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3188. BMSR_100BASE4;
  3189. break;
  3190. case MII_PHYSID1: /* PHYS ID 1 */
  3191. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3192. dev->dev_addr[2];
  3193. rc = (rc >> 5) & 0xFFFF;
  3194. break;
  3195. case MII_PHYSID2: /* PHYS ID 2 */
  3196. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3197. break;
  3198. case MII_ADVERTISE: /* Advertisement control reg */
  3199. rc = ADVERTISE_ALL;
  3200. break;
  3201. case MII_LPA: /* Link partner ability reg */
  3202. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3203. LPA_100BASE4 | LPA_LPACK;
  3204. break;
  3205. case MII_EXPANSION: /* Expansion register */
  3206. break;
  3207. case MII_DCOUNTER: /* disconnect counter */
  3208. break;
  3209. case MII_FCSCOUNTER: /* false carrier counter */
  3210. break;
  3211. case MII_NWAYTEST: /* N-way auto-neg test register */
  3212. break;
  3213. case MII_RERRCOUNTER: /* rx error counter */
  3214. rc = card->stats.rx_errors;
  3215. break;
  3216. case MII_SREVISION: /* silicon revision */
  3217. break;
  3218. case MII_RESV1: /* reserved 1 */
  3219. break;
  3220. case MII_LBRERROR: /* loopback, rx, bypass error */
  3221. break;
  3222. case MII_PHYADDR: /* physical address */
  3223. break;
  3224. case MII_RESV2: /* reserved 2 */
  3225. break;
  3226. case MII_TPISTATUS: /* TPI status for 10mbps */
  3227. break;
  3228. case MII_NCONFIG: /* network interface config */
  3229. break;
  3230. default:
  3231. break;
  3232. }
  3233. return rc;
  3234. }
  3235. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3236. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3237. struct qeth_cmd_buffer *iob, int len,
  3238. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3239. unsigned long),
  3240. void *reply_param)
  3241. {
  3242. u16 s1, s2;
  3243. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3244. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3245. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3246. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3247. /* adjust PDU length fields in IPA_PDU_HEADER */
  3248. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3249. s2 = (u32) len;
  3250. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3251. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3252. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3253. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3254. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3255. reply_cb, reply_param);
  3256. }
  3257. static int qeth_snmp_command_cb(struct qeth_card *card,
  3258. struct qeth_reply *reply, unsigned long sdata)
  3259. {
  3260. struct qeth_ipa_cmd *cmd;
  3261. struct qeth_arp_query_info *qinfo;
  3262. struct qeth_snmp_cmd *snmp;
  3263. unsigned char *data;
  3264. __u16 data_len;
  3265. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3266. cmd = (struct qeth_ipa_cmd *) sdata;
  3267. data = (unsigned char *)((char *)cmd - reply->offset);
  3268. qinfo = (struct qeth_arp_query_info *) reply->param;
  3269. snmp = &cmd->data.setadapterparms.data.snmp;
  3270. if (cmd->hdr.return_code) {
  3271. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3272. return 0;
  3273. }
  3274. if (cmd->data.setadapterparms.hdr.return_code) {
  3275. cmd->hdr.return_code =
  3276. cmd->data.setadapterparms.hdr.return_code;
  3277. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3278. return 0;
  3279. }
  3280. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3281. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3282. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3283. else
  3284. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3285. /* check if there is enough room in userspace */
  3286. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3287. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3288. cmd->hdr.return_code = -ENOMEM;
  3289. return 0;
  3290. }
  3291. QETH_CARD_TEXT_(card, 4, "snore%i",
  3292. cmd->data.setadapterparms.hdr.used_total);
  3293. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3294. cmd->data.setadapterparms.hdr.seq_no);
  3295. /*copy entries to user buffer*/
  3296. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3297. memcpy(qinfo->udata + qinfo->udata_offset,
  3298. (char *)snmp,
  3299. data_len + offsetof(struct qeth_snmp_cmd, data));
  3300. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3301. } else {
  3302. memcpy(qinfo->udata + qinfo->udata_offset,
  3303. (char *)&snmp->request, data_len);
  3304. }
  3305. qinfo->udata_offset += data_len;
  3306. /* check if all replies received ... */
  3307. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3308. cmd->data.setadapterparms.hdr.used_total);
  3309. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3310. cmd->data.setadapterparms.hdr.seq_no);
  3311. if (cmd->data.setadapterparms.hdr.seq_no <
  3312. cmd->data.setadapterparms.hdr.used_total)
  3313. return 1;
  3314. return 0;
  3315. }
  3316. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3317. {
  3318. struct qeth_cmd_buffer *iob;
  3319. struct qeth_ipa_cmd *cmd;
  3320. struct qeth_snmp_ureq *ureq;
  3321. int req_len;
  3322. struct qeth_arp_query_info qinfo = {0, };
  3323. int rc = 0;
  3324. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3325. if (card->info.guestlan)
  3326. return -EOPNOTSUPP;
  3327. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3328. (!card->options.layer2)) {
  3329. return -EOPNOTSUPP;
  3330. }
  3331. /* skip 4 bytes (data_len struct member) to get req_len */
  3332. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3333. return -EFAULT;
  3334. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  3335. if (IS_ERR(ureq)) {
  3336. QETH_CARD_TEXT(card, 2, "snmpnome");
  3337. return PTR_ERR(ureq);
  3338. }
  3339. qinfo.udata_len = ureq->hdr.data_len;
  3340. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3341. if (!qinfo.udata) {
  3342. kfree(ureq);
  3343. return -ENOMEM;
  3344. }
  3345. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3346. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3347. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3348. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3349. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3350. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3351. qeth_snmp_command_cb, (void *)&qinfo);
  3352. if (rc)
  3353. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3354. QETH_CARD_IFNAME(card), rc);
  3355. else {
  3356. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3357. rc = -EFAULT;
  3358. }
  3359. kfree(ureq);
  3360. kfree(qinfo.udata);
  3361. return rc;
  3362. }
  3363. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3364. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3365. {
  3366. switch (card->info.type) {
  3367. case QETH_CARD_TYPE_IQD:
  3368. return 2;
  3369. default:
  3370. return 0;
  3371. }
  3372. }
  3373. static void qeth_determine_capabilities(struct qeth_card *card)
  3374. {
  3375. int rc;
  3376. int length;
  3377. char *prcd;
  3378. struct ccw_device *ddev;
  3379. int ddev_offline = 0;
  3380. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3381. ddev = CARD_DDEV(card);
  3382. if (!ddev->online) {
  3383. ddev_offline = 1;
  3384. rc = ccw_device_set_online(ddev);
  3385. if (rc) {
  3386. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3387. goto out;
  3388. }
  3389. }
  3390. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3391. if (rc) {
  3392. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3393. dev_name(&card->gdev->dev), rc);
  3394. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3395. goto out_offline;
  3396. }
  3397. qeth_configure_unitaddr(card, prcd);
  3398. qeth_configure_blkt_default(card, prcd);
  3399. kfree(prcd);
  3400. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  3401. if (rc)
  3402. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3403. out_offline:
  3404. if (ddev_offline == 1)
  3405. ccw_device_set_offline(ddev);
  3406. out:
  3407. return;
  3408. }
  3409. static int qeth_qdio_establish(struct qeth_card *card)
  3410. {
  3411. struct qdio_initialize init_data;
  3412. char *qib_param_field;
  3413. struct qdio_buffer **in_sbal_ptrs;
  3414. struct qdio_buffer **out_sbal_ptrs;
  3415. int i, j, k;
  3416. int rc = 0;
  3417. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3418. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3419. GFP_KERNEL);
  3420. if (!qib_param_field)
  3421. return -ENOMEM;
  3422. qeth_create_qib_param_field(card, qib_param_field);
  3423. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3424. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3425. GFP_KERNEL);
  3426. if (!in_sbal_ptrs) {
  3427. kfree(qib_param_field);
  3428. return -ENOMEM;
  3429. }
  3430. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3431. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3432. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3433. out_sbal_ptrs =
  3434. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3435. sizeof(void *), GFP_KERNEL);
  3436. if (!out_sbal_ptrs) {
  3437. kfree(in_sbal_ptrs);
  3438. kfree(qib_param_field);
  3439. return -ENOMEM;
  3440. }
  3441. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3442. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3443. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3444. card->qdio.out_qs[i]->bufs[j].buffer);
  3445. }
  3446. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3447. init_data.cdev = CARD_DDEV(card);
  3448. init_data.q_format = qeth_get_qdio_q_format(card);
  3449. init_data.qib_param_field_format = 0;
  3450. init_data.qib_param_field = qib_param_field;
  3451. init_data.no_input_qs = 1;
  3452. init_data.no_output_qs = card->qdio.no_out_queues;
  3453. init_data.input_handler = card->discipline.input_handler;
  3454. init_data.output_handler = card->discipline.output_handler;
  3455. init_data.queue_start_poll = card->discipline.start_poll;
  3456. init_data.int_parm = (unsigned long) card;
  3457. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3458. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3459. init_data.scan_threshold =
  3460. (card->info.type == QETH_CARD_TYPE_IQD) ? 8 : 32;
  3461. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3462. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3463. rc = qdio_allocate(&init_data);
  3464. if (rc) {
  3465. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3466. goto out;
  3467. }
  3468. rc = qdio_establish(&init_data);
  3469. if (rc) {
  3470. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3471. qdio_free(CARD_DDEV(card));
  3472. }
  3473. }
  3474. out:
  3475. kfree(out_sbal_ptrs);
  3476. kfree(in_sbal_ptrs);
  3477. kfree(qib_param_field);
  3478. return rc;
  3479. }
  3480. static void qeth_core_free_card(struct qeth_card *card)
  3481. {
  3482. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3483. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3484. qeth_clean_channel(&card->read);
  3485. qeth_clean_channel(&card->write);
  3486. if (card->dev)
  3487. free_netdev(card->dev);
  3488. kfree(card->ip_tbd_list);
  3489. qeth_free_qdio_buffers(card);
  3490. unregister_service_level(&card->qeth_service_level);
  3491. kfree(card);
  3492. }
  3493. static struct ccw_device_id qeth_ids[] = {
  3494. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  3495. .driver_info = QETH_CARD_TYPE_OSD},
  3496. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  3497. .driver_info = QETH_CARD_TYPE_IQD},
  3498. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  3499. .driver_info = QETH_CARD_TYPE_OSN},
  3500. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  3501. .driver_info = QETH_CARD_TYPE_OSM},
  3502. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  3503. .driver_info = QETH_CARD_TYPE_OSX},
  3504. {},
  3505. };
  3506. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3507. static struct ccw_driver qeth_ccw_driver = {
  3508. .name = "qeth",
  3509. .ids = qeth_ids,
  3510. .probe = ccwgroup_probe_ccwdev,
  3511. .remove = ccwgroup_remove_ccwdev,
  3512. };
  3513. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3514. unsigned long driver_id)
  3515. {
  3516. return ccwgroup_create_from_string(root_dev, driver_id,
  3517. &qeth_ccw_driver, 3, buf);
  3518. }
  3519. int qeth_core_hardsetup_card(struct qeth_card *card)
  3520. {
  3521. int retries = 0;
  3522. int rc;
  3523. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3524. atomic_set(&card->force_alloc_skb, 0);
  3525. qeth_get_channel_path_desc(card);
  3526. retry:
  3527. if (retries)
  3528. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  3529. dev_name(&card->gdev->dev));
  3530. ccw_device_set_offline(CARD_DDEV(card));
  3531. ccw_device_set_offline(CARD_WDEV(card));
  3532. ccw_device_set_offline(CARD_RDEV(card));
  3533. rc = ccw_device_set_online(CARD_RDEV(card));
  3534. if (rc)
  3535. goto retriable;
  3536. rc = ccw_device_set_online(CARD_WDEV(card));
  3537. if (rc)
  3538. goto retriable;
  3539. rc = ccw_device_set_online(CARD_DDEV(card));
  3540. if (rc)
  3541. goto retriable;
  3542. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3543. retriable:
  3544. if (rc == -ERESTARTSYS) {
  3545. QETH_DBF_TEXT(SETUP, 2, "break1");
  3546. return rc;
  3547. } else if (rc) {
  3548. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3549. if (++retries > 3)
  3550. goto out;
  3551. else
  3552. goto retry;
  3553. }
  3554. qeth_determine_capabilities(card);
  3555. qeth_init_tokens(card);
  3556. qeth_init_func_level(card);
  3557. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3558. if (rc == -ERESTARTSYS) {
  3559. QETH_DBF_TEXT(SETUP, 2, "break2");
  3560. return rc;
  3561. } else if (rc) {
  3562. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3563. if (--retries < 0)
  3564. goto out;
  3565. else
  3566. goto retry;
  3567. }
  3568. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3569. if (rc == -ERESTARTSYS) {
  3570. QETH_DBF_TEXT(SETUP, 2, "break3");
  3571. return rc;
  3572. } else if (rc) {
  3573. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3574. if (--retries < 0)
  3575. goto out;
  3576. else
  3577. goto retry;
  3578. }
  3579. card->read_or_write_problem = 0;
  3580. rc = qeth_mpc_initialize(card);
  3581. if (rc) {
  3582. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3583. goto out;
  3584. }
  3585. return 0;
  3586. out:
  3587. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  3588. "an error on the device\n");
  3589. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  3590. dev_name(&card->gdev->dev), rc);
  3591. return rc;
  3592. }
  3593. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3594. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3595. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3596. {
  3597. struct page *page = virt_to_page(element->addr);
  3598. if (*pskb == NULL) {
  3599. /* the upper protocol layers assume that there is data in the
  3600. * skb itself. Copy a small amount (64 bytes) to make them
  3601. * happy. */
  3602. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3603. if (!(*pskb))
  3604. return -ENOMEM;
  3605. skb_reserve(*pskb, ETH_HLEN);
  3606. if (data_len <= 64) {
  3607. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3608. data_len);
  3609. } else {
  3610. get_page(page);
  3611. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3612. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3613. data_len - 64);
  3614. (*pskb)->data_len += data_len - 64;
  3615. (*pskb)->len += data_len - 64;
  3616. (*pskb)->truesize += data_len - 64;
  3617. (*pfrag)++;
  3618. }
  3619. } else {
  3620. get_page(page);
  3621. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3622. (*pskb)->data_len += data_len;
  3623. (*pskb)->len += data_len;
  3624. (*pskb)->truesize += data_len;
  3625. (*pfrag)++;
  3626. }
  3627. return 0;
  3628. }
  3629. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3630. struct qdio_buffer *buffer,
  3631. struct qdio_buffer_element **__element, int *__offset,
  3632. struct qeth_hdr **hdr)
  3633. {
  3634. struct qdio_buffer_element *element = *__element;
  3635. int offset = *__offset;
  3636. struct sk_buff *skb = NULL;
  3637. int skb_len = 0;
  3638. void *data_ptr;
  3639. int data_len;
  3640. int headroom = 0;
  3641. int use_rx_sg = 0;
  3642. int frag = 0;
  3643. /* qeth_hdr must not cross element boundaries */
  3644. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3645. if (qeth_is_last_sbale(element))
  3646. return NULL;
  3647. element++;
  3648. offset = 0;
  3649. if (element->length < sizeof(struct qeth_hdr))
  3650. return NULL;
  3651. }
  3652. *hdr = element->addr + offset;
  3653. offset += sizeof(struct qeth_hdr);
  3654. switch ((*hdr)->hdr.l2.id) {
  3655. case QETH_HEADER_TYPE_LAYER2:
  3656. skb_len = (*hdr)->hdr.l2.pkt_length;
  3657. break;
  3658. case QETH_HEADER_TYPE_LAYER3:
  3659. skb_len = (*hdr)->hdr.l3.length;
  3660. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3661. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3662. headroom = TR_HLEN;
  3663. else
  3664. headroom = ETH_HLEN;
  3665. break;
  3666. case QETH_HEADER_TYPE_OSN:
  3667. skb_len = (*hdr)->hdr.osn.pdu_length;
  3668. headroom = sizeof(struct qeth_hdr);
  3669. break;
  3670. default:
  3671. break;
  3672. }
  3673. if (!skb_len)
  3674. return NULL;
  3675. if ((skb_len >= card->options.rx_sg_cb) &&
  3676. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3677. (!atomic_read(&card->force_alloc_skb))) {
  3678. use_rx_sg = 1;
  3679. } else {
  3680. skb = dev_alloc_skb(skb_len + headroom);
  3681. if (!skb)
  3682. goto no_mem;
  3683. if (headroom)
  3684. skb_reserve(skb, headroom);
  3685. }
  3686. data_ptr = element->addr + offset;
  3687. while (skb_len) {
  3688. data_len = min(skb_len, (int)(element->length - offset));
  3689. if (data_len) {
  3690. if (use_rx_sg) {
  3691. if (qeth_create_skb_frag(element, &skb, offset,
  3692. &frag, data_len))
  3693. goto no_mem;
  3694. } else {
  3695. memcpy(skb_put(skb, data_len), data_ptr,
  3696. data_len);
  3697. }
  3698. }
  3699. skb_len -= data_len;
  3700. if (skb_len) {
  3701. if (qeth_is_last_sbale(element)) {
  3702. QETH_CARD_TEXT(card, 4, "unexeob");
  3703. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  3704. dev_kfree_skb_any(skb);
  3705. card->stats.rx_errors++;
  3706. return NULL;
  3707. }
  3708. element++;
  3709. offset = 0;
  3710. data_ptr = element->addr;
  3711. } else {
  3712. offset += data_len;
  3713. }
  3714. }
  3715. *__element = element;
  3716. *__offset = offset;
  3717. if (use_rx_sg && card->options.performance_stats) {
  3718. card->perf_stats.sg_skbs_rx++;
  3719. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3720. }
  3721. return skb;
  3722. no_mem:
  3723. if (net_ratelimit()) {
  3724. QETH_CARD_TEXT(card, 2, "noskbmem");
  3725. }
  3726. card->stats.rx_dropped++;
  3727. return NULL;
  3728. }
  3729. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3730. static void qeth_unregister_dbf_views(void)
  3731. {
  3732. int x;
  3733. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3734. debug_unregister(qeth_dbf[x].id);
  3735. qeth_dbf[x].id = NULL;
  3736. }
  3737. }
  3738. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  3739. {
  3740. char dbf_txt_buf[32];
  3741. va_list args;
  3742. if (level > id->level)
  3743. return;
  3744. va_start(args, fmt);
  3745. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3746. va_end(args);
  3747. debug_text_event(id, level, dbf_txt_buf);
  3748. }
  3749. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3750. static int qeth_register_dbf_views(void)
  3751. {
  3752. int ret;
  3753. int x;
  3754. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3755. /* register the areas */
  3756. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3757. qeth_dbf[x].pages,
  3758. qeth_dbf[x].areas,
  3759. qeth_dbf[x].len);
  3760. if (qeth_dbf[x].id == NULL) {
  3761. qeth_unregister_dbf_views();
  3762. return -ENOMEM;
  3763. }
  3764. /* register a view */
  3765. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3766. if (ret) {
  3767. qeth_unregister_dbf_views();
  3768. return ret;
  3769. }
  3770. /* set a passing level */
  3771. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3772. }
  3773. return 0;
  3774. }
  3775. int qeth_core_load_discipline(struct qeth_card *card,
  3776. enum qeth_discipline_id discipline)
  3777. {
  3778. int rc = 0;
  3779. switch (discipline) {
  3780. case QETH_DISCIPLINE_LAYER3:
  3781. card->discipline.ccwgdriver = try_then_request_module(
  3782. symbol_get(qeth_l3_ccwgroup_driver),
  3783. "qeth_l3");
  3784. break;
  3785. case QETH_DISCIPLINE_LAYER2:
  3786. card->discipline.ccwgdriver = try_then_request_module(
  3787. symbol_get(qeth_l2_ccwgroup_driver),
  3788. "qeth_l2");
  3789. break;
  3790. }
  3791. if (!card->discipline.ccwgdriver) {
  3792. dev_err(&card->gdev->dev, "There is no kernel module to "
  3793. "support discipline %d\n", discipline);
  3794. rc = -EINVAL;
  3795. }
  3796. return rc;
  3797. }
  3798. void qeth_core_free_discipline(struct qeth_card *card)
  3799. {
  3800. if (card->options.layer2)
  3801. symbol_put(qeth_l2_ccwgroup_driver);
  3802. else
  3803. symbol_put(qeth_l3_ccwgroup_driver);
  3804. card->discipline.ccwgdriver = NULL;
  3805. }
  3806. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3807. {
  3808. struct qeth_card *card;
  3809. struct device *dev;
  3810. int rc;
  3811. unsigned long flags;
  3812. char dbf_name[20];
  3813. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3814. dev = &gdev->dev;
  3815. if (!get_device(dev))
  3816. return -ENODEV;
  3817. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3818. card = qeth_alloc_card();
  3819. if (!card) {
  3820. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3821. rc = -ENOMEM;
  3822. goto err_dev;
  3823. }
  3824. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  3825. dev_name(&gdev->dev));
  3826. card->debug = debug_register(dbf_name, 2, 1, 8);
  3827. if (!card->debug) {
  3828. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  3829. rc = -ENOMEM;
  3830. goto err_card;
  3831. }
  3832. debug_register_view(card->debug, &debug_hex_ascii_view);
  3833. card->read.ccwdev = gdev->cdev[0];
  3834. card->write.ccwdev = gdev->cdev[1];
  3835. card->data.ccwdev = gdev->cdev[2];
  3836. dev_set_drvdata(&gdev->dev, card);
  3837. card->gdev = gdev;
  3838. gdev->cdev[0]->handler = qeth_irq;
  3839. gdev->cdev[1]->handler = qeth_irq;
  3840. gdev->cdev[2]->handler = qeth_irq;
  3841. rc = qeth_determine_card_type(card);
  3842. if (rc) {
  3843. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3844. goto err_dbf;
  3845. }
  3846. rc = qeth_setup_card(card);
  3847. if (rc) {
  3848. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3849. goto err_dbf;
  3850. }
  3851. if (card->info.type == QETH_CARD_TYPE_OSN)
  3852. rc = qeth_core_create_osn_attributes(dev);
  3853. else
  3854. rc = qeth_core_create_device_attributes(dev);
  3855. if (rc)
  3856. goto err_dbf;
  3857. switch (card->info.type) {
  3858. case QETH_CARD_TYPE_OSN:
  3859. case QETH_CARD_TYPE_OSM:
  3860. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3861. if (rc)
  3862. goto err_attr;
  3863. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3864. if (rc)
  3865. goto err_disc;
  3866. case QETH_CARD_TYPE_OSD:
  3867. case QETH_CARD_TYPE_OSX:
  3868. default:
  3869. break;
  3870. }
  3871. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3872. list_add_tail(&card->list, &qeth_core_card_list.list);
  3873. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3874. qeth_determine_capabilities(card);
  3875. return 0;
  3876. err_disc:
  3877. qeth_core_free_discipline(card);
  3878. err_attr:
  3879. if (card->info.type == QETH_CARD_TYPE_OSN)
  3880. qeth_core_remove_osn_attributes(dev);
  3881. else
  3882. qeth_core_remove_device_attributes(dev);
  3883. err_dbf:
  3884. debug_unregister(card->debug);
  3885. err_card:
  3886. qeth_core_free_card(card);
  3887. err_dev:
  3888. put_device(dev);
  3889. return rc;
  3890. }
  3891. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3892. {
  3893. unsigned long flags;
  3894. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3895. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3896. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3897. qeth_core_remove_osn_attributes(&gdev->dev);
  3898. } else {
  3899. qeth_core_remove_device_attributes(&gdev->dev);
  3900. }
  3901. if (card->discipline.ccwgdriver) {
  3902. card->discipline.ccwgdriver->remove(gdev);
  3903. qeth_core_free_discipline(card);
  3904. }
  3905. debug_unregister(card->debug);
  3906. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3907. list_del(&card->list);
  3908. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3909. qeth_core_free_card(card);
  3910. dev_set_drvdata(&gdev->dev, NULL);
  3911. put_device(&gdev->dev);
  3912. return;
  3913. }
  3914. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3915. {
  3916. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3917. int rc = 0;
  3918. int def_discipline;
  3919. if (!card->discipline.ccwgdriver) {
  3920. if (card->info.type == QETH_CARD_TYPE_IQD)
  3921. def_discipline = QETH_DISCIPLINE_LAYER3;
  3922. else
  3923. def_discipline = QETH_DISCIPLINE_LAYER2;
  3924. rc = qeth_core_load_discipline(card, def_discipline);
  3925. if (rc)
  3926. goto err;
  3927. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3928. if (rc)
  3929. goto err;
  3930. }
  3931. rc = card->discipline.ccwgdriver->set_online(gdev);
  3932. err:
  3933. return rc;
  3934. }
  3935. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3936. {
  3937. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3938. return card->discipline.ccwgdriver->set_offline(gdev);
  3939. }
  3940. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3941. {
  3942. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3943. if (card->discipline.ccwgdriver &&
  3944. card->discipline.ccwgdriver->shutdown)
  3945. card->discipline.ccwgdriver->shutdown(gdev);
  3946. }
  3947. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  3948. {
  3949. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3950. if (card->discipline.ccwgdriver &&
  3951. card->discipline.ccwgdriver->prepare)
  3952. return card->discipline.ccwgdriver->prepare(gdev);
  3953. return 0;
  3954. }
  3955. static void qeth_core_complete(struct ccwgroup_device *gdev)
  3956. {
  3957. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3958. if (card->discipline.ccwgdriver &&
  3959. card->discipline.ccwgdriver->complete)
  3960. card->discipline.ccwgdriver->complete(gdev);
  3961. }
  3962. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  3963. {
  3964. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3965. if (card->discipline.ccwgdriver &&
  3966. card->discipline.ccwgdriver->freeze)
  3967. return card->discipline.ccwgdriver->freeze(gdev);
  3968. return 0;
  3969. }
  3970. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  3971. {
  3972. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3973. if (card->discipline.ccwgdriver &&
  3974. card->discipline.ccwgdriver->thaw)
  3975. return card->discipline.ccwgdriver->thaw(gdev);
  3976. return 0;
  3977. }
  3978. static int qeth_core_restore(struct ccwgroup_device *gdev)
  3979. {
  3980. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3981. if (card->discipline.ccwgdriver &&
  3982. card->discipline.ccwgdriver->restore)
  3983. return card->discipline.ccwgdriver->restore(gdev);
  3984. return 0;
  3985. }
  3986. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3987. .owner = THIS_MODULE,
  3988. .name = "qeth",
  3989. .driver_id = 0xD8C5E3C8,
  3990. .probe = qeth_core_probe_device,
  3991. .remove = qeth_core_remove_device,
  3992. .set_online = qeth_core_set_online,
  3993. .set_offline = qeth_core_set_offline,
  3994. .shutdown = qeth_core_shutdown,
  3995. .prepare = qeth_core_prepare,
  3996. .complete = qeth_core_complete,
  3997. .freeze = qeth_core_freeze,
  3998. .thaw = qeth_core_thaw,
  3999. .restore = qeth_core_restore,
  4000. };
  4001. static ssize_t
  4002. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  4003. size_t count)
  4004. {
  4005. int err;
  4006. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  4007. qeth_core_ccwgroup_driver.driver_id);
  4008. if (err)
  4009. return err;
  4010. else
  4011. return count;
  4012. }
  4013. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4014. static struct {
  4015. const char str[ETH_GSTRING_LEN];
  4016. } qeth_ethtool_stats_keys[] = {
  4017. /* 0 */{"rx skbs"},
  4018. {"rx buffers"},
  4019. {"tx skbs"},
  4020. {"tx buffers"},
  4021. {"tx skbs no packing"},
  4022. {"tx buffers no packing"},
  4023. {"tx skbs packing"},
  4024. {"tx buffers packing"},
  4025. {"tx sg skbs"},
  4026. {"tx sg frags"},
  4027. /* 10 */{"rx sg skbs"},
  4028. {"rx sg frags"},
  4029. {"rx sg page allocs"},
  4030. {"tx large kbytes"},
  4031. {"tx large count"},
  4032. {"tx pk state ch n->p"},
  4033. {"tx pk state ch p->n"},
  4034. {"tx pk watermark low"},
  4035. {"tx pk watermark high"},
  4036. {"queue 0 buffer usage"},
  4037. /* 20 */{"queue 1 buffer usage"},
  4038. {"queue 2 buffer usage"},
  4039. {"queue 3 buffer usage"},
  4040. {"rx poll time"},
  4041. {"rx poll count"},
  4042. {"rx do_QDIO time"},
  4043. {"rx do_QDIO count"},
  4044. {"tx handler time"},
  4045. {"tx handler count"},
  4046. {"tx time"},
  4047. /* 30 */{"tx count"},
  4048. {"tx do_QDIO time"},
  4049. {"tx do_QDIO count"},
  4050. {"tx csum"},
  4051. {"tx lin"},
  4052. };
  4053. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4054. {
  4055. switch (stringset) {
  4056. case ETH_SS_STATS:
  4057. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4058. default:
  4059. return -EINVAL;
  4060. }
  4061. }
  4062. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4063. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4064. struct ethtool_stats *stats, u64 *data)
  4065. {
  4066. struct qeth_card *card = dev->ml_priv;
  4067. data[0] = card->stats.rx_packets -
  4068. card->perf_stats.initial_rx_packets;
  4069. data[1] = card->perf_stats.bufs_rec;
  4070. data[2] = card->stats.tx_packets -
  4071. card->perf_stats.initial_tx_packets;
  4072. data[3] = card->perf_stats.bufs_sent;
  4073. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4074. - card->perf_stats.skbs_sent_pack;
  4075. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4076. data[6] = card->perf_stats.skbs_sent_pack;
  4077. data[7] = card->perf_stats.bufs_sent_pack;
  4078. data[8] = card->perf_stats.sg_skbs_sent;
  4079. data[9] = card->perf_stats.sg_frags_sent;
  4080. data[10] = card->perf_stats.sg_skbs_rx;
  4081. data[11] = card->perf_stats.sg_frags_rx;
  4082. data[12] = card->perf_stats.sg_alloc_page_rx;
  4083. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4084. data[14] = card->perf_stats.large_send_cnt;
  4085. data[15] = card->perf_stats.sc_dp_p;
  4086. data[16] = card->perf_stats.sc_p_dp;
  4087. data[17] = QETH_LOW_WATERMARK_PACK;
  4088. data[18] = QETH_HIGH_WATERMARK_PACK;
  4089. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4090. data[20] = (card->qdio.no_out_queues > 1) ?
  4091. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4092. data[21] = (card->qdio.no_out_queues > 2) ?
  4093. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4094. data[22] = (card->qdio.no_out_queues > 3) ?
  4095. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4096. data[23] = card->perf_stats.inbound_time;
  4097. data[24] = card->perf_stats.inbound_cnt;
  4098. data[25] = card->perf_stats.inbound_do_qdio_time;
  4099. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4100. data[27] = card->perf_stats.outbound_handler_time;
  4101. data[28] = card->perf_stats.outbound_handler_cnt;
  4102. data[29] = card->perf_stats.outbound_time;
  4103. data[30] = card->perf_stats.outbound_cnt;
  4104. data[31] = card->perf_stats.outbound_do_qdio_time;
  4105. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4106. data[33] = card->perf_stats.tx_csum;
  4107. data[34] = card->perf_stats.tx_lin;
  4108. }
  4109. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4110. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4111. {
  4112. switch (stringset) {
  4113. case ETH_SS_STATS:
  4114. memcpy(data, &qeth_ethtool_stats_keys,
  4115. sizeof(qeth_ethtool_stats_keys));
  4116. break;
  4117. default:
  4118. WARN_ON(1);
  4119. break;
  4120. }
  4121. }
  4122. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4123. void qeth_core_get_drvinfo(struct net_device *dev,
  4124. struct ethtool_drvinfo *info)
  4125. {
  4126. struct qeth_card *card = dev->ml_priv;
  4127. if (card->options.layer2)
  4128. strcpy(info->driver, "qeth_l2");
  4129. else
  4130. strcpy(info->driver, "qeth_l3");
  4131. strcpy(info->version, "1.0");
  4132. strcpy(info->fw_version, card->info.mcl_level);
  4133. sprintf(info->bus_info, "%s/%s/%s",
  4134. CARD_RDEV_ID(card),
  4135. CARD_WDEV_ID(card),
  4136. CARD_DDEV_ID(card));
  4137. }
  4138. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4139. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4140. struct ethtool_cmd *ecmd)
  4141. {
  4142. struct qeth_card *card = netdev->ml_priv;
  4143. enum qeth_link_types link_type;
  4144. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4145. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4146. else
  4147. link_type = card->info.link_type;
  4148. ecmd->transceiver = XCVR_INTERNAL;
  4149. ecmd->supported = SUPPORTED_Autoneg;
  4150. ecmd->advertising = ADVERTISED_Autoneg;
  4151. ecmd->duplex = DUPLEX_FULL;
  4152. ecmd->autoneg = AUTONEG_ENABLE;
  4153. switch (link_type) {
  4154. case QETH_LINK_TYPE_FAST_ETH:
  4155. case QETH_LINK_TYPE_LANE_ETH100:
  4156. ecmd->supported |= SUPPORTED_10baseT_Half |
  4157. SUPPORTED_10baseT_Full |
  4158. SUPPORTED_100baseT_Half |
  4159. SUPPORTED_100baseT_Full |
  4160. SUPPORTED_TP;
  4161. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4162. ADVERTISED_10baseT_Full |
  4163. ADVERTISED_100baseT_Half |
  4164. ADVERTISED_100baseT_Full |
  4165. ADVERTISED_TP;
  4166. ecmd->speed = SPEED_100;
  4167. ecmd->port = PORT_TP;
  4168. break;
  4169. case QETH_LINK_TYPE_GBIT_ETH:
  4170. case QETH_LINK_TYPE_LANE_ETH1000:
  4171. ecmd->supported |= SUPPORTED_10baseT_Half |
  4172. SUPPORTED_10baseT_Full |
  4173. SUPPORTED_100baseT_Half |
  4174. SUPPORTED_100baseT_Full |
  4175. SUPPORTED_1000baseT_Half |
  4176. SUPPORTED_1000baseT_Full |
  4177. SUPPORTED_FIBRE;
  4178. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4179. ADVERTISED_10baseT_Full |
  4180. ADVERTISED_100baseT_Half |
  4181. ADVERTISED_100baseT_Full |
  4182. ADVERTISED_1000baseT_Half |
  4183. ADVERTISED_1000baseT_Full |
  4184. ADVERTISED_FIBRE;
  4185. ecmd->speed = SPEED_1000;
  4186. ecmd->port = PORT_FIBRE;
  4187. break;
  4188. case QETH_LINK_TYPE_10GBIT_ETH:
  4189. ecmd->supported |= SUPPORTED_10baseT_Half |
  4190. SUPPORTED_10baseT_Full |
  4191. SUPPORTED_100baseT_Half |
  4192. SUPPORTED_100baseT_Full |
  4193. SUPPORTED_1000baseT_Half |
  4194. SUPPORTED_1000baseT_Full |
  4195. SUPPORTED_10000baseT_Full |
  4196. SUPPORTED_FIBRE;
  4197. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4198. ADVERTISED_10baseT_Full |
  4199. ADVERTISED_100baseT_Half |
  4200. ADVERTISED_100baseT_Full |
  4201. ADVERTISED_1000baseT_Half |
  4202. ADVERTISED_1000baseT_Full |
  4203. ADVERTISED_10000baseT_Full |
  4204. ADVERTISED_FIBRE;
  4205. ecmd->speed = SPEED_10000;
  4206. ecmd->port = PORT_FIBRE;
  4207. break;
  4208. default:
  4209. ecmd->supported |= SUPPORTED_10baseT_Half |
  4210. SUPPORTED_10baseT_Full |
  4211. SUPPORTED_TP;
  4212. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4213. ADVERTISED_10baseT_Full |
  4214. ADVERTISED_TP;
  4215. ecmd->speed = SPEED_10;
  4216. ecmd->port = PORT_TP;
  4217. }
  4218. return 0;
  4219. }
  4220. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4221. static int __init qeth_core_init(void)
  4222. {
  4223. int rc;
  4224. pr_info("loading core functions\n");
  4225. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4226. rwlock_init(&qeth_core_card_list.rwlock);
  4227. rc = qeth_register_dbf_views();
  4228. if (rc)
  4229. goto out_err;
  4230. rc = ccw_driver_register(&qeth_ccw_driver);
  4231. if (rc)
  4232. goto ccw_err;
  4233. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4234. if (rc)
  4235. goto ccwgroup_err;
  4236. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4237. &driver_attr_group);
  4238. if (rc)
  4239. goto driver_err;
  4240. qeth_core_root_dev = root_device_register("qeth");
  4241. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4242. if (rc)
  4243. goto register_err;
  4244. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4245. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4246. if (!qeth_core_header_cache) {
  4247. rc = -ENOMEM;
  4248. goto slab_err;
  4249. }
  4250. return 0;
  4251. slab_err:
  4252. root_device_unregister(qeth_core_root_dev);
  4253. register_err:
  4254. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4255. &driver_attr_group);
  4256. driver_err:
  4257. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4258. ccwgroup_err:
  4259. ccw_driver_unregister(&qeth_ccw_driver);
  4260. ccw_err:
  4261. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4262. qeth_unregister_dbf_views();
  4263. out_err:
  4264. pr_err("Initializing the qeth device driver failed\n");
  4265. return rc;
  4266. }
  4267. static void __exit qeth_core_exit(void)
  4268. {
  4269. root_device_unregister(qeth_core_root_dev);
  4270. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4271. &driver_attr_group);
  4272. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4273. ccw_driver_unregister(&qeth_ccw_driver);
  4274. kmem_cache_destroy(qeth_core_header_cache);
  4275. qeth_unregister_dbf_views();
  4276. pr_info("core functions removed\n");
  4277. }
  4278. module_init(qeth_core_init);
  4279. module_exit(qeth_core_exit);
  4280. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4281. MODULE_DESCRIPTION("qeth core functions");
  4282. MODULE_LICENSE("GPL");