mpc8379_mds.dts 6.7 KB

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  1. /*
  2. * MPC8379E MDS Device Tree Source
  3. *
  4. * Copyright 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "fsl,mpc8379emds";
  14. compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. PowerPC,8379@0 {
  28. device_type = "cpu";
  29. reg = <0>;
  30. d-cache-line-size = <0x20>;
  31. i-cache-line-size = <0x20>;
  32. d-cache-size = <0x8000>; // L1, 32K
  33. i-cache-size = <0x8000>; // L1, 32K
  34. timebase-frequency = <0>;
  35. bus-frequency = <0>;
  36. clock-frequency = <0>;
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. reg = <0x00000000 0x20000000>; // 512MB at 0
  42. };
  43. soc@e0000000 {
  44. #address-cells = <1>;
  45. #size-cells = <1>;
  46. device_type = "soc";
  47. ranges = <0x0 0xe0000000 0x00100000>;
  48. reg = <0xe0000000 0x00000200>;
  49. bus-frequency = <0>;
  50. wdt@200 {
  51. compatible = "mpc83xx_wdt";
  52. reg = <0x200 0x100>;
  53. };
  54. i2c@3000 {
  55. #address-cells = <1>;
  56. #size-cells = <0>;
  57. cell-index = <0>;
  58. compatible = "fsl-i2c";
  59. reg = <0x3000 0x100>;
  60. interrupts = <0xe 0x8>;
  61. interrupt-parent = < &ipic >;
  62. dfsrr;
  63. };
  64. i2c@3100 {
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. cell-index = <1>;
  68. compatible = "fsl-i2c";
  69. reg = <0x3100 0x100>;
  70. interrupts = <0xf 0x8>;
  71. interrupt-parent = < &ipic >;
  72. dfsrr;
  73. };
  74. spi@7000 {
  75. compatible = "fsl_spi";
  76. reg = <0x7000 0x1000>;
  77. interrupts = <0x10 0x8>;
  78. interrupt-parent = < &ipic >;
  79. mode = "cpu";
  80. };
  81. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  82. usb@23000 {
  83. compatible = "fsl-usb2-dr";
  84. reg = <0x23000 0x1000>;
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. interrupt-parent = < &ipic >;
  88. interrupts = <0x26 0x8>;
  89. phy_type = "utmi_wide";
  90. };
  91. mdio@24520 {
  92. #address-cells = <1>;
  93. #size-cells = <0>;
  94. compatible = "fsl,gianfar-mdio";
  95. reg = <0x24520 0x20>;
  96. phy2: ethernet-phy@2 {
  97. interrupt-parent = < &ipic >;
  98. interrupts = <0x11 0x8>;
  99. reg = <2>;
  100. device_type = "ethernet-phy";
  101. };
  102. phy3: ethernet-phy@3 {
  103. interrupt-parent = < &ipic >;
  104. interrupts = <0x12 0x8>;
  105. reg = <3>;
  106. device_type = "ethernet-phy";
  107. };
  108. };
  109. enet0: ethernet@24000 {
  110. cell-index = <0>;
  111. device_type = "network";
  112. model = "eTSEC";
  113. compatible = "gianfar";
  114. reg = <0x24000 0x1000>;
  115. local-mac-address = [ 00 00 00 00 00 00 ];
  116. interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
  117. phy-connection-type = "mii";
  118. interrupt-parent = < &ipic >;
  119. phy-handle = < &phy2 >;
  120. };
  121. enet1: ethernet@25000 {
  122. cell-index = <1>;
  123. device_type = "network";
  124. model = "eTSEC";
  125. compatible = "gianfar";
  126. reg = <0x25000 0x1000>;
  127. local-mac-address = [ 00 00 00 00 00 00 ];
  128. interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
  129. phy-connection-type = "mii";
  130. interrupt-parent = < &ipic >;
  131. phy-handle = < &phy3 >;
  132. };
  133. serial0: serial@4500 {
  134. cell-index = <0>;
  135. device_type = "serial";
  136. compatible = "ns16550";
  137. reg = <0x4500 0x100>;
  138. clock-frequency = <0>;
  139. interrupts = <0x9 0x8>;
  140. interrupt-parent = < &ipic >;
  141. };
  142. serial1: serial@4600 {
  143. cell-index = <1>;
  144. device_type = "serial";
  145. compatible = "ns16550";
  146. reg = <0x4600 0x100>;
  147. clock-frequency = <0>;
  148. interrupts = <0xa 0x8>;
  149. interrupt-parent = < &ipic >;
  150. };
  151. crypto@30000 {
  152. model = "SEC3";
  153. compatible = "talitos";
  154. reg = <0x30000 0x10000>;
  155. interrupts = <0xb 0x8>;
  156. interrupt-parent = < &ipic >;
  157. /* Rev. 3.0 geometry */
  158. num-channels = <4>;
  159. channel-fifo-len = <0x18>;
  160. exec-units-mask = <0x000001fe>;
  161. descriptor-types-mask = <0x03ab0ebf>;
  162. };
  163. sdhc@2e000 {
  164. model = "eSDHC";
  165. compatible = "fsl,esdhc";
  166. reg = <0x2e000 0x1000>;
  167. interrupts = <0x2a 0x8>;
  168. interrupt-parent = < &ipic >;
  169. };
  170. sata@18000 {
  171. compatible = "fsl,mpc8379-sata";
  172. reg = <0x18000 0x1000>;
  173. interrupts = <0x2c 0x8>;
  174. interrupt-parent = < &ipic >;
  175. };
  176. sata@19000 {
  177. compatible = "fsl,mpc8379-sata";
  178. reg = <0x19000 0x1000>;
  179. interrupts = <0x2d 0x8>;
  180. interrupt-parent = < &ipic >;
  181. };
  182. sata@1a000 {
  183. compatible = "fsl,mpc8379-sata";
  184. reg = <0x1a000 0x1000>;
  185. interrupts = <0x2e 0x8>;
  186. interrupt-parent = < &ipic >;
  187. };
  188. sata@1b000 {
  189. compatible = "fsl,mpc8379-sata";
  190. reg = <0x1b000 0x1000>;
  191. interrupts = <0x2f 0x8>;
  192. interrupt-parent = < &ipic >;
  193. };
  194. /* IPIC
  195. * interrupts cell = <intr #, sense>
  196. * sense values match linux IORESOURCE_IRQ_* defines:
  197. * sense == 8: Level, low assertion
  198. * sense == 2: Edge, high-to-low change
  199. */
  200. ipic: pic@700 {
  201. compatible = "fsl,ipic";
  202. interrupt-controller;
  203. #address-cells = <0>;
  204. #interrupt-cells = <2>;
  205. reg = <0x700 0x100>;
  206. };
  207. };
  208. pci0: pci@e0008500 {
  209. cell-index = <0>;
  210. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  211. interrupt-map = <
  212. /* IDSEL 0x11 */
  213. 0x8800 0x0 0x0 0x1 &ipic 0x14 0x8
  214. 0x8800 0x0 0x0 0x2 &ipic 0x15 0x8
  215. 0x8800 0x0 0x0 0x3 &ipic 0x16 0x8
  216. 0x8800 0x0 0x0 0x4 &ipic 0x17 0x8
  217. /* IDSEL 0x12 */
  218. 0x9000 0x0 0x0 0x1 &ipic 0x16 0x8
  219. 0x9000 0x0 0x0 0x2 &ipic 0x17 0x8
  220. 0x9000 0x0 0x0 0x3 &ipic 0x14 0x8
  221. 0x9000 0x0 0x0 0x4 &ipic 0x15 0x8
  222. /* IDSEL 0x13 */
  223. 0x9800 0x0 0x0 0x1 &ipic 0x17 0x8
  224. 0x9800 0x0 0x0 0x2 &ipic 0x14 0x8
  225. 0x9800 0x0 0x0 0x3 &ipic 0x15 0x8
  226. 0x9800 0x0 0x0 0x4 &ipic 0x16 0x8
  227. /* IDSEL 0x15 */
  228. 0xa800 0x0 0x0 0x1 &ipic 0x14 0x8
  229. 0xa800 0x0 0x0 0x2 &ipic 0x15 0x8
  230. 0xa800 0x0 0x0 0x3 &ipic 0x16 0x8
  231. 0xa800 0x0 0x0 0x4 &ipic 0x17 0x8
  232. /* IDSEL 0x16 */
  233. 0xb000 0x0 0x0 0x1 &ipic 0x17 0x8
  234. 0xb000 0x0 0x0 0x2 &ipic 0x14 0x8
  235. 0xb000 0x0 0x0 0x3 &ipic 0x15 0x8
  236. 0xb000 0x0 0x0 0x4 &ipic 0x16 0x8
  237. /* IDSEL 0x17 */
  238. 0xb800 0x0 0x0 0x1 &ipic 0x16 0x8
  239. 0xb800 0x0 0x0 0x2 &ipic 0x17 0x8
  240. 0xb800 0x0 0x0 0x3 &ipic 0x14 0x8
  241. 0xb800 0x0 0x0 0x4 &ipic 0x15 0x8
  242. /* IDSEL 0x18 */
  243. 0xc000 0x0 0x0 0x1 &ipic 0x15 0x8
  244. 0xc000 0x0 0x0 0x2 &ipic 0x16 0x8
  245. 0xc000 0x0 0x0 0x3 &ipic 0x17 0x8
  246. 0xc000 0x0 0x0 0x4 &ipic 0x14 0x8>;
  247. interrupt-parent = < &ipic >;
  248. interrupts = <0x42 0x8>;
  249. bus-range = <0 0>;
  250. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  251. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  252. 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
  253. clock-frequency = <0>;
  254. #interrupt-cells = <1>;
  255. #size-cells = <2>;
  256. #address-cells = <3>;
  257. reg = <0xe0008500 0x100>;
  258. compatible = "fsl,mpc8349-pci";
  259. device_type = "pci";
  260. };
  261. };