mpc8313erdb.dts 5.9 KB

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  1. /*
  2. * MPC8313E RDB Device Tree Source
  3. *
  4. * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. / {
  12. model = "MPC8313ERDB";
  13. compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
  14. #address-cells = <1>;
  15. #size-cells = <1>;
  16. aliases {
  17. ethernet0 = &enet0;
  18. ethernet1 = &enet1;
  19. serial0 = &serial0;
  20. serial1 = &serial1;
  21. pci0 = &pci0;
  22. };
  23. cpus {
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. PowerPC,8313@0 {
  27. device_type = "cpu";
  28. reg = <0>;
  29. d-cache-line-size = <20>; // 32 bytes
  30. i-cache-line-size = <20>; // 32 bytes
  31. d-cache-size = <4000>; // L1, 16K
  32. i-cache-size = <4000>; // L1, 16K
  33. timebase-frequency = <0>; // from bootloader
  34. bus-frequency = <0>; // from bootloader
  35. clock-frequency = <0>; // from bootloader
  36. };
  37. };
  38. memory {
  39. device_type = "memory";
  40. reg = <00000000 08000000>; // 128MB at 0
  41. };
  42. localbus@e0005000 {
  43. #address-cells = <2>;
  44. #size-cells = <1>;
  45. compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
  46. reg = <e0005000 1000>;
  47. interrupts = <d#77 8>;
  48. interrupt-parent = <&ipic>;
  49. // CS0 and CS1 are swapped when
  50. // booting from nand, but the
  51. // addresses are the same.
  52. ranges = <0 0 fe000000 00800000
  53. 1 0 e2800000 00008000
  54. 2 0 f0000000 00020000
  55. 3 0 fa000000 00008000>;
  56. flash@0,0 {
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. compatible = "cfi-flash";
  60. reg = <0 0 800000>;
  61. bank-width = <2>;
  62. device-width = <1>;
  63. };
  64. nand@1,0 {
  65. #address-cells = <1>;
  66. #size-cells = <1>;
  67. compatible = "fsl,mpc8313-fcm-nand",
  68. "fsl,elbc-fcm-nand";
  69. reg = <1 0 2000>;
  70. u-boot@0 {
  71. reg = <0 100000>;
  72. read-only;
  73. };
  74. kernel@100000 {
  75. reg = <100000 300000>;
  76. };
  77. fs@400000 {
  78. reg = <400000 1c00000>;
  79. };
  80. };
  81. };
  82. soc8313@e0000000 {
  83. #address-cells = <1>;
  84. #size-cells = <1>;
  85. device_type = "soc";
  86. compatible = "simple-bus";
  87. ranges = <0 e0000000 00100000>;
  88. reg = <e0000000 00000200>;
  89. bus-frequency = <0>;
  90. wdt@200 {
  91. device_type = "watchdog";
  92. compatible = "mpc83xx_wdt";
  93. reg = <200 100>;
  94. };
  95. i2c@3000 {
  96. #address-cells = <1>;
  97. #size-cells = <0>;
  98. cell-index = <0>;
  99. compatible = "fsl-i2c";
  100. reg = <3000 100>;
  101. interrupts = <e 8>;
  102. interrupt-parent = < &ipic >;
  103. dfsrr;
  104. };
  105. i2c@3100 {
  106. #address-cells = <1>;
  107. #size-cells = <0>;
  108. cell-index = <1>;
  109. compatible = "fsl-i2c";
  110. reg = <3100 100>;
  111. interrupts = <f 8>;
  112. interrupt-parent = < &ipic >;
  113. dfsrr;
  114. };
  115. spi@7000 {
  116. device_type = "spi";
  117. compatible = "fsl_spi";
  118. reg = <7000 1000>;
  119. interrupts = <10 8>;
  120. interrupt-parent = < &ipic >;
  121. mode = "cpu";
  122. };
  123. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  124. usb@23000 {
  125. compatible = "fsl-usb2-dr";
  126. reg = <23000 1000>;
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. interrupt-parent = < &ipic >;
  130. interrupts = <26 8>;
  131. phy_type = "utmi_wide";
  132. };
  133. mdio@24520 {
  134. #address-cells = <1>;
  135. #size-cells = <0>;
  136. compatible = "fsl,gianfar-mdio";
  137. reg = <24520 20>;
  138. phy1: ethernet-phy@1 {
  139. interrupt-parent = < &ipic >;
  140. interrupts = <13 8>;
  141. reg = <1>;
  142. device_type = "ethernet-phy";
  143. };
  144. phy4: ethernet-phy@4 {
  145. interrupt-parent = < &ipic >;
  146. interrupts = <14 8>;
  147. reg = <4>;
  148. device_type = "ethernet-phy";
  149. };
  150. };
  151. enet0: ethernet@24000 {
  152. cell-index = <0>;
  153. device_type = "network";
  154. model = "eTSEC";
  155. compatible = "gianfar";
  156. reg = <24000 1000>;
  157. local-mac-address = [ 00 00 00 00 00 00 ];
  158. interrupts = <25 8 24 8 23 8>;
  159. interrupt-parent = < &ipic >;
  160. phy-handle = < &phy1 >;
  161. };
  162. enet1: ethernet@25000 {
  163. cell-index = <1>;
  164. device_type = "network";
  165. model = "eTSEC";
  166. compatible = "gianfar";
  167. reg = <25000 1000>;
  168. local-mac-address = [ 00 00 00 00 00 00 ];
  169. interrupts = <22 8 21 8 20 8>;
  170. interrupt-parent = < &ipic >;
  171. phy-handle = < &phy4 >;
  172. };
  173. serial0: serial@4500 {
  174. cell-index = <0>;
  175. device_type = "serial";
  176. compatible = "ns16550";
  177. reg = <4500 100>;
  178. clock-frequency = <0>;
  179. interrupts = <9 8>;
  180. interrupt-parent = < &ipic >;
  181. };
  182. serial1: serial@4600 {
  183. cell-index = <1>;
  184. device_type = "serial";
  185. compatible = "ns16550";
  186. reg = <4600 100>;
  187. clock-frequency = <0>;
  188. interrupts = <a 8>;
  189. interrupt-parent = < &ipic >;
  190. };
  191. crypto@30000 {
  192. device_type = "crypto";
  193. model = "SEC2";
  194. compatible = "talitos";
  195. reg = <30000 7000>;
  196. interrupts = <b 8>;
  197. interrupt-parent = < &ipic >;
  198. /* Rev. 2.2 */
  199. num-channels = <1>;
  200. channel-fifo-len = <18>;
  201. exec-units-mask = <0000004c>;
  202. descriptor-types-mask = <0122003f>;
  203. };
  204. /* IPIC
  205. * interrupts cell = <intr #, sense>
  206. * sense values match linux IORESOURCE_IRQ_* defines:
  207. * sense == 8: Level, low assertion
  208. * sense == 2: Edge, high-to-low change
  209. */
  210. ipic: pic@700 {
  211. interrupt-controller;
  212. #address-cells = <0>;
  213. #interrupt-cells = <2>;
  214. reg = <700 100>;
  215. device_type = "ipic";
  216. };
  217. };
  218. pci0: pci@e0008500 {
  219. cell-index = <1>;
  220. interrupt-map-mask = <f800 0 0 7>;
  221. interrupt-map = <
  222. /* IDSEL 0x0E -mini PCI */
  223. 7000 0 0 1 &ipic 12 8
  224. 7000 0 0 2 &ipic 12 8
  225. 7000 0 0 3 &ipic 12 8
  226. 7000 0 0 4 &ipic 12 8
  227. /* IDSEL 0x0F - PCI slot */
  228. 7800 0 0 1 &ipic 11 8
  229. 7800 0 0 2 &ipic 12 8
  230. 7800 0 0 3 &ipic 11 8
  231. 7800 0 0 4 &ipic 12 8>;
  232. interrupt-parent = < &ipic >;
  233. interrupts = <42 8>;
  234. bus-range = <0 0>;
  235. ranges = <02000000 0 90000000 90000000 0 10000000
  236. 42000000 0 80000000 80000000 0 10000000
  237. 01000000 0 00000000 e2000000 0 00100000>;
  238. clock-frequency = <3f940aa>;
  239. #interrupt-cells = <1>;
  240. #size-cells = <2>;
  241. #address-cells = <3>;
  242. reg = <e0008500 100>;
  243. compatible = "fsl,mpc8349-pci";
  244. device_type = "pci";
  245. };
  246. };