i40e_main.c 198 KB

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  1. /*******************************************************************************
  2. *
  3. * Intel Ethernet Controller XL710 Family Linux Driver
  4. * Copyright(c) 2013 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms and conditions of the GNU General Public License,
  8. * version 2, as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program; if not, write to the Free Software Foundation, Inc.,
  17. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18. *
  19. * The full GNU General Public License is included in this distribution in
  20. * the file called "COPYING".
  21. *
  22. * Contact Information:
  23. * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25. *
  26. ******************************************************************************/
  27. /* Local includes */
  28. #include "i40e.h"
  29. const char i40e_driver_name[] = "i40e";
  30. static const char i40e_driver_string[] =
  31. "Intel(R) Ethernet Connection XL710 Network Driver";
  32. #define DRV_KERN "-k"
  33. #define DRV_VERSION_MAJOR 0
  34. #define DRV_VERSION_MINOR 3
  35. #define DRV_VERSION_BUILD 9
  36. #define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
  37. __stringify(DRV_VERSION_MINOR) "." \
  38. __stringify(DRV_VERSION_BUILD) DRV_KERN
  39. const char i40e_driver_version_str[] = DRV_VERSION;
  40. static const char i40e_copyright[] = "Copyright (c) 2013 Intel Corporation.";
  41. /* a bit of forward declarations */
  42. static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
  43. static void i40e_handle_reset_warning(struct i40e_pf *pf);
  44. static int i40e_add_vsi(struct i40e_vsi *vsi);
  45. static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
  46. static int i40e_setup_pf_switch(struct i40e_pf *pf);
  47. static int i40e_setup_misc_vector(struct i40e_pf *pf);
  48. static void i40e_determine_queue_usage(struct i40e_pf *pf);
  49. static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
  50. /* i40e_pci_tbl - PCI Device ID Table
  51. *
  52. * Last entry must be all 0s
  53. *
  54. * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  55. * Class, Class Mask, private data (not used) }
  56. */
  57. static DEFINE_PCI_DEVICE_TABLE(i40e_pci_tbl) = {
  58. {PCI_VDEVICE(INTEL, I40E_SFP_XL710_DEVICE_ID), 0},
  59. {PCI_VDEVICE(INTEL, I40E_SFP_X710_DEVICE_ID), 0},
  60. {PCI_VDEVICE(INTEL, I40E_QEMU_DEVICE_ID), 0},
  61. {PCI_VDEVICE(INTEL, I40E_KX_A_DEVICE_ID), 0},
  62. {PCI_VDEVICE(INTEL, I40E_KX_B_DEVICE_ID), 0},
  63. {PCI_VDEVICE(INTEL, I40E_KX_C_DEVICE_ID), 0},
  64. {PCI_VDEVICE(INTEL, I40E_KX_D_DEVICE_ID), 0},
  65. {PCI_VDEVICE(INTEL, I40E_QSFP_A_DEVICE_ID), 0},
  66. {PCI_VDEVICE(INTEL, I40E_QSFP_B_DEVICE_ID), 0},
  67. {PCI_VDEVICE(INTEL, I40E_QSFP_C_DEVICE_ID), 0},
  68. /* required last entry */
  69. {0, }
  70. };
  71. MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
  72. #define I40E_MAX_VF_COUNT 128
  73. static int debug = -1;
  74. module_param(debug, int, 0);
  75. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  76. MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
  77. MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
  78. MODULE_LICENSE("GPL");
  79. MODULE_VERSION(DRV_VERSION);
  80. /**
  81. * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
  82. * @hw: pointer to the HW structure
  83. * @mem: ptr to mem struct to fill out
  84. * @size: size of memory requested
  85. * @alignment: what to align the allocation to
  86. **/
  87. int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
  88. u64 size, u32 alignment)
  89. {
  90. struct i40e_pf *pf = (struct i40e_pf *)hw->back;
  91. mem->size = ALIGN(size, alignment);
  92. mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
  93. &mem->pa, GFP_KERNEL);
  94. if (!mem->va)
  95. return -ENOMEM;
  96. return 0;
  97. }
  98. /**
  99. * i40e_free_dma_mem_d - OS specific memory free for shared code
  100. * @hw: pointer to the HW structure
  101. * @mem: ptr to mem struct to free
  102. **/
  103. int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
  104. {
  105. struct i40e_pf *pf = (struct i40e_pf *)hw->back;
  106. dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
  107. mem->va = NULL;
  108. mem->pa = 0;
  109. mem->size = 0;
  110. return 0;
  111. }
  112. /**
  113. * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
  114. * @hw: pointer to the HW structure
  115. * @mem: ptr to mem struct to fill out
  116. * @size: size of memory requested
  117. **/
  118. int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
  119. u32 size)
  120. {
  121. mem->size = size;
  122. mem->va = kzalloc(size, GFP_KERNEL);
  123. if (!mem->va)
  124. return -ENOMEM;
  125. return 0;
  126. }
  127. /**
  128. * i40e_free_virt_mem_d - OS specific memory free for shared code
  129. * @hw: pointer to the HW structure
  130. * @mem: ptr to mem struct to free
  131. **/
  132. int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
  133. {
  134. /* it's ok to kfree a NULL pointer */
  135. kfree(mem->va);
  136. mem->va = NULL;
  137. mem->size = 0;
  138. return 0;
  139. }
  140. /**
  141. * i40e_get_lump - find a lump of free generic resource
  142. * @pf: board private structure
  143. * @pile: the pile of resource to search
  144. * @needed: the number of items needed
  145. * @id: an owner id to stick on the items assigned
  146. *
  147. * Returns the base item index of the lump, or negative for error
  148. *
  149. * The search_hint trick and lack of advanced fit-finding only work
  150. * because we're highly likely to have all the same size lump requests.
  151. * Linear search time and any fragmentation should be minimal.
  152. **/
  153. static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
  154. u16 needed, u16 id)
  155. {
  156. int ret = -ENOMEM;
  157. int i, j;
  158. if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
  159. dev_info(&pf->pdev->dev,
  160. "param err: pile=%p needed=%d id=0x%04x\n",
  161. pile, needed, id);
  162. return -EINVAL;
  163. }
  164. /* start the linear search with an imperfect hint */
  165. i = pile->search_hint;
  166. while (i < pile->num_entries) {
  167. /* skip already allocated entries */
  168. if (pile->list[i] & I40E_PILE_VALID_BIT) {
  169. i++;
  170. continue;
  171. }
  172. /* do we have enough in this lump? */
  173. for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
  174. if (pile->list[i+j] & I40E_PILE_VALID_BIT)
  175. break;
  176. }
  177. if (j == needed) {
  178. /* there was enough, so assign it to the requestor */
  179. for (j = 0; j < needed; j++)
  180. pile->list[i+j] = id | I40E_PILE_VALID_BIT;
  181. ret = i;
  182. pile->search_hint = i + j;
  183. break;
  184. } else {
  185. /* not enough, so skip over it and continue looking */
  186. i += j;
  187. }
  188. }
  189. return ret;
  190. }
  191. /**
  192. * i40e_put_lump - return a lump of generic resource
  193. * @pile: the pile of resource to search
  194. * @index: the base item index
  195. * @id: the owner id of the items assigned
  196. *
  197. * Returns the count of items in the lump
  198. **/
  199. static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
  200. {
  201. int valid_id = (id | I40E_PILE_VALID_BIT);
  202. int count = 0;
  203. int i;
  204. if (!pile || index >= pile->num_entries)
  205. return -EINVAL;
  206. for (i = index;
  207. i < pile->num_entries && pile->list[i] == valid_id;
  208. i++) {
  209. pile->list[i] = 0;
  210. count++;
  211. }
  212. if (count && index < pile->search_hint)
  213. pile->search_hint = index;
  214. return count;
  215. }
  216. /**
  217. * i40e_service_event_schedule - Schedule the service task to wake up
  218. * @pf: board private structure
  219. *
  220. * If not already scheduled, this puts the task into the work queue
  221. **/
  222. static void i40e_service_event_schedule(struct i40e_pf *pf)
  223. {
  224. if (!test_bit(__I40E_DOWN, &pf->state) &&
  225. !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
  226. !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
  227. schedule_work(&pf->service_task);
  228. }
  229. /**
  230. * i40e_tx_timeout - Respond to a Tx Hang
  231. * @netdev: network interface device structure
  232. *
  233. * If any port has noticed a Tx timeout, it is likely that the whole
  234. * device is munged, not just the one netdev port, so go for the full
  235. * reset.
  236. **/
  237. static void i40e_tx_timeout(struct net_device *netdev)
  238. {
  239. struct i40e_netdev_priv *np = netdev_priv(netdev);
  240. struct i40e_vsi *vsi = np->vsi;
  241. struct i40e_pf *pf = vsi->back;
  242. pf->tx_timeout_count++;
  243. if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
  244. pf->tx_timeout_recovery_level = 0;
  245. pf->tx_timeout_last_recovery = jiffies;
  246. netdev_info(netdev, "tx_timeout recovery level %d\n",
  247. pf->tx_timeout_recovery_level);
  248. switch (pf->tx_timeout_recovery_level) {
  249. case 0:
  250. /* disable and re-enable queues for the VSI */
  251. if (in_interrupt()) {
  252. set_bit(__I40E_REINIT_REQUESTED, &pf->state);
  253. set_bit(__I40E_REINIT_REQUESTED, &vsi->state);
  254. } else {
  255. i40e_vsi_reinit_locked(vsi);
  256. }
  257. break;
  258. case 1:
  259. set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
  260. break;
  261. case 2:
  262. set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
  263. break;
  264. case 3:
  265. set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
  266. break;
  267. default:
  268. netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
  269. i40e_down(vsi);
  270. break;
  271. }
  272. i40e_service_event_schedule(pf);
  273. pf->tx_timeout_recovery_level++;
  274. }
  275. /**
  276. * i40e_release_rx_desc - Store the new tail and head values
  277. * @rx_ring: ring to bump
  278. * @val: new head index
  279. **/
  280. static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
  281. {
  282. rx_ring->next_to_use = val;
  283. /* Force memory writes to complete before letting h/w
  284. * know there are new descriptors to fetch. (Only
  285. * applicable for weak-ordered memory model archs,
  286. * such as IA-64).
  287. */
  288. wmb();
  289. writel(val, rx_ring->tail);
  290. }
  291. /**
  292. * i40e_get_vsi_stats_struct - Get System Network Statistics
  293. * @vsi: the VSI we care about
  294. *
  295. * Returns the address of the device statistics structure.
  296. * The statistics are actually updated from the service task.
  297. **/
  298. struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
  299. {
  300. return &vsi->net_stats;
  301. }
  302. /**
  303. * i40e_get_netdev_stats_struct - Get statistics for netdev interface
  304. * @netdev: network interface device structure
  305. *
  306. * Returns the address of the device statistics structure.
  307. * The statistics are actually updated from the service task.
  308. **/
  309. static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
  310. struct net_device *netdev,
  311. struct rtnl_link_stats64 *storage)
  312. {
  313. struct i40e_netdev_priv *np = netdev_priv(netdev);
  314. struct i40e_vsi *vsi = np->vsi;
  315. *storage = *i40e_get_vsi_stats_struct(vsi);
  316. return storage;
  317. }
  318. /**
  319. * i40e_vsi_reset_stats - Resets all stats of the given vsi
  320. * @vsi: the VSI to have its stats reset
  321. **/
  322. void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
  323. {
  324. struct rtnl_link_stats64 *ns;
  325. int i;
  326. if (!vsi)
  327. return;
  328. ns = i40e_get_vsi_stats_struct(vsi);
  329. memset(ns, 0, sizeof(*ns));
  330. memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
  331. memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
  332. memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
  333. if (vsi->rx_rings)
  334. for (i = 0; i < vsi->num_queue_pairs; i++) {
  335. memset(&vsi->rx_rings[i].rx_stats, 0 ,
  336. sizeof(vsi->rx_rings[i].rx_stats));
  337. memset(&vsi->tx_rings[i].tx_stats, 0,
  338. sizeof(vsi->tx_rings[i].tx_stats));
  339. }
  340. vsi->stat_offsets_loaded = false;
  341. }
  342. /**
  343. * i40e_pf_reset_stats - Reset all of the stats for the given pf
  344. * @pf: the PF to be reset
  345. **/
  346. void i40e_pf_reset_stats(struct i40e_pf *pf)
  347. {
  348. memset(&pf->stats, 0, sizeof(pf->stats));
  349. memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
  350. pf->stat_offsets_loaded = false;
  351. }
  352. /**
  353. * i40e_stat_update48 - read and update a 48 bit stat from the chip
  354. * @hw: ptr to the hardware info
  355. * @hireg: the high 32 bit reg to read
  356. * @loreg: the low 32 bit reg to read
  357. * @offset_loaded: has the initial offset been loaded yet
  358. * @offset: ptr to current offset value
  359. * @stat: ptr to the stat
  360. *
  361. * Since the device stats are not reset at PFReset, they likely will not
  362. * be zeroed when the driver starts. We'll save the first values read
  363. * and use them as offsets to be subtracted from the raw values in order
  364. * to report stats that count from zero. In the process, we also manage
  365. * the potential roll-over.
  366. **/
  367. static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
  368. bool offset_loaded, u64 *offset, u64 *stat)
  369. {
  370. u64 new_data;
  371. if (hw->device_id == I40E_QEMU_DEVICE_ID) {
  372. new_data = rd32(hw, loreg);
  373. new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
  374. } else {
  375. new_data = rd64(hw, loreg);
  376. }
  377. if (!offset_loaded)
  378. *offset = new_data;
  379. if (likely(new_data >= *offset))
  380. *stat = new_data - *offset;
  381. else
  382. *stat = (new_data + ((u64)1 << 48)) - *offset;
  383. *stat &= 0xFFFFFFFFFFFFULL;
  384. }
  385. /**
  386. * i40e_stat_update32 - read and update a 32 bit stat from the chip
  387. * @hw: ptr to the hardware info
  388. * @reg: the hw reg to read
  389. * @offset_loaded: has the initial offset been loaded yet
  390. * @offset: ptr to current offset value
  391. * @stat: ptr to the stat
  392. **/
  393. static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
  394. bool offset_loaded, u64 *offset, u64 *stat)
  395. {
  396. u32 new_data;
  397. new_data = rd32(hw, reg);
  398. if (!offset_loaded)
  399. *offset = new_data;
  400. if (likely(new_data >= *offset))
  401. *stat = (u32)(new_data - *offset);
  402. else
  403. *stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
  404. }
  405. /**
  406. * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
  407. * @vsi: the VSI to be updated
  408. **/
  409. void i40e_update_eth_stats(struct i40e_vsi *vsi)
  410. {
  411. int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
  412. struct i40e_pf *pf = vsi->back;
  413. struct i40e_hw *hw = &pf->hw;
  414. struct i40e_eth_stats *oes;
  415. struct i40e_eth_stats *es; /* device's eth stats */
  416. es = &vsi->eth_stats;
  417. oes = &vsi->eth_stats_offsets;
  418. /* Gather up the stats that the hw collects */
  419. i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
  420. vsi->stat_offsets_loaded,
  421. &oes->tx_errors, &es->tx_errors);
  422. i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
  423. vsi->stat_offsets_loaded,
  424. &oes->rx_discards, &es->rx_discards);
  425. i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
  426. I40E_GLV_GORCL(stat_idx),
  427. vsi->stat_offsets_loaded,
  428. &oes->rx_bytes, &es->rx_bytes);
  429. i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
  430. I40E_GLV_UPRCL(stat_idx),
  431. vsi->stat_offsets_loaded,
  432. &oes->rx_unicast, &es->rx_unicast);
  433. i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
  434. I40E_GLV_MPRCL(stat_idx),
  435. vsi->stat_offsets_loaded,
  436. &oes->rx_multicast, &es->rx_multicast);
  437. i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
  438. I40E_GLV_BPRCL(stat_idx),
  439. vsi->stat_offsets_loaded,
  440. &oes->rx_broadcast, &es->rx_broadcast);
  441. i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
  442. I40E_GLV_GOTCL(stat_idx),
  443. vsi->stat_offsets_loaded,
  444. &oes->tx_bytes, &es->tx_bytes);
  445. i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
  446. I40E_GLV_UPTCL(stat_idx),
  447. vsi->stat_offsets_loaded,
  448. &oes->tx_unicast, &es->tx_unicast);
  449. i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
  450. I40E_GLV_MPTCL(stat_idx),
  451. vsi->stat_offsets_loaded,
  452. &oes->tx_multicast, &es->tx_multicast);
  453. i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
  454. I40E_GLV_BPTCL(stat_idx),
  455. vsi->stat_offsets_loaded,
  456. &oes->tx_broadcast, &es->tx_broadcast);
  457. vsi->stat_offsets_loaded = true;
  458. }
  459. /**
  460. * i40e_update_veb_stats - Update Switch component statistics
  461. * @veb: the VEB being updated
  462. **/
  463. static void i40e_update_veb_stats(struct i40e_veb *veb)
  464. {
  465. struct i40e_pf *pf = veb->pf;
  466. struct i40e_hw *hw = &pf->hw;
  467. struct i40e_eth_stats *oes;
  468. struct i40e_eth_stats *es; /* device's eth stats */
  469. int idx = 0;
  470. idx = veb->stats_idx;
  471. es = &veb->stats;
  472. oes = &veb->stats_offsets;
  473. /* Gather up the stats that the hw collects */
  474. i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
  475. veb->stat_offsets_loaded,
  476. &oes->tx_discards, &es->tx_discards);
  477. i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
  478. veb->stat_offsets_loaded,
  479. &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
  480. i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
  481. veb->stat_offsets_loaded,
  482. &oes->rx_bytes, &es->rx_bytes);
  483. i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
  484. veb->stat_offsets_loaded,
  485. &oes->rx_unicast, &es->rx_unicast);
  486. i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
  487. veb->stat_offsets_loaded,
  488. &oes->rx_multicast, &es->rx_multicast);
  489. i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
  490. veb->stat_offsets_loaded,
  491. &oes->rx_broadcast, &es->rx_broadcast);
  492. i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
  493. veb->stat_offsets_loaded,
  494. &oes->tx_bytes, &es->tx_bytes);
  495. i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
  496. veb->stat_offsets_loaded,
  497. &oes->tx_unicast, &es->tx_unicast);
  498. i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
  499. veb->stat_offsets_loaded,
  500. &oes->tx_multicast, &es->tx_multicast);
  501. i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
  502. veb->stat_offsets_loaded,
  503. &oes->tx_broadcast, &es->tx_broadcast);
  504. veb->stat_offsets_loaded = true;
  505. }
  506. /**
  507. * i40e_update_link_xoff_rx - Update XOFF received in link flow control mode
  508. * @pf: the corresponding PF
  509. *
  510. * Update the Rx XOFF counter (PAUSE frames) in link flow control mode
  511. **/
  512. static void i40e_update_link_xoff_rx(struct i40e_pf *pf)
  513. {
  514. struct i40e_hw_port_stats *osd = &pf->stats_offsets;
  515. struct i40e_hw_port_stats *nsd = &pf->stats;
  516. struct i40e_hw *hw = &pf->hw;
  517. u64 xoff = 0;
  518. u16 i, v;
  519. if ((hw->fc.current_mode != I40E_FC_FULL) &&
  520. (hw->fc.current_mode != I40E_FC_RX_PAUSE))
  521. return;
  522. xoff = nsd->link_xoff_rx;
  523. i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
  524. pf->stat_offsets_loaded,
  525. &osd->link_xoff_rx, &nsd->link_xoff_rx);
  526. /* No new LFC xoff rx */
  527. if (!(nsd->link_xoff_rx - xoff))
  528. return;
  529. /* Clear the __I40E_HANG_CHECK_ARMED bit for all Tx rings */
  530. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  531. struct i40e_vsi *vsi = pf->vsi[v];
  532. if (!vsi)
  533. continue;
  534. for (i = 0; i < vsi->num_queue_pairs; i++) {
  535. struct i40e_ring *ring = &vsi->tx_rings[i];
  536. clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
  537. }
  538. }
  539. }
  540. /**
  541. * i40e_update_prio_xoff_rx - Update XOFF received in PFC mode
  542. * @pf: the corresponding PF
  543. *
  544. * Update the Rx XOFF counter (PAUSE frames) in PFC mode
  545. **/
  546. static void i40e_update_prio_xoff_rx(struct i40e_pf *pf)
  547. {
  548. struct i40e_hw_port_stats *osd = &pf->stats_offsets;
  549. struct i40e_hw_port_stats *nsd = &pf->stats;
  550. bool xoff[I40E_MAX_TRAFFIC_CLASS] = {false};
  551. struct i40e_dcbx_config *dcb_cfg;
  552. struct i40e_hw *hw = &pf->hw;
  553. u16 i, v;
  554. u8 tc;
  555. dcb_cfg = &hw->local_dcbx_config;
  556. /* See if DCB enabled with PFC TC */
  557. if (!(pf->flags & I40E_FLAG_DCB_ENABLED) ||
  558. !(dcb_cfg->pfc.pfcenable)) {
  559. i40e_update_link_xoff_rx(pf);
  560. return;
  561. }
  562. for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
  563. u64 prio_xoff = nsd->priority_xoff_rx[i];
  564. i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
  565. pf->stat_offsets_loaded,
  566. &osd->priority_xoff_rx[i],
  567. &nsd->priority_xoff_rx[i]);
  568. /* No new PFC xoff rx */
  569. if (!(nsd->priority_xoff_rx[i] - prio_xoff))
  570. continue;
  571. /* Get the TC for given priority */
  572. tc = dcb_cfg->etscfg.prioritytable[i];
  573. xoff[tc] = true;
  574. }
  575. /* Clear the __I40E_HANG_CHECK_ARMED bit for Tx rings */
  576. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  577. struct i40e_vsi *vsi = pf->vsi[v];
  578. if (!vsi)
  579. continue;
  580. for (i = 0; i < vsi->num_queue_pairs; i++) {
  581. struct i40e_ring *ring = &vsi->tx_rings[i];
  582. tc = ring->dcb_tc;
  583. if (xoff[tc])
  584. clear_bit(__I40E_HANG_CHECK_ARMED,
  585. &ring->state);
  586. }
  587. }
  588. }
  589. /**
  590. * i40e_update_stats - Update the board statistics counters.
  591. * @vsi: the VSI to be updated
  592. *
  593. * There are a few instances where we store the same stat in a
  594. * couple of different structs. This is partly because we have
  595. * the netdev stats that need to be filled out, which is slightly
  596. * different from the "eth_stats" defined by the chip and used in
  597. * VF communications. We sort it all out here in a central place.
  598. **/
  599. void i40e_update_stats(struct i40e_vsi *vsi)
  600. {
  601. struct i40e_pf *pf = vsi->back;
  602. struct i40e_hw *hw = &pf->hw;
  603. struct rtnl_link_stats64 *ons;
  604. struct rtnl_link_stats64 *ns; /* netdev stats */
  605. struct i40e_eth_stats *oes;
  606. struct i40e_eth_stats *es; /* device's eth stats */
  607. u32 tx_restart, tx_busy;
  608. u32 rx_page, rx_buf;
  609. u64 rx_p, rx_b;
  610. u64 tx_p, tx_b;
  611. int i;
  612. u16 q;
  613. if (test_bit(__I40E_DOWN, &vsi->state) ||
  614. test_bit(__I40E_CONFIG_BUSY, &pf->state))
  615. return;
  616. ns = i40e_get_vsi_stats_struct(vsi);
  617. ons = &vsi->net_stats_offsets;
  618. es = &vsi->eth_stats;
  619. oes = &vsi->eth_stats_offsets;
  620. /* Gather up the netdev and vsi stats that the driver collects
  621. * on the fly during packet processing
  622. */
  623. rx_b = rx_p = 0;
  624. tx_b = tx_p = 0;
  625. tx_restart = tx_busy = 0;
  626. rx_page = 0;
  627. rx_buf = 0;
  628. for (q = 0; q < vsi->num_queue_pairs; q++) {
  629. struct i40e_ring *p;
  630. p = &vsi->rx_rings[q];
  631. rx_b += p->rx_stats.bytes;
  632. rx_p += p->rx_stats.packets;
  633. rx_buf += p->rx_stats.alloc_rx_buff_failed;
  634. rx_page += p->rx_stats.alloc_rx_page_failed;
  635. p = &vsi->tx_rings[q];
  636. tx_b += p->tx_stats.bytes;
  637. tx_p += p->tx_stats.packets;
  638. tx_restart += p->tx_stats.restart_queue;
  639. tx_busy += p->tx_stats.tx_busy;
  640. }
  641. vsi->tx_restart = tx_restart;
  642. vsi->tx_busy = tx_busy;
  643. vsi->rx_page_failed = rx_page;
  644. vsi->rx_buf_failed = rx_buf;
  645. ns->rx_packets = rx_p;
  646. ns->rx_bytes = rx_b;
  647. ns->tx_packets = tx_p;
  648. ns->tx_bytes = tx_b;
  649. i40e_update_eth_stats(vsi);
  650. /* update netdev stats from eth stats */
  651. ons->rx_errors = oes->rx_errors;
  652. ns->rx_errors = es->rx_errors;
  653. ons->tx_errors = oes->tx_errors;
  654. ns->tx_errors = es->tx_errors;
  655. ons->multicast = oes->rx_multicast;
  656. ns->multicast = es->rx_multicast;
  657. ons->tx_dropped = oes->tx_discards;
  658. ns->tx_dropped = es->tx_discards;
  659. /* Get the port data only if this is the main PF VSI */
  660. if (vsi == pf->vsi[pf->lan_vsi]) {
  661. struct i40e_hw_port_stats *nsd = &pf->stats;
  662. struct i40e_hw_port_stats *osd = &pf->stats_offsets;
  663. i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
  664. I40E_GLPRT_GORCL(hw->port),
  665. pf->stat_offsets_loaded,
  666. &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
  667. i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
  668. I40E_GLPRT_GOTCL(hw->port),
  669. pf->stat_offsets_loaded,
  670. &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
  671. i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
  672. pf->stat_offsets_loaded,
  673. &osd->eth.rx_discards,
  674. &nsd->eth.rx_discards);
  675. i40e_stat_update32(hw, I40E_GLPRT_TDPC(hw->port),
  676. pf->stat_offsets_loaded,
  677. &osd->eth.tx_discards,
  678. &nsd->eth.tx_discards);
  679. i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
  680. I40E_GLPRT_MPRCL(hw->port),
  681. pf->stat_offsets_loaded,
  682. &osd->eth.rx_multicast,
  683. &nsd->eth.rx_multicast);
  684. i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
  685. pf->stat_offsets_loaded,
  686. &osd->tx_dropped_link_down,
  687. &nsd->tx_dropped_link_down);
  688. i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
  689. pf->stat_offsets_loaded,
  690. &osd->crc_errors, &nsd->crc_errors);
  691. ns->rx_crc_errors = nsd->crc_errors;
  692. i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
  693. pf->stat_offsets_loaded,
  694. &osd->illegal_bytes, &nsd->illegal_bytes);
  695. ns->rx_errors = nsd->crc_errors
  696. + nsd->illegal_bytes;
  697. i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
  698. pf->stat_offsets_loaded,
  699. &osd->mac_local_faults,
  700. &nsd->mac_local_faults);
  701. i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
  702. pf->stat_offsets_loaded,
  703. &osd->mac_remote_faults,
  704. &nsd->mac_remote_faults);
  705. i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
  706. pf->stat_offsets_loaded,
  707. &osd->rx_length_errors,
  708. &nsd->rx_length_errors);
  709. ns->rx_length_errors = nsd->rx_length_errors;
  710. i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
  711. pf->stat_offsets_loaded,
  712. &osd->link_xon_rx, &nsd->link_xon_rx);
  713. i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
  714. pf->stat_offsets_loaded,
  715. &osd->link_xon_tx, &nsd->link_xon_tx);
  716. i40e_update_prio_xoff_rx(pf); /* handles I40E_GLPRT_LXOFFRXC */
  717. i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
  718. pf->stat_offsets_loaded,
  719. &osd->link_xoff_tx, &nsd->link_xoff_tx);
  720. for (i = 0; i < 8; i++) {
  721. i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
  722. pf->stat_offsets_loaded,
  723. &osd->priority_xon_rx[i],
  724. &nsd->priority_xon_rx[i]);
  725. i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
  726. pf->stat_offsets_loaded,
  727. &osd->priority_xon_tx[i],
  728. &nsd->priority_xon_tx[i]);
  729. i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
  730. pf->stat_offsets_loaded,
  731. &osd->priority_xoff_tx[i],
  732. &nsd->priority_xoff_tx[i]);
  733. i40e_stat_update32(hw,
  734. I40E_GLPRT_RXON2OFFCNT(hw->port, i),
  735. pf->stat_offsets_loaded,
  736. &osd->priority_xon_2_xoff[i],
  737. &nsd->priority_xon_2_xoff[i]);
  738. }
  739. i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
  740. I40E_GLPRT_PRC64L(hw->port),
  741. pf->stat_offsets_loaded,
  742. &osd->rx_size_64, &nsd->rx_size_64);
  743. i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
  744. I40E_GLPRT_PRC127L(hw->port),
  745. pf->stat_offsets_loaded,
  746. &osd->rx_size_127, &nsd->rx_size_127);
  747. i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
  748. I40E_GLPRT_PRC255L(hw->port),
  749. pf->stat_offsets_loaded,
  750. &osd->rx_size_255, &nsd->rx_size_255);
  751. i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
  752. I40E_GLPRT_PRC511L(hw->port),
  753. pf->stat_offsets_loaded,
  754. &osd->rx_size_511, &nsd->rx_size_511);
  755. i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
  756. I40E_GLPRT_PRC1023L(hw->port),
  757. pf->stat_offsets_loaded,
  758. &osd->rx_size_1023, &nsd->rx_size_1023);
  759. i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
  760. I40E_GLPRT_PRC1522L(hw->port),
  761. pf->stat_offsets_loaded,
  762. &osd->rx_size_1522, &nsd->rx_size_1522);
  763. i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
  764. I40E_GLPRT_PRC9522L(hw->port),
  765. pf->stat_offsets_loaded,
  766. &osd->rx_size_big, &nsd->rx_size_big);
  767. i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
  768. I40E_GLPRT_PTC64L(hw->port),
  769. pf->stat_offsets_loaded,
  770. &osd->tx_size_64, &nsd->tx_size_64);
  771. i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
  772. I40E_GLPRT_PTC127L(hw->port),
  773. pf->stat_offsets_loaded,
  774. &osd->tx_size_127, &nsd->tx_size_127);
  775. i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
  776. I40E_GLPRT_PTC255L(hw->port),
  777. pf->stat_offsets_loaded,
  778. &osd->tx_size_255, &nsd->tx_size_255);
  779. i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
  780. I40E_GLPRT_PTC511L(hw->port),
  781. pf->stat_offsets_loaded,
  782. &osd->tx_size_511, &nsd->tx_size_511);
  783. i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
  784. I40E_GLPRT_PTC1023L(hw->port),
  785. pf->stat_offsets_loaded,
  786. &osd->tx_size_1023, &nsd->tx_size_1023);
  787. i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
  788. I40E_GLPRT_PTC1522L(hw->port),
  789. pf->stat_offsets_loaded,
  790. &osd->tx_size_1522, &nsd->tx_size_1522);
  791. i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
  792. I40E_GLPRT_PTC9522L(hw->port),
  793. pf->stat_offsets_loaded,
  794. &osd->tx_size_big, &nsd->tx_size_big);
  795. i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
  796. pf->stat_offsets_loaded,
  797. &osd->rx_undersize, &nsd->rx_undersize);
  798. i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
  799. pf->stat_offsets_loaded,
  800. &osd->rx_fragments, &nsd->rx_fragments);
  801. i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
  802. pf->stat_offsets_loaded,
  803. &osd->rx_oversize, &nsd->rx_oversize);
  804. i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
  805. pf->stat_offsets_loaded,
  806. &osd->rx_jabber, &nsd->rx_jabber);
  807. }
  808. pf->stat_offsets_loaded = true;
  809. }
  810. /**
  811. * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
  812. * @vsi: the VSI to be searched
  813. * @macaddr: the MAC address
  814. * @vlan: the vlan
  815. * @is_vf: make sure its a vf filter, else doesn't matter
  816. * @is_netdev: make sure its a netdev filter, else doesn't matter
  817. *
  818. * Returns ptr to the filter object or NULL
  819. **/
  820. static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
  821. u8 *macaddr, s16 vlan,
  822. bool is_vf, bool is_netdev)
  823. {
  824. struct i40e_mac_filter *f;
  825. if (!vsi || !macaddr)
  826. return NULL;
  827. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  828. if ((ether_addr_equal(macaddr, f->macaddr)) &&
  829. (vlan == f->vlan) &&
  830. (!is_vf || f->is_vf) &&
  831. (!is_netdev || f->is_netdev))
  832. return f;
  833. }
  834. return NULL;
  835. }
  836. /**
  837. * i40e_find_mac - Find a mac addr in the macvlan filters list
  838. * @vsi: the VSI to be searched
  839. * @macaddr: the MAC address we are searching for
  840. * @is_vf: make sure its a vf filter, else doesn't matter
  841. * @is_netdev: make sure its a netdev filter, else doesn't matter
  842. *
  843. * Returns the first filter with the provided MAC address or NULL if
  844. * MAC address was not found
  845. **/
  846. struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
  847. bool is_vf, bool is_netdev)
  848. {
  849. struct i40e_mac_filter *f;
  850. if (!vsi || !macaddr)
  851. return NULL;
  852. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  853. if ((ether_addr_equal(macaddr, f->macaddr)) &&
  854. (!is_vf || f->is_vf) &&
  855. (!is_netdev || f->is_netdev))
  856. return f;
  857. }
  858. return NULL;
  859. }
  860. /**
  861. * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
  862. * @vsi: the VSI to be searched
  863. *
  864. * Returns true if VSI is in vlan mode or false otherwise
  865. **/
  866. bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
  867. {
  868. struct i40e_mac_filter *f;
  869. /* Only -1 for all the filters denotes not in vlan mode
  870. * so we have to go through all the list in order to make sure
  871. */
  872. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  873. if (f->vlan >= 0)
  874. return true;
  875. }
  876. return false;
  877. }
  878. /**
  879. * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
  880. * @vsi: the VSI to be searched
  881. * @macaddr: the mac address to be filtered
  882. * @is_vf: true if it is a vf
  883. * @is_netdev: true if it is a netdev
  884. *
  885. * Goes through all the macvlan filters and adds a
  886. * macvlan filter for each unique vlan that already exists
  887. *
  888. * Returns first filter found on success, else NULL
  889. **/
  890. struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
  891. bool is_vf, bool is_netdev)
  892. {
  893. struct i40e_mac_filter *f;
  894. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  895. if (!i40e_find_filter(vsi, macaddr, f->vlan,
  896. is_vf, is_netdev)) {
  897. if (!i40e_add_filter(vsi, macaddr, f->vlan,
  898. is_vf, is_netdev))
  899. return NULL;
  900. }
  901. }
  902. return list_first_entry_or_null(&vsi->mac_filter_list,
  903. struct i40e_mac_filter, list);
  904. }
  905. /**
  906. * i40e_add_filter - Add a mac/vlan filter to the VSI
  907. * @vsi: the VSI to be searched
  908. * @macaddr: the MAC address
  909. * @vlan: the vlan
  910. * @is_vf: make sure its a vf filter, else doesn't matter
  911. * @is_netdev: make sure its a netdev filter, else doesn't matter
  912. *
  913. * Returns ptr to the filter object or NULL when no memory available.
  914. **/
  915. struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
  916. u8 *macaddr, s16 vlan,
  917. bool is_vf, bool is_netdev)
  918. {
  919. struct i40e_mac_filter *f;
  920. if (!vsi || !macaddr)
  921. return NULL;
  922. f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
  923. if (!f) {
  924. f = kzalloc(sizeof(*f), GFP_ATOMIC);
  925. if (!f)
  926. goto add_filter_out;
  927. memcpy(f->macaddr, macaddr, ETH_ALEN);
  928. f->vlan = vlan;
  929. f->changed = true;
  930. INIT_LIST_HEAD(&f->list);
  931. list_add(&f->list, &vsi->mac_filter_list);
  932. }
  933. /* increment counter and add a new flag if needed */
  934. if (is_vf) {
  935. if (!f->is_vf) {
  936. f->is_vf = true;
  937. f->counter++;
  938. }
  939. } else if (is_netdev) {
  940. if (!f->is_netdev) {
  941. f->is_netdev = true;
  942. f->counter++;
  943. }
  944. } else {
  945. f->counter++;
  946. }
  947. /* changed tells sync_filters_subtask to
  948. * push the filter down to the firmware
  949. */
  950. if (f->changed) {
  951. vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
  952. vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
  953. }
  954. add_filter_out:
  955. return f;
  956. }
  957. /**
  958. * i40e_del_filter - Remove a mac/vlan filter from the VSI
  959. * @vsi: the VSI to be searched
  960. * @macaddr: the MAC address
  961. * @vlan: the vlan
  962. * @is_vf: make sure it's a vf filter, else doesn't matter
  963. * @is_netdev: make sure it's a netdev filter, else doesn't matter
  964. **/
  965. void i40e_del_filter(struct i40e_vsi *vsi,
  966. u8 *macaddr, s16 vlan,
  967. bool is_vf, bool is_netdev)
  968. {
  969. struct i40e_mac_filter *f;
  970. if (!vsi || !macaddr)
  971. return;
  972. f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
  973. if (!f || f->counter == 0)
  974. return;
  975. if (is_vf) {
  976. if (f->is_vf) {
  977. f->is_vf = false;
  978. f->counter--;
  979. }
  980. } else if (is_netdev) {
  981. if (f->is_netdev) {
  982. f->is_netdev = false;
  983. f->counter--;
  984. }
  985. } else {
  986. /* make sure we don't remove a filter in use by vf or netdev */
  987. int min_f = 0;
  988. min_f += (f->is_vf ? 1 : 0);
  989. min_f += (f->is_netdev ? 1 : 0);
  990. if (f->counter > min_f)
  991. f->counter--;
  992. }
  993. /* counter == 0 tells sync_filters_subtask to
  994. * remove the filter from the firmware's list
  995. */
  996. if (f->counter == 0) {
  997. f->changed = true;
  998. vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
  999. vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
  1000. }
  1001. }
  1002. /**
  1003. * i40e_set_mac - NDO callback to set mac address
  1004. * @netdev: network interface device structure
  1005. * @p: pointer to an address structure
  1006. *
  1007. * Returns 0 on success, negative on failure
  1008. **/
  1009. static int i40e_set_mac(struct net_device *netdev, void *p)
  1010. {
  1011. struct i40e_netdev_priv *np = netdev_priv(netdev);
  1012. struct i40e_vsi *vsi = np->vsi;
  1013. struct sockaddr *addr = p;
  1014. struct i40e_mac_filter *f;
  1015. if (!is_valid_ether_addr(addr->sa_data))
  1016. return -EADDRNOTAVAIL;
  1017. netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
  1018. if (ether_addr_equal(netdev->dev_addr, addr->sa_data))
  1019. return 0;
  1020. if (vsi->type == I40E_VSI_MAIN) {
  1021. i40e_status ret;
  1022. ret = i40e_aq_mac_address_write(&vsi->back->hw,
  1023. I40E_AQC_WRITE_TYPE_LAA_ONLY,
  1024. addr->sa_data, NULL);
  1025. if (ret) {
  1026. netdev_info(netdev,
  1027. "Addr change for Main VSI failed: %d\n",
  1028. ret);
  1029. return -EADDRNOTAVAIL;
  1030. }
  1031. memcpy(vsi->back->hw.mac.addr, addr->sa_data, netdev->addr_len);
  1032. }
  1033. /* In order to be sure to not drop any packets, add the new address
  1034. * then delete the old one.
  1035. */
  1036. f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY, false, false);
  1037. if (!f)
  1038. return -ENOMEM;
  1039. i40e_sync_vsi_filters(vsi);
  1040. i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY, false, false);
  1041. i40e_sync_vsi_filters(vsi);
  1042. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  1043. return 0;
  1044. }
  1045. /**
  1046. * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
  1047. * @vsi: the VSI being setup
  1048. * @ctxt: VSI context structure
  1049. * @enabled_tc: Enabled TCs bitmap
  1050. * @is_add: True if called before Add VSI
  1051. *
  1052. * Setup VSI queue mapping for enabled traffic classes.
  1053. **/
  1054. static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
  1055. struct i40e_vsi_context *ctxt,
  1056. u8 enabled_tc,
  1057. bool is_add)
  1058. {
  1059. struct i40e_pf *pf = vsi->back;
  1060. u16 sections = 0;
  1061. u8 netdev_tc = 0;
  1062. u16 numtc = 0;
  1063. u16 qcount;
  1064. u8 offset;
  1065. u16 qmap;
  1066. int i;
  1067. sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
  1068. offset = 0;
  1069. if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
  1070. /* Find numtc from enabled TC bitmap */
  1071. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  1072. if (enabled_tc & (1 << i)) /* TC is enabled */
  1073. numtc++;
  1074. }
  1075. if (!numtc) {
  1076. dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
  1077. numtc = 1;
  1078. }
  1079. } else {
  1080. /* At least TC0 is enabled in case of non-DCB case */
  1081. numtc = 1;
  1082. }
  1083. vsi->tc_config.numtc = numtc;
  1084. vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
  1085. /* Setup queue offset/count for all TCs for given VSI */
  1086. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  1087. /* See if the given TC is enabled for the given VSI */
  1088. if (vsi->tc_config.enabled_tc & (1 << i)) { /* TC is enabled */
  1089. int pow, num_qps;
  1090. vsi->tc_config.tc_info[i].qoffset = offset;
  1091. switch (vsi->type) {
  1092. case I40E_VSI_MAIN:
  1093. if (i == 0)
  1094. qcount = pf->rss_size;
  1095. else
  1096. qcount = pf->num_tc_qps;
  1097. vsi->tc_config.tc_info[i].qcount = qcount;
  1098. break;
  1099. case I40E_VSI_FDIR:
  1100. case I40E_VSI_SRIOV:
  1101. case I40E_VSI_VMDQ2:
  1102. default:
  1103. qcount = vsi->alloc_queue_pairs;
  1104. vsi->tc_config.tc_info[i].qcount = qcount;
  1105. WARN_ON(i != 0);
  1106. break;
  1107. }
  1108. /* find the power-of-2 of the number of queue pairs */
  1109. num_qps = vsi->tc_config.tc_info[i].qcount;
  1110. pow = 0;
  1111. while (num_qps &&
  1112. ((1 << pow) < vsi->tc_config.tc_info[i].qcount)) {
  1113. pow++;
  1114. num_qps >>= 1;
  1115. }
  1116. vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
  1117. qmap =
  1118. (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
  1119. (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
  1120. offset += vsi->tc_config.tc_info[i].qcount;
  1121. } else {
  1122. /* TC is not enabled so set the offset to
  1123. * default queue and allocate one queue
  1124. * for the given TC.
  1125. */
  1126. vsi->tc_config.tc_info[i].qoffset = 0;
  1127. vsi->tc_config.tc_info[i].qcount = 1;
  1128. vsi->tc_config.tc_info[i].netdev_tc = 0;
  1129. qmap = 0;
  1130. }
  1131. ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
  1132. }
  1133. /* Set actual Tx/Rx queue pairs */
  1134. vsi->num_queue_pairs = offset;
  1135. /* Scheduler section valid can only be set for ADD VSI */
  1136. if (is_add) {
  1137. sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
  1138. ctxt->info.up_enable_bits = enabled_tc;
  1139. }
  1140. if (vsi->type == I40E_VSI_SRIOV) {
  1141. ctxt->info.mapping_flags |=
  1142. cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
  1143. for (i = 0; i < vsi->num_queue_pairs; i++)
  1144. ctxt->info.queue_mapping[i] =
  1145. cpu_to_le16(vsi->base_queue + i);
  1146. } else {
  1147. ctxt->info.mapping_flags |=
  1148. cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
  1149. ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
  1150. }
  1151. ctxt->info.valid_sections |= cpu_to_le16(sections);
  1152. }
  1153. /**
  1154. * i40e_set_rx_mode - NDO callback to set the netdev filters
  1155. * @netdev: network interface device structure
  1156. **/
  1157. static void i40e_set_rx_mode(struct net_device *netdev)
  1158. {
  1159. struct i40e_netdev_priv *np = netdev_priv(netdev);
  1160. struct i40e_mac_filter *f, *ftmp;
  1161. struct i40e_vsi *vsi = np->vsi;
  1162. struct netdev_hw_addr *uca;
  1163. struct netdev_hw_addr *mca;
  1164. struct netdev_hw_addr *ha;
  1165. /* add addr if not already in the filter list */
  1166. netdev_for_each_uc_addr(uca, netdev) {
  1167. if (!i40e_find_mac(vsi, uca->addr, false, true)) {
  1168. if (i40e_is_vsi_in_vlan(vsi))
  1169. i40e_put_mac_in_vlan(vsi, uca->addr,
  1170. false, true);
  1171. else
  1172. i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
  1173. false, true);
  1174. }
  1175. }
  1176. netdev_for_each_mc_addr(mca, netdev) {
  1177. if (!i40e_find_mac(vsi, mca->addr, false, true)) {
  1178. if (i40e_is_vsi_in_vlan(vsi))
  1179. i40e_put_mac_in_vlan(vsi, mca->addr,
  1180. false, true);
  1181. else
  1182. i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
  1183. false, true);
  1184. }
  1185. }
  1186. /* remove filter if not in netdev list */
  1187. list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
  1188. bool found = false;
  1189. if (!f->is_netdev)
  1190. continue;
  1191. if (is_multicast_ether_addr(f->macaddr)) {
  1192. netdev_for_each_mc_addr(mca, netdev) {
  1193. if (ether_addr_equal(mca->addr, f->macaddr)) {
  1194. found = true;
  1195. break;
  1196. }
  1197. }
  1198. } else {
  1199. netdev_for_each_uc_addr(uca, netdev) {
  1200. if (ether_addr_equal(uca->addr, f->macaddr)) {
  1201. found = true;
  1202. break;
  1203. }
  1204. }
  1205. for_each_dev_addr(netdev, ha) {
  1206. if (ether_addr_equal(ha->addr, f->macaddr)) {
  1207. found = true;
  1208. break;
  1209. }
  1210. }
  1211. }
  1212. if (!found)
  1213. i40e_del_filter(
  1214. vsi, f->macaddr, I40E_VLAN_ANY, false, true);
  1215. }
  1216. /* check for other flag changes */
  1217. if (vsi->current_netdev_flags != vsi->netdev->flags) {
  1218. vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
  1219. vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
  1220. }
  1221. }
  1222. /**
  1223. * i40e_sync_vsi_filters - Update the VSI filter list to the HW
  1224. * @vsi: ptr to the VSI
  1225. *
  1226. * Push any outstanding VSI filter changes through the AdminQ.
  1227. *
  1228. * Returns 0 or error value
  1229. **/
  1230. int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
  1231. {
  1232. struct i40e_mac_filter *f, *ftmp;
  1233. bool promisc_forced_on = false;
  1234. bool add_happened = false;
  1235. int filter_list_len = 0;
  1236. u32 changed_flags = 0;
  1237. i40e_status aq_ret = 0;
  1238. struct i40e_pf *pf;
  1239. int num_add = 0;
  1240. int num_del = 0;
  1241. u16 cmd_flags;
  1242. /* empty array typed pointers, kcalloc later */
  1243. struct i40e_aqc_add_macvlan_element_data *add_list;
  1244. struct i40e_aqc_remove_macvlan_element_data *del_list;
  1245. while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
  1246. usleep_range(1000, 2000);
  1247. pf = vsi->back;
  1248. if (vsi->netdev) {
  1249. changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
  1250. vsi->current_netdev_flags = vsi->netdev->flags;
  1251. }
  1252. if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
  1253. vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
  1254. filter_list_len = pf->hw.aq.asq_buf_size /
  1255. sizeof(struct i40e_aqc_remove_macvlan_element_data);
  1256. del_list = kcalloc(filter_list_len,
  1257. sizeof(struct i40e_aqc_remove_macvlan_element_data),
  1258. GFP_KERNEL);
  1259. if (!del_list)
  1260. return -ENOMEM;
  1261. list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
  1262. if (!f->changed)
  1263. continue;
  1264. if (f->counter != 0)
  1265. continue;
  1266. f->changed = false;
  1267. cmd_flags = 0;
  1268. /* add to delete list */
  1269. memcpy(del_list[num_del].mac_addr,
  1270. f->macaddr, ETH_ALEN);
  1271. del_list[num_del].vlan_tag =
  1272. cpu_to_le16((u16)(f->vlan ==
  1273. I40E_VLAN_ANY ? 0 : f->vlan));
  1274. /* vlan0 as wild card to allow packets from all vlans */
  1275. if (f->vlan == I40E_VLAN_ANY ||
  1276. (vsi->netdev && !(vsi->netdev->features &
  1277. NETIF_F_HW_VLAN_CTAG_FILTER)))
  1278. cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
  1279. cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
  1280. del_list[num_del].flags = cmd_flags;
  1281. num_del++;
  1282. /* unlink from filter list */
  1283. list_del(&f->list);
  1284. kfree(f);
  1285. /* flush a full buffer */
  1286. if (num_del == filter_list_len) {
  1287. aq_ret = i40e_aq_remove_macvlan(&pf->hw,
  1288. vsi->seid, del_list, num_del,
  1289. NULL);
  1290. num_del = 0;
  1291. memset(del_list, 0, sizeof(*del_list));
  1292. if (aq_ret)
  1293. dev_info(&pf->pdev->dev,
  1294. "ignoring delete macvlan error, err %d, aq_err %d while flushing a full buffer\n",
  1295. aq_ret,
  1296. pf->hw.aq.asq_last_status);
  1297. }
  1298. }
  1299. if (num_del) {
  1300. aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
  1301. del_list, num_del, NULL);
  1302. num_del = 0;
  1303. if (aq_ret)
  1304. dev_info(&pf->pdev->dev,
  1305. "ignoring delete macvlan error, err %d, aq_err %d\n",
  1306. aq_ret, pf->hw.aq.asq_last_status);
  1307. }
  1308. kfree(del_list);
  1309. del_list = NULL;
  1310. /* do all the adds now */
  1311. filter_list_len = pf->hw.aq.asq_buf_size /
  1312. sizeof(struct i40e_aqc_add_macvlan_element_data),
  1313. add_list = kcalloc(filter_list_len,
  1314. sizeof(struct i40e_aqc_add_macvlan_element_data),
  1315. GFP_KERNEL);
  1316. if (!add_list)
  1317. return -ENOMEM;
  1318. list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
  1319. if (!f->changed)
  1320. continue;
  1321. if (f->counter == 0)
  1322. continue;
  1323. f->changed = false;
  1324. add_happened = true;
  1325. cmd_flags = 0;
  1326. /* add to add array */
  1327. memcpy(add_list[num_add].mac_addr,
  1328. f->macaddr, ETH_ALEN);
  1329. add_list[num_add].vlan_tag =
  1330. cpu_to_le16(
  1331. (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
  1332. add_list[num_add].queue_number = 0;
  1333. cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
  1334. /* vlan0 as wild card to allow packets from all vlans */
  1335. if (f->vlan == I40E_VLAN_ANY || (vsi->netdev &&
  1336. !(vsi->netdev->features &
  1337. NETIF_F_HW_VLAN_CTAG_FILTER)))
  1338. cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
  1339. add_list[num_add].flags = cpu_to_le16(cmd_flags);
  1340. num_add++;
  1341. /* flush a full buffer */
  1342. if (num_add == filter_list_len) {
  1343. aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
  1344. add_list, num_add,
  1345. NULL);
  1346. num_add = 0;
  1347. if (aq_ret)
  1348. break;
  1349. memset(add_list, 0, sizeof(*add_list));
  1350. }
  1351. }
  1352. if (num_add) {
  1353. aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
  1354. add_list, num_add, NULL);
  1355. num_add = 0;
  1356. }
  1357. kfree(add_list);
  1358. add_list = NULL;
  1359. if (add_happened && (!aq_ret)) {
  1360. /* do nothing */;
  1361. } else if (add_happened && (aq_ret)) {
  1362. dev_info(&pf->pdev->dev,
  1363. "add filter failed, err %d, aq_err %d\n",
  1364. aq_ret, pf->hw.aq.asq_last_status);
  1365. if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
  1366. !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
  1367. &vsi->state)) {
  1368. promisc_forced_on = true;
  1369. set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
  1370. &vsi->state);
  1371. dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
  1372. }
  1373. }
  1374. }
  1375. /* check for changes in promiscuous modes */
  1376. if (changed_flags & IFF_ALLMULTI) {
  1377. bool cur_multipromisc;
  1378. cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
  1379. aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
  1380. vsi->seid,
  1381. cur_multipromisc,
  1382. NULL);
  1383. if (aq_ret)
  1384. dev_info(&pf->pdev->dev,
  1385. "set multi promisc failed, err %d, aq_err %d\n",
  1386. aq_ret, pf->hw.aq.asq_last_status);
  1387. }
  1388. if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
  1389. bool cur_promisc;
  1390. cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
  1391. test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
  1392. &vsi->state));
  1393. aq_ret = i40e_aq_set_vsi_unicast_promiscuous(&vsi->back->hw,
  1394. vsi->seid,
  1395. cur_promisc, NULL);
  1396. if (aq_ret)
  1397. dev_info(&pf->pdev->dev,
  1398. "set uni promisc failed, err %d, aq_err %d\n",
  1399. aq_ret, pf->hw.aq.asq_last_status);
  1400. }
  1401. clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
  1402. return 0;
  1403. }
  1404. /**
  1405. * i40e_sync_filters_subtask - Sync the VSI filter list with HW
  1406. * @pf: board private structure
  1407. **/
  1408. static void i40e_sync_filters_subtask(struct i40e_pf *pf)
  1409. {
  1410. int v;
  1411. if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
  1412. return;
  1413. pf->flags &= ~I40E_FLAG_FILTER_SYNC;
  1414. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  1415. if (pf->vsi[v] &&
  1416. (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED))
  1417. i40e_sync_vsi_filters(pf->vsi[v]);
  1418. }
  1419. }
  1420. /**
  1421. * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
  1422. * @netdev: network interface device structure
  1423. * @new_mtu: new value for maximum frame size
  1424. *
  1425. * Returns 0 on success, negative on failure
  1426. **/
  1427. static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
  1428. {
  1429. struct i40e_netdev_priv *np = netdev_priv(netdev);
  1430. int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
  1431. struct i40e_vsi *vsi = np->vsi;
  1432. /* MTU < 68 is an error and causes problems on some kernels */
  1433. if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
  1434. return -EINVAL;
  1435. netdev_info(netdev, "changing MTU from %d to %d\n",
  1436. netdev->mtu, new_mtu);
  1437. netdev->mtu = new_mtu;
  1438. if (netif_running(netdev))
  1439. i40e_vsi_reinit_locked(vsi);
  1440. return 0;
  1441. }
  1442. /**
  1443. * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
  1444. * @vsi: the vsi being adjusted
  1445. **/
  1446. void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
  1447. {
  1448. struct i40e_vsi_context ctxt;
  1449. i40e_status ret;
  1450. if ((vsi->info.valid_sections &
  1451. cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
  1452. ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
  1453. return; /* already enabled */
  1454. vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
  1455. vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
  1456. I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
  1457. ctxt.seid = vsi->seid;
  1458. memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
  1459. ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
  1460. if (ret) {
  1461. dev_info(&vsi->back->pdev->dev,
  1462. "%s: update vsi failed, aq_err=%d\n",
  1463. __func__, vsi->back->hw.aq.asq_last_status);
  1464. }
  1465. }
  1466. /**
  1467. * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
  1468. * @vsi: the vsi being adjusted
  1469. **/
  1470. void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
  1471. {
  1472. struct i40e_vsi_context ctxt;
  1473. i40e_status ret;
  1474. if ((vsi->info.valid_sections &
  1475. cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
  1476. ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
  1477. I40E_AQ_VSI_PVLAN_EMOD_MASK))
  1478. return; /* already disabled */
  1479. vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
  1480. vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
  1481. I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
  1482. ctxt.seid = vsi->seid;
  1483. memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
  1484. ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
  1485. if (ret) {
  1486. dev_info(&vsi->back->pdev->dev,
  1487. "%s: update vsi failed, aq_err=%d\n",
  1488. __func__, vsi->back->hw.aq.asq_last_status);
  1489. }
  1490. }
  1491. /**
  1492. * i40e_vlan_rx_register - Setup or shutdown vlan offload
  1493. * @netdev: network interface to be adjusted
  1494. * @features: netdev features to test if VLAN offload is enabled or not
  1495. **/
  1496. static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
  1497. {
  1498. struct i40e_netdev_priv *np = netdev_priv(netdev);
  1499. struct i40e_vsi *vsi = np->vsi;
  1500. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1501. i40e_vlan_stripping_enable(vsi);
  1502. else
  1503. i40e_vlan_stripping_disable(vsi);
  1504. }
  1505. /**
  1506. * i40e_vsi_add_vlan - Add vsi membership for given vlan
  1507. * @vsi: the vsi being configured
  1508. * @vid: vlan id to be added (0 = untagged only , -1 = any)
  1509. **/
  1510. int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
  1511. {
  1512. struct i40e_mac_filter *f, *add_f;
  1513. bool is_netdev, is_vf;
  1514. int ret;
  1515. is_vf = (vsi->type == I40E_VSI_SRIOV);
  1516. is_netdev = !!(vsi->netdev);
  1517. if (is_netdev) {
  1518. add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
  1519. is_vf, is_netdev);
  1520. if (!add_f) {
  1521. dev_info(&vsi->back->pdev->dev,
  1522. "Could not add vlan filter %d for %pM\n",
  1523. vid, vsi->netdev->dev_addr);
  1524. return -ENOMEM;
  1525. }
  1526. }
  1527. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  1528. add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
  1529. if (!add_f) {
  1530. dev_info(&vsi->back->pdev->dev,
  1531. "Could not add vlan filter %d for %pM\n",
  1532. vid, f->macaddr);
  1533. return -ENOMEM;
  1534. }
  1535. }
  1536. ret = i40e_sync_vsi_filters(vsi);
  1537. if (ret) {
  1538. dev_info(&vsi->back->pdev->dev,
  1539. "Could not sync filters for vid %d\n", vid);
  1540. return ret;
  1541. }
  1542. /* Now if we add a vlan tag, make sure to check if it is the first
  1543. * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
  1544. * with 0, so we now accept untagged and specified tagged traffic
  1545. * (and not any taged and untagged)
  1546. */
  1547. if (vid > 0) {
  1548. if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
  1549. I40E_VLAN_ANY,
  1550. is_vf, is_netdev)) {
  1551. i40e_del_filter(vsi, vsi->netdev->dev_addr,
  1552. I40E_VLAN_ANY, is_vf, is_netdev);
  1553. add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
  1554. is_vf, is_netdev);
  1555. if (!add_f) {
  1556. dev_info(&vsi->back->pdev->dev,
  1557. "Could not add filter 0 for %pM\n",
  1558. vsi->netdev->dev_addr);
  1559. return -ENOMEM;
  1560. }
  1561. }
  1562. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  1563. if (i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
  1564. is_vf, is_netdev)) {
  1565. i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
  1566. is_vf, is_netdev);
  1567. add_f = i40e_add_filter(vsi, f->macaddr,
  1568. 0, is_vf, is_netdev);
  1569. if (!add_f) {
  1570. dev_info(&vsi->back->pdev->dev,
  1571. "Could not add filter 0 for %pM\n",
  1572. f->macaddr);
  1573. return -ENOMEM;
  1574. }
  1575. }
  1576. }
  1577. ret = i40e_sync_vsi_filters(vsi);
  1578. }
  1579. return ret;
  1580. }
  1581. /**
  1582. * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
  1583. * @vsi: the vsi being configured
  1584. * @vid: vlan id to be removed (0 = untagged only , -1 = any)
  1585. **/
  1586. int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
  1587. {
  1588. struct net_device *netdev = vsi->netdev;
  1589. struct i40e_mac_filter *f, *add_f;
  1590. bool is_vf, is_netdev;
  1591. int filter_count = 0;
  1592. int ret;
  1593. is_vf = (vsi->type == I40E_VSI_SRIOV);
  1594. is_netdev = !!(netdev);
  1595. if (is_netdev)
  1596. i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
  1597. list_for_each_entry(f, &vsi->mac_filter_list, list)
  1598. i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
  1599. ret = i40e_sync_vsi_filters(vsi);
  1600. if (ret) {
  1601. dev_info(&vsi->back->pdev->dev, "Could not sync filters\n");
  1602. return ret;
  1603. }
  1604. /* go through all the filters for this VSI and if there is only
  1605. * vid == 0 it means there are no other filters, so vid 0 must
  1606. * be replaced with -1. This signifies that we should from now
  1607. * on accept any traffic (with any tag present, or untagged)
  1608. */
  1609. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  1610. if (is_netdev) {
  1611. if (f->vlan &&
  1612. ether_addr_equal(netdev->dev_addr, f->macaddr))
  1613. filter_count++;
  1614. }
  1615. if (f->vlan)
  1616. filter_count++;
  1617. }
  1618. if (!filter_count && is_netdev) {
  1619. i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
  1620. f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
  1621. is_vf, is_netdev);
  1622. if (!f) {
  1623. dev_info(&vsi->back->pdev->dev,
  1624. "Could not add filter %d for %pM\n",
  1625. I40E_VLAN_ANY, netdev->dev_addr);
  1626. return -ENOMEM;
  1627. }
  1628. }
  1629. if (!filter_count) {
  1630. list_for_each_entry(f, &vsi->mac_filter_list, list) {
  1631. i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
  1632. add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
  1633. is_vf, is_netdev);
  1634. if (!add_f) {
  1635. dev_info(&vsi->back->pdev->dev,
  1636. "Could not add filter %d for %pM\n",
  1637. I40E_VLAN_ANY, f->macaddr);
  1638. return -ENOMEM;
  1639. }
  1640. }
  1641. }
  1642. return i40e_sync_vsi_filters(vsi);
  1643. }
  1644. /**
  1645. * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
  1646. * @netdev: network interface to be adjusted
  1647. * @vid: vlan id to be added
  1648. **/
  1649. static int i40e_vlan_rx_add_vid(struct net_device *netdev,
  1650. __always_unused __be16 proto, u16 vid)
  1651. {
  1652. struct i40e_netdev_priv *np = netdev_priv(netdev);
  1653. struct i40e_vsi *vsi = np->vsi;
  1654. int ret;
  1655. if (vid > 4095)
  1656. return 0;
  1657. netdev_info(vsi->netdev, "adding %pM vid=%d\n",
  1658. netdev->dev_addr, vid);
  1659. /* If the network stack called us with vid = 0, we should
  1660. * indicate to i40e_vsi_add_vlan() that we want to receive
  1661. * any traffic (i.e. with any vlan tag, or untagged)
  1662. */
  1663. ret = i40e_vsi_add_vlan(vsi, vid ? vid : I40E_VLAN_ANY);
  1664. if (!ret) {
  1665. if (vid < VLAN_N_VID)
  1666. set_bit(vid, vsi->active_vlans);
  1667. }
  1668. return 0;
  1669. }
  1670. /**
  1671. * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
  1672. * @netdev: network interface to be adjusted
  1673. * @vid: vlan id to be removed
  1674. **/
  1675. static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
  1676. __always_unused __be16 proto, u16 vid)
  1677. {
  1678. struct i40e_netdev_priv *np = netdev_priv(netdev);
  1679. struct i40e_vsi *vsi = np->vsi;
  1680. netdev_info(vsi->netdev, "removing %pM vid=%d\n",
  1681. netdev->dev_addr, vid);
  1682. /* return code is ignored as there is nothing a user
  1683. * can do about failure to remove and a log message was
  1684. * already printed from another function
  1685. */
  1686. i40e_vsi_kill_vlan(vsi, vid);
  1687. clear_bit(vid, vsi->active_vlans);
  1688. return 0;
  1689. }
  1690. /**
  1691. * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
  1692. * @vsi: the vsi being brought back up
  1693. **/
  1694. static void i40e_restore_vlan(struct i40e_vsi *vsi)
  1695. {
  1696. u16 vid;
  1697. if (!vsi->netdev)
  1698. return;
  1699. i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
  1700. for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
  1701. i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
  1702. vid);
  1703. }
  1704. /**
  1705. * i40e_vsi_add_pvid - Add pvid for the VSI
  1706. * @vsi: the vsi being adjusted
  1707. * @vid: the vlan id to set as a PVID
  1708. **/
  1709. int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
  1710. {
  1711. struct i40e_vsi_context ctxt;
  1712. i40e_status aq_ret;
  1713. vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
  1714. vsi->info.pvid = cpu_to_le16(vid);
  1715. vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
  1716. vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
  1717. ctxt.seid = vsi->seid;
  1718. memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
  1719. aq_ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
  1720. if (aq_ret) {
  1721. dev_info(&vsi->back->pdev->dev,
  1722. "%s: update vsi failed, aq_err=%d\n",
  1723. __func__, vsi->back->hw.aq.asq_last_status);
  1724. return -ENOENT;
  1725. }
  1726. return 0;
  1727. }
  1728. /**
  1729. * i40e_vsi_remove_pvid - Remove the pvid from the VSI
  1730. * @vsi: the vsi being adjusted
  1731. *
  1732. * Just use the vlan_rx_register() service to put it back to normal
  1733. **/
  1734. void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
  1735. {
  1736. vsi->info.pvid = 0;
  1737. i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
  1738. }
  1739. /**
  1740. * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
  1741. * @vsi: ptr to the VSI
  1742. *
  1743. * If this function returns with an error, then it's possible one or
  1744. * more of the rings is populated (while the rest are not). It is the
  1745. * callers duty to clean those orphaned rings.
  1746. *
  1747. * Return 0 on success, negative on failure
  1748. **/
  1749. static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
  1750. {
  1751. int i, err = 0;
  1752. for (i = 0; i < vsi->num_queue_pairs && !err; i++)
  1753. err = i40e_setup_tx_descriptors(&vsi->tx_rings[i]);
  1754. return err;
  1755. }
  1756. /**
  1757. * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
  1758. * @vsi: ptr to the VSI
  1759. *
  1760. * Free VSI's transmit software resources
  1761. **/
  1762. static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
  1763. {
  1764. int i;
  1765. for (i = 0; i < vsi->num_queue_pairs; i++)
  1766. if (vsi->tx_rings[i].desc)
  1767. i40e_free_tx_resources(&vsi->tx_rings[i]);
  1768. }
  1769. /**
  1770. * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
  1771. * @vsi: ptr to the VSI
  1772. *
  1773. * If this function returns with an error, then it's possible one or
  1774. * more of the rings is populated (while the rest are not). It is the
  1775. * callers duty to clean those orphaned rings.
  1776. *
  1777. * Return 0 on success, negative on failure
  1778. **/
  1779. static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
  1780. {
  1781. int i, err = 0;
  1782. for (i = 0; i < vsi->num_queue_pairs && !err; i++)
  1783. err = i40e_setup_rx_descriptors(&vsi->rx_rings[i]);
  1784. return err;
  1785. }
  1786. /**
  1787. * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
  1788. * @vsi: ptr to the VSI
  1789. *
  1790. * Free all receive software resources
  1791. **/
  1792. static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
  1793. {
  1794. int i;
  1795. for (i = 0; i < vsi->num_queue_pairs; i++)
  1796. if (vsi->rx_rings[i].desc)
  1797. i40e_free_rx_resources(&vsi->rx_rings[i]);
  1798. }
  1799. /**
  1800. * i40e_configure_tx_ring - Configure a transmit ring context and rest
  1801. * @ring: The Tx ring to configure
  1802. *
  1803. * Configure the Tx descriptor ring in the HMC context.
  1804. **/
  1805. static int i40e_configure_tx_ring(struct i40e_ring *ring)
  1806. {
  1807. struct i40e_vsi *vsi = ring->vsi;
  1808. u16 pf_q = vsi->base_queue + ring->queue_index;
  1809. struct i40e_hw *hw = &vsi->back->hw;
  1810. struct i40e_hmc_obj_txq tx_ctx;
  1811. i40e_status err = 0;
  1812. u32 qtx_ctl = 0;
  1813. /* some ATR related tx ring init */
  1814. if (vsi->back->flags & I40E_FLAG_FDIR_ATR_ENABLED) {
  1815. ring->atr_sample_rate = vsi->back->atr_sample_rate;
  1816. ring->atr_count = 0;
  1817. } else {
  1818. ring->atr_sample_rate = 0;
  1819. }
  1820. /* initialize XPS */
  1821. if (ring->q_vector && ring->netdev &&
  1822. !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
  1823. netif_set_xps_queue(ring->netdev,
  1824. &ring->q_vector->affinity_mask,
  1825. ring->queue_index);
  1826. /* clear the context structure first */
  1827. memset(&tx_ctx, 0, sizeof(tx_ctx));
  1828. tx_ctx.new_context = 1;
  1829. tx_ctx.base = (ring->dma / 128);
  1830. tx_ctx.qlen = ring->count;
  1831. tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FDIR_ENABLED |
  1832. I40E_FLAG_FDIR_ATR_ENABLED));
  1833. /* As part of VSI creation/update, FW allocates certain
  1834. * Tx arbitration queue sets for each TC enabled for
  1835. * the VSI. The FW returns the handles to these queue
  1836. * sets as part of the response buffer to Add VSI,
  1837. * Update VSI, etc. AQ commands. It is expected that
  1838. * these queue set handles be associated with the Tx
  1839. * queues by the driver as part of the TX queue context
  1840. * initialization. This has to be done regardless of
  1841. * DCB as by default everything is mapped to TC0.
  1842. */
  1843. tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
  1844. tx_ctx.rdylist_act = 0;
  1845. /* clear the context in the HMC */
  1846. err = i40e_clear_lan_tx_queue_context(hw, pf_q);
  1847. if (err) {
  1848. dev_info(&vsi->back->pdev->dev,
  1849. "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
  1850. ring->queue_index, pf_q, err);
  1851. return -ENOMEM;
  1852. }
  1853. /* set the context in the HMC */
  1854. err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
  1855. if (err) {
  1856. dev_info(&vsi->back->pdev->dev,
  1857. "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
  1858. ring->queue_index, pf_q, err);
  1859. return -ENOMEM;
  1860. }
  1861. /* Now associate this queue with this PCI function */
  1862. qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
  1863. qtx_ctl |= ((hw->hmc.hmc_fn_id << I40E_QTX_CTL_PF_INDX_SHIFT)
  1864. & I40E_QTX_CTL_PF_INDX_MASK);
  1865. wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
  1866. i40e_flush(hw);
  1867. clear_bit(__I40E_HANG_CHECK_ARMED, &ring->state);
  1868. /* cache tail off for easier writes later */
  1869. ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
  1870. return 0;
  1871. }
  1872. /**
  1873. * i40e_configure_rx_ring - Configure a receive ring context
  1874. * @ring: The Rx ring to configure
  1875. *
  1876. * Configure the Rx descriptor ring in the HMC context.
  1877. **/
  1878. static int i40e_configure_rx_ring(struct i40e_ring *ring)
  1879. {
  1880. struct i40e_vsi *vsi = ring->vsi;
  1881. u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
  1882. u16 pf_q = vsi->base_queue + ring->queue_index;
  1883. struct i40e_hw *hw = &vsi->back->hw;
  1884. struct i40e_hmc_obj_rxq rx_ctx;
  1885. i40e_status err = 0;
  1886. ring->state = 0;
  1887. /* clear the context structure first */
  1888. memset(&rx_ctx, 0, sizeof(rx_ctx));
  1889. ring->rx_buf_len = vsi->rx_buf_len;
  1890. ring->rx_hdr_len = vsi->rx_hdr_len;
  1891. rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
  1892. rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
  1893. rx_ctx.base = (ring->dma / 128);
  1894. rx_ctx.qlen = ring->count;
  1895. if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
  1896. set_ring_16byte_desc_enabled(ring);
  1897. rx_ctx.dsize = 0;
  1898. } else {
  1899. rx_ctx.dsize = 1;
  1900. }
  1901. rx_ctx.dtype = vsi->dtype;
  1902. if (vsi->dtype) {
  1903. set_ring_ps_enabled(ring);
  1904. rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
  1905. I40E_RX_SPLIT_IP |
  1906. I40E_RX_SPLIT_TCP_UDP |
  1907. I40E_RX_SPLIT_SCTP;
  1908. } else {
  1909. rx_ctx.hsplit_0 = 0;
  1910. }
  1911. rx_ctx.rxmax = min_t(u16, vsi->max_frame,
  1912. (chain_len * ring->rx_buf_len));
  1913. rx_ctx.tphrdesc_ena = 1;
  1914. rx_ctx.tphwdesc_ena = 1;
  1915. rx_ctx.tphdata_ena = 1;
  1916. rx_ctx.tphhead_ena = 1;
  1917. rx_ctx.lrxqthresh = 2;
  1918. rx_ctx.crcstrip = 1;
  1919. rx_ctx.l2tsel = 1;
  1920. rx_ctx.showiv = 1;
  1921. /* clear the context in the HMC */
  1922. err = i40e_clear_lan_rx_queue_context(hw, pf_q);
  1923. if (err) {
  1924. dev_info(&vsi->back->pdev->dev,
  1925. "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
  1926. ring->queue_index, pf_q, err);
  1927. return -ENOMEM;
  1928. }
  1929. /* set the context in the HMC */
  1930. err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
  1931. if (err) {
  1932. dev_info(&vsi->back->pdev->dev,
  1933. "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
  1934. ring->queue_index, pf_q, err);
  1935. return -ENOMEM;
  1936. }
  1937. /* cache tail for quicker writes, and clear the reg before use */
  1938. ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
  1939. writel(0, ring->tail);
  1940. i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
  1941. return 0;
  1942. }
  1943. /**
  1944. * i40e_vsi_configure_tx - Configure the VSI for Tx
  1945. * @vsi: VSI structure describing this set of rings and resources
  1946. *
  1947. * Configure the Tx VSI for operation.
  1948. **/
  1949. static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
  1950. {
  1951. int err = 0;
  1952. u16 i;
  1953. for (i = 0; (i < vsi->num_queue_pairs) && (!err); i++)
  1954. err = i40e_configure_tx_ring(&vsi->tx_rings[i]);
  1955. return err;
  1956. }
  1957. /**
  1958. * i40e_vsi_configure_rx - Configure the VSI for Rx
  1959. * @vsi: the VSI being configured
  1960. *
  1961. * Configure the Rx VSI for operation.
  1962. **/
  1963. static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
  1964. {
  1965. int err = 0;
  1966. u16 i;
  1967. if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
  1968. vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
  1969. + ETH_FCS_LEN + VLAN_HLEN;
  1970. else
  1971. vsi->max_frame = I40E_RXBUFFER_2048;
  1972. /* figure out correct receive buffer length */
  1973. switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
  1974. I40E_FLAG_RX_PS_ENABLED)) {
  1975. case I40E_FLAG_RX_1BUF_ENABLED:
  1976. vsi->rx_hdr_len = 0;
  1977. vsi->rx_buf_len = vsi->max_frame;
  1978. vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
  1979. break;
  1980. case I40E_FLAG_RX_PS_ENABLED:
  1981. vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
  1982. vsi->rx_buf_len = I40E_RXBUFFER_2048;
  1983. vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
  1984. break;
  1985. default:
  1986. vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
  1987. vsi->rx_buf_len = I40E_RXBUFFER_2048;
  1988. vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
  1989. break;
  1990. }
  1991. /* round up for the chip's needs */
  1992. vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
  1993. (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
  1994. vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
  1995. (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
  1996. /* set up individual rings */
  1997. for (i = 0; i < vsi->num_queue_pairs && !err; i++)
  1998. err = i40e_configure_rx_ring(&vsi->rx_rings[i]);
  1999. return err;
  2000. }
  2001. /**
  2002. * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
  2003. * @vsi: ptr to the VSI
  2004. **/
  2005. static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
  2006. {
  2007. u16 qoffset, qcount;
  2008. int i, n;
  2009. if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED))
  2010. return;
  2011. for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
  2012. if (!(vsi->tc_config.enabled_tc & (1 << n)))
  2013. continue;
  2014. qoffset = vsi->tc_config.tc_info[n].qoffset;
  2015. qcount = vsi->tc_config.tc_info[n].qcount;
  2016. for (i = qoffset; i < (qoffset + qcount); i++) {
  2017. struct i40e_ring *rx_ring = &vsi->rx_rings[i];
  2018. struct i40e_ring *tx_ring = &vsi->tx_rings[i];
  2019. rx_ring->dcb_tc = n;
  2020. tx_ring->dcb_tc = n;
  2021. }
  2022. }
  2023. }
  2024. /**
  2025. * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
  2026. * @vsi: ptr to the VSI
  2027. **/
  2028. static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
  2029. {
  2030. if (vsi->netdev)
  2031. i40e_set_rx_mode(vsi->netdev);
  2032. }
  2033. /**
  2034. * i40e_vsi_configure - Set up the VSI for action
  2035. * @vsi: the VSI being configured
  2036. **/
  2037. static int i40e_vsi_configure(struct i40e_vsi *vsi)
  2038. {
  2039. int err;
  2040. i40e_set_vsi_rx_mode(vsi);
  2041. i40e_restore_vlan(vsi);
  2042. i40e_vsi_config_dcb_rings(vsi);
  2043. err = i40e_vsi_configure_tx(vsi);
  2044. if (!err)
  2045. err = i40e_vsi_configure_rx(vsi);
  2046. return err;
  2047. }
  2048. /**
  2049. * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
  2050. * @vsi: the VSI being configured
  2051. **/
  2052. static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
  2053. {
  2054. struct i40e_pf *pf = vsi->back;
  2055. struct i40e_q_vector *q_vector;
  2056. struct i40e_hw *hw = &pf->hw;
  2057. u16 vector;
  2058. int i, q;
  2059. u32 val;
  2060. u32 qp;
  2061. /* The interrupt indexing is offset by 1 in the PFINT_ITRn
  2062. * and PFINT_LNKLSTn registers, e.g.:
  2063. * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
  2064. */
  2065. qp = vsi->base_queue;
  2066. vector = vsi->base_vector;
  2067. q_vector = vsi->q_vectors;
  2068. for (i = 0; i < vsi->num_q_vectors; i++, q_vector++, vector++) {
  2069. q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
  2070. q_vector->rx.latency_range = I40E_LOW_LATENCY;
  2071. wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
  2072. q_vector->rx.itr);
  2073. q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
  2074. q_vector->tx.latency_range = I40E_LOW_LATENCY;
  2075. wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
  2076. q_vector->tx.itr);
  2077. /* Linked list for the queuepairs assigned to this vector */
  2078. wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
  2079. for (q = 0; q < q_vector->num_ringpairs; q++) {
  2080. val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
  2081. (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
  2082. (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
  2083. (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
  2084. (I40E_QUEUE_TYPE_TX
  2085. << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
  2086. wr32(hw, I40E_QINT_RQCTL(qp), val);
  2087. val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
  2088. (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
  2089. (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
  2090. ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
  2091. (I40E_QUEUE_TYPE_RX
  2092. << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
  2093. /* Terminate the linked list */
  2094. if (q == (q_vector->num_ringpairs - 1))
  2095. val |= (I40E_QUEUE_END_OF_LIST
  2096. << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
  2097. wr32(hw, I40E_QINT_TQCTL(qp), val);
  2098. qp++;
  2099. }
  2100. }
  2101. i40e_flush(hw);
  2102. }
  2103. /**
  2104. * i40e_enable_misc_int_causes - enable the non-queue interrupts
  2105. * @hw: ptr to the hardware info
  2106. **/
  2107. static void i40e_enable_misc_int_causes(struct i40e_hw *hw)
  2108. {
  2109. u32 val;
  2110. /* clear things first */
  2111. wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
  2112. rd32(hw, I40E_PFINT_ICR0); /* read to clear */
  2113. val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
  2114. I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
  2115. I40E_PFINT_ICR0_ENA_GRST_MASK |
  2116. I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
  2117. I40E_PFINT_ICR0_ENA_GPIO_MASK |
  2118. I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK |
  2119. I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
  2120. I40E_PFINT_ICR0_ENA_VFLR_MASK |
  2121. I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
  2122. wr32(hw, I40E_PFINT_ICR0_ENA, val);
  2123. /* SW_ITR_IDX = 0, but don't change INTENA */
  2124. wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK |
  2125. I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK);
  2126. /* OTHER_ITR_IDX = 0 */
  2127. wr32(hw, I40E_PFINT_STAT_CTL0, 0);
  2128. }
  2129. /**
  2130. * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
  2131. * @vsi: the VSI being configured
  2132. **/
  2133. static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
  2134. {
  2135. struct i40e_q_vector *q_vector = vsi->q_vectors;
  2136. struct i40e_pf *pf = vsi->back;
  2137. struct i40e_hw *hw = &pf->hw;
  2138. u32 val;
  2139. /* set the ITR configuration */
  2140. q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
  2141. q_vector->rx.latency_range = I40E_LOW_LATENCY;
  2142. wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
  2143. q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
  2144. q_vector->tx.latency_range = I40E_LOW_LATENCY;
  2145. wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
  2146. i40e_enable_misc_int_causes(hw);
  2147. /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
  2148. wr32(hw, I40E_PFINT_LNKLST0, 0);
  2149. /* Associate the queue pair to the vector and enable the q int */
  2150. val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
  2151. (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
  2152. (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
  2153. wr32(hw, I40E_QINT_RQCTL(0), val);
  2154. val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
  2155. (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
  2156. (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
  2157. wr32(hw, I40E_QINT_TQCTL(0), val);
  2158. i40e_flush(hw);
  2159. }
  2160. /**
  2161. * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
  2162. * @pf: board private structure
  2163. **/
  2164. static void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
  2165. {
  2166. struct i40e_hw *hw = &pf->hw;
  2167. u32 val;
  2168. val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
  2169. I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
  2170. (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
  2171. wr32(hw, I40E_PFINT_DYN_CTL0, val);
  2172. i40e_flush(hw);
  2173. }
  2174. /**
  2175. * i40e_irq_dynamic_enable - Enable default interrupt generation settings
  2176. * @vsi: pointer to a vsi
  2177. * @vector: enable a particular Hw Interrupt vector
  2178. **/
  2179. void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
  2180. {
  2181. struct i40e_pf *pf = vsi->back;
  2182. struct i40e_hw *hw = &pf->hw;
  2183. u32 val;
  2184. val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
  2185. I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
  2186. (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
  2187. wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
  2188. i40e_flush(hw);
  2189. }
  2190. /**
  2191. * i40e_msix_clean_rings - MSIX mode Interrupt Handler
  2192. * @irq: interrupt number
  2193. * @data: pointer to a q_vector
  2194. **/
  2195. static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
  2196. {
  2197. struct i40e_q_vector *q_vector = data;
  2198. if (!q_vector->tx.ring[0] && !q_vector->rx.ring[0])
  2199. return IRQ_HANDLED;
  2200. napi_schedule(&q_vector->napi);
  2201. return IRQ_HANDLED;
  2202. }
  2203. /**
  2204. * i40e_fdir_clean_rings - Interrupt Handler for FDIR rings
  2205. * @irq: interrupt number
  2206. * @data: pointer to a q_vector
  2207. **/
  2208. static irqreturn_t i40e_fdir_clean_rings(int irq, void *data)
  2209. {
  2210. struct i40e_q_vector *q_vector = data;
  2211. if (!q_vector->tx.ring[0] && !q_vector->rx.ring[0])
  2212. return IRQ_HANDLED;
  2213. pr_info("fdir ring cleaning needed\n");
  2214. return IRQ_HANDLED;
  2215. }
  2216. /**
  2217. * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
  2218. * @vsi: the VSI being configured
  2219. * @basename: name for the vector
  2220. *
  2221. * Allocates MSI-X vectors and requests interrupts from the kernel.
  2222. **/
  2223. static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
  2224. {
  2225. int q_vectors = vsi->num_q_vectors;
  2226. struct i40e_pf *pf = vsi->back;
  2227. int base = vsi->base_vector;
  2228. int rx_int_idx = 0;
  2229. int tx_int_idx = 0;
  2230. int vector, err;
  2231. for (vector = 0; vector < q_vectors; vector++) {
  2232. struct i40e_q_vector *q_vector = &(vsi->q_vectors[vector]);
  2233. if (q_vector->tx.ring[0] && q_vector->rx.ring[0]) {
  2234. snprintf(q_vector->name, sizeof(q_vector->name) - 1,
  2235. "%s-%s-%d", basename, "TxRx", rx_int_idx++);
  2236. tx_int_idx++;
  2237. } else if (q_vector->rx.ring[0]) {
  2238. snprintf(q_vector->name, sizeof(q_vector->name) - 1,
  2239. "%s-%s-%d", basename, "rx", rx_int_idx++);
  2240. } else if (q_vector->tx.ring[0]) {
  2241. snprintf(q_vector->name, sizeof(q_vector->name) - 1,
  2242. "%s-%s-%d", basename, "tx", tx_int_idx++);
  2243. } else {
  2244. /* skip this unused q_vector */
  2245. continue;
  2246. }
  2247. err = request_irq(pf->msix_entries[base + vector].vector,
  2248. vsi->irq_handler,
  2249. 0,
  2250. q_vector->name,
  2251. q_vector);
  2252. if (err) {
  2253. dev_info(&pf->pdev->dev,
  2254. "%s: request_irq failed, error: %d\n",
  2255. __func__, err);
  2256. goto free_queue_irqs;
  2257. }
  2258. /* assign the mask for this irq */
  2259. irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
  2260. &q_vector->affinity_mask);
  2261. }
  2262. return 0;
  2263. free_queue_irqs:
  2264. while (vector) {
  2265. vector--;
  2266. irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
  2267. NULL);
  2268. free_irq(pf->msix_entries[base + vector].vector,
  2269. &(vsi->q_vectors[vector]));
  2270. }
  2271. return err;
  2272. }
  2273. /**
  2274. * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
  2275. * @vsi: the VSI being un-configured
  2276. **/
  2277. static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
  2278. {
  2279. struct i40e_pf *pf = vsi->back;
  2280. struct i40e_hw *hw = &pf->hw;
  2281. int base = vsi->base_vector;
  2282. int i;
  2283. for (i = 0; i < vsi->num_queue_pairs; i++) {
  2284. wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i].reg_idx), 0);
  2285. wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i].reg_idx), 0);
  2286. }
  2287. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  2288. for (i = vsi->base_vector;
  2289. i < (vsi->num_q_vectors + vsi->base_vector); i++)
  2290. wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
  2291. i40e_flush(hw);
  2292. for (i = 0; i < vsi->num_q_vectors; i++)
  2293. synchronize_irq(pf->msix_entries[i + base].vector);
  2294. } else {
  2295. /* Legacy and MSI mode - this stops all interrupt handling */
  2296. wr32(hw, I40E_PFINT_ICR0_ENA, 0);
  2297. wr32(hw, I40E_PFINT_DYN_CTL0, 0);
  2298. i40e_flush(hw);
  2299. synchronize_irq(pf->pdev->irq);
  2300. }
  2301. }
  2302. /**
  2303. * i40e_vsi_enable_irq - Enable IRQ for the given VSI
  2304. * @vsi: the VSI being configured
  2305. **/
  2306. static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
  2307. {
  2308. struct i40e_pf *pf = vsi->back;
  2309. int i;
  2310. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  2311. for (i = vsi->base_vector;
  2312. i < (vsi->num_q_vectors + vsi->base_vector); i++)
  2313. i40e_irq_dynamic_enable(vsi, i);
  2314. } else {
  2315. i40e_irq_dynamic_enable_icr0(pf);
  2316. }
  2317. return 0;
  2318. }
  2319. /**
  2320. * i40e_stop_misc_vector - Stop the vector that handles non-queue events
  2321. * @pf: board private structure
  2322. **/
  2323. static void i40e_stop_misc_vector(struct i40e_pf *pf)
  2324. {
  2325. /* Disable ICR 0 */
  2326. wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
  2327. i40e_flush(&pf->hw);
  2328. }
  2329. /**
  2330. * i40e_intr - MSI/Legacy and non-queue interrupt handler
  2331. * @irq: interrupt number
  2332. * @data: pointer to a q_vector
  2333. *
  2334. * This is the handler used for all MSI/Legacy interrupts, and deals
  2335. * with both queue and non-queue interrupts. This is also used in
  2336. * MSIX mode to handle the non-queue interrupts.
  2337. **/
  2338. static irqreturn_t i40e_intr(int irq, void *data)
  2339. {
  2340. struct i40e_pf *pf = (struct i40e_pf *)data;
  2341. struct i40e_hw *hw = &pf->hw;
  2342. u32 icr0, icr0_remaining;
  2343. u32 val, ena_mask;
  2344. icr0 = rd32(hw, I40E_PFINT_ICR0);
  2345. /* if sharing a legacy IRQ, we might get called w/o an intr pending */
  2346. if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
  2347. return IRQ_NONE;
  2348. val = rd32(hw, I40E_PFINT_DYN_CTL0);
  2349. val = val | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK;
  2350. wr32(hw, I40E_PFINT_DYN_CTL0, val);
  2351. ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
  2352. /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
  2353. if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
  2354. /* temporarily disable queue cause for NAPI processing */
  2355. u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
  2356. qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
  2357. wr32(hw, I40E_QINT_RQCTL(0), qval);
  2358. qval = rd32(hw, I40E_QINT_TQCTL(0));
  2359. qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
  2360. wr32(hw, I40E_QINT_TQCTL(0), qval);
  2361. i40e_flush(hw);
  2362. if (!test_bit(__I40E_DOWN, &pf->state))
  2363. napi_schedule(&pf->vsi[pf->lan_vsi]->q_vectors[0].napi);
  2364. }
  2365. if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
  2366. ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
  2367. set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
  2368. }
  2369. if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
  2370. ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
  2371. set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
  2372. }
  2373. if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
  2374. ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
  2375. set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
  2376. }
  2377. if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
  2378. if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
  2379. set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
  2380. ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
  2381. val = rd32(hw, I40E_GLGEN_RSTAT);
  2382. val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
  2383. >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
  2384. if (val & I40E_RESET_CORER)
  2385. pf->corer_count++;
  2386. else if (val & I40E_RESET_GLOBR)
  2387. pf->globr_count++;
  2388. else if (val & I40E_RESET_EMPR)
  2389. pf->empr_count++;
  2390. }
  2391. /* If a critical error is pending we have no choice but to reset the
  2392. * device.
  2393. * Report and mask out any remaining unexpected interrupts.
  2394. */
  2395. icr0_remaining = icr0 & ena_mask;
  2396. if (icr0_remaining) {
  2397. dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
  2398. icr0_remaining);
  2399. if ((icr0_remaining & I40E_PFINT_ICR0_HMC_ERR_MASK) ||
  2400. (icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
  2401. (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
  2402. (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK) ||
  2403. (icr0_remaining & I40E_PFINT_ICR0_MAL_DETECT_MASK)) {
  2404. if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
  2405. dev_info(&pf->pdev->dev, "HMC error interrupt\n");
  2406. } else {
  2407. dev_info(&pf->pdev->dev, "device will be reset\n");
  2408. set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
  2409. i40e_service_event_schedule(pf);
  2410. }
  2411. }
  2412. ena_mask &= ~icr0_remaining;
  2413. }
  2414. /* re-enable interrupt causes */
  2415. wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
  2416. i40e_flush(hw);
  2417. if (!test_bit(__I40E_DOWN, &pf->state)) {
  2418. i40e_service_event_schedule(pf);
  2419. i40e_irq_dynamic_enable_icr0(pf);
  2420. }
  2421. return IRQ_HANDLED;
  2422. }
  2423. /**
  2424. * i40e_map_vector_to_rxq - Assigns the Rx queue to the vector
  2425. * @vsi: the VSI being configured
  2426. * @v_idx: vector index
  2427. * @r_idx: rx queue index
  2428. **/
  2429. static void map_vector_to_rxq(struct i40e_vsi *vsi, int v_idx, int r_idx)
  2430. {
  2431. struct i40e_q_vector *q_vector = &(vsi->q_vectors[v_idx]);
  2432. struct i40e_ring *rx_ring = &(vsi->rx_rings[r_idx]);
  2433. rx_ring->q_vector = q_vector;
  2434. q_vector->rx.ring[q_vector->rx.count] = rx_ring;
  2435. q_vector->rx.count++;
  2436. q_vector->rx.latency_range = I40E_LOW_LATENCY;
  2437. q_vector->vsi = vsi;
  2438. }
  2439. /**
  2440. * i40e_map_vector_to_txq - Assigns the Tx queue to the vector
  2441. * @vsi: the VSI being configured
  2442. * @v_idx: vector index
  2443. * @t_idx: tx queue index
  2444. **/
  2445. static void map_vector_to_txq(struct i40e_vsi *vsi, int v_idx, int t_idx)
  2446. {
  2447. struct i40e_q_vector *q_vector = &(vsi->q_vectors[v_idx]);
  2448. struct i40e_ring *tx_ring = &(vsi->tx_rings[t_idx]);
  2449. tx_ring->q_vector = q_vector;
  2450. q_vector->tx.ring[q_vector->tx.count] = tx_ring;
  2451. q_vector->tx.count++;
  2452. q_vector->tx.latency_range = I40E_LOW_LATENCY;
  2453. q_vector->num_ringpairs++;
  2454. q_vector->vsi = vsi;
  2455. }
  2456. /**
  2457. * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
  2458. * @vsi: the VSI being configured
  2459. *
  2460. * This function maps descriptor rings to the queue-specific vectors
  2461. * we were allotted through the MSI-X enabling code. Ideally, we'd have
  2462. * one vector per queue pair, but on a constrained vector budget, we
  2463. * group the queue pairs as "efficiently" as possible.
  2464. **/
  2465. static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
  2466. {
  2467. int qp_remaining = vsi->num_queue_pairs;
  2468. int q_vectors = vsi->num_q_vectors;
  2469. int qp_per_vector;
  2470. int v_start = 0;
  2471. int qp_idx = 0;
  2472. /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
  2473. * group them so there are multiple queues per vector.
  2474. */
  2475. for (; v_start < q_vectors && qp_remaining; v_start++) {
  2476. qp_per_vector = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
  2477. for (; qp_per_vector;
  2478. qp_per_vector--, qp_idx++, qp_remaining--) {
  2479. map_vector_to_rxq(vsi, v_start, qp_idx);
  2480. map_vector_to_txq(vsi, v_start, qp_idx);
  2481. }
  2482. }
  2483. }
  2484. /**
  2485. * i40e_vsi_request_irq - Request IRQ from the OS
  2486. * @vsi: the VSI being configured
  2487. * @basename: name for the vector
  2488. **/
  2489. static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
  2490. {
  2491. struct i40e_pf *pf = vsi->back;
  2492. int err;
  2493. if (pf->flags & I40E_FLAG_MSIX_ENABLED)
  2494. err = i40e_vsi_request_irq_msix(vsi, basename);
  2495. else if (pf->flags & I40E_FLAG_MSI_ENABLED)
  2496. err = request_irq(pf->pdev->irq, i40e_intr, 0,
  2497. pf->misc_int_name, pf);
  2498. else
  2499. err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
  2500. pf->misc_int_name, pf);
  2501. if (err)
  2502. dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
  2503. return err;
  2504. }
  2505. #ifdef CONFIG_NET_POLL_CONTROLLER
  2506. /**
  2507. * i40e_netpoll - A Polling 'interrupt'handler
  2508. * @netdev: network interface device structure
  2509. *
  2510. * This is used by netconsole to send skbs without having to re-enable
  2511. * interrupts. It's not called while the normal interrupt routine is executing.
  2512. **/
  2513. static void i40e_netpoll(struct net_device *netdev)
  2514. {
  2515. struct i40e_netdev_priv *np = netdev_priv(netdev);
  2516. struct i40e_vsi *vsi = np->vsi;
  2517. struct i40e_pf *pf = vsi->back;
  2518. int i;
  2519. /* if interface is down do nothing */
  2520. if (test_bit(__I40E_DOWN, &vsi->state))
  2521. return;
  2522. pf->flags |= I40E_FLAG_IN_NETPOLL;
  2523. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  2524. for (i = 0; i < vsi->num_q_vectors; i++)
  2525. i40e_msix_clean_rings(0, &vsi->q_vectors[i]);
  2526. } else {
  2527. i40e_intr(pf->pdev->irq, netdev);
  2528. }
  2529. pf->flags &= ~I40E_FLAG_IN_NETPOLL;
  2530. }
  2531. #endif
  2532. /**
  2533. * i40e_vsi_control_tx - Start or stop a VSI's rings
  2534. * @vsi: the VSI being configured
  2535. * @enable: start or stop the rings
  2536. **/
  2537. static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
  2538. {
  2539. struct i40e_pf *pf = vsi->back;
  2540. struct i40e_hw *hw = &pf->hw;
  2541. int i, j, pf_q;
  2542. u32 tx_reg;
  2543. pf_q = vsi->base_queue;
  2544. for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
  2545. j = 1000;
  2546. do {
  2547. usleep_range(1000, 2000);
  2548. tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
  2549. } while (j-- && ((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT)
  2550. ^ (tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)) & 1);
  2551. if (enable) {
  2552. /* is STAT set ? */
  2553. if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) {
  2554. dev_info(&pf->pdev->dev,
  2555. "Tx %d already enabled\n", i);
  2556. continue;
  2557. }
  2558. } else {
  2559. /* is !STAT set ? */
  2560. if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) {
  2561. dev_info(&pf->pdev->dev,
  2562. "Tx %d already disabled\n", i);
  2563. continue;
  2564. }
  2565. }
  2566. /* turn on/off the queue */
  2567. if (enable)
  2568. tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK |
  2569. I40E_QTX_ENA_QENA_STAT_MASK;
  2570. else
  2571. tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
  2572. wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
  2573. /* wait for the change to finish */
  2574. for (j = 0; j < 10; j++) {
  2575. tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
  2576. if (enable) {
  2577. if ((tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
  2578. break;
  2579. } else {
  2580. if (!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
  2581. break;
  2582. }
  2583. udelay(10);
  2584. }
  2585. if (j >= 10) {
  2586. dev_info(&pf->pdev->dev, "Tx ring %d %sable timeout\n",
  2587. pf_q, (enable ? "en" : "dis"));
  2588. return -ETIMEDOUT;
  2589. }
  2590. }
  2591. return 0;
  2592. }
  2593. /**
  2594. * i40e_vsi_control_rx - Start or stop a VSI's rings
  2595. * @vsi: the VSI being configured
  2596. * @enable: start or stop the rings
  2597. **/
  2598. static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
  2599. {
  2600. struct i40e_pf *pf = vsi->back;
  2601. struct i40e_hw *hw = &pf->hw;
  2602. int i, j, pf_q;
  2603. u32 rx_reg;
  2604. pf_q = vsi->base_queue;
  2605. for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
  2606. j = 1000;
  2607. do {
  2608. usleep_range(1000, 2000);
  2609. rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
  2610. } while (j-- && ((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT)
  2611. ^ (rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT)) & 1);
  2612. if (enable) {
  2613. /* is STAT set ? */
  2614. if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
  2615. continue;
  2616. } else {
  2617. /* is !STAT set ? */
  2618. if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
  2619. continue;
  2620. }
  2621. /* turn on/off the queue */
  2622. if (enable)
  2623. rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK |
  2624. I40E_QRX_ENA_QENA_STAT_MASK;
  2625. else
  2626. rx_reg &= ~(I40E_QRX_ENA_QENA_REQ_MASK |
  2627. I40E_QRX_ENA_QENA_STAT_MASK);
  2628. wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
  2629. /* wait for the change to finish */
  2630. for (j = 0; j < 10; j++) {
  2631. rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
  2632. if (enable) {
  2633. if ((rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
  2634. break;
  2635. } else {
  2636. if (!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
  2637. break;
  2638. }
  2639. udelay(10);
  2640. }
  2641. if (j >= 10) {
  2642. dev_info(&pf->pdev->dev, "Rx ring %d %sable timeout\n",
  2643. pf_q, (enable ? "en" : "dis"));
  2644. return -ETIMEDOUT;
  2645. }
  2646. }
  2647. return 0;
  2648. }
  2649. /**
  2650. * i40e_vsi_control_rings - Start or stop a VSI's rings
  2651. * @vsi: the VSI being configured
  2652. * @enable: start or stop the rings
  2653. **/
  2654. static int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
  2655. {
  2656. int ret;
  2657. /* do rx first for enable and last for disable */
  2658. if (request) {
  2659. ret = i40e_vsi_control_rx(vsi, request);
  2660. if (ret)
  2661. return ret;
  2662. ret = i40e_vsi_control_tx(vsi, request);
  2663. } else {
  2664. ret = i40e_vsi_control_tx(vsi, request);
  2665. if (ret)
  2666. return ret;
  2667. ret = i40e_vsi_control_rx(vsi, request);
  2668. }
  2669. return ret;
  2670. }
  2671. /**
  2672. * i40e_vsi_free_irq - Free the irq association with the OS
  2673. * @vsi: the VSI being configured
  2674. **/
  2675. static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
  2676. {
  2677. struct i40e_pf *pf = vsi->back;
  2678. struct i40e_hw *hw = &pf->hw;
  2679. int base = vsi->base_vector;
  2680. u32 val, qp;
  2681. int i;
  2682. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  2683. if (!vsi->q_vectors)
  2684. return;
  2685. for (i = 0; i < vsi->num_q_vectors; i++) {
  2686. u16 vector = i + base;
  2687. /* free only the irqs that were actually requested */
  2688. if (vsi->q_vectors[i].num_ringpairs == 0)
  2689. continue;
  2690. /* clear the affinity_mask in the IRQ descriptor */
  2691. irq_set_affinity_hint(pf->msix_entries[vector].vector,
  2692. NULL);
  2693. free_irq(pf->msix_entries[vector].vector,
  2694. &vsi->q_vectors[i]);
  2695. /* Tear down the interrupt queue link list
  2696. *
  2697. * We know that they come in pairs and always
  2698. * the Rx first, then the Tx. To clear the
  2699. * link list, stick the EOL value into the
  2700. * next_q field of the registers.
  2701. */
  2702. val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
  2703. qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
  2704. >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
  2705. val |= I40E_QUEUE_END_OF_LIST
  2706. << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
  2707. wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
  2708. while (qp != I40E_QUEUE_END_OF_LIST) {
  2709. u32 next;
  2710. val = rd32(hw, I40E_QINT_RQCTL(qp));
  2711. val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
  2712. I40E_QINT_RQCTL_MSIX0_INDX_MASK |
  2713. I40E_QINT_RQCTL_CAUSE_ENA_MASK |
  2714. I40E_QINT_RQCTL_INTEVENT_MASK);
  2715. val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
  2716. I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
  2717. wr32(hw, I40E_QINT_RQCTL(qp), val);
  2718. val = rd32(hw, I40E_QINT_TQCTL(qp));
  2719. next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
  2720. >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
  2721. val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
  2722. I40E_QINT_TQCTL_MSIX0_INDX_MASK |
  2723. I40E_QINT_TQCTL_CAUSE_ENA_MASK |
  2724. I40E_QINT_TQCTL_INTEVENT_MASK);
  2725. val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
  2726. I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
  2727. wr32(hw, I40E_QINT_TQCTL(qp), val);
  2728. qp = next;
  2729. }
  2730. }
  2731. } else {
  2732. free_irq(pf->pdev->irq, pf);
  2733. val = rd32(hw, I40E_PFINT_LNKLST0);
  2734. qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
  2735. >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
  2736. val |= I40E_QUEUE_END_OF_LIST
  2737. << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
  2738. wr32(hw, I40E_PFINT_LNKLST0, val);
  2739. val = rd32(hw, I40E_QINT_RQCTL(qp));
  2740. val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
  2741. I40E_QINT_RQCTL_MSIX0_INDX_MASK |
  2742. I40E_QINT_RQCTL_CAUSE_ENA_MASK |
  2743. I40E_QINT_RQCTL_INTEVENT_MASK);
  2744. val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
  2745. I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
  2746. wr32(hw, I40E_QINT_RQCTL(qp), val);
  2747. val = rd32(hw, I40E_QINT_TQCTL(qp));
  2748. val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
  2749. I40E_QINT_TQCTL_MSIX0_INDX_MASK |
  2750. I40E_QINT_TQCTL_CAUSE_ENA_MASK |
  2751. I40E_QINT_TQCTL_INTEVENT_MASK);
  2752. val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
  2753. I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
  2754. wr32(hw, I40E_QINT_TQCTL(qp), val);
  2755. }
  2756. }
  2757. /**
  2758. * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
  2759. * @vsi: the VSI being un-configured
  2760. *
  2761. * This frees the memory allocated to the q_vectors and
  2762. * deletes references to the NAPI struct.
  2763. **/
  2764. static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
  2765. {
  2766. int v_idx;
  2767. for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) {
  2768. struct i40e_q_vector *q_vector = &vsi->q_vectors[v_idx];
  2769. int r_idx;
  2770. if (!q_vector)
  2771. continue;
  2772. /* disassociate q_vector from rings */
  2773. for (r_idx = 0; r_idx < q_vector->tx.count; r_idx++)
  2774. q_vector->tx.ring[r_idx]->q_vector = NULL;
  2775. for (r_idx = 0; r_idx < q_vector->rx.count; r_idx++)
  2776. q_vector->rx.ring[r_idx]->q_vector = NULL;
  2777. /* only VSI w/ an associated netdev is set up w/ NAPI */
  2778. if (vsi->netdev)
  2779. netif_napi_del(&q_vector->napi);
  2780. }
  2781. kfree(vsi->q_vectors);
  2782. }
  2783. /**
  2784. * i40e_reset_interrupt_capability - Disable interrupt setup in OS
  2785. * @pf: board private structure
  2786. **/
  2787. static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
  2788. {
  2789. /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
  2790. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  2791. pci_disable_msix(pf->pdev);
  2792. kfree(pf->msix_entries);
  2793. pf->msix_entries = NULL;
  2794. } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
  2795. pci_disable_msi(pf->pdev);
  2796. }
  2797. pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
  2798. }
  2799. /**
  2800. * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
  2801. * @pf: board private structure
  2802. *
  2803. * We go through and clear interrupt specific resources and reset the structure
  2804. * to pre-load conditions
  2805. **/
  2806. static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
  2807. {
  2808. int i;
  2809. i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
  2810. for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
  2811. if (pf->vsi[i])
  2812. i40e_vsi_free_q_vectors(pf->vsi[i]);
  2813. i40e_reset_interrupt_capability(pf);
  2814. }
  2815. /**
  2816. * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
  2817. * @vsi: the VSI being configured
  2818. **/
  2819. static void i40e_napi_enable_all(struct i40e_vsi *vsi)
  2820. {
  2821. int q_idx;
  2822. if (!vsi->netdev)
  2823. return;
  2824. for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
  2825. napi_enable(&vsi->q_vectors[q_idx].napi);
  2826. }
  2827. /**
  2828. * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
  2829. * @vsi: the VSI being configured
  2830. **/
  2831. static void i40e_napi_disable_all(struct i40e_vsi *vsi)
  2832. {
  2833. int q_idx;
  2834. if (!vsi->netdev)
  2835. return;
  2836. for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
  2837. napi_disable(&vsi->q_vectors[q_idx].napi);
  2838. }
  2839. /**
  2840. * i40e_quiesce_vsi - Pause a given VSI
  2841. * @vsi: the VSI being paused
  2842. **/
  2843. static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
  2844. {
  2845. if (test_bit(__I40E_DOWN, &vsi->state))
  2846. return;
  2847. set_bit(__I40E_NEEDS_RESTART, &vsi->state);
  2848. if (vsi->netdev && netif_running(vsi->netdev)) {
  2849. vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
  2850. } else {
  2851. set_bit(__I40E_DOWN, &vsi->state);
  2852. i40e_down(vsi);
  2853. }
  2854. }
  2855. /**
  2856. * i40e_unquiesce_vsi - Resume a given VSI
  2857. * @vsi: the VSI being resumed
  2858. **/
  2859. static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
  2860. {
  2861. if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
  2862. return;
  2863. clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
  2864. if (vsi->netdev && netif_running(vsi->netdev))
  2865. vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
  2866. else
  2867. i40e_up(vsi); /* this clears the DOWN bit */
  2868. }
  2869. /**
  2870. * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
  2871. * @pf: the PF
  2872. **/
  2873. static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
  2874. {
  2875. int v;
  2876. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  2877. if (pf->vsi[v])
  2878. i40e_quiesce_vsi(pf->vsi[v]);
  2879. }
  2880. }
  2881. /**
  2882. * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
  2883. * @pf: the PF
  2884. **/
  2885. static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
  2886. {
  2887. int v;
  2888. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  2889. if (pf->vsi[v])
  2890. i40e_unquiesce_vsi(pf->vsi[v]);
  2891. }
  2892. }
  2893. /**
  2894. * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
  2895. * @dcbcfg: the corresponding DCBx configuration structure
  2896. *
  2897. * Return the number of TCs from given DCBx configuration
  2898. **/
  2899. static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
  2900. {
  2901. int num_tc = 0, i;
  2902. /* Scan the ETS Config Priority Table to find
  2903. * traffic class enabled for a given priority
  2904. * and use the traffic class index to get the
  2905. * number of traffic classes enabled
  2906. */
  2907. for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
  2908. if (dcbcfg->etscfg.prioritytable[i] > num_tc)
  2909. num_tc = dcbcfg->etscfg.prioritytable[i];
  2910. }
  2911. /* Traffic class index starts from zero so
  2912. * increment to return the actual count
  2913. */
  2914. num_tc++;
  2915. return num_tc;
  2916. }
  2917. /**
  2918. * i40e_dcb_get_enabled_tc - Get enabled traffic classes
  2919. * @dcbcfg: the corresponding DCBx configuration structure
  2920. *
  2921. * Query the current DCB configuration and return the number of
  2922. * traffic classes enabled from the given DCBX config
  2923. **/
  2924. static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
  2925. {
  2926. u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
  2927. u8 enabled_tc = 1;
  2928. u8 i;
  2929. for (i = 0; i < num_tc; i++)
  2930. enabled_tc |= 1 << i;
  2931. return enabled_tc;
  2932. }
  2933. /**
  2934. * i40e_pf_get_num_tc - Get enabled traffic classes for PF
  2935. * @pf: PF being queried
  2936. *
  2937. * Return number of traffic classes enabled for the given PF
  2938. **/
  2939. static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
  2940. {
  2941. struct i40e_hw *hw = &pf->hw;
  2942. u8 i, enabled_tc;
  2943. u8 num_tc = 0;
  2944. struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
  2945. /* If DCB is not enabled then always in single TC */
  2946. if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
  2947. return 1;
  2948. /* MFP mode return count of enabled TCs for this PF */
  2949. if (pf->flags & I40E_FLAG_MFP_ENABLED) {
  2950. enabled_tc = pf->hw.func_caps.enabled_tcmap;
  2951. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  2952. if (enabled_tc & (1 << i))
  2953. num_tc++;
  2954. }
  2955. return num_tc;
  2956. }
  2957. /* SFP mode will be enabled for all TCs on port */
  2958. return i40e_dcb_get_num_tc(dcbcfg);
  2959. }
  2960. /**
  2961. * i40e_pf_get_default_tc - Get bitmap for first enabled TC
  2962. * @pf: PF being queried
  2963. *
  2964. * Return a bitmap for first enabled traffic class for this PF.
  2965. **/
  2966. static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
  2967. {
  2968. u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
  2969. u8 i = 0;
  2970. if (!enabled_tc)
  2971. return 0x1; /* TC0 */
  2972. /* Find the first enabled TC */
  2973. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  2974. if (enabled_tc & (1 << i))
  2975. break;
  2976. }
  2977. return 1 << i;
  2978. }
  2979. /**
  2980. * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
  2981. * @pf: PF being queried
  2982. *
  2983. * Return a bitmap for enabled traffic classes for this PF.
  2984. **/
  2985. static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
  2986. {
  2987. /* If DCB is not enabled for this PF then just return default TC */
  2988. if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
  2989. return i40e_pf_get_default_tc(pf);
  2990. /* MFP mode will have enabled TCs set by FW */
  2991. if (pf->flags & I40E_FLAG_MFP_ENABLED)
  2992. return pf->hw.func_caps.enabled_tcmap;
  2993. /* SFP mode we want PF to be enabled for all TCs */
  2994. return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
  2995. }
  2996. /**
  2997. * i40e_vsi_get_bw_info - Query VSI BW Information
  2998. * @vsi: the VSI being queried
  2999. *
  3000. * Returns 0 on success, negative value on failure
  3001. **/
  3002. static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
  3003. {
  3004. struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
  3005. struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
  3006. struct i40e_pf *pf = vsi->back;
  3007. struct i40e_hw *hw = &pf->hw;
  3008. i40e_status aq_ret;
  3009. u32 tc_bw_max;
  3010. int i;
  3011. /* Get the VSI level BW configuration */
  3012. aq_ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
  3013. if (aq_ret) {
  3014. dev_info(&pf->pdev->dev,
  3015. "couldn't get pf vsi bw config, err %d, aq_err %d\n",
  3016. aq_ret, pf->hw.aq.asq_last_status);
  3017. return -EINVAL;
  3018. }
  3019. /* Get the VSI level BW configuration per TC */
  3020. aq_ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
  3021. NULL);
  3022. if (aq_ret) {
  3023. dev_info(&pf->pdev->dev,
  3024. "couldn't get pf vsi ets bw config, err %d, aq_err %d\n",
  3025. aq_ret, pf->hw.aq.asq_last_status);
  3026. return -EINVAL;
  3027. }
  3028. if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
  3029. dev_info(&pf->pdev->dev,
  3030. "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
  3031. bw_config.tc_valid_bits,
  3032. bw_ets_config.tc_valid_bits);
  3033. /* Still continuing */
  3034. }
  3035. vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
  3036. vsi->bw_max_quanta = bw_config.max_bw;
  3037. tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
  3038. (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
  3039. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  3040. vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
  3041. vsi->bw_ets_limit_credits[i] =
  3042. le16_to_cpu(bw_ets_config.credits[i]);
  3043. /* 3 bits out of 4 for each TC */
  3044. vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
  3045. }
  3046. return 0;
  3047. }
  3048. /**
  3049. * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
  3050. * @vsi: the VSI being configured
  3051. * @enabled_tc: TC bitmap
  3052. * @bw_credits: BW shared credits per TC
  3053. *
  3054. * Returns 0 on success, negative value on failure
  3055. **/
  3056. static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
  3057. u8 *bw_share)
  3058. {
  3059. struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
  3060. i40e_status aq_ret;
  3061. int i;
  3062. bw_data.tc_valid_bits = enabled_tc;
  3063. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
  3064. bw_data.tc_bw_credits[i] = bw_share[i];
  3065. aq_ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
  3066. NULL);
  3067. if (aq_ret) {
  3068. dev_info(&vsi->back->pdev->dev,
  3069. "%s: AQ command Config VSI BW allocation per TC failed = %d\n",
  3070. __func__, vsi->back->hw.aq.asq_last_status);
  3071. return -EINVAL;
  3072. }
  3073. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
  3074. vsi->info.qs_handle[i] = bw_data.qs_handles[i];
  3075. return 0;
  3076. }
  3077. /**
  3078. * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
  3079. * @vsi: the VSI being configured
  3080. * @enabled_tc: TC map to be enabled
  3081. *
  3082. **/
  3083. static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
  3084. {
  3085. struct net_device *netdev = vsi->netdev;
  3086. struct i40e_pf *pf = vsi->back;
  3087. struct i40e_hw *hw = &pf->hw;
  3088. u8 netdev_tc = 0;
  3089. int i;
  3090. struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
  3091. if (!netdev)
  3092. return;
  3093. if (!enabled_tc) {
  3094. netdev_reset_tc(netdev);
  3095. return;
  3096. }
  3097. /* Set up actual enabled TCs on the VSI */
  3098. if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
  3099. return;
  3100. /* set per TC queues for the VSI */
  3101. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  3102. /* Only set TC queues for enabled tcs
  3103. *
  3104. * e.g. For a VSI that has TC0 and TC3 enabled the
  3105. * enabled_tc bitmap would be 0x00001001; the driver
  3106. * will set the numtc for netdev as 2 that will be
  3107. * referenced by the netdev layer as TC 0 and 1.
  3108. */
  3109. if (vsi->tc_config.enabled_tc & (1 << i))
  3110. netdev_set_tc_queue(netdev,
  3111. vsi->tc_config.tc_info[i].netdev_tc,
  3112. vsi->tc_config.tc_info[i].qcount,
  3113. vsi->tc_config.tc_info[i].qoffset);
  3114. }
  3115. /* Assign UP2TC map for the VSI */
  3116. for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
  3117. /* Get the actual TC# for the UP */
  3118. u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
  3119. /* Get the mapped netdev TC# for the UP */
  3120. netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
  3121. netdev_set_prio_tc_map(netdev, i, netdev_tc);
  3122. }
  3123. }
  3124. /**
  3125. * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
  3126. * @vsi: the VSI being configured
  3127. * @ctxt: the ctxt buffer returned from AQ VSI update param command
  3128. **/
  3129. static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
  3130. struct i40e_vsi_context *ctxt)
  3131. {
  3132. /* copy just the sections touched not the entire info
  3133. * since not all sections are valid as returned by
  3134. * update vsi params
  3135. */
  3136. vsi->info.mapping_flags = ctxt->info.mapping_flags;
  3137. memcpy(&vsi->info.queue_mapping,
  3138. &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
  3139. memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
  3140. sizeof(vsi->info.tc_mapping));
  3141. }
  3142. /**
  3143. * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
  3144. * @vsi: VSI to be configured
  3145. * @enabled_tc: TC bitmap
  3146. *
  3147. * This configures a particular VSI for TCs that are mapped to the
  3148. * given TC bitmap. It uses default bandwidth share for TCs across
  3149. * VSIs to configure TC for a particular VSI.
  3150. *
  3151. * NOTE:
  3152. * It is expected that the VSI queues have been quisced before calling
  3153. * this function.
  3154. **/
  3155. static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
  3156. {
  3157. u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
  3158. struct i40e_vsi_context ctxt;
  3159. int ret = 0;
  3160. int i;
  3161. /* Check if enabled_tc is same as existing or new TCs */
  3162. if (vsi->tc_config.enabled_tc == enabled_tc)
  3163. return ret;
  3164. /* Enable ETS TCs with equal BW Share for now across all VSIs */
  3165. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  3166. if (enabled_tc & (1 << i))
  3167. bw_share[i] = 1;
  3168. }
  3169. ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
  3170. if (ret) {
  3171. dev_info(&vsi->back->pdev->dev,
  3172. "Failed configuring TC map %d for VSI %d\n",
  3173. enabled_tc, vsi->seid);
  3174. goto out;
  3175. }
  3176. /* Update Queue Pairs Mapping for currently enabled UPs */
  3177. ctxt.seid = vsi->seid;
  3178. ctxt.pf_num = vsi->back->hw.pf_id;
  3179. ctxt.vf_num = 0;
  3180. ctxt.uplink_seid = vsi->uplink_seid;
  3181. memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
  3182. i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
  3183. /* Update the VSI after updating the VSI queue-mapping information */
  3184. ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
  3185. if (ret) {
  3186. dev_info(&vsi->back->pdev->dev,
  3187. "update vsi failed, aq_err=%d\n",
  3188. vsi->back->hw.aq.asq_last_status);
  3189. goto out;
  3190. }
  3191. /* update the local VSI info with updated queue map */
  3192. i40e_vsi_update_queue_map(vsi, &ctxt);
  3193. vsi->info.valid_sections = 0;
  3194. /* Update current VSI BW information */
  3195. ret = i40e_vsi_get_bw_info(vsi);
  3196. if (ret) {
  3197. dev_info(&vsi->back->pdev->dev,
  3198. "Failed updating vsi bw info, aq_err=%d\n",
  3199. vsi->back->hw.aq.asq_last_status);
  3200. goto out;
  3201. }
  3202. /* Update the netdev TC setup */
  3203. i40e_vsi_config_netdev_tc(vsi, enabled_tc);
  3204. out:
  3205. return ret;
  3206. }
  3207. /**
  3208. * i40e_up_complete - Finish the last steps of bringing up a connection
  3209. * @vsi: the VSI being configured
  3210. **/
  3211. static int i40e_up_complete(struct i40e_vsi *vsi)
  3212. {
  3213. struct i40e_pf *pf = vsi->back;
  3214. int err;
  3215. if (pf->flags & I40E_FLAG_MSIX_ENABLED)
  3216. i40e_vsi_configure_msix(vsi);
  3217. else
  3218. i40e_configure_msi_and_legacy(vsi);
  3219. /* start rings */
  3220. err = i40e_vsi_control_rings(vsi, true);
  3221. if (err)
  3222. return err;
  3223. clear_bit(__I40E_DOWN, &vsi->state);
  3224. i40e_napi_enable_all(vsi);
  3225. i40e_vsi_enable_irq(vsi);
  3226. if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
  3227. (vsi->netdev)) {
  3228. netif_tx_start_all_queues(vsi->netdev);
  3229. netif_carrier_on(vsi->netdev);
  3230. }
  3231. i40e_service_event_schedule(pf);
  3232. return 0;
  3233. }
  3234. /**
  3235. * i40e_vsi_reinit_locked - Reset the VSI
  3236. * @vsi: the VSI being configured
  3237. *
  3238. * Rebuild the ring structs after some configuration
  3239. * has changed, e.g. MTU size.
  3240. **/
  3241. static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
  3242. {
  3243. struct i40e_pf *pf = vsi->back;
  3244. WARN_ON(in_interrupt());
  3245. while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
  3246. usleep_range(1000, 2000);
  3247. i40e_down(vsi);
  3248. /* Give a VF some time to respond to the reset. The
  3249. * two second wait is based upon the watchdog cycle in
  3250. * the VF driver.
  3251. */
  3252. if (vsi->type == I40E_VSI_SRIOV)
  3253. msleep(2000);
  3254. i40e_up(vsi);
  3255. clear_bit(__I40E_CONFIG_BUSY, &pf->state);
  3256. }
  3257. /**
  3258. * i40e_up - Bring the connection back up after being down
  3259. * @vsi: the VSI being configured
  3260. **/
  3261. int i40e_up(struct i40e_vsi *vsi)
  3262. {
  3263. int err;
  3264. err = i40e_vsi_configure(vsi);
  3265. if (!err)
  3266. err = i40e_up_complete(vsi);
  3267. return err;
  3268. }
  3269. /**
  3270. * i40e_down - Shutdown the connection processing
  3271. * @vsi: the VSI being stopped
  3272. **/
  3273. void i40e_down(struct i40e_vsi *vsi)
  3274. {
  3275. int i;
  3276. /* It is assumed that the caller of this function
  3277. * sets the vsi->state __I40E_DOWN bit.
  3278. */
  3279. if (vsi->netdev) {
  3280. netif_carrier_off(vsi->netdev);
  3281. netif_tx_disable(vsi->netdev);
  3282. }
  3283. i40e_vsi_disable_irq(vsi);
  3284. i40e_vsi_control_rings(vsi, false);
  3285. i40e_napi_disable_all(vsi);
  3286. for (i = 0; i < vsi->num_queue_pairs; i++) {
  3287. i40e_clean_tx_ring(&vsi->tx_rings[i]);
  3288. i40e_clean_rx_ring(&vsi->rx_rings[i]);
  3289. }
  3290. }
  3291. /**
  3292. * i40e_setup_tc - configure multiple traffic classes
  3293. * @netdev: net device to configure
  3294. * @tc: number of traffic classes to enable
  3295. **/
  3296. static int i40e_setup_tc(struct net_device *netdev, u8 tc)
  3297. {
  3298. struct i40e_netdev_priv *np = netdev_priv(netdev);
  3299. struct i40e_vsi *vsi = np->vsi;
  3300. struct i40e_pf *pf = vsi->back;
  3301. u8 enabled_tc = 0;
  3302. int ret = -EINVAL;
  3303. int i;
  3304. /* Check if DCB enabled to continue */
  3305. if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
  3306. netdev_info(netdev, "DCB is not enabled for adapter\n");
  3307. goto exit;
  3308. }
  3309. /* Check if MFP enabled */
  3310. if (pf->flags & I40E_FLAG_MFP_ENABLED) {
  3311. netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
  3312. goto exit;
  3313. }
  3314. /* Check whether tc count is within enabled limit */
  3315. if (tc > i40e_pf_get_num_tc(pf)) {
  3316. netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
  3317. goto exit;
  3318. }
  3319. /* Generate TC map for number of tc requested */
  3320. for (i = 0; i < tc; i++)
  3321. enabled_tc |= (1 << i);
  3322. /* Requesting same TC configuration as already enabled */
  3323. if (enabled_tc == vsi->tc_config.enabled_tc)
  3324. return 0;
  3325. /* Quiesce VSI queues */
  3326. i40e_quiesce_vsi(vsi);
  3327. /* Configure VSI for enabled TCs */
  3328. ret = i40e_vsi_config_tc(vsi, enabled_tc);
  3329. if (ret) {
  3330. netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
  3331. vsi->seid);
  3332. goto exit;
  3333. }
  3334. /* Unquiesce VSI */
  3335. i40e_unquiesce_vsi(vsi);
  3336. exit:
  3337. return ret;
  3338. }
  3339. /**
  3340. * i40e_open - Called when a network interface is made active
  3341. * @netdev: network interface device structure
  3342. *
  3343. * The open entry point is called when a network interface is made
  3344. * active by the system (IFF_UP). At this point all resources needed
  3345. * for transmit and receive operations are allocated, the interrupt
  3346. * handler is registered with the OS, the netdev watchdog subtask is
  3347. * enabled, and the stack is notified that the interface is ready.
  3348. *
  3349. * Returns 0 on success, negative value on failure
  3350. **/
  3351. static int i40e_open(struct net_device *netdev)
  3352. {
  3353. struct i40e_netdev_priv *np = netdev_priv(netdev);
  3354. struct i40e_vsi *vsi = np->vsi;
  3355. struct i40e_pf *pf = vsi->back;
  3356. char int_name[IFNAMSIZ];
  3357. int err;
  3358. /* disallow open during test */
  3359. if (test_bit(__I40E_TESTING, &pf->state))
  3360. return -EBUSY;
  3361. netif_carrier_off(netdev);
  3362. /* allocate descriptors */
  3363. err = i40e_vsi_setup_tx_resources(vsi);
  3364. if (err)
  3365. goto err_setup_tx;
  3366. err = i40e_vsi_setup_rx_resources(vsi);
  3367. if (err)
  3368. goto err_setup_rx;
  3369. err = i40e_vsi_configure(vsi);
  3370. if (err)
  3371. goto err_setup_rx;
  3372. snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
  3373. dev_driver_string(&pf->pdev->dev), netdev->name);
  3374. err = i40e_vsi_request_irq(vsi, int_name);
  3375. if (err)
  3376. goto err_setup_rx;
  3377. err = i40e_up_complete(vsi);
  3378. if (err)
  3379. goto err_up_complete;
  3380. if ((vsi->type == I40E_VSI_MAIN) || (vsi->type == I40E_VSI_VMDQ2)) {
  3381. err = i40e_aq_set_vsi_broadcast(&pf->hw, vsi->seid, true, NULL);
  3382. if (err)
  3383. netdev_info(netdev,
  3384. "couldn't set broadcast err %d aq_err %d\n",
  3385. err, pf->hw.aq.asq_last_status);
  3386. }
  3387. return 0;
  3388. err_up_complete:
  3389. i40e_down(vsi);
  3390. i40e_vsi_free_irq(vsi);
  3391. err_setup_rx:
  3392. i40e_vsi_free_rx_resources(vsi);
  3393. err_setup_tx:
  3394. i40e_vsi_free_tx_resources(vsi);
  3395. if (vsi == pf->vsi[pf->lan_vsi])
  3396. i40e_do_reset(pf, (1 << __I40E_PF_RESET_REQUESTED));
  3397. return err;
  3398. }
  3399. /**
  3400. * i40e_close - Disables a network interface
  3401. * @netdev: network interface device structure
  3402. *
  3403. * The close entry point is called when an interface is de-activated
  3404. * by the OS. The hardware is still under the driver's control, but
  3405. * this netdev interface is disabled.
  3406. *
  3407. * Returns 0, this is not allowed to fail
  3408. **/
  3409. static int i40e_close(struct net_device *netdev)
  3410. {
  3411. struct i40e_netdev_priv *np = netdev_priv(netdev);
  3412. struct i40e_vsi *vsi = np->vsi;
  3413. if (test_and_set_bit(__I40E_DOWN, &vsi->state))
  3414. return 0;
  3415. i40e_down(vsi);
  3416. i40e_vsi_free_irq(vsi);
  3417. i40e_vsi_free_tx_resources(vsi);
  3418. i40e_vsi_free_rx_resources(vsi);
  3419. return 0;
  3420. }
  3421. /**
  3422. * i40e_do_reset - Start a PF or Core Reset sequence
  3423. * @pf: board private structure
  3424. * @reset_flags: which reset is requested
  3425. *
  3426. * The essential difference in resets is that the PF Reset
  3427. * doesn't clear the packet buffers, doesn't reset the PE
  3428. * firmware, and doesn't bother the other PFs on the chip.
  3429. **/
  3430. void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
  3431. {
  3432. u32 val;
  3433. WARN_ON(in_interrupt());
  3434. /* do the biggest reset indicated */
  3435. if (reset_flags & (1 << __I40E_GLOBAL_RESET_REQUESTED)) {
  3436. /* Request a Global Reset
  3437. *
  3438. * This will start the chip's countdown to the actual full
  3439. * chip reset event, and a warning interrupt to be sent
  3440. * to all PFs, including the requestor. Our handler
  3441. * for the warning interrupt will deal with the shutdown
  3442. * and recovery of the switch setup.
  3443. */
  3444. dev_info(&pf->pdev->dev, "GlobalR requested\n");
  3445. val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
  3446. val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
  3447. wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
  3448. } else if (reset_flags & (1 << __I40E_CORE_RESET_REQUESTED)) {
  3449. /* Request a Core Reset
  3450. *
  3451. * Same as Global Reset, except does *not* include the MAC/PHY
  3452. */
  3453. dev_info(&pf->pdev->dev, "CoreR requested\n");
  3454. val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
  3455. val |= I40E_GLGEN_RTRIG_CORER_MASK;
  3456. wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
  3457. i40e_flush(&pf->hw);
  3458. } else if (reset_flags & (1 << __I40E_PF_RESET_REQUESTED)) {
  3459. /* Request a PF Reset
  3460. *
  3461. * Resets only the PF-specific registers
  3462. *
  3463. * This goes directly to the tear-down and rebuild of
  3464. * the switch, since we need to do all the recovery as
  3465. * for the Core Reset.
  3466. */
  3467. dev_info(&pf->pdev->dev, "PFR requested\n");
  3468. i40e_handle_reset_warning(pf);
  3469. } else if (reset_flags & (1 << __I40E_REINIT_REQUESTED)) {
  3470. int v;
  3471. /* Find the VSI(s) that requested a re-init */
  3472. dev_info(&pf->pdev->dev,
  3473. "VSI reinit requested\n");
  3474. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  3475. struct i40e_vsi *vsi = pf->vsi[v];
  3476. if (vsi != NULL &&
  3477. test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
  3478. i40e_vsi_reinit_locked(pf->vsi[v]);
  3479. clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
  3480. }
  3481. }
  3482. /* no further action needed, so return now */
  3483. return;
  3484. } else {
  3485. dev_info(&pf->pdev->dev,
  3486. "bad reset request 0x%08x\n", reset_flags);
  3487. return;
  3488. }
  3489. }
  3490. /**
  3491. * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
  3492. * @pf: board private structure
  3493. * @e: event info posted on ARQ
  3494. *
  3495. * Handler for LAN Queue Overflow Event generated by the firmware for PF
  3496. * and VF queues
  3497. **/
  3498. static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
  3499. struct i40e_arq_event_info *e)
  3500. {
  3501. struct i40e_aqc_lan_overflow *data =
  3502. (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
  3503. u32 queue = le32_to_cpu(data->prtdcb_rupto);
  3504. u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
  3505. struct i40e_hw *hw = &pf->hw;
  3506. struct i40e_vf *vf;
  3507. u16 vf_id;
  3508. dev_info(&pf->pdev->dev, "%s: Rx Queue Number = %d QTX_CTL=0x%08x\n",
  3509. __func__, queue, qtx_ctl);
  3510. /* Queue belongs to VF, find the VF and issue VF reset */
  3511. if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
  3512. >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
  3513. vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
  3514. >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
  3515. vf_id -= hw->func_caps.vf_base_id;
  3516. vf = &pf->vf[vf_id];
  3517. i40e_vc_notify_vf_reset(vf);
  3518. /* Allow VF to process pending reset notification */
  3519. msleep(20);
  3520. i40e_reset_vf(vf, false);
  3521. }
  3522. }
  3523. /**
  3524. * i40e_service_event_complete - Finish up the service event
  3525. * @pf: board private structure
  3526. **/
  3527. static void i40e_service_event_complete(struct i40e_pf *pf)
  3528. {
  3529. BUG_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
  3530. /* flush memory to make sure state is correct before next watchog */
  3531. smp_mb__before_clear_bit();
  3532. clear_bit(__I40E_SERVICE_SCHED, &pf->state);
  3533. }
  3534. /**
  3535. * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
  3536. * @pf: board private structure
  3537. **/
  3538. static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
  3539. {
  3540. if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
  3541. return;
  3542. pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
  3543. /* if interface is down do nothing */
  3544. if (test_bit(__I40E_DOWN, &pf->state))
  3545. return;
  3546. }
  3547. /**
  3548. * i40e_vsi_link_event - notify VSI of a link event
  3549. * @vsi: vsi to be notified
  3550. * @link_up: link up or down
  3551. **/
  3552. static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
  3553. {
  3554. if (!vsi)
  3555. return;
  3556. switch (vsi->type) {
  3557. case I40E_VSI_MAIN:
  3558. if (!vsi->netdev || !vsi->netdev_registered)
  3559. break;
  3560. if (link_up) {
  3561. netif_carrier_on(vsi->netdev);
  3562. netif_tx_wake_all_queues(vsi->netdev);
  3563. } else {
  3564. netif_carrier_off(vsi->netdev);
  3565. netif_tx_stop_all_queues(vsi->netdev);
  3566. }
  3567. break;
  3568. case I40E_VSI_SRIOV:
  3569. break;
  3570. case I40E_VSI_VMDQ2:
  3571. case I40E_VSI_CTRL:
  3572. case I40E_VSI_MIRROR:
  3573. default:
  3574. /* there is no notification for other VSIs */
  3575. break;
  3576. }
  3577. }
  3578. /**
  3579. * i40e_veb_link_event - notify elements on the veb of a link event
  3580. * @veb: veb to be notified
  3581. * @link_up: link up or down
  3582. **/
  3583. static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
  3584. {
  3585. struct i40e_pf *pf;
  3586. int i;
  3587. if (!veb || !veb->pf)
  3588. return;
  3589. pf = veb->pf;
  3590. /* depth first... */
  3591. for (i = 0; i < I40E_MAX_VEB; i++)
  3592. if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
  3593. i40e_veb_link_event(pf->veb[i], link_up);
  3594. /* ... now the local VSIs */
  3595. for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
  3596. if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
  3597. i40e_vsi_link_event(pf->vsi[i], link_up);
  3598. }
  3599. /**
  3600. * i40e_link_event - Update netif_carrier status
  3601. * @pf: board private structure
  3602. **/
  3603. static void i40e_link_event(struct i40e_pf *pf)
  3604. {
  3605. bool new_link, old_link;
  3606. new_link = (pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP);
  3607. old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
  3608. if (new_link == old_link)
  3609. return;
  3610. netdev_info(pf->vsi[pf->lan_vsi]->netdev,
  3611. "NIC Link is %s\n", (new_link ? "Up" : "Down"));
  3612. /* Notify the base of the switch tree connected to
  3613. * the link. Floating VEBs are not notified.
  3614. */
  3615. if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
  3616. i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
  3617. else
  3618. i40e_vsi_link_event(pf->vsi[pf->lan_vsi], new_link);
  3619. if (pf->vf)
  3620. i40e_vc_notify_link_state(pf);
  3621. }
  3622. /**
  3623. * i40e_check_hang_subtask - Check for hung queues and dropped interrupts
  3624. * @pf: board private structure
  3625. *
  3626. * Set the per-queue flags to request a check for stuck queues in the irq
  3627. * clean functions, then force interrupts to be sure the irq clean is called.
  3628. **/
  3629. static void i40e_check_hang_subtask(struct i40e_pf *pf)
  3630. {
  3631. int i, v;
  3632. /* If we're down or resetting, just bail */
  3633. if (test_bit(__I40E_CONFIG_BUSY, &pf->state))
  3634. return;
  3635. /* for each VSI/netdev
  3636. * for each Tx queue
  3637. * set the check flag
  3638. * for each q_vector
  3639. * force an interrupt
  3640. */
  3641. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  3642. struct i40e_vsi *vsi = pf->vsi[v];
  3643. int armed = 0;
  3644. if (!pf->vsi[v] ||
  3645. test_bit(__I40E_DOWN, &vsi->state) ||
  3646. (vsi->netdev && !netif_carrier_ok(vsi->netdev)))
  3647. continue;
  3648. for (i = 0; i < vsi->num_queue_pairs; i++) {
  3649. set_check_for_tx_hang(&vsi->tx_rings[i]);
  3650. if (test_bit(__I40E_HANG_CHECK_ARMED,
  3651. &vsi->tx_rings[i].state))
  3652. armed++;
  3653. }
  3654. if (armed) {
  3655. if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
  3656. wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0,
  3657. (I40E_PFINT_DYN_CTL0_INTENA_MASK |
  3658. I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK));
  3659. } else {
  3660. u16 vec = vsi->base_vector - 1;
  3661. u32 val = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
  3662. I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK);
  3663. for (i = 0; i < vsi->num_q_vectors; i++, vec++)
  3664. wr32(&vsi->back->hw,
  3665. I40E_PFINT_DYN_CTLN(vec), val);
  3666. }
  3667. i40e_flush(&vsi->back->hw);
  3668. }
  3669. }
  3670. }
  3671. /**
  3672. * i40e_watchdog_subtask - Check and bring link up
  3673. * @pf: board private structure
  3674. **/
  3675. static void i40e_watchdog_subtask(struct i40e_pf *pf)
  3676. {
  3677. int i;
  3678. /* if interface is down do nothing */
  3679. if (test_bit(__I40E_DOWN, &pf->state) ||
  3680. test_bit(__I40E_CONFIG_BUSY, &pf->state))
  3681. return;
  3682. /* Update the stats for active netdevs so the network stack
  3683. * can look at updated numbers whenever it cares to
  3684. */
  3685. for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
  3686. if (pf->vsi[i] && pf->vsi[i]->netdev)
  3687. i40e_update_stats(pf->vsi[i]);
  3688. /* Update the stats for the active switching components */
  3689. for (i = 0; i < I40E_MAX_VEB; i++)
  3690. if (pf->veb[i])
  3691. i40e_update_veb_stats(pf->veb[i]);
  3692. }
  3693. /**
  3694. * i40e_reset_subtask - Set up for resetting the device and driver
  3695. * @pf: board private structure
  3696. **/
  3697. static void i40e_reset_subtask(struct i40e_pf *pf)
  3698. {
  3699. u32 reset_flags = 0;
  3700. if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
  3701. reset_flags |= (1 << __I40E_REINIT_REQUESTED);
  3702. clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
  3703. }
  3704. if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
  3705. reset_flags |= (1 << __I40E_PF_RESET_REQUESTED);
  3706. clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
  3707. }
  3708. if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
  3709. reset_flags |= (1 << __I40E_CORE_RESET_REQUESTED);
  3710. clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
  3711. }
  3712. if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
  3713. reset_flags |= (1 << __I40E_GLOBAL_RESET_REQUESTED);
  3714. clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
  3715. }
  3716. /* If there's a recovery already waiting, it takes
  3717. * precedence before starting a new reset sequence.
  3718. */
  3719. if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
  3720. i40e_handle_reset_warning(pf);
  3721. return;
  3722. }
  3723. /* If we're already down or resetting, just bail */
  3724. if (reset_flags &&
  3725. !test_bit(__I40E_DOWN, &pf->state) &&
  3726. !test_bit(__I40E_CONFIG_BUSY, &pf->state))
  3727. i40e_do_reset(pf, reset_flags);
  3728. }
  3729. /**
  3730. * i40e_handle_link_event - Handle link event
  3731. * @pf: board private structure
  3732. * @e: event info posted on ARQ
  3733. **/
  3734. static void i40e_handle_link_event(struct i40e_pf *pf,
  3735. struct i40e_arq_event_info *e)
  3736. {
  3737. struct i40e_hw *hw = &pf->hw;
  3738. struct i40e_aqc_get_link_status *status =
  3739. (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
  3740. struct i40e_link_status *hw_link_info = &hw->phy.link_info;
  3741. /* save off old link status information */
  3742. memcpy(&pf->hw.phy.link_info_old, hw_link_info,
  3743. sizeof(pf->hw.phy.link_info_old));
  3744. /* update link status */
  3745. hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
  3746. hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
  3747. hw_link_info->link_info = status->link_info;
  3748. hw_link_info->an_info = status->an_info;
  3749. hw_link_info->ext_info = status->ext_info;
  3750. hw_link_info->lse_enable =
  3751. le16_to_cpu(status->command_flags) &
  3752. I40E_AQ_LSE_ENABLE;
  3753. /* process the event */
  3754. i40e_link_event(pf);
  3755. /* Do a new status request to re-enable LSE reporting
  3756. * and load new status information into the hw struct,
  3757. * then see if the status changed while processing the
  3758. * initial event.
  3759. */
  3760. i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
  3761. i40e_link_event(pf);
  3762. }
  3763. /**
  3764. * i40e_clean_adminq_subtask - Clean the AdminQ rings
  3765. * @pf: board private structure
  3766. **/
  3767. static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
  3768. {
  3769. struct i40e_arq_event_info event;
  3770. struct i40e_hw *hw = &pf->hw;
  3771. u16 pending, i = 0;
  3772. i40e_status ret;
  3773. u16 opcode;
  3774. u32 val;
  3775. if (!test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state))
  3776. return;
  3777. event.msg_size = I40E_MAX_AQ_BUF_SIZE;
  3778. event.msg_buf = kzalloc(event.msg_size, GFP_KERNEL);
  3779. if (!event.msg_buf)
  3780. return;
  3781. do {
  3782. ret = i40e_clean_arq_element(hw, &event, &pending);
  3783. if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) {
  3784. dev_info(&pf->pdev->dev, "No ARQ event found\n");
  3785. break;
  3786. } else if (ret) {
  3787. dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
  3788. break;
  3789. }
  3790. opcode = le16_to_cpu(event.desc.opcode);
  3791. switch (opcode) {
  3792. case i40e_aqc_opc_get_link_status:
  3793. i40e_handle_link_event(pf, &event);
  3794. break;
  3795. case i40e_aqc_opc_send_msg_to_pf:
  3796. ret = i40e_vc_process_vf_msg(pf,
  3797. le16_to_cpu(event.desc.retval),
  3798. le32_to_cpu(event.desc.cookie_high),
  3799. le32_to_cpu(event.desc.cookie_low),
  3800. event.msg_buf,
  3801. event.msg_size);
  3802. break;
  3803. case i40e_aqc_opc_lldp_update_mib:
  3804. dev_info(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
  3805. break;
  3806. case i40e_aqc_opc_event_lan_overflow:
  3807. dev_info(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
  3808. i40e_handle_lan_overflow_event(pf, &event);
  3809. break;
  3810. default:
  3811. dev_info(&pf->pdev->dev,
  3812. "ARQ Error: Unknown event %d received\n",
  3813. event.desc.opcode);
  3814. break;
  3815. }
  3816. } while (pending && (i++ < pf->adminq_work_limit));
  3817. clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
  3818. /* re-enable Admin queue interrupt cause */
  3819. val = rd32(hw, I40E_PFINT_ICR0_ENA);
  3820. val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
  3821. wr32(hw, I40E_PFINT_ICR0_ENA, val);
  3822. i40e_flush(hw);
  3823. kfree(event.msg_buf);
  3824. }
  3825. /**
  3826. * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
  3827. * @veb: pointer to the VEB instance
  3828. *
  3829. * This is a recursive function that first builds the attached VSIs then
  3830. * recurses in to build the next layer of VEB. We track the connections
  3831. * through our own index numbers because the seid's from the HW could
  3832. * change across the reset.
  3833. **/
  3834. static int i40e_reconstitute_veb(struct i40e_veb *veb)
  3835. {
  3836. struct i40e_vsi *ctl_vsi = NULL;
  3837. struct i40e_pf *pf = veb->pf;
  3838. int v, veb_idx;
  3839. int ret;
  3840. /* build VSI that owns this VEB, temporarily attached to base VEB */
  3841. for (v = 0; v < pf->hw.func_caps.num_vsis && !ctl_vsi; v++) {
  3842. if (pf->vsi[v] &&
  3843. pf->vsi[v]->veb_idx == veb->idx &&
  3844. pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
  3845. ctl_vsi = pf->vsi[v];
  3846. break;
  3847. }
  3848. }
  3849. if (!ctl_vsi) {
  3850. dev_info(&pf->pdev->dev,
  3851. "missing owner VSI for veb_idx %d\n", veb->idx);
  3852. ret = -ENOENT;
  3853. goto end_reconstitute;
  3854. }
  3855. if (ctl_vsi != pf->vsi[pf->lan_vsi])
  3856. ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
  3857. ret = i40e_add_vsi(ctl_vsi);
  3858. if (ret) {
  3859. dev_info(&pf->pdev->dev,
  3860. "rebuild of owner VSI failed: %d\n", ret);
  3861. goto end_reconstitute;
  3862. }
  3863. i40e_vsi_reset_stats(ctl_vsi);
  3864. /* create the VEB in the switch and move the VSI onto the VEB */
  3865. ret = i40e_add_veb(veb, ctl_vsi);
  3866. if (ret)
  3867. goto end_reconstitute;
  3868. /* create the remaining VSIs attached to this VEB */
  3869. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  3870. if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
  3871. continue;
  3872. if (pf->vsi[v]->veb_idx == veb->idx) {
  3873. struct i40e_vsi *vsi = pf->vsi[v];
  3874. vsi->uplink_seid = veb->seid;
  3875. ret = i40e_add_vsi(vsi);
  3876. if (ret) {
  3877. dev_info(&pf->pdev->dev,
  3878. "rebuild of vsi_idx %d failed: %d\n",
  3879. v, ret);
  3880. goto end_reconstitute;
  3881. }
  3882. i40e_vsi_reset_stats(vsi);
  3883. }
  3884. }
  3885. /* create any VEBs attached to this VEB - RECURSION */
  3886. for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
  3887. if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
  3888. pf->veb[veb_idx]->uplink_seid = veb->seid;
  3889. ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
  3890. if (ret)
  3891. break;
  3892. }
  3893. }
  3894. end_reconstitute:
  3895. return ret;
  3896. }
  3897. /**
  3898. * i40e_get_capabilities - get info about the HW
  3899. * @pf: the PF struct
  3900. **/
  3901. static int i40e_get_capabilities(struct i40e_pf *pf)
  3902. {
  3903. struct i40e_aqc_list_capabilities_element_resp *cap_buf;
  3904. u16 data_size;
  3905. int buf_len;
  3906. int err;
  3907. buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
  3908. do {
  3909. cap_buf = kzalloc(buf_len, GFP_KERNEL);
  3910. if (!cap_buf)
  3911. return -ENOMEM;
  3912. /* this loads the data into the hw struct for us */
  3913. err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
  3914. &data_size,
  3915. i40e_aqc_opc_list_func_capabilities,
  3916. NULL);
  3917. /* data loaded, buffer no longer needed */
  3918. kfree(cap_buf);
  3919. if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
  3920. /* retry with a larger buffer */
  3921. buf_len = data_size;
  3922. } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
  3923. dev_info(&pf->pdev->dev,
  3924. "capability discovery failed: aq=%d\n",
  3925. pf->hw.aq.asq_last_status);
  3926. return -ENODEV;
  3927. }
  3928. } while (err);
  3929. if (pf->hw.debug_mask & I40E_DEBUG_USER)
  3930. dev_info(&pf->pdev->dev,
  3931. "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
  3932. pf->hw.pf_id, pf->hw.func_caps.num_vfs,
  3933. pf->hw.func_caps.num_msix_vectors,
  3934. pf->hw.func_caps.num_msix_vectors_vf,
  3935. pf->hw.func_caps.fd_filters_guaranteed,
  3936. pf->hw.func_caps.fd_filters_best_effort,
  3937. pf->hw.func_caps.num_tx_qp,
  3938. pf->hw.func_caps.num_vsis);
  3939. return 0;
  3940. }
  3941. /**
  3942. * i40e_fdir_setup - initialize the Flow Director resources
  3943. * @pf: board private structure
  3944. **/
  3945. static void i40e_fdir_setup(struct i40e_pf *pf)
  3946. {
  3947. struct i40e_vsi *vsi;
  3948. bool new_vsi = false;
  3949. int err, i;
  3950. if (!(pf->flags & (I40E_FLAG_FDIR_ENABLED|I40E_FLAG_FDIR_ATR_ENABLED)))
  3951. return;
  3952. pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
  3953. /* find existing or make new FDIR VSI */
  3954. vsi = NULL;
  3955. for (i = 0; i < pf->hw.func_caps.num_vsis; i++)
  3956. if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
  3957. vsi = pf->vsi[i];
  3958. if (!vsi) {
  3959. vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->mac_seid, 0);
  3960. if (!vsi) {
  3961. dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
  3962. pf->flags &= ~I40E_FLAG_FDIR_ENABLED;
  3963. return;
  3964. }
  3965. new_vsi = true;
  3966. }
  3967. WARN_ON(vsi->base_queue != I40E_FDIR_RING);
  3968. i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_rings);
  3969. err = i40e_vsi_setup_tx_resources(vsi);
  3970. if (!err)
  3971. err = i40e_vsi_setup_rx_resources(vsi);
  3972. if (!err)
  3973. err = i40e_vsi_configure(vsi);
  3974. if (!err && new_vsi) {
  3975. char int_name[IFNAMSIZ + 9];
  3976. snprintf(int_name, sizeof(int_name) - 1, "%s-fdir",
  3977. dev_driver_string(&pf->pdev->dev));
  3978. err = i40e_vsi_request_irq(vsi, int_name);
  3979. }
  3980. if (!err)
  3981. err = i40e_up_complete(vsi);
  3982. clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
  3983. }
  3984. /**
  3985. * i40e_fdir_teardown - release the Flow Director resources
  3986. * @pf: board private structure
  3987. **/
  3988. static void i40e_fdir_teardown(struct i40e_pf *pf)
  3989. {
  3990. int i;
  3991. for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
  3992. if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
  3993. i40e_vsi_release(pf->vsi[i]);
  3994. break;
  3995. }
  3996. }
  3997. }
  3998. /**
  3999. * i40e_handle_reset_warning - prep for the core to reset
  4000. * @pf: board private structure
  4001. *
  4002. * Close up the VFs and other things in prep for a Core Reset,
  4003. * then get ready to rebuild the world.
  4004. **/
  4005. static void i40e_handle_reset_warning(struct i40e_pf *pf)
  4006. {
  4007. struct i40e_driver_version dv;
  4008. struct i40e_hw *hw = &pf->hw;
  4009. i40e_status ret;
  4010. u32 v;
  4011. clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
  4012. if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
  4013. return;
  4014. dev_info(&pf->pdev->dev, "Tearing down internal switch for reset\n");
  4015. i40e_vc_notify_reset(pf);
  4016. /* quiesce the VSIs and their queues that are not already DOWN */
  4017. i40e_pf_quiesce_all_vsi(pf);
  4018. for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
  4019. if (pf->vsi[v])
  4020. pf->vsi[v]->seid = 0;
  4021. }
  4022. i40e_shutdown_adminq(&pf->hw);
  4023. /* Now we wait for GRST to settle out.
  4024. * We don't have to delete the VEBs or VSIs from the hw switch
  4025. * because the reset will make them disappear.
  4026. */
  4027. ret = i40e_pf_reset(hw);
  4028. if (ret)
  4029. dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
  4030. pf->pfr_count++;
  4031. if (test_bit(__I40E_DOWN, &pf->state))
  4032. goto end_core_reset;
  4033. dev_info(&pf->pdev->dev, "Rebuilding internal switch\n");
  4034. /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
  4035. ret = i40e_init_adminq(&pf->hw);
  4036. if (ret) {
  4037. dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
  4038. goto end_core_reset;
  4039. }
  4040. ret = i40e_get_capabilities(pf);
  4041. if (ret) {
  4042. dev_info(&pf->pdev->dev, "i40e_get_capabilities failed, %d\n",
  4043. ret);
  4044. goto end_core_reset;
  4045. }
  4046. /* call shutdown HMC */
  4047. ret = i40e_shutdown_lan_hmc(hw);
  4048. if (ret) {
  4049. dev_info(&pf->pdev->dev, "shutdown_lan_hmc failed: %d\n", ret);
  4050. goto end_core_reset;
  4051. }
  4052. ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
  4053. hw->func_caps.num_rx_qp,
  4054. pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
  4055. if (ret) {
  4056. dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
  4057. goto end_core_reset;
  4058. }
  4059. ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
  4060. if (ret) {
  4061. dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
  4062. goto end_core_reset;
  4063. }
  4064. /* do basic switch setup */
  4065. ret = i40e_setup_pf_switch(pf);
  4066. if (ret)
  4067. goto end_core_reset;
  4068. /* Rebuild the VSIs and VEBs that existed before reset.
  4069. * They are still in our local switch element arrays, so only
  4070. * need to rebuild the switch model in the HW.
  4071. *
  4072. * If there were VEBs but the reconstitution failed, we'll try
  4073. * try to recover minimal use by getting the basic PF VSI working.
  4074. */
  4075. if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
  4076. dev_info(&pf->pdev->dev, "attempting to rebuild switch\n");
  4077. /* find the one VEB connected to the MAC, and find orphans */
  4078. for (v = 0; v < I40E_MAX_VEB; v++) {
  4079. if (!pf->veb[v])
  4080. continue;
  4081. if (pf->veb[v]->uplink_seid == pf->mac_seid ||
  4082. pf->veb[v]->uplink_seid == 0) {
  4083. ret = i40e_reconstitute_veb(pf->veb[v]);
  4084. if (!ret)
  4085. continue;
  4086. /* If Main VEB failed, we're in deep doodoo,
  4087. * so give up rebuilding the switch and set up
  4088. * for minimal rebuild of PF VSI.
  4089. * If orphan failed, we'll report the error
  4090. * but try to keep going.
  4091. */
  4092. if (pf->veb[v]->uplink_seid == pf->mac_seid) {
  4093. dev_info(&pf->pdev->dev,
  4094. "rebuild of switch failed: %d, will try to set up simple PF connection\n",
  4095. ret);
  4096. pf->vsi[pf->lan_vsi]->uplink_seid
  4097. = pf->mac_seid;
  4098. break;
  4099. } else if (pf->veb[v]->uplink_seid == 0) {
  4100. dev_info(&pf->pdev->dev,
  4101. "rebuild of orphan VEB failed: %d\n",
  4102. ret);
  4103. }
  4104. }
  4105. }
  4106. }
  4107. if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
  4108. dev_info(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
  4109. /* no VEB, so rebuild only the Main VSI */
  4110. ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
  4111. if (ret) {
  4112. dev_info(&pf->pdev->dev,
  4113. "rebuild of Main VSI failed: %d\n", ret);
  4114. goto end_core_reset;
  4115. }
  4116. }
  4117. /* reinit the misc interrupt */
  4118. if (pf->flags & I40E_FLAG_MSIX_ENABLED)
  4119. ret = i40e_setup_misc_vector(pf);
  4120. /* restart the VSIs that were rebuilt and running before the reset */
  4121. i40e_pf_unquiesce_all_vsi(pf);
  4122. /* tell the firmware that we're starting */
  4123. dv.major_version = DRV_VERSION_MAJOR;
  4124. dv.minor_version = DRV_VERSION_MINOR;
  4125. dv.build_version = DRV_VERSION_BUILD;
  4126. dv.subbuild_version = 0;
  4127. i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
  4128. dev_info(&pf->pdev->dev, "PF reset done\n");
  4129. end_core_reset:
  4130. clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
  4131. }
  4132. /**
  4133. * i40e_handle_mdd_event
  4134. * @pf: pointer to the pf structure
  4135. *
  4136. * Called from the MDD irq handler to identify possibly malicious vfs
  4137. **/
  4138. static void i40e_handle_mdd_event(struct i40e_pf *pf)
  4139. {
  4140. struct i40e_hw *hw = &pf->hw;
  4141. bool mdd_detected = false;
  4142. struct i40e_vf *vf;
  4143. u32 reg;
  4144. int i;
  4145. if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
  4146. return;
  4147. /* find what triggered the MDD event */
  4148. reg = rd32(hw, I40E_GL_MDET_TX);
  4149. if (reg & I40E_GL_MDET_TX_VALID_MASK) {
  4150. u8 func = (reg & I40E_GL_MDET_TX_FUNCTION_MASK)
  4151. >> I40E_GL_MDET_TX_FUNCTION_SHIFT;
  4152. u8 event = (reg & I40E_GL_MDET_TX_EVENT_SHIFT)
  4153. >> I40E_GL_MDET_TX_EVENT_SHIFT;
  4154. u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK)
  4155. >> I40E_GL_MDET_TX_QUEUE_SHIFT;
  4156. dev_info(&pf->pdev->dev,
  4157. "Malicious Driver Detection TX event 0x%02x on q %d of function 0x%02x\n",
  4158. event, queue, func);
  4159. wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
  4160. mdd_detected = true;
  4161. }
  4162. reg = rd32(hw, I40E_GL_MDET_RX);
  4163. if (reg & I40E_GL_MDET_RX_VALID_MASK) {
  4164. u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK)
  4165. >> I40E_GL_MDET_RX_FUNCTION_SHIFT;
  4166. u8 event = (reg & I40E_GL_MDET_RX_EVENT_SHIFT)
  4167. >> I40E_GL_MDET_RX_EVENT_SHIFT;
  4168. u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK)
  4169. >> I40E_GL_MDET_RX_QUEUE_SHIFT;
  4170. dev_info(&pf->pdev->dev,
  4171. "Malicious Driver Detection RX event 0x%02x on q %d of function 0x%02x\n",
  4172. event, queue, func);
  4173. wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
  4174. mdd_detected = true;
  4175. }
  4176. /* see if one of the VFs needs its hand slapped */
  4177. for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
  4178. vf = &(pf->vf[i]);
  4179. reg = rd32(hw, I40E_VP_MDET_TX(i));
  4180. if (reg & I40E_VP_MDET_TX_VALID_MASK) {
  4181. wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
  4182. vf->num_mdd_events++;
  4183. dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
  4184. }
  4185. reg = rd32(hw, I40E_VP_MDET_RX(i));
  4186. if (reg & I40E_VP_MDET_RX_VALID_MASK) {
  4187. wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
  4188. vf->num_mdd_events++;
  4189. dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
  4190. }
  4191. if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
  4192. dev_info(&pf->pdev->dev,
  4193. "Too many MDD events on VF %d, disabled\n", i);
  4194. dev_info(&pf->pdev->dev,
  4195. "Use PF Control I/F to re-enable the VF\n");
  4196. set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
  4197. }
  4198. }
  4199. /* re-enable mdd interrupt cause */
  4200. clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
  4201. reg = rd32(hw, I40E_PFINT_ICR0_ENA);
  4202. reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
  4203. wr32(hw, I40E_PFINT_ICR0_ENA, reg);
  4204. i40e_flush(hw);
  4205. }
  4206. /**
  4207. * i40e_service_task - Run the driver's async subtasks
  4208. * @work: pointer to work_struct containing our data
  4209. **/
  4210. static void i40e_service_task(struct work_struct *work)
  4211. {
  4212. struct i40e_pf *pf = container_of(work,
  4213. struct i40e_pf,
  4214. service_task);
  4215. unsigned long start_time = jiffies;
  4216. i40e_reset_subtask(pf);
  4217. i40e_handle_mdd_event(pf);
  4218. i40e_vc_process_vflr_event(pf);
  4219. i40e_watchdog_subtask(pf);
  4220. i40e_fdir_reinit_subtask(pf);
  4221. i40e_check_hang_subtask(pf);
  4222. i40e_sync_filters_subtask(pf);
  4223. i40e_clean_adminq_subtask(pf);
  4224. i40e_service_event_complete(pf);
  4225. /* If the tasks have taken longer than one timer cycle or there
  4226. * is more work to be done, reschedule the service task now
  4227. * rather than wait for the timer to tick again.
  4228. */
  4229. if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
  4230. test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
  4231. test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
  4232. test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
  4233. i40e_service_event_schedule(pf);
  4234. }
  4235. /**
  4236. * i40e_service_timer - timer callback
  4237. * @data: pointer to PF struct
  4238. **/
  4239. static void i40e_service_timer(unsigned long data)
  4240. {
  4241. struct i40e_pf *pf = (struct i40e_pf *)data;
  4242. mod_timer(&pf->service_timer,
  4243. round_jiffies(jiffies + pf->service_timer_period));
  4244. i40e_service_event_schedule(pf);
  4245. }
  4246. /**
  4247. * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
  4248. * @vsi: the VSI being configured
  4249. **/
  4250. static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
  4251. {
  4252. struct i40e_pf *pf = vsi->back;
  4253. switch (vsi->type) {
  4254. case I40E_VSI_MAIN:
  4255. vsi->alloc_queue_pairs = pf->num_lan_qps;
  4256. vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
  4257. I40E_REQ_DESCRIPTOR_MULTIPLE);
  4258. if (pf->flags & I40E_FLAG_MSIX_ENABLED)
  4259. vsi->num_q_vectors = pf->num_lan_msix;
  4260. else
  4261. vsi->num_q_vectors = 1;
  4262. break;
  4263. case I40E_VSI_FDIR:
  4264. vsi->alloc_queue_pairs = 1;
  4265. vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
  4266. I40E_REQ_DESCRIPTOR_MULTIPLE);
  4267. vsi->num_q_vectors = 1;
  4268. break;
  4269. case I40E_VSI_VMDQ2:
  4270. vsi->alloc_queue_pairs = pf->num_vmdq_qps;
  4271. vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
  4272. I40E_REQ_DESCRIPTOR_MULTIPLE);
  4273. vsi->num_q_vectors = pf->num_vmdq_msix;
  4274. break;
  4275. case I40E_VSI_SRIOV:
  4276. vsi->alloc_queue_pairs = pf->num_vf_qps;
  4277. vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
  4278. I40E_REQ_DESCRIPTOR_MULTIPLE);
  4279. break;
  4280. default:
  4281. WARN_ON(1);
  4282. return -ENODATA;
  4283. }
  4284. return 0;
  4285. }
  4286. /**
  4287. * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
  4288. * @pf: board private structure
  4289. * @type: type of VSI
  4290. *
  4291. * On error: returns error code (negative)
  4292. * On success: returns vsi index in PF (positive)
  4293. **/
  4294. static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
  4295. {
  4296. int ret = -ENODEV;
  4297. struct i40e_vsi *vsi;
  4298. int vsi_idx;
  4299. int i;
  4300. /* Need to protect the allocation of the VSIs at the PF level */
  4301. mutex_lock(&pf->switch_mutex);
  4302. /* VSI list may be fragmented if VSI creation/destruction has
  4303. * been happening. We can afford to do a quick scan to look
  4304. * for any free VSIs in the list.
  4305. *
  4306. * find next empty vsi slot, looping back around if necessary
  4307. */
  4308. i = pf->next_vsi;
  4309. while (i < pf->hw.func_caps.num_vsis && pf->vsi[i])
  4310. i++;
  4311. if (i >= pf->hw.func_caps.num_vsis) {
  4312. i = 0;
  4313. while (i < pf->next_vsi && pf->vsi[i])
  4314. i++;
  4315. }
  4316. if (i < pf->hw.func_caps.num_vsis && !pf->vsi[i]) {
  4317. vsi_idx = i; /* Found one! */
  4318. } else {
  4319. ret = -ENODEV;
  4320. goto err_alloc_vsi; /* out of VSI slots! */
  4321. }
  4322. pf->next_vsi = ++i;
  4323. vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
  4324. if (!vsi) {
  4325. ret = -ENOMEM;
  4326. goto err_alloc_vsi;
  4327. }
  4328. vsi->type = type;
  4329. vsi->back = pf;
  4330. set_bit(__I40E_DOWN, &vsi->state);
  4331. vsi->flags = 0;
  4332. vsi->idx = vsi_idx;
  4333. vsi->rx_itr_setting = pf->rx_itr_default;
  4334. vsi->tx_itr_setting = pf->tx_itr_default;
  4335. vsi->netdev_registered = false;
  4336. vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
  4337. INIT_LIST_HEAD(&vsi->mac_filter_list);
  4338. i40e_set_num_rings_in_vsi(vsi);
  4339. /* Setup default MSIX irq handler for VSI */
  4340. i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
  4341. pf->vsi[vsi_idx] = vsi;
  4342. ret = vsi_idx;
  4343. err_alloc_vsi:
  4344. mutex_unlock(&pf->switch_mutex);
  4345. return ret;
  4346. }
  4347. /**
  4348. * i40e_vsi_clear - Deallocate the VSI provided
  4349. * @vsi: the VSI being un-configured
  4350. **/
  4351. static int i40e_vsi_clear(struct i40e_vsi *vsi)
  4352. {
  4353. struct i40e_pf *pf;
  4354. if (!vsi)
  4355. return 0;
  4356. if (!vsi->back)
  4357. goto free_vsi;
  4358. pf = vsi->back;
  4359. mutex_lock(&pf->switch_mutex);
  4360. if (!pf->vsi[vsi->idx]) {
  4361. dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
  4362. vsi->idx, vsi->idx, vsi, vsi->type);
  4363. goto unlock_vsi;
  4364. }
  4365. if (pf->vsi[vsi->idx] != vsi) {
  4366. dev_err(&pf->pdev->dev,
  4367. "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
  4368. pf->vsi[vsi->idx]->idx,
  4369. pf->vsi[vsi->idx],
  4370. pf->vsi[vsi->idx]->type,
  4371. vsi->idx, vsi, vsi->type);
  4372. goto unlock_vsi;
  4373. }
  4374. /* updates the pf for this cleared vsi */
  4375. i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
  4376. i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
  4377. pf->vsi[vsi->idx] = NULL;
  4378. if (vsi->idx < pf->next_vsi)
  4379. pf->next_vsi = vsi->idx;
  4380. unlock_vsi:
  4381. mutex_unlock(&pf->switch_mutex);
  4382. free_vsi:
  4383. kfree(vsi);
  4384. return 0;
  4385. }
  4386. /**
  4387. * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
  4388. * @vsi: the VSI being configured
  4389. **/
  4390. static int i40e_alloc_rings(struct i40e_vsi *vsi)
  4391. {
  4392. struct i40e_pf *pf = vsi->back;
  4393. int ret = 0;
  4394. int i;
  4395. vsi->rx_rings = kcalloc(vsi->alloc_queue_pairs,
  4396. sizeof(struct i40e_ring), GFP_KERNEL);
  4397. if (!vsi->rx_rings) {
  4398. ret = -ENOMEM;
  4399. goto err_alloc_rings;
  4400. }
  4401. vsi->tx_rings = kcalloc(vsi->alloc_queue_pairs,
  4402. sizeof(struct i40e_ring), GFP_KERNEL);
  4403. if (!vsi->tx_rings) {
  4404. ret = -ENOMEM;
  4405. kfree(vsi->rx_rings);
  4406. goto err_alloc_rings;
  4407. }
  4408. /* Set basic values in the rings to be used later during open() */
  4409. for (i = 0; i < vsi->alloc_queue_pairs; i++) {
  4410. struct i40e_ring *rx_ring = &vsi->rx_rings[i];
  4411. struct i40e_ring *tx_ring = &vsi->tx_rings[i];
  4412. tx_ring->queue_index = i;
  4413. tx_ring->reg_idx = vsi->base_queue + i;
  4414. tx_ring->ring_active = false;
  4415. tx_ring->vsi = vsi;
  4416. tx_ring->netdev = vsi->netdev;
  4417. tx_ring->dev = &pf->pdev->dev;
  4418. tx_ring->count = vsi->num_desc;
  4419. tx_ring->size = 0;
  4420. tx_ring->dcb_tc = 0;
  4421. rx_ring->queue_index = i;
  4422. rx_ring->reg_idx = vsi->base_queue + i;
  4423. rx_ring->ring_active = false;
  4424. rx_ring->vsi = vsi;
  4425. rx_ring->netdev = vsi->netdev;
  4426. rx_ring->dev = &pf->pdev->dev;
  4427. rx_ring->count = vsi->num_desc;
  4428. rx_ring->size = 0;
  4429. rx_ring->dcb_tc = 0;
  4430. if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
  4431. set_ring_16byte_desc_enabled(rx_ring);
  4432. else
  4433. clear_ring_16byte_desc_enabled(rx_ring);
  4434. }
  4435. err_alloc_rings:
  4436. return ret;
  4437. }
  4438. /**
  4439. * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
  4440. * @vsi: the VSI being cleaned
  4441. **/
  4442. static int i40e_vsi_clear_rings(struct i40e_vsi *vsi)
  4443. {
  4444. if (vsi) {
  4445. kfree(vsi->rx_rings);
  4446. kfree(vsi->tx_rings);
  4447. }
  4448. return 0;
  4449. }
  4450. /**
  4451. * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
  4452. * @pf: board private structure
  4453. * @vectors: the number of MSI-X vectors to request
  4454. *
  4455. * Returns the number of vectors reserved, or error
  4456. **/
  4457. static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
  4458. {
  4459. int err = 0;
  4460. pf->num_msix_entries = 0;
  4461. while (vectors >= I40E_MIN_MSIX) {
  4462. err = pci_enable_msix(pf->pdev, pf->msix_entries, vectors);
  4463. if (err == 0) {
  4464. /* good to go */
  4465. pf->num_msix_entries = vectors;
  4466. break;
  4467. } else if (err < 0) {
  4468. /* total failure */
  4469. dev_info(&pf->pdev->dev,
  4470. "MSI-X vector reservation failed: %d\n", err);
  4471. vectors = 0;
  4472. break;
  4473. } else {
  4474. /* err > 0 is the hint for retry */
  4475. dev_info(&pf->pdev->dev,
  4476. "MSI-X vectors wanted %d, retrying with %d\n",
  4477. vectors, err);
  4478. vectors = err;
  4479. }
  4480. }
  4481. if (vectors > 0 && vectors < I40E_MIN_MSIX) {
  4482. dev_info(&pf->pdev->dev,
  4483. "Couldn't get enough vectors, only %d available\n",
  4484. vectors);
  4485. vectors = 0;
  4486. }
  4487. return vectors;
  4488. }
  4489. /**
  4490. * i40e_init_msix - Setup the MSIX capability
  4491. * @pf: board private structure
  4492. *
  4493. * Work with the OS to set up the MSIX vectors needed.
  4494. *
  4495. * Returns 0 on success, negative on failure
  4496. **/
  4497. static int i40e_init_msix(struct i40e_pf *pf)
  4498. {
  4499. i40e_status err = 0;
  4500. struct i40e_hw *hw = &pf->hw;
  4501. int v_budget, i;
  4502. int vec;
  4503. if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
  4504. return -ENODEV;
  4505. /* The number of vectors we'll request will be comprised of:
  4506. * - Add 1 for "other" cause for Admin Queue events, etc.
  4507. * - The number of LAN queue pairs
  4508. * already adjusted for the NUMA node
  4509. * assumes symmetric Tx/Rx pairing
  4510. * - The number of VMDq pairs
  4511. * Once we count this up, try the request.
  4512. *
  4513. * If we can't get what we want, we'll simplify to nearly nothing
  4514. * and try again. If that still fails, we punt.
  4515. */
  4516. pf->num_lan_msix = pf->num_lan_qps;
  4517. pf->num_vmdq_msix = pf->num_vmdq_qps;
  4518. v_budget = 1 + pf->num_lan_msix;
  4519. v_budget += (pf->num_vmdq_vsis * pf->num_vmdq_msix);
  4520. if (pf->flags & I40E_FLAG_FDIR_ENABLED)
  4521. v_budget++;
  4522. /* Scale down if necessary, and the rings will share vectors */
  4523. v_budget = min_t(int, v_budget, hw->func_caps.num_msix_vectors);
  4524. pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
  4525. GFP_KERNEL);
  4526. if (!pf->msix_entries)
  4527. return -ENOMEM;
  4528. for (i = 0; i < v_budget; i++)
  4529. pf->msix_entries[i].entry = i;
  4530. vec = i40e_reserve_msix_vectors(pf, v_budget);
  4531. if (vec < I40E_MIN_MSIX) {
  4532. pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
  4533. kfree(pf->msix_entries);
  4534. pf->msix_entries = NULL;
  4535. return -ENODEV;
  4536. } else if (vec == I40E_MIN_MSIX) {
  4537. /* Adjust for minimal MSIX use */
  4538. dev_info(&pf->pdev->dev, "Features disabled, not enough MSIX vectors\n");
  4539. pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
  4540. pf->num_vmdq_vsis = 0;
  4541. pf->num_vmdq_qps = 0;
  4542. pf->num_vmdq_msix = 0;
  4543. pf->num_lan_qps = 1;
  4544. pf->num_lan_msix = 1;
  4545. } else if (vec != v_budget) {
  4546. /* Scale vector usage down */
  4547. pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
  4548. vec--; /* reserve the misc vector */
  4549. /* partition out the remaining vectors */
  4550. switch (vec) {
  4551. case 2:
  4552. pf->num_vmdq_vsis = 1;
  4553. pf->num_lan_msix = 1;
  4554. break;
  4555. case 3:
  4556. pf->num_vmdq_vsis = 1;
  4557. pf->num_lan_msix = 2;
  4558. break;
  4559. default:
  4560. pf->num_lan_msix = min_t(int, (vec / 2),
  4561. pf->num_lan_qps);
  4562. pf->num_vmdq_vsis = min_t(int, (vec - pf->num_lan_msix),
  4563. I40E_DEFAULT_NUM_VMDQ_VSI);
  4564. break;
  4565. }
  4566. }
  4567. return err;
  4568. }
  4569. /**
  4570. * i40e_alloc_q_vectors - Allocate memory for interrupt vectors
  4571. * @vsi: the VSI being configured
  4572. *
  4573. * We allocate one q_vector per queue interrupt. If allocation fails we
  4574. * return -ENOMEM.
  4575. **/
  4576. static int i40e_alloc_q_vectors(struct i40e_vsi *vsi)
  4577. {
  4578. struct i40e_pf *pf = vsi->back;
  4579. int v_idx, num_q_vectors;
  4580. /* if not MSIX, give the one vector only to the LAN VSI */
  4581. if (pf->flags & I40E_FLAG_MSIX_ENABLED)
  4582. num_q_vectors = vsi->num_q_vectors;
  4583. else if (vsi == pf->vsi[pf->lan_vsi])
  4584. num_q_vectors = 1;
  4585. else
  4586. return -EINVAL;
  4587. vsi->q_vectors = kcalloc(num_q_vectors,
  4588. sizeof(struct i40e_q_vector),
  4589. GFP_KERNEL);
  4590. if (!vsi->q_vectors)
  4591. return -ENOMEM;
  4592. for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
  4593. vsi->q_vectors[v_idx].vsi = vsi;
  4594. vsi->q_vectors[v_idx].v_idx = v_idx;
  4595. cpumask_set_cpu(v_idx, &vsi->q_vectors[v_idx].affinity_mask);
  4596. if (vsi->netdev)
  4597. netif_napi_add(vsi->netdev, &vsi->q_vectors[v_idx].napi,
  4598. i40e_napi_poll, vsi->work_limit);
  4599. }
  4600. return 0;
  4601. }
  4602. /**
  4603. * i40e_init_interrupt_scheme - Determine proper interrupt scheme
  4604. * @pf: board private structure to initialize
  4605. **/
  4606. static void i40e_init_interrupt_scheme(struct i40e_pf *pf)
  4607. {
  4608. int err = 0;
  4609. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  4610. err = i40e_init_msix(pf);
  4611. if (err) {
  4612. pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
  4613. I40E_FLAG_MQ_ENABLED |
  4614. I40E_FLAG_DCB_ENABLED |
  4615. I40E_FLAG_SRIOV_ENABLED |
  4616. I40E_FLAG_FDIR_ENABLED |
  4617. I40E_FLAG_FDIR_ATR_ENABLED |
  4618. I40E_FLAG_VMDQ_ENABLED);
  4619. /* rework the queue expectations without MSIX */
  4620. i40e_determine_queue_usage(pf);
  4621. }
  4622. }
  4623. if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
  4624. (pf->flags & I40E_FLAG_MSI_ENABLED)) {
  4625. err = pci_enable_msi(pf->pdev);
  4626. if (err) {
  4627. dev_info(&pf->pdev->dev,
  4628. "MSI init failed (%d), trying legacy.\n", err);
  4629. pf->flags &= ~I40E_FLAG_MSI_ENABLED;
  4630. }
  4631. }
  4632. /* track first vector for misc interrupts */
  4633. err = i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT-1);
  4634. }
  4635. /**
  4636. * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
  4637. * @pf: board private structure
  4638. *
  4639. * This sets up the handler for MSIX 0, which is used to manage the
  4640. * non-queue interrupts, e.g. AdminQ and errors. This is not used
  4641. * when in MSI or Legacy interrupt mode.
  4642. **/
  4643. static int i40e_setup_misc_vector(struct i40e_pf *pf)
  4644. {
  4645. struct i40e_hw *hw = &pf->hw;
  4646. int err = 0;
  4647. /* Only request the irq if this is the first time through, and
  4648. * not when we're rebuilding after a Reset
  4649. */
  4650. if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
  4651. err = request_irq(pf->msix_entries[0].vector,
  4652. i40e_intr, 0, pf->misc_int_name, pf);
  4653. if (err) {
  4654. dev_info(&pf->pdev->dev,
  4655. "request_irq for msix_misc failed: %d\n", err);
  4656. return -EFAULT;
  4657. }
  4658. }
  4659. i40e_enable_misc_int_causes(hw);
  4660. /* associate no queues to the misc vector */
  4661. wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
  4662. wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
  4663. i40e_flush(hw);
  4664. i40e_irq_dynamic_enable_icr0(pf);
  4665. return err;
  4666. }
  4667. /**
  4668. * i40e_config_rss - Prepare for RSS if used
  4669. * @pf: board private structure
  4670. **/
  4671. static int i40e_config_rss(struct i40e_pf *pf)
  4672. {
  4673. struct i40e_hw *hw = &pf->hw;
  4674. u32 lut = 0;
  4675. int i, j;
  4676. u64 hena;
  4677. /* Set of random keys generated using kernel random number generator */
  4678. static const u32 seed[I40E_PFQF_HKEY_MAX_INDEX + 1] = {0x41b01687,
  4679. 0x183cfd8c, 0xce880440, 0x580cbc3c, 0x35897377,
  4680. 0x328b25e1, 0x4fa98922, 0xb7d90c14, 0xd5bad70d,
  4681. 0xcd15a2c1, 0xe8580225, 0x4a1e9d11, 0xfe5731be};
  4682. /* Fill out hash function seed */
  4683. for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
  4684. wr32(hw, I40E_PFQF_HKEY(i), seed[i]);
  4685. /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
  4686. hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
  4687. ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
  4688. hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
  4689. ((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
  4690. ((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) |
  4691. ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
  4692. ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
  4693. ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
  4694. ((u64)1 << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
  4695. ((u64)1 << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) |
  4696. ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4)|
  4697. ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6);
  4698. wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
  4699. wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
  4700. /* Populate the LUT with max no. of queues in round robin fashion */
  4701. for (i = 0, j = 0; i < pf->hw.func_caps.rss_table_size; i++, j++) {
  4702. /* The assumption is that lan qp count will be the highest
  4703. * qp count for any PF VSI that needs RSS.
  4704. * If multiple VSIs need RSS support, all the qp counts
  4705. * for those VSIs should be a power of 2 for RSS to work.
  4706. * If LAN VSI is the only consumer for RSS then this requirement
  4707. * is not necessary.
  4708. */
  4709. if (j == pf->rss_size)
  4710. j = 0;
  4711. /* lut = 4-byte sliding window of 4 lut entries */
  4712. lut = (lut << 8) | (j &
  4713. ((0x1 << pf->hw.func_caps.rss_table_entry_width) - 1));
  4714. /* On i = 3, we have 4 entries in lut; write to the register */
  4715. if ((i & 3) == 3)
  4716. wr32(hw, I40E_PFQF_HLUT(i >> 2), lut);
  4717. }
  4718. i40e_flush(hw);
  4719. return 0;
  4720. }
  4721. /**
  4722. * i40e_sw_init - Initialize general software structures (struct i40e_pf)
  4723. * @pf: board private structure to initialize
  4724. *
  4725. * i40e_sw_init initializes the Adapter private data structure.
  4726. * Fields are initialized based on PCI device information and
  4727. * OS network device settings (MTU size).
  4728. **/
  4729. static int i40e_sw_init(struct i40e_pf *pf)
  4730. {
  4731. int err = 0;
  4732. int size;
  4733. pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
  4734. (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
  4735. if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
  4736. if (I40E_DEBUG_USER & debug)
  4737. pf->hw.debug_mask = debug;
  4738. pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
  4739. I40E_DEFAULT_MSG_ENABLE);
  4740. }
  4741. /* Set default capability flags */
  4742. pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
  4743. I40E_FLAG_MSI_ENABLED |
  4744. I40E_FLAG_MSIX_ENABLED |
  4745. I40E_FLAG_RX_PS_ENABLED |
  4746. I40E_FLAG_MQ_ENABLED |
  4747. I40E_FLAG_RX_1BUF_ENABLED;
  4748. pf->rss_size_max = 0x1 << pf->hw.func_caps.rss_table_entry_width;
  4749. if (pf->hw.func_caps.rss) {
  4750. pf->flags |= I40E_FLAG_RSS_ENABLED;
  4751. pf->rss_size = min_t(int, pf->rss_size_max,
  4752. nr_cpus_node(numa_node_id()));
  4753. } else {
  4754. pf->rss_size = 1;
  4755. }
  4756. if (pf->hw.func_caps.dcb)
  4757. pf->num_tc_qps = I40E_DEFAULT_QUEUES_PER_TC;
  4758. else
  4759. pf->num_tc_qps = 0;
  4760. if (pf->hw.func_caps.fd) {
  4761. /* FW/NVM is not yet fixed in this regard */
  4762. if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
  4763. (pf->hw.func_caps.fd_filters_best_effort > 0)) {
  4764. pf->flags |= I40E_FLAG_FDIR_ATR_ENABLED;
  4765. dev_info(&pf->pdev->dev,
  4766. "Flow Director ATR mode Enabled\n");
  4767. pf->flags |= I40E_FLAG_FDIR_ENABLED;
  4768. dev_info(&pf->pdev->dev,
  4769. "Flow Director Side Band mode Enabled\n");
  4770. pf->fdir_pf_filter_count =
  4771. pf->hw.func_caps.fd_filters_guaranteed;
  4772. }
  4773. } else {
  4774. pf->fdir_pf_filter_count = 0;
  4775. }
  4776. if (pf->hw.func_caps.vmdq) {
  4777. pf->flags |= I40E_FLAG_VMDQ_ENABLED;
  4778. pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
  4779. pf->num_vmdq_qps = I40E_DEFAULT_QUEUES_PER_VMDQ;
  4780. }
  4781. /* MFP mode enabled */
  4782. if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.mfp_mode_1) {
  4783. pf->flags |= I40E_FLAG_MFP_ENABLED;
  4784. dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
  4785. }
  4786. #ifdef CONFIG_PCI_IOV
  4787. if (pf->hw.func_caps.num_vfs) {
  4788. pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
  4789. pf->flags |= I40E_FLAG_SRIOV_ENABLED;
  4790. pf->num_req_vfs = min_t(int,
  4791. pf->hw.func_caps.num_vfs,
  4792. I40E_MAX_VF_COUNT);
  4793. }
  4794. #endif /* CONFIG_PCI_IOV */
  4795. pf->eeprom_version = 0xDEAD;
  4796. pf->lan_veb = I40E_NO_VEB;
  4797. pf->lan_vsi = I40E_NO_VSI;
  4798. /* set up queue assignment tracking */
  4799. size = sizeof(struct i40e_lump_tracking)
  4800. + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
  4801. pf->qp_pile = kzalloc(size, GFP_KERNEL);
  4802. if (!pf->qp_pile) {
  4803. err = -ENOMEM;
  4804. goto sw_init_done;
  4805. }
  4806. pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
  4807. pf->qp_pile->search_hint = 0;
  4808. /* set up vector assignment tracking */
  4809. size = sizeof(struct i40e_lump_tracking)
  4810. + (sizeof(u16) * pf->hw.func_caps.num_msix_vectors);
  4811. pf->irq_pile = kzalloc(size, GFP_KERNEL);
  4812. if (!pf->irq_pile) {
  4813. kfree(pf->qp_pile);
  4814. err = -ENOMEM;
  4815. goto sw_init_done;
  4816. }
  4817. pf->irq_pile->num_entries = pf->hw.func_caps.num_msix_vectors;
  4818. pf->irq_pile->search_hint = 0;
  4819. mutex_init(&pf->switch_mutex);
  4820. sw_init_done:
  4821. return err;
  4822. }
  4823. /**
  4824. * i40e_set_features - set the netdev feature flags
  4825. * @netdev: ptr to the netdev being adjusted
  4826. * @features: the feature set that the stack is suggesting
  4827. **/
  4828. static int i40e_set_features(struct net_device *netdev,
  4829. netdev_features_t features)
  4830. {
  4831. struct i40e_netdev_priv *np = netdev_priv(netdev);
  4832. struct i40e_vsi *vsi = np->vsi;
  4833. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  4834. i40e_vlan_stripping_enable(vsi);
  4835. else
  4836. i40e_vlan_stripping_disable(vsi);
  4837. return 0;
  4838. }
  4839. static const struct net_device_ops i40e_netdev_ops = {
  4840. .ndo_open = i40e_open,
  4841. .ndo_stop = i40e_close,
  4842. .ndo_start_xmit = i40e_lan_xmit_frame,
  4843. .ndo_get_stats64 = i40e_get_netdev_stats_struct,
  4844. .ndo_set_rx_mode = i40e_set_rx_mode,
  4845. .ndo_validate_addr = eth_validate_addr,
  4846. .ndo_set_mac_address = i40e_set_mac,
  4847. .ndo_change_mtu = i40e_change_mtu,
  4848. .ndo_tx_timeout = i40e_tx_timeout,
  4849. .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
  4850. .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
  4851. #ifdef CONFIG_NET_POLL_CONTROLLER
  4852. .ndo_poll_controller = i40e_netpoll,
  4853. #endif
  4854. .ndo_setup_tc = i40e_setup_tc,
  4855. .ndo_set_features = i40e_set_features,
  4856. .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
  4857. .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
  4858. .ndo_set_vf_tx_rate = i40e_ndo_set_vf_bw,
  4859. .ndo_get_vf_config = i40e_ndo_get_vf_config,
  4860. };
  4861. /**
  4862. * i40e_config_netdev - Setup the netdev flags
  4863. * @vsi: the VSI being configured
  4864. *
  4865. * Returns 0 on success, negative value on failure
  4866. **/
  4867. static int i40e_config_netdev(struct i40e_vsi *vsi)
  4868. {
  4869. struct i40e_pf *pf = vsi->back;
  4870. struct i40e_hw *hw = &pf->hw;
  4871. struct i40e_netdev_priv *np;
  4872. struct net_device *netdev;
  4873. u8 mac_addr[ETH_ALEN];
  4874. int etherdev_size;
  4875. etherdev_size = sizeof(struct i40e_netdev_priv);
  4876. netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
  4877. if (!netdev)
  4878. return -ENOMEM;
  4879. vsi->netdev = netdev;
  4880. np = netdev_priv(netdev);
  4881. np->vsi = vsi;
  4882. netdev->hw_enc_features = NETIF_F_IP_CSUM |
  4883. NETIF_F_GSO_UDP_TUNNEL |
  4884. NETIF_F_TSO |
  4885. NETIF_F_SG;
  4886. netdev->features = NETIF_F_SG |
  4887. NETIF_F_IP_CSUM |
  4888. NETIF_F_SCTP_CSUM |
  4889. NETIF_F_HIGHDMA |
  4890. NETIF_F_GSO_UDP_TUNNEL |
  4891. NETIF_F_HW_VLAN_CTAG_TX |
  4892. NETIF_F_HW_VLAN_CTAG_RX |
  4893. NETIF_F_HW_VLAN_CTAG_FILTER |
  4894. NETIF_F_IPV6_CSUM |
  4895. NETIF_F_TSO |
  4896. NETIF_F_TSO6 |
  4897. NETIF_F_RXCSUM |
  4898. NETIF_F_RXHASH |
  4899. 0;
  4900. /* copy netdev features into list of user selectable features */
  4901. netdev->hw_features |= netdev->features;
  4902. if (vsi->type == I40E_VSI_MAIN) {
  4903. SET_NETDEV_DEV(netdev, &pf->pdev->dev);
  4904. memcpy(mac_addr, hw->mac.perm_addr, ETH_ALEN);
  4905. } else {
  4906. /* relate the VSI_VMDQ name to the VSI_MAIN name */
  4907. snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
  4908. pf->vsi[pf->lan_vsi]->netdev->name);
  4909. random_ether_addr(mac_addr);
  4910. i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
  4911. }
  4912. memcpy(netdev->dev_addr, mac_addr, ETH_ALEN);
  4913. memcpy(netdev->perm_addr, mac_addr, ETH_ALEN);
  4914. /* vlan gets same features (except vlan offload)
  4915. * after any tweaks for specific VSI types
  4916. */
  4917. netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
  4918. NETIF_F_HW_VLAN_CTAG_RX |
  4919. NETIF_F_HW_VLAN_CTAG_FILTER);
  4920. netdev->priv_flags |= IFF_UNICAST_FLT;
  4921. netdev->priv_flags |= IFF_SUPP_NOFCS;
  4922. /* Setup netdev TC information */
  4923. i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
  4924. netdev->netdev_ops = &i40e_netdev_ops;
  4925. netdev->watchdog_timeo = 5 * HZ;
  4926. i40e_set_ethtool_ops(netdev);
  4927. return 0;
  4928. }
  4929. /**
  4930. * i40e_vsi_delete - Delete a VSI from the switch
  4931. * @vsi: the VSI being removed
  4932. *
  4933. * Returns 0 on success, negative value on failure
  4934. **/
  4935. static void i40e_vsi_delete(struct i40e_vsi *vsi)
  4936. {
  4937. /* remove default VSI is not allowed */
  4938. if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
  4939. return;
  4940. /* there is no HW VSI for FDIR */
  4941. if (vsi->type == I40E_VSI_FDIR)
  4942. return;
  4943. i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
  4944. return;
  4945. }
  4946. /**
  4947. * i40e_add_vsi - Add a VSI to the switch
  4948. * @vsi: the VSI being configured
  4949. *
  4950. * This initializes a VSI context depending on the VSI type to be added and
  4951. * passes it down to the add_vsi aq command.
  4952. **/
  4953. static int i40e_add_vsi(struct i40e_vsi *vsi)
  4954. {
  4955. int ret = -ENODEV;
  4956. struct i40e_mac_filter *f, *ftmp;
  4957. struct i40e_pf *pf = vsi->back;
  4958. struct i40e_hw *hw = &pf->hw;
  4959. struct i40e_vsi_context ctxt;
  4960. u8 enabled_tc = 0x1; /* TC0 enabled */
  4961. int f_count = 0;
  4962. memset(&ctxt, 0, sizeof(ctxt));
  4963. switch (vsi->type) {
  4964. case I40E_VSI_MAIN:
  4965. /* The PF's main VSI is already setup as part of the
  4966. * device initialization, so we'll not bother with
  4967. * the add_vsi call, but we will retrieve the current
  4968. * VSI context.
  4969. */
  4970. ctxt.seid = pf->main_vsi_seid;
  4971. ctxt.pf_num = pf->hw.pf_id;
  4972. ctxt.vf_num = 0;
  4973. ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
  4974. ctxt.flags = I40E_AQ_VSI_TYPE_PF;
  4975. if (ret) {
  4976. dev_info(&pf->pdev->dev,
  4977. "couldn't get pf vsi config, err %d, aq_err %d\n",
  4978. ret, pf->hw.aq.asq_last_status);
  4979. return -ENOENT;
  4980. }
  4981. memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
  4982. vsi->info.valid_sections = 0;
  4983. vsi->seid = ctxt.seid;
  4984. vsi->id = ctxt.vsi_number;
  4985. enabled_tc = i40e_pf_get_tc_map(pf);
  4986. /* MFP mode setup queue map and update VSI */
  4987. if (pf->flags & I40E_FLAG_MFP_ENABLED) {
  4988. memset(&ctxt, 0, sizeof(ctxt));
  4989. ctxt.seid = pf->main_vsi_seid;
  4990. ctxt.pf_num = pf->hw.pf_id;
  4991. ctxt.vf_num = 0;
  4992. i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
  4993. ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
  4994. if (ret) {
  4995. dev_info(&pf->pdev->dev,
  4996. "update vsi failed, aq_err=%d\n",
  4997. pf->hw.aq.asq_last_status);
  4998. ret = -ENOENT;
  4999. goto err;
  5000. }
  5001. /* update the local VSI info queue map */
  5002. i40e_vsi_update_queue_map(vsi, &ctxt);
  5003. vsi->info.valid_sections = 0;
  5004. } else {
  5005. /* Default/Main VSI is only enabled for TC0
  5006. * reconfigure it to enable all TCs that are
  5007. * available on the port in SFP mode.
  5008. */
  5009. ret = i40e_vsi_config_tc(vsi, enabled_tc);
  5010. if (ret) {
  5011. dev_info(&pf->pdev->dev,
  5012. "failed to configure TCs for main VSI tc_map 0x%08x, err %d, aq_err %d\n",
  5013. enabled_tc, ret,
  5014. pf->hw.aq.asq_last_status);
  5015. ret = -ENOENT;
  5016. }
  5017. }
  5018. break;
  5019. case I40E_VSI_FDIR:
  5020. /* no queue mapping or actual HW VSI needed */
  5021. vsi->info.valid_sections = 0;
  5022. vsi->seid = 0;
  5023. vsi->id = 0;
  5024. i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
  5025. return 0;
  5026. break;
  5027. case I40E_VSI_VMDQ2:
  5028. ctxt.pf_num = hw->pf_id;
  5029. ctxt.vf_num = 0;
  5030. ctxt.uplink_seid = vsi->uplink_seid;
  5031. ctxt.connection_type = 0x1; /* regular data port */
  5032. ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
  5033. ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
  5034. /* This VSI is connected to VEB so the switch_id
  5035. * should be set to zero by default.
  5036. */
  5037. ctxt.info.switch_id = 0;
  5038. ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
  5039. ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
  5040. /* Setup the VSI tx/rx queue map for TC0 only for now */
  5041. i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
  5042. break;
  5043. case I40E_VSI_SRIOV:
  5044. ctxt.pf_num = hw->pf_id;
  5045. ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
  5046. ctxt.uplink_seid = vsi->uplink_seid;
  5047. ctxt.connection_type = 0x1; /* regular data port */
  5048. ctxt.flags = I40E_AQ_VSI_TYPE_VF;
  5049. ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
  5050. /* This VSI is connected to VEB so the switch_id
  5051. * should be set to zero by default.
  5052. */
  5053. ctxt.info.switch_id = cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
  5054. ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
  5055. ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
  5056. /* Setup the VSI tx/rx queue map for TC0 only for now */
  5057. i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
  5058. break;
  5059. default:
  5060. return -ENODEV;
  5061. }
  5062. if (vsi->type != I40E_VSI_MAIN) {
  5063. ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
  5064. if (ret) {
  5065. dev_info(&vsi->back->pdev->dev,
  5066. "add vsi failed, aq_err=%d\n",
  5067. vsi->back->hw.aq.asq_last_status);
  5068. ret = -ENOENT;
  5069. goto err;
  5070. }
  5071. memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
  5072. vsi->info.valid_sections = 0;
  5073. vsi->seid = ctxt.seid;
  5074. vsi->id = ctxt.vsi_number;
  5075. }
  5076. /* If macvlan filters already exist, force them to get loaded */
  5077. list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
  5078. f->changed = true;
  5079. f_count++;
  5080. }
  5081. if (f_count) {
  5082. vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
  5083. pf->flags |= I40E_FLAG_FILTER_SYNC;
  5084. }
  5085. /* Update VSI BW information */
  5086. ret = i40e_vsi_get_bw_info(vsi);
  5087. if (ret) {
  5088. dev_info(&pf->pdev->dev,
  5089. "couldn't get vsi bw info, err %d, aq_err %d\n",
  5090. ret, pf->hw.aq.asq_last_status);
  5091. /* VSI is already added so not tearing that up */
  5092. ret = 0;
  5093. }
  5094. err:
  5095. return ret;
  5096. }
  5097. /**
  5098. * i40e_vsi_release - Delete a VSI and free its resources
  5099. * @vsi: the VSI being removed
  5100. *
  5101. * Returns 0 on success or < 0 on error
  5102. **/
  5103. int i40e_vsi_release(struct i40e_vsi *vsi)
  5104. {
  5105. struct i40e_mac_filter *f, *ftmp;
  5106. struct i40e_veb *veb = NULL;
  5107. struct i40e_pf *pf;
  5108. u16 uplink_seid;
  5109. int i, n;
  5110. pf = vsi->back;
  5111. /* release of a VEB-owner or last VSI is not allowed */
  5112. if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
  5113. dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
  5114. vsi->seid, vsi->uplink_seid);
  5115. return -ENODEV;
  5116. }
  5117. if (vsi == pf->vsi[pf->lan_vsi] &&
  5118. !test_bit(__I40E_DOWN, &pf->state)) {
  5119. dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
  5120. return -ENODEV;
  5121. }
  5122. uplink_seid = vsi->uplink_seid;
  5123. if (vsi->type != I40E_VSI_SRIOV) {
  5124. if (vsi->netdev_registered) {
  5125. vsi->netdev_registered = false;
  5126. if (vsi->netdev) {
  5127. /* results in a call to i40e_close() */
  5128. unregister_netdev(vsi->netdev);
  5129. free_netdev(vsi->netdev);
  5130. vsi->netdev = NULL;
  5131. }
  5132. } else {
  5133. if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
  5134. i40e_down(vsi);
  5135. i40e_vsi_free_irq(vsi);
  5136. i40e_vsi_free_tx_resources(vsi);
  5137. i40e_vsi_free_rx_resources(vsi);
  5138. }
  5139. i40e_vsi_disable_irq(vsi);
  5140. }
  5141. list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
  5142. i40e_del_filter(vsi, f->macaddr, f->vlan,
  5143. f->is_vf, f->is_netdev);
  5144. i40e_sync_vsi_filters(vsi);
  5145. i40e_vsi_delete(vsi);
  5146. i40e_vsi_free_q_vectors(vsi);
  5147. i40e_vsi_clear_rings(vsi);
  5148. i40e_vsi_clear(vsi);
  5149. /* If this was the last thing on the VEB, except for the
  5150. * controlling VSI, remove the VEB, which puts the controlling
  5151. * VSI onto the next level down in the switch.
  5152. *
  5153. * Well, okay, there's one more exception here: don't remove
  5154. * the orphan VEBs yet. We'll wait for an explicit remove request
  5155. * from up the network stack.
  5156. */
  5157. for (n = 0, i = 0; i < pf->hw.func_caps.num_vsis; i++) {
  5158. if (pf->vsi[i] &&
  5159. pf->vsi[i]->uplink_seid == uplink_seid &&
  5160. (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
  5161. n++; /* count the VSIs */
  5162. }
  5163. }
  5164. for (i = 0; i < I40E_MAX_VEB; i++) {
  5165. if (!pf->veb[i])
  5166. continue;
  5167. if (pf->veb[i]->uplink_seid == uplink_seid)
  5168. n++; /* count the VEBs */
  5169. if (pf->veb[i]->seid == uplink_seid)
  5170. veb = pf->veb[i];
  5171. }
  5172. if (n == 0 && veb && veb->uplink_seid != 0)
  5173. i40e_veb_release(veb);
  5174. return 0;
  5175. }
  5176. /**
  5177. * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
  5178. * @vsi: ptr to the VSI
  5179. *
  5180. * This should only be called after i40e_vsi_mem_alloc() which allocates the
  5181. * corresponding SW VSI structure and initializes num_queue_pairs for the
  5182. * newly allocated VSI.
  5183. *
  5184. * Returns 0 on success or negative on failure
  5185. **/
  5186. static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
  5187. {
  5188. int ret = -ENOENT;
  5189. struct i40e_pf *pf = vsi->back;
  5190. if (vsi->q_vectors) {
  5191. dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
  5192. vsi->seid);
  5193. return -EEXIST;
  5194. }
  5195. if (vsi->base_vector) {
  5196. dev_info(&pf->pdev->dev,
  5197. "VSI %d has non-zero base vector %d\n",
  5198. vsi->seid, vsi->base_vector);
  5199. return -EEXIST;
  5200. }
  5201. ret = i40e_alloc_q_vectors(vsi);
  5202. if (ret) {
  5203. dev_info(&pf->pdev->dev,
  5204. "failed to allocate %d q_vector for VSI %d, ret=%d\n",
  5205. vsi->num_q_vectors, vsi->seid, ret);
  5206. vsi->num_q_vectors = 0;
  5207. goto vector_setup_out;
  5208. }
  5209. vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
  5210. vsi->num_q_vectors, vsi->idx);
  5211. if (vsi->base_vector < 0) {
  5212. dev_info(&pf->pdev->dev,
  5213. "failed to get q tracking for VSI %d, err=%d\n",
  5214. vsi->seid, vsi->base_vector);
  5215. i40e_vsi_free_q_vectors(vsi);
  5216. ret = -ENOENT;
  5217. goto vector_setup_out;
  5218. }
  5219. vector_setup_out:
  5220. return ret;
  5221. }
  5222. /**
  5223. * i40e_vsi_setup - Set up a VSI by a given type
  5224. * @pf: board private structure
  5225. * @type: VSI type
  5226. * @uplink_seid: the switch element to link to
  5227. * @param1: usage depends upon VSI type. For VF types, indicates VF id
  5228. *
  5229. * This allocates the sw VSI structure and its queue resources, then add a VSI
  5230. * to the identified VEB.
  5231. *
  5232. * Returns pointer to the successfully allocated and configure VSI sw struct on
  5233. * success, otherwise returns NULL on failure.
  5234. **/
  5235. struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
  5236. u16 uplink_seid, u32 param1)
  5237. {
  5238. struct i40e_vsi *vsi = NULL;
  5239. struct i40e_veb *veb = NULL;
  5240. int ret, i;
  5241. int v_idx;
  5242. /* The requested uplink_seid must be either
  5243. * - the PF's port seid
  5244. * no VEB is needed because this is the PF
  5245. * or this is a Flow Director special case VSI
  5246. * - seid of an existing VEB
  5247. * - seid of a VSI that owns an existing VEB
  5248. * - seid of a VSI that doesn't own a VEB
  5249. * a new VEB is created and the VSI becomes the owner
  5250. * - seid of the PF VSI, which is what creates the first VEB
  5251. * this is a special case of the previous
  5252. *
  5253. * Find which uplink_seid we were given and create a new VEB if needed
  5254. */
  5255. for (i = 0; i < I40E_MAX_VEB; i++) {
  5256. if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
  5257. veb = pf->veb[i];
  5258. break;
  5259. }
  5260. }
  5261. if (!veb && uplink_seid != pf->mac_seid) {
  5262. for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
  5263. if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
  5264. vsi = pf->vsi[i];
  5265. break;
  5266. }
  5267. }
  5268. if (!vsi) {
  5269. dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
  5270. uplink_seid);
  5271. return NULL;
  5272. }
  5273. if (vsi->uplink_seid == pf->mac_seid)
  5274. veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
  5275. vsi->tc_config.enabled_tc);
  5276. else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
  5277. veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
  5278. vsi->tc_config.enabled_tc);
  5279. for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
  5280. if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
  5281. veb = pf->veb[i];
  5282. }
  5283. if (!veb) {
  5284. dev_info(&pf->pdev->dev, "couldn't add VEB\n");
  5285. return NULL;
  5286. }
  5287. vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
  5288. uplink_seid = veb->seid;
  5289. }
  5290. /* get vsi sw struct */
  5291. v_idx = i40e_vsi_mem_alloc(pf, type);
  5292. if (v_idx < 0)
  5293. goto err_alloc;
  5294. vsi = pf->vsi[v_idx];
  5295. vsi->type = type;
  5296. vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
  5297. if (type == I40E_VSI_MAIN)
  5298. pf->lan_vsi = v_idx;
  5299. else if (type == I40E_VSI_SRIOV)
  5300. vsi->vf_id = param1;
  5301. /* assign it some queues */
  5302. ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
  5303. if (ret < 0) {
  5304. dev_info(&pf->pdev->dev, "VSI %d get_lump failed %d\n",
  5305. vsi->seid, ret);
  5306. goto err_vsi;
  5307. }
  5308. vsi->base_queue = ret;
  5309. /* get a VSI from the hardware */
  5310. vsi->uplink_seid = uplink_seid;
  5311. ret = i40e_add_vsi(vsi);
  5312. if (ret)
  5313. goto err_vsi;
  5314. switch (vsi->type) {
  5315. /* setup the netdev if needed */
  5316. case I40E_VSI_MAIN:
  5317. case I40E_VSI_VMDQ2:
  5318. ret = i40e_config_netdev(vsi);
  5319. if (ret)
  5320. goto err_netdev;
  5321. ret = register_netdev(vsi->netdev);
  5322. if (ret)
  5323. goto err_netdev;
  5324. vsi->netdev_registered = true;
  5325. netif_carrier_off(vsi->netdev);
  5326. /* fall through */
  5327. case I40E_VSI_FDIR:
  5328. /* set up vectors and rings if needed */
  5329. ret = i40e_vsi_setup_vectors(vsi);
  5330. if (ret)
  5331. goto err_msix;
  5332. ret = i40e_alloc_rings(vsi);
  5333. if (ret)
  5334. goto err_rings;
  5335. /* map all of the rings to the q_vectors */
  5336. i40e_vsi_map_rings_to_vectors(vsi);
  5337. i40e_vsi_reset_stats(vsi);
  5338. break;
  5339. default:
  5340. /* no netdev or rings for the other VSI types */
  5341. break;
  5342. }
  5343. return vsi;
  5344. err_rings:
  5345. i40e_vsi_free_q_vectors(vsi);
  5346. err_msix:
  5347. if (vsi->netdev_registered) {
  5348. vsi->netdev_registered = false;
  5349. unregister_netdev(vsi->netdev);
  5350. free_netdev(vsi->netdev);
  5351. vsi->netdev = NULL;
  5352. }
  5353. err_netdev:
  5354. i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
  5355. err_vsi:
  5356. i40e_vsi_clear(vsi);
  5357. err_alloc:
  5358. return NULL;
  5359. }
  5360. /**
  5361. * i40e_veb_get_bw_info - Query VEB BW information
  5362. * @veb: the veb to query
  5363. *
  5364. * Query the Tx scheduler BW configuration data for given VEB
  5365. **/
  5366. static int i40e_veb_get_bw_info(struct i40e_veb *veb)
  5367. {
  5368. struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
  5369. struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
  5370. struct i40e_pf *pf = veb->pf;
  5371. struct i40e_hw *hw = &pf->hw;
  5372. u32 tc_bw_max;
  5373. int ret = 0;
  5374. int i;
  5375. ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
  5376. &bw_data, NULL);
  5377. if (ret) {
  5378. dev_info(&pf->pdev->dev,
  5379. "query veb bw config failed, aq_err=%d\n",
  5380. hw->aq.asq_last_status);
  5381. goto out;
  5382. }
  5383. ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
  5384. &ets_data, NULL);
  5385. if (ret) {
  5386. dev_info(&pf->pdev->dev,
  5387. "query veb bw ets config failed, aq_err=%d\n",
  5388. hw->aq.asq_last_status);
  5389. goto out;
  5390. }
  5391. veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
  5392. veb->bw_max_quanta = ets_data.tc_bw_max;
  5393. veb->is_abs_credits = bw_data.absolute_credits_enable;
  5394. tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
  5395. (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
  5396. for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
  5397. veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
  5398. veb->bw_tc_limit_credits[i] =
  5399. le16_to_cpu(bw_data.tc_bw_limits[i]);
  5400. veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
  5401. }
  5402. out:
  5403. return ret;
  5404. }
  5405. /**
  5406. * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
  5407. * @pf: board private structure
  5408. *
  5409. * On error: returns error code (negative)
  5410. * On success: returns vsi index in PF (positive)
  5411. **/
  5412. static int i40e_veb_mem_alloc(struct i40e_pf *pf)
  5413. {
  5414. int ret = -ENOENT;
  5415. struct i40e_veb *veb;
  5416. int i;
  5417. /* Need to protect the allocation of switch elements at the PF level */
  5418. mutex_lock(&pf->switch_mutex);
  5419. /* VEB list may be fragmented if VEB creation/destruction has
  5420. * been happening. We can afford to do a quick scan to look
  5421. * for any free slots in the list.
  5422. *
  5423. * find next empty veb slot, looping back around if necessary
  5424. */
  5425. i = 0;
  5426. while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
  5427. i++;
  5428. if (i >= I40E_MAX_VEB) {
  5429. ret = -ENOMEM;
  5430. goto err_alloc_veb; /* out of VEB slots! */
  5431. }
  5432. veb = kzalloc(sizeof(*veb), GFP_KERNEL);
  5433. if (!veb) {
  5434. ret = -ENOMEM;
  5435. goto err_alloc_veb;
  5436. }
  5437. veb->pf = pf;
  5438. veb->idx = i;
  5439. veb->enabled_tc = 1;
  5440. pf->veb[i] = veb;
  5441. ret = i;
  5442. err_alloc_veb:
  5443. mutex_unlock(&pf->switch_mutex);
  5444. return ret;
  5445. }
  5446. /**
  5447. * i40e_switch_branch_release - Delete a branch of the switch tree
  5448. * @branch: where to start deleting
  5449. *
  5450. * This uses recursion to find the tips of the branch to be
  5451. * removed, deleting until we get back to and can delete this VEB.
  5452. **/
  5453. static void i40e_switch_branch_release(struct i40e_veb *branch)
  5454. {
  5455. struct i40e_pf *pf = branch->pf;
  5456. u16 branch_seid = branch->seid;
  5457. u16 veb_idx = branch->idx;
  5458. int i;
  5459. /* release any VEBs on this VEB - RECURSION */
  5460. for (i = 0; i < I40E_MAX_VEB; i++) {
  5461. if (!pf->veb[i])
  5462. continue;
  5463. if (pf->veb[i]->uplink_seid == branch->seid)
  5464. i40e_switch_branch_release(pf->veb[i]);
  5465. }
  5466. /* Release the VSIs on this VEB, but not the owner VSI.
  5467. *
  5468. * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
  5469. * the VEB itself, so don't use (*branch) after this loop.
  5470. */
  5471. for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
  5472. if (!pf->vsi[i])
  5473. continue;
  5474. if (pf->vsi[i]->uplink_seid == branch_seid &&
  5475. (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
  5476. i40e_vsi_release(pf->vsi[i]);
  5477. }
  5478. }
  5479. /* There's one corner case where the VEB might not have been
  5480. * removed, so double check it here and remove it if needed.
  5481. * This case happens if the veb was created from the debugfs
  5482. * commands and no VSIs were added to it.
  5483. */
  5484. if (pf->veb[veb_idx])
  5485. i40e_veb_release(pf->veb[veb_idx]);
  5486. }
  5487. /**
  5488. * i40e_veb_clear - remove veb struct
  5489. * @veb: the veb to remove
  5490. **/
  5491. static void i40e_veb_clear(struct i40e_veb *veb)
  5492. {
  5493. if (!veb)
  5494. return;
  5495. if (veb->pf) {
  5496. struct i40e_pf *pf = veb->pf;
  5497. mutex_lock(&pf->switch_mutex);
  5498. if (pf->veb[veb->idx] == veb)
  5499. pf->veb[veb->idx] = NULL;
  5500. mutex_unlock(&pf->switch_mutex);
  5501. }
  5502. kfree(veb);
  5503. }
  5504. /**
  5505. * i40e_veb_release - Delete a VEB and free its resources
  5506. * @veb: the VEB being removed
  5507. **/
  5508. void i40e_veb_release(struct i40e_veb *veb)
  5509. {
  5510. struct i40e_vsi *vsi = NULL;
  5511. struct i40e_pf *pf;
  5512. int i, n = 0;
  5513. pf = veb->pf;
  5514. /* find the remaining VSI and check for extras */
  5515. for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
  5516. if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
  5517. n++;
  5518. vsi = pf->vsi[i];
  5519. }
  5520. }
  5521. if (n != 1) {
  5522. dev_info(&pf->pdev->dev,
  5523. "can't remove VEB %d with %d VSIs left\n",
  5524. veb->seid, n);
  5525. return;
  5526. }
  5527. /* move the remaining VSI to uplink veb */
  5528. vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
  5529. if (veb->uplink_seid) {
  5530. vsi->uplink_seid = veb->uplink_seid;
  5531. if (veb->uplink_seid == pf->mac_seid)
  5532. vsi->veb_idx = I40E_NO_VEB;
  5533. else
  5534. vsi->veb_idx = veb->veb_idx;
  5535. } else {
  5536. /* floating VEB */
  5537. vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
  5538. vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
  5539. }
  5540. i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
  5541. i40e_veb_clear(veb);
  5542. return;
  5543. }
  5544. /**
  5545. * i40e_add_veb - create the VEB in the switch
  5546. * @veb: the VEB to be instantiated
  5547. * @vsi: the controlling VSI
  5548. **/
  5549. static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
  5550. {
  5551. bool is_default = (vsi->idx == vsi->back->lan_vsi);
  5552. int ret;
  5553. /* get a VEB from the hardware */
  5554. ret = i40e_aq_add_veb(&veb->pf->hw, veb->uplink_seid, vsi->seid,
  5555. veb->enabled_tc, is_default, &veb->seid, NULL);
  5556. if (ret) {
  5557. dev_info(&veb->pf->pdev->dev,
  5558. "couldn't add VEB, err %d, aq_err %d\n",
  5559. ret, veb->pf->hw.aq.asq_last_status);
  5560. return -EPERM;
  5561. }
  5562. /* get statistics counter */
  5563. ret = i40e_aq_get_veb_parameters(&veb->pf->hw, veb->seid, NULL, NULL,
  5564. &veb->stats_idx, NULL, NULL, NULL);
  5565. if (ret) {
  5566. dev_info(&veb->pf->pdev->dev,
  5567. "couldn't get VEB statistics idx, err %d, aq_err %d\n",
  5568. ret, veb->pf->hw.aq.asq_last_status);
  5569. return -EPERM;
  5570. }
  5571. ret = i40e_veb_get_bw_info(veb);
  5572. if (ret) {
  5573. dev_info(&veb->pf->pdev->dev,
  5574. "couldn't get VEB bw info, err %d, aq_err %d\n",
  5575. ret, veb->pf->hw.aq.asq_last_status);
  5576. i40e_aq_delete_element(&veb->pf->hw, veb->seid, NULL);
  5577. return -ENOENT;
  5578. }
  5579. vsi->uplink_seid = veb->seid;
  5580. vsi->veb_idx = veb->idx;
  5581. vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
  5582. return 0;
  5583. }
  5584. /**
  5585. * i40e_veb_setup - Set up a VEB
  5586. * @pf: board private structure
  5587. * @flags: VEB setup flags
  5588. * @uplink_seid: the switch element to link to
  5589. * @vsi_seid: the initial VSI seid
  5590. * @enabled_tc: Enabled TC bit-map
  5591. *
  5592. * This allocates the sw VEB structure and links it into the switch
  5593. * It is possible and legal for this to be a duplicate of an already
  5594. * existing VEB. It is also possible for both uplink and vsi seids
  5595. * to be zero, in order to create a floating VEB.
  5596. *
  5597. * Returns pointer to the successfully allocated VEB sw struct on
  5598. * success, otherwise returns NULL on failure.
  5599. **/
  5600. struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
  5601. u16 uplink_seid, u16 vsi_seid,
  5602. u8 enabled_tc)
  5603. {
  5604. struct i40e_veb *veb, *uplink_veb = NULL;
  5605. int vsi_idx, veb_idx;
  5606. int ret;
  5607. /* if one seid is 0, the other must be 0 to create a floating relay */
  5608. if ((uplink_seid == 0 || vsi_seid == 0) &&
  5609. (uplink_seid + vsi_seid != 0)) {
  5610. dev_info(&pf->pdev->dev,
  5611. "one, not both seid's are 0: uplink=%d vsi=%d\n",
  5612. uplink_seid, vsi_seid);
  5613. return NULL;
  5614. }
  5615. /* make sure there is such a vsi and uplink */
  5616. for (vsi_idx = 0; vsi_idx < pf->hw.func_caps.num_vsis; vsi_idx++)
  5617. if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
  5618. break;
  5619. if (vsi_idx >= pf->hw.func_caps.num_vsis && vsi_seid != 0) {
  5620. dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
  5621. vsi_seid);
  5622. return NULL;
  5623. }
  5624. if (uplink_seid && uplink_seid != pf->mac_seid) {
  5625. for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
  5626. if (pf->veb[veb_idx] &&
  5627. pf->veb[veb_idx]->seid == uplink_seid) {
  5628. uplink_veb = pf->veb[veb_idx];
  5629. break;
  5630. }
  5631. }
  5632. if (!uplink_veb) {
  5633. dev_info(&pf->pdev->dev,
  5634. "uplink seid %d not found\n", uplink_seid);
  5635. return NULL;
  5636. }
  5637. }
  5638. /* get veb sw struct */
  5639. veb_idx = i40e_veb_mem_alloc(pf);
  5640. if (veb_idx < 0)
  5641. goto err_alloc;
  5642. veb = pf->veb[veb_idx];
  5643. veb->flags = flags;
  5644. veb->uplink_seid = uplink_seid;
  5645. veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
  5646. veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
  5647. /* create the VEB in the switch */
  5648. ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
  5649. if (ret)
  5650. goto err_veb;
  5651. return veb;
  5652. err_veb:
  5653. i40e_veb_clear(veb);
  5654. err_alloc:
  5655. return NULL;
  5656. }
  5657. /**
  5658. * i40e_setup_pf_switch_element - set pf vars based on switch type
  5659. * @pf: board private structure
  5660. * @ele: element we are building info from
  5661. * @num_reported: total number of elements
  5662. * @printconfig: should we print the contents
  5663. *
  5664. * helper function to assist in extracting a few useful SEID values.
  5665. **/
  5666. static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
  5667. struct i40e_aqc_switch_config_element_resp *ele,
  5668. u16 num_reported, bool printconfig)
  5669. {
  5670. u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
  5671. u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
  5672. u8 element_type = ele->element_type;
  5673. u16 seid = le16_to_cpu(ele->seid);
  5674. if (printconfig)
  5675. dev_info(&pf->pdev->dev,
  5676. "type=%d seid=%d uplink=%d downlink=%d\n",
  5677. element_type, seid, uplink_seid, downlink_seid);
  5678. switch (element_type) {
  5679. case I40E_SWITCH_ELEMENT_TYPE_MAC:
  5680. pf->mac_seid = seid;
  5681. break;
  5682. case I40E_SWITCH_ELEMENT_TYPE_VEB:
  5683. /* Main VEB? */
  5684. if (uplink_seid != pf->mac_seid)
  5685. break;
  5686. if (pf->lan_veb == I40E_NO_VEB) {
  5687. int v;
  5688. /* find existing or else empty VEB */
  5689. for (v = 0; v < I40E_MAX_VEB; v++) {
  5690. if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
  5691. pf->lan_veb = v;
  5692. break;
  5693. }
  5694. }
  5695. if (pf->lan_veb == I40E_NO_VEB) {
  5696. v = i40e_veb_mem_alloc(pf);
  5697. if (v < 0)
  5698. break;
  5699. pf->lan_veb = v;
  5700. }
  5701. }
  5702. pf->veb[pf->lan_veb]->seid = seid;
  5703. pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
  5704. pf->veb[pf->lan_veb]->pf = pf;
  5705. pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
  5706. break;
  5707. case I40E_SWITCH_ELEMENT_TYPE_VSI:
  5708. if (num_reported != 1)
  5709. break;
  5710. /* This is immediately after a reset so we can assume this is
  5711. * the PF's VSI
  5712. */
  5713. pf->mac_seid = uplink_seid;
  5714. pf->pf_seid = downlink_seid;
  5715. pf->main_vsi_seid = seid;
  5716. if (printconfig)
  5717. dev_info(&pf->pdev->dev,
  5718. "pf_seid=%d main_vsi_seid=%d\n",
  5719. pf->pf_seid, pf->main_vsi_seid);
  5720. break;
  5721. case I40E_SWITCH_ELEMENT_TYPE_PF:
  5722. case I40E_SWITCH_ELEMENT_TYPE_VF:
  5723. case I40E_SWITCH_ELEMENT_TYPE_EMP:
  5724. case I40E_SWITCH_ELEMENT_TYPE_BMC:
  5725. case I40E_SWITCH_ELEMENT_TYPE_PE:
  5726. case I40E_SWITCH_ELEMENT_TYPE_PA:
  5727. /* ignore these for now */
  5728. break;
  5729. default:
  5730. dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
  5731. element_type, seid);
  5732. break;
  5733. }
  5734. }
  5735. /**
  5736. * i40e_fetch_switch_configuration - Get switch config from firmware
  5737. * @pf: board private structure
  5738. * @printconfig: should we print the contents
  5739. *
  5740. * Get the current switch configuration from the device and
  5741. * extract a few useful SEID values.
  5742. **/
  5743. int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
  5744. {
  5745. struct i40e_aqc_get_switch_config_resp *sw_config;
  5746. u16 next_seid = 0;
  5747. int ret = 0;
  5748. u8 *aq_buf;
  5749. int i;
  5750. aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
  5751. if (!aq_buf)
  5752. return -ENOMEM;
  5753. sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
  5754. do {
  5755. u16 num_reported, num_total;
  5756. ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
  5757. I40E_AQ_LARGE_BUF,
  5758. &next_seid, NULL);
  5759. if (ret) {
  5760. dev_info(&pf->pdev->dev,
  5761. "get switch config failed %d aq_err=%x\n",
  5762. ret, pf->hw.aq.asq_last_status);
  5763. kfree(aq_buf);
  5764. return -ENOENT;
  5765. }
  5766. num_reported = le16_to_cpu(sw_config->header.num_reported);
  5767. num_total = le16_to_cpu(sw_config->header.num_total);
  5768. if (printconfig)
  5769. dev_info(&pf->pdev->dev,
  5770. "header: %d reported %d total\n",
  5771. num_reported, num_total);
  5772. if (num_reported) {
  5773. int sz = sizeof(*sw_config) * num_reported;
  5774. kfree(pf->sw_config);
  5775. pf->sw_config = kzalloc(sz, GFP_KERNEL);
  5776. if (pf->sw_config)
  5777. memcpy(pf->sw_config, sw_config, sz);
  5778. }
  5779. for (i = 0; i < num_reported; i++) {
  5780. struct i40e_aqc_switch_config_element_resp *ele =
  5781. &sw_config->element[i];
  5782. i40e_setup_pf_switch_element(pf, ele, num_reported,
  5783. printconfig);
  5784. }
  5785. } while (next_seid != 0);
  5786. kfree(aq_buf);
  5787. return ret;
  5788. }
  5789. /**
  5790. * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
  5791. * @pf: board private structure
  5792. *
  5793. * Returns 0 on success, negative value on failure
  5794. **/
  5795. static int i40e_setup_pf_switch(struct i40e_pf *pf)
  5796. {
  5797. int ret;
  5798. /* find out what's out there already */
  5799. ret = i40e_fetch_switch_configuration(pf, false);
  5800. if (ret) {
  5801. dev_info(&pf->pdev->dev,
  5802. "couldn't fetch switch config, err %d, aq_err %d\n",
  5803. ret, pf->hw.aq.asq_last_status);
  5804. return ret;
  5805. }
  5806. i40e_pf_reset_stats(pf);
  5807. /* fdir VSI must happen first to be sure it gets queue 0, but only
  5808. * if there is enough room for the fdir VSI
  5809. */
  5810. if (pf->num_lan_qps > 1)
  5811. i40e_fdir_setup(pf);
  5812. /* first time setup */
  5813. if (pf->lan_vsi == I40E_NO_VSI) {
  5814. struct i40e_vsi *vsi = NULL;
  5815. u16 uplink_seid;
  5816. /* Set up the PF VSI associated with the PF's main VSI
  5817. * that is already in the HW switch
  5818. */
  5819. if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
  5820. uplink_seid = pf->veb[pf->lan_veb]->seid;
  5821. else
  5822. uplink_seid = pf->mac_seid;
  5823. vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
  5824. if (!vsi) {
  5825. dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
  5826. i40e_fdir_teardown(pf);
  5827. return -EAGAIN;
  5828. }
  5829. /* accommodate kcompat by copying the main VSI queue count
  5830. * into the pf, since this newer code pushes the pf queue
  5831. * info down a level into a VSI
  5832. */
  5833. pf->num_rx_queues = vsi->alloc_queue_pairs;
  5834. pf->num_tx_queues = vsi->alloc_queue_pairs;
  5835. } else {
  5836. /* force a reset of TC and queue layout configurations */
  5837. u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
  5838. pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
  5839. pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
  5840. i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
  5841. }
  5842. i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
  5843. /* Setup static PF queue filter control settings */
  5844. ret = i40e_setup_pf_filter_control(pf);
  5845. if (ret) {
  5846. dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
  5847. ret);
  5848. /* Failure here should not stop continuing other steps */
  5849. }
  5850. /* enable RSS in the HW, even for only one queue, as the stack can use
  5851. * the hash
  5852. */
  5853. if ((pf->flags & I40E_FLAG_RSS_ENABLED))
  5854. i40e_config_rss(pf);
  5855. /* fill in link information and enable LSE reporting */
  5856. i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
  5857. i40e_link_event(pf);
  5858. /* Initialize user-specifics link properties */
  5859. pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
  5860. I40E_AQ_AN_COMPLETED) ? true : false);
  5861. pf->hw.fc.requested_mode = I40E_FC_DEFAULT;
  5862. if (pf->hw.phy.link_info.an_info &
  5863. (I40E_AQ_LINK_PAUSE_TX | I40E_AQ_LINK_PAUSE_RX))
  5864. pf->hw.fc.current_mode = I40E_FC_FULL;
  5865. else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
  5866. pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
  5867. else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
  5868. pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
  5869. else
  5870. pf->hw.fc.current_mode = I40E_FC_DEFAULT;
  5871. return ret;
  5872. }
  5873. /**
  5874. * i40e_set_rss_size - helper to set rss_size
  5875. * @pf: board private structure
  5876. * @queues_left: how many queues
  5877. */
  5878. static u16 i40e_set_rss_size(struct i40e_pf *pf, int queues_left)
  5879. {
  5880. int num_tc0;
  5881. num_tc0 = min_t(int, queues_left, pf->rss_size_max);
  5882. num_tc0 = min_t(int, num_tc0, nr_cpus_node(numa_node_id()));
  5883. num_tc0 = rounddown_pow_of_two(num_tc0);
  5884. return num_tc0;
  5885. }
  5886. /**
  5887. * i40e_determine_queue_usage - Work out queue distribution
  5888. * @pf: board private structure
  5889. **/
  5890. static void i40e_determine_queue_usage(struct i40e_pf *pf)
  5891. {
  5892. int accum_tc_size;
  5893. int queues_left;
  5894. pf->num_lan_qps = 0;
  5895. pf->num_tc_qps = rounddown_pow_of_two(pf->num_tc_qps);
  5896. accum_tc_size = (I40E_MAX_TRAFFIC_CLASS - 1) * pf->num_tc_qps;
  5897. /* Find the max queues to be put into basic use. We'll always be
  5898. * using TC0, whether or not DCB is running, and TC0 will get the
  5899. * big RSS set.
  5900. */
  5901. queues_left = pf->hw.func_caps.num_tx_qp;
  5902. if (!((pf->flags & I40E_FLAG_MSIX_ENABLED) &&
  5903. (pf->flags & I40E_FLAG_MQ_ENABLED)) ||
  5904. !(pf->flags & (I40E_FLAG_RSS_ENABLED |
  5905. I40E_FLAG_FDIR_ENABLED | I40E_FLAG_DCB_ENABLED)) ||
  5906. (queues_left == 1)) {
  5907. /* one qp for PF, no queues for anything else */
  5908. queues_left = 0;
  5909. pf->rss_size = pf->num_lan_qps = 1;
  5910. /* make sure all the fancies are disabled */
  5911. pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
  5912. I40E_FLAG_MQ_ENABLED |
  5913. I40E_FLAG_FDIR_ENABLED |
  5914. I40E_FLAG_FDIR_ATR_ENABLED |
  5915. I40E_FLAG_DCB_ENABLED |
  5916. I40E_FLAG_SRIOV_ENABLED |
  5917. I40E_FLAG_VMDQ_ENABLED);
  5918. } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
  5919. !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
  5920. !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
  5921. pf->rss_size = i40e_set_rss_size(pf, queues_left);
  5922. queues_left -= pf->rss_size;
  5923. pf->num_lan_qps = pf->rss_size;
  5924. } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
  5925. !(pf->flags & I40E_FLAG_FDIR_ENABLED) &&
  5926. (pf->flags & I40E_FLAG_DCB_ENABLED)) {
  5927. /* save num_tc_qps queues for TCs 1 thru 7 and the rest
  5928. * are set up for RSS in TC0
  5929. */
  5930. queues_left -= accum_tc_size;
  5931. pf->rss_size = i40e_set_rss_size(pf, queues_left);
  5932. queues_left -= pf->rss_size;
  5933. if (queues_left < 0) {
  5934. dev_info(&pf->pdev->dev, "not enough queues for DCB\n");
  5935. return;
  5936. }
  5937. pf->num_lan_qps = pf->rss_size + accum_tc_size;
  5938. } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
  5939. (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
  5940. !(pf->flags & I40E_FLAG_DCB_ENABLED)) {
  5941. queues_left -= 1; /* save 1 queue for FD */
  5942. pf->rss_size = i40e_set_rss_size(pf, queues_left);
  5943. queues_left -= pf->rss_size;
  5944. if (queues_left < 0) {
  5945. dev_info(&pf->pdev->dev, "not enough queues for Flow Director\n");
  5946. return;
  5947. }
  5948. pf->num_lan_qps = pf->rss_size;
  5949. } else if (pf->flags & I40E_FLAG_RSS_ENABLED &&
  5950. (pf->flags & I40E_FLAG_FDIR_ENABLED) &&
  5951. (pf->flags & I40E_FLAG_DCB_ENABLED)) {
  5952. /* save 1 queue for TCs 1 thru 7,
  5953. * 1 queue for flow director,
  5954. * and the rest are set up for RSS in TC0
  5955. */
  5956. queues_left -= 1;
  5957. queues_left -= accum_tc_size;
  5958. pf->rss_size = i40e_set_rss_size(pf, queues_left);
  5959. queues_left -= pf->rss_size;
  5960. if (queues_left < 0) {
  5961. dev_info(&pf->pdev->dev, "not enough queues for DCB and Flow Director\n");
  5962. return;
  5963. }
  5964. pf->num_lan_qps = pf->rss_size + accum_tc_size;
  5965. } else {
  5966. dev_info(&pf->pdev->dev,
  5967. "Invalid configuration, flags=0x%08llx\n", pf->flags);
  5968. return;
  5969. }
  5970. if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
  5971. pf->num_vf_qps && pf->num_req_vfs && queues_left) {
  5972. pf->num_req_vfs = min_t(int, pf->num_req_vfs, (queues_left /
  5973. pf->num_vf_qps));
  5974. queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
  5975. }
  5976. if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
  5977. pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
  5978. pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
  5979. (queues_left / pf->num_vmdq_qps));
  5980. queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
  5981. }
  5982. return;
  5983. }
  5984. /**
  5985. * i40e_setup_pf_filter_control - Setup PF static filter control
  5986. * @pf: PF to be setup
  5987. *
  5988. * i40e_setup_pf_filter_control sets up a pf's initial filter control
  5989. * settings. If PE/FCoE are enabled then it will also set the per PF
  5990. * based filter sizes required for them. It also enables Flow director,
  5991. * ethertype and macvlan type filter settings for the pf.
  5992. *
  5993. * Returns 0 on success, negative on failure
  5994. **/
  5995. static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
  5996. {
  5997. struct i40e_filter_control_settings *settings = &pf->filter_settings;
  5998. settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
  5999. /* Flow Director is enabled */
  6000. if (pf->flags & (I40E_FLAG_FDIR_ENABLED | I40E_FLAG_FDIR_ATR_ENABLED))
  6001. settings->enable_fdir = true;
  6002. /* Ethtype and MACVLAN filters enabled for PF */
  6003. settings->enable_ethtype = true;
  6004. settings->enable_macvlan = true;
  6005. if (i40e_set_filter_control(&pf->hw, settings))
  6006. return -ENOENT;
  6007. return 0;
  6008. }
  6009. /**
  6010. * i40e_probe - Device initialization routine
  6011. * @pdev: PCI device information struct
  6012. * @ent: entry in i40e_pci_tbl
  6013. *
  6014. * i40e_probe initializes a pf identified by a pci_dev structure.
  6015. * The OS initialization, configuring of the pf private structure,
  6016. * and a hardware reset occur.
  6017. *
  6018. * Returns 0 on success, negative on failure
  6019. **/
  6020. static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6021. {
  6022. struct i40e_driver_version dv;
  6023. struct i40e_pf *pf;
  6024. struct i40e_hw *hw;
  6025. int err = 0;
  6026. u32 len;
  6027. err = pci_enable_device_mem(pdev);
  6028. if (err)
  6029. return err;
  6030. /* set up for high or low dma */
  6031. if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
  6032. /* coherent mask for the same size will always succeed if
  6033. * dma_set_mask does
  6034. */
  6035. dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
  6036. } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
  6037. dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
  6038. } else {
  6039. dev_err(&pdev->dev, "DMA configuration failed: %d\n", err);
  6040. err = -EIO;
  6041. goto err_dma;
  6042. }
  6043. /* set up pci connections */
  6044. err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
  6045. IORESOURCE_MEM), i40e_driver_name);
  6046. if (err) {
  6047. dev_info(&pdev->dev,
  6048. "pci_request_selected_regions failed %d\n", err);
  6049. goto err_pci_reg;
  6050. }
  6051. pci_enable_pcie_error_reporting(pdev);
  6052. pci_set_master(pdev);
  6053. /* Now that we have a PCI connection, we need to do the
  6054. * low level device setup. This is primarily setting up
  6055. * the Admin Queue structures and then querying for the
  6056. * device's current profile information.
  6057. */
  6058. pf = kzalloc(sizeof(*pf), GFP_KERNEL);
  6059. if (!pf) {
  6060. err = -ENOMEM;
  6061. goto err_pf_alloc;
  6062. }
  6063. pf->next_vsi = 0;
  6064. pf->pdev = pdev;
  6065. set_bit(__I40E_DOWN, &pf->state);
  6066. hw = &pf->hw;
  6067. hw->back = pf;
  6068. hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
  6069. pci_resource_len(pdev, 0));
  6070. if (!hw->hw_addr) {
  6071. err = -EIO;
  6072. dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
  6073. (unsigned int)pci_resource_start(pdev, 0),
  6074. (unsigned int)pci_resource_len(pdev, 0), err);
  6075. goto err_ioremap;
  6076. }
  6077. hw->vendor_id = pdev->vendor;
  6078. hw->device_id = pdev->device;
  6079. pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
  6080. hw->subsystem_vendor_id = pdev->subsystem_vendor;
  6081. hw->subsystem_device_id = pdev->subsystem_device;
  6082. hw->bus.device = PCI_SLOT(pdev->devfn);
  6083. hw->bus.func = PCI_FUNC(pdev->devfn);
  6084. /* Reset here to make sure all is clean and to define PF 'n' */
  6085. err = i40e_pf_reset(hw);
  6086. if (err) {
  6087. dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
  6088. goto err_pf_reset;
  6089. }
  6090. pf->pfr_count++;
  6091. hw->aq.num_arq_entries = I40E_AQ_LEN;
  6092. hw->aq.num_asq_entries = I40E_AQ_LEN;
  6093. hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
  6094. hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
  6095. pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
  6096. snprintf(pf->misc_int_name, sizeof(pf->misc_int_name) - 1,
  6097. "%s-pf%d:misc",
  6098. dev_driver_string(&pf->pdev->dev), pf->hw.pf_id);
  6099. err = i40e_init_shared_code(hw);
  6100. if (err) {
  6101. dev_info(&pdev->dev, "init_shared_code failed: %d\n", err);
  6102. goto err_pf_reset;
  6103. }
  6104. err = i40e_init_adminq(hw);
  6105. dev_info(&pdev->dev, "%s\n", i40e_fw_version_str(hw));
  6106. if (err) {
  6107. dev_info(&pdev->dev,
  6108. "init_adminq failed: %d expecting API %02x.%02x\n",
  6109. err,
  6110. I40E_FW_API_VERSION_MAJOR, I40E_FW_API_VERSION_MINOR);
  6111. goto err_pf_reset;
  6112. }
  6113. err = i40e_get_capabilities(pf);
  6114. if (err)
  6115. goto err_adminq_setup;
  6116. err = i40e_sw_init(pf);
  6117. if (err) {
  6118. dev_info(&pdev->dev, "sw_init failed: %d\n", err);
  6119. goto err_sw_init;
  6120. }
  6121. err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
  6122. hw->func_caps.num_rx_qp,
  6123. pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
  6124. if (err) {
  6125. dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
  6126. goto err_init_lan_hmc;
  6127. }
  6128. err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
  6129. if (err) {
  6130. dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
  6131. err = -ENOENT;
  6132. goto err_configure_lan_hmc;
  6133. }
  6134. i40e_get_mac_addr(hw, hw->mac.addr);
  6135. if (i40e_validate_mac_addr(hw->mac.addr)) {
  6136. dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
  6137. err = -EIO;
  6138. goto err_mac_addr;
  6139. }
  6140. dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
  6141. memcpy(hw->mac.perm_addr, hw->mac.addr, ETH_ALEN);
  6142. pci_set_drvdata(pdev, pf);
  6143. pci_save_state(pdev);
  6144. /* set up periodic task facility */
  6145. setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
  6146. pf->service_timer_period = HZ;
  6147. INIT_WORK(&pf->service_task, i40e_service_task);
  6148. clear_bit(__I40E_SERVICE_SCHED, &pf->state);
  6149. pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
  6150. pf->link_check_timeout = jiffies;
  6151. /* set up the main switch operations */
  6152. i40e_determine_queue_usage(pf);
  6153. i40e_init_interrupt_scheme(pf);
  6154. /* Set up the *vsi struct based on the number of VSIs in the HW,
  6155. * and set up our local tracking of the MAIN PF vsi.
  6156. */
  6157. len = sizeof(struct i40e_vsi *) * pf->hw.func_caps.num_vsis;
  6158. pf->vsi = kzalloc(len, GFP_KERNEL);
  6159. if (!pf->vsi)
  6160. goto err_switch_setup;
  6161. err = i40e_setup_pf_switch(pf);
  6162. if (err) {
  6163. dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
  6164. goto err_vsis;
  6165. }
  6166. /* The main driver is (mostly) up and happy. We need to set this state
  6167. * before setting up the misc vector or we get a race and the vector
  6168. * ends up disabled forever.
  6169. */
  6170. clear_bit(__I40E_DOWN, &pf->state);
  6171. /* In case of MSIX we are going to setup the misc vector right here
  6172. * to handle admin queue events etc. In case of legacy and MSI
  6173. * the misc functionality and queue processing is combined in
  6174. * the same vector and that gets setup at open.
  6175. */
  6176. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  6177. err = i40e_setup_misc_vector(pf);
  6178. if (err) {
  6179. dev_info(&pdev->dev,
  6180. "setup of misc vector failed: %d\n", err);
  6181. goto err_vsis;
  6182. }
  6183. }
  6184. /* prep for VF support */
  6185. if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
  6186. (pf->flags & I40E_FLAG_MSIX_ENABLED)) {
  6187. u32 val;
  6188. /* disable link interrupts for VFs */
  6189. val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
  6190. val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
  6191. wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
  6192. i40e_flush(hw);
  6193. }
  6194. i40e_dbg_pf_init(pf);
  6195. /* tell the firmware that we're starting */
  6196. dv.major_version = DRV_VERSION_MAJOR;
  6197. dv.minor_version = DRV_VERSION_MINOR;
  6198. dv.build_version = DRV_VERSION_BUILD;
  6199. dv.subbuild_version = 0;
  6200. i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
  6201. /* since everything's happy, start the service_task timer */
  6202. mod_timer(&pf->service_timer,
  6203. round_jiffies(jiffies + pf->service_timer_period));
  6204. return 0;
  6205. /* Unwind what we've done if something failed in the setup */
  6206. err_vsis:
  6207. set_bit(__I40E_DOWN, &pf->state);
  6208. err_switch_setup:
  6209. i40e_clear_interrupt_scheme(pf);
  6210. kfree(pf->vsi);
  6211. del_timer_sync(&pf->service_timer);
  6212. err_mac_addr:
  6213. err_configure_lan_hmc:
  6214. (void)i40e_shutdown_lan_hmc(hw);
  6215. err_init_lan_hmc:
  6216. kfree(pf->qp_pile);
  6217. kfree(pf->irq_pile);
  6218. err_sw_init:
  6219. err_adminq_setup:
  6220. (void)i40e_shutdown_adminq(hw);
  6221. err_pf_reset:
  6222. iounmap(hw->hw_addr);
  6223. err_ioremap:
  6224. kfree(pf);
  6225. err_pf_alloc:
  6226. pci_disable_pcie_error_reporting(pdev);
  6227. pci_release_selected_regions(pdev,
  6228. pci_select_bars(pdev, IORESOURCE_MEM));
  6229. err_pci_reg:
  6230. err_dma:
  6231. pci_disable_device(pdev);
  6232. return err;
  6233. }
  6234. /**
  6235. * i40e_remove - Device removal routine
  6236. * @pdev: PCI device information struct
  6237. *
  6238. * i40e_remove is called by the PCI subsystem to alert the driver
  6239. * that is should release a PCI device. This could be caused by a
  6240. * Hot-Plug event, or because the driver is going to be removed from
  6241. * memory.
  6242. **/
  6243. static void i40e_remove(struct pci_dev *pdev)
  6244. {
  6245. struct i40e_pf *pf = pci_get_drvdata(pdev);
  6246. i40e_status ret_code;
  6247. u32 reg;
  6248. int i;
  6249. i40e_dbg_pf_exit(pf);
  6250. if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
  6251. i40e_free_vfs(pf);
  6252. pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
  6253. }
  6254. /* no more scheduling of any task */
  6255. set_bit(__I40E_DOWN, &pf->state);
  6256. del_timer_sync(&pf->service_timer);
  6257. cancel_work_sync(&pf->service_task);
  6258. i40e_fdir_teardown(pf);
  6259. /* If there is a switch structure or any orphans, remove them.
  6260. * This will leave only the PF's VSI remaining.
  6261. */
  6262. for (i = 0; i < I40E_MAX_VEB; i++) {
  6263. if (!pf->veb[i])
  6264. continue;
  6265. if (pf->veb[i]->uplink_seid == pf->mac_seid ||
  6266. pf->veb[i]->uplink_seid == 0)
  6267. i40e_switch_branch_release(pf->veb[i]);
  6268. }
  6269. /* Now we can shutdown the PF's VSI, just before we kill
  6270. * adminq and hmc.
  6271. */
  6272. if (pf->vsi[pf->lan_vsi])
  6273. i40e_vsi_release(pf->vsi[pf->lan_vsi]);
  6274. i40e_stop_misc_vector(pf);
  6275. if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
  6276. synchronize_irq(pf->msix_entries[0].vector);
  6277. free_irq(pf->msix_entries[0].vector, pf);
  6278. }
  6279. /* shutdown and destroy the HMC */
  6280. ret_code = i40e_shutdown_lan_hmc(&pf->hw);
  6281. if (ret_code)
  6282. dev_warn(&pdev->dev,
  6283. "Failed to destroy the HMC resources: %d\n", ret_code);
  6284. /* shutdown the adminq */
  6285. i40e_aq_queue_shutdown(&pf->hw, true);
  6286. ret_code = i40e_shutdown_adminq(&pf->hw);
  6287. if (ret_code)
  6288. dev_warn(&pdev->dev,
  6289. "Failed to destroy the Admin Queue resources: %d\n",
  6290. ret_code);
  6291. /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
  6292. i40e_clear_interrupt_scheme(pf);
  6293. for (i = 0; i < pf->hw.func_caps.num_vsis; i++) {
  6294. if (pf->vsi[i]) {
  6295. i40e_vsi_clear_rings(pf->vsi[i]);
  6296. i40e_vsi_clear(pf->vsi[i]);
  6297. pf->vsi[i] = NULL;
  6298. }
  6299. }
  6300. for (i = 0; i < I40E_MAX_VEB; i++) {
  6301. kfree(pf->veb[i]);
  6302. pf->veb[i] = NULL;
  6303. }
  6304. kfree(pf->qp_pile);
  6305. kfree(pf->irq_pile);
  6306. kfree(pf->sw_config);
  6307. kfree(pf->vsi);
  6308. /* force a PF reset to clean anything leftover */
  6309. reg = rd32(&pf->hw, I40E_PFGEN_CTRL);
  6310. wr32(&pf->hw, I40E_PFGEN_CTRL, (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
  6311. i40e_flush(&pf->hw);
  6312. iounmap(pf->hw.hw_addr);
  6313. kfree(pf);
  6314. pci_release_selected_regions(pdev,
  6315. pci_select_bars(pdev, IORESOURCE_MEM));
  6316. pci_disable_pcie_error_reporting(pdev);
  6317. pci_disable_device(pdev);
  6318. }
  6319. /**
  6320. * i40e_pci_error_detected - warning that something funky happened in PCI land
  6321. * @pdev: PCI device information struct
  6322. *
  6323. * Called to warn that something happened and the error handling steps
  6324. * are in progress. Allows the driver to quiesce things, be ready for
  6325. * remediation.
  6326. **/
  6327. static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
  6328. enum pci_channel_state error)
  6329. {
  6330. struct i40e_pf *pf = pci_get_drvdata(pdev);
  6331. dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
  6332. /* shutdown all operations */
  6333. i40e_pf_quiesce_all_vsi(pf);
  6334. /* Request a slot reset */
  6335. return PCI_ERS_RESULT_NEED_RESET;
  6336. }
  6337. /**
  6338. * i40e_pci_error_slot_reset - a PCI slot reset just happened
  6339. * @pdev: PCI device information struct
  6340. *
  6341. * Called to find if the driver can work with the device now that
  6342. * the pci slot has been reset. If a basic connection seems good
  6343. * (registers are readable and have sane content) then return a
  6344. * happy little PCI_ERS_RESULT_xxx.
  6345. **/
  6346. static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
  6347. {
  6348. struct i40e_pf *pf = pci_get_drvdata(pdev);
  6349. pci_ers_result_t result;
  6350. int err;
  6351. u32 reg;
  6352. dev_info(&pdev->dev, "%s\n", __func__);
  6353. if (pci_enable_device_mem(pdev)) {
  6354. dev_info(&pdev->dev,
  6355. "Cannot re-enable PCI device after reset.\n");
  6356. result = PCI_ERS_RESULT_DISCONNECT;
  6357. } else {
  6358. pci_set_master(pdev);
  6359. pci_restore_state(pdev);
  6360. pci_save_state(pdev);
  6361. pci_wake_from_d3(pdev, false);
  6362. reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
  6363. if (reg == 0)
  6364. result = PCI_ERS_RESULT_RECOVERED;
  6365. else
  6366. result = PCI_ERS_RESULT_DISCONNECT;
  6367. }
  6368. err = pci_cleanup_aer_uncorrect_error_status(pdev);
  6369. if (err) {
  6370. dev_info(&pdev->dev,
  6371. "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
  6372. err);
  6373. /* non-fatal, continue */
  6374. }
  6375. return result;
  6376. }
  6377. /**
  6378. * i40e_pci_error_resume - restart operations after PCI error recovery
  6379. * @pdev: PCI device information struct
  6380. *
  6381. * Called to allow the driver to bring things back up after PCI error
  6382. * and/or reset recovery has finished.
  6383. **/
  6384. static void i40e_pci_error_resume(struct pci_dev *pdev)
  6385. {
  6386. struct i40e_pf *pf = pci_get_drvdata(pdev);
  6387. dev_info(&pdev->dev, "%s\n", __func__);
  6388. i40e_handle_reset_warning(pf);
  6389. }
  6390. static const struct pci_error_handlers i40e_err_handler = {
  6391. .error_detected = i40e_pci_error_detected,
  6392. .slot_reset = i40e_pci_error_slot_reset,
  6393. .resume = i40e_pci_error_resume,
  6394. };
  6395. static struct pci_driver i40e_driver = {
  6396. .name = i40e_driver_name,
  6397. .id_table = i40e_pci_tbl,
  6398. .probe = i40e_probe,
  6399. .remove = i40e_remove,
  6400. .err_handler = &i40e_err_handler,
  6401. .sriov_configure = i40e_pci_sriov_configure,
  6402. };
  6403. /**
  6404. * i40e_init_module - Driver registration routine
  6405. *
  6406. * i40e_init_module is the first routine called when the driver is
  6407. * loaded. All it does is register with the PCI subsystem.
  6408. **/
  6409. static int __init i40e_init_module(void)
  6410. {
  6411. pr_info("%s: %s - version %s\n", i40e_driver_name,
  6412. i40e_driver_string, i40e_driver_version_str);
  6413. pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
  6414. i40e_dbg_init();
  6415. return pci_register_driver(&i40e_driver);
  6416. }
  6417. module_init(i40e_init_module);
  6418. /**
  6419. * i40e_exit_module - Driver exit cleanup routine
  6420. *
  6421. * i40e_exit_module is called just before the driver is removed
  6422. * from memory.
  6423. **/
  6424. static void __exit i40e_exit_module(void)
  6425. {
  6426. pci_unregister_driver(&i40e_driver);
  6427. i40e_dbg_exit();
  6428. }
  6429. module_exit(i40e_exit_module);