cputable.c 27 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/config.h>
  13. #include <linux/string.h>
  14. #include <linux/sched.h>
  15. #include <linux/threads.h>
  16. #include <linux/init.h>
  17. #include <linux/module.h>
  18. #include <asm/oprofile_impl.h>
  19. #include <asm/cputable.h>
  20. struct cpu_spec* cur_cpu_spec = NULL;
  21. EXPORT_SYMBOL(cur_cpu_spec);
  22. /* NOTE:
  23. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  24. * the responsibility of the appropriate CPU save/restore functions to
  25. * eventually copy these settings over. Those save/restore aren't yet
  26. * part of the cputable though. That has to be fixed for both ppc32
  27. * and ppc64
  28. */
  29. #ifdef CONFIG_PPC64
  30. extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
  31. extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
  32. extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
  33. #else
  34. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  38. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  39. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  40. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  42. #endif /* CONFIG_PPC32 */
  43. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  44. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  45. * ones as well...
  46. */
  47. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  48. PPC_FEATURE_HAS_MMU)
  49. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  50. /* We only set the spe features if the kernel was compiled with
  51. * spe support
  52. */
  53. #ifdef CONFIG_SPE
  54. #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
  55. #else
  56. #define PPC_FEATURE_SPE_COMP 0
  57. #endif
  58. struct cpu_spec cpu_specs[] = {
  59. #ifdef CONFIG_PPC64
  60. { /* Power3 */
  61. .pvr_mask = 0xffff0000,
  62. .pvr_value = 0x00400000,
  63. .cpu_name = "POWER3 (630)",
  64. .cpu_features = CPU_FTRS_POWER3,
  65. .cpu_user_features = COMMON_USER_PPC64,
  66. .icache_bsize = 128,
  67. .dcache_bsize = 128,
  68. .num_pmcs = 8,
  69. .cpu_setup = __setup_cpu_power3,
  70. #ifdef CONFIG_OPROFILE
  71. .oprofile_cpu_type = "ppc64/power3",
  72. .oprofile_model = &op_model_rs64,
  73. #endif
  74. },
  75. { /* Power3+ */
  76. .pvr_mask = 0xffff0000,
  77. .pvr_value = 0x00410000,
  78. .cpu_name = "POWER3 (630+)",
  79. .cpu_features = CPU_FTRS_POWER3,
  80. .cpu_user_features = COMMON_USER_PPC64,
  81. .icache_bsize = 128,
  82. .dcache_bsize = 128,
  83. .num_pmcs = 8,
  84. .cpu_setup = __setup_cpu_power3,
  85. #ifdef CONFIG_OPROFILE
  86. .oprofile_cpu_type = "ppc64/power3",
  87. .oprofile_model = &op_model_rs64,
  88. #endif
  89. },
  90. { /* Northstar */
  91. .pvr_mask = 0xffff0000,
  92. .pvr_value = 0x00330000,
  93. .cpu_name = "RS64-II (northstar)",
  94. .cpu_features = CPU_FTRS_RS64,
  95. .cpu_user_features = COMMON_USER_PPC64,
  96. .icache_bsize = 128,
  97. .dcache_bsize = 128,
  98. .num_pmcs = 8,
  99. .cpu_setup = __setup_cpu_power3,
  100. #ifdef CONFIG_OPROFILE
  101. .oprofile_cpu_type = "ppc64/rs64",
  102. .oprofile_model = &op_model_rs64,
  103. #endif
  104. },
  105. { /* Pulsar */
  106. .pvr_mask = 0xffff0000,
  107. .pvr_value = 0x00340000,
  108. .cpu_name = "RS64-III (pulsar)",
  109. .cpu_features = CPU_FTRS_RS64,
  110. .cpu_user_features = COMMON_USER_PPC64,
  111. .icache_bsize = 128,
  112. .dcache_bsize = 128,
  113. .num_pmcs = 8,
  114. .cpu_setup = __setup_cpu_power3,
  115. #ifdef CONFIG_OPROFILE
  116. .oprofile_cpu_type = "ppc64/rs64",
  117. .oprofile_model = &op_model_rs64,
  118. #endif
  119. },
  120. { /* I-star */
  121. .pvr_mask = 0xffff0000,
  122. .pvr_value = 0x00360000,
  123. .cpu_name = "RS64-III (icestar)",
  124. .cpu_features = CPU_FTRS_RS64,
  125. .cpu_user_features = COMMON_USER_PPC64,
  126. .icache_bsize = 128,
  127. .dcache_bsize = 128,
  128. .num_pmcs = 8,
  129. .cpu_setup = __setup_cpu_power3,
  130. #ifdef CONFIG_OPROFILE
  131. .oprofile_cpu_type = "ppc64/rs64",
  132. .oprofile_model = &op_model_rs64,
  133. #endif
  134. },
  135. { /* S-star */
  136. .pvr_mask = 0xffff0000,
  137. .pvr_value = 0x00370000,
  138. .cpu_name = "RS64-IV (sstar)",
  139. .cpu_features = CPU_FTRS_RS64,
  140. .cpu_user_features = COMMON_USER_PPC64,
  141. .icache_bsize = 128,
  142. .dcache_bsize = 128,
  143. .num_pmcs = 8,
  144. .cpu_setup = __setup_cpu_power3,
  145. #ifdef CONFIG_OPROFILE
  146. .oprofile_cpu_type = "ppc64/rs64",
  147. .oprofile_model = &op_model_rs64,
  148. #endif
  149. },
  150. { /* Power4 */
  151. .pvr_mask = 0xffff0000,
  152. .pvr_value = 0x00350000,
  153. .cpu_name = "POWER4 (gp)",
  154. .cpu_features = CPU_FTRS_POWER4,
  155. .cpu_user_features = COMMON_USER_PPC64,
  156. .icache_bsize = 128,
  157. .dcache_bsize = 128,
  158. .num_pmcs = 8,
  159. .cpu_setup = __setup_cpu_power4,
  160. #ifdef CONFIG_OPROFILE
  161. .oprofile_cpu_type = "ppc64/power4",
  162. .oprofile_model = &op_model_rs64,
  163. #endif
  164. },
  165. { /* Power4+ */
  166. .pvr_mask = 0xffff0000,
  167. .pvr_value = 0x00380000,
  168. .cpu_name = "POWER4+ (gq)",
  169. .cpu_features = CPU_FTRS_POWER4,
  170. .cpu_user_features = COMMON_USER_PPC64,
  171. .icache_bsize = 128,
  172. .dcache_bsize = 128,
  173. .num_pmcs = 8,
  174. .cpu_setup = __setup_cpu_power4,
  175. #ifdef CONFIG_OPROFILE
  176. .oprofile_cpu_type = "ppc64/power4",
  177. .oprofile_model = &op_model_power4,
  178. #endif
  179. },
  180. { /* PPC970 */
  181. .pvr_mask = 0xffff0000,
  182. .pvr_value = 0x00390000,
  183. .cpu_name = "PPC970",
  184. .cpu_features = CPU_FTRS_PPC970,
  185. .cpu_user_features = COMMON_USER_PPC64 |
  186. PPC_FEATURE_HAS_ALTIVEC_COMP,
  187. .icache_bsize = 128,
  188. .dcache_bsize = 128,
  189. .num_pmcs = 8,
  190. .cpu_setup = __setup_cpu_ppc970,
  191. #ifdef CONFIG_OPROFILE
  192. .oprofile_cpu_type = "ppc64/970",
  193. .oprofile_model = &op_model_power4,
  194. #endif
  195. },
  196. #endif /* CONFIG_PPC64 */
  197. #if defined(CONFIG_PPC64) || defined(CONFIG_POWER4)
  198. { /* PPC970FX */
  199. .pvr_mask = 0xffff0000,
  200. .pvr_value = 0x003c0000,
  201. .cpu_name = "PPC970FX",
  202. #ifdef CONFIG_PPC32
  203. .cpu_features = CPU_FTRS_970_32,
  204. #else
  205. .cpu_features = CPU_FTRS_PPC970,
  206. #endif
  207. .cpu_user_features = COMMON_USER_PPC64 |
  208. PPC_FEATURE_HAS_ALTIVEC_COMP,
  209. .icache_bsize = 128,
  210. .dcache_bsize = 128,
  211. .num_pmcs = 8,
  212. .cpu_setup = __setup_cpu_ppc970,
  213. #ifdef CONFIG_OPROFILE
  214. .oprofile_cpu_type = "ppc64/970",
  215. .oprofile_model = &op_model_power4,
  216. #endif
  217. },
  218. #endif /* defined(CONFIG_PPC64) || defined(CONFIG_POWER4) */
  219. #ifdef CONFIG_PPC64
  220. { /* PPC970MP */
  221. .pvr_mask = 0xffff0000,
  222. .pvr_value = 0x00440000,
  223. .cpu_name = "PPC970MP",
  224. .cpu_features = CPU_FTRS_PPC970,
  225. .cpu_user_features = COMMON_USER_PPC64 |
  226. PPC_FEATURE_HAS_ALTIVEC_COMP,
  227. .icache_bsize = 128,
  228. .dcache_bsize = 128,
  229. .cpu_setup = __setup_cpu_ppc970,
  230. #ifdef CONFIG_OPROFILE
  231. .oprofile_cpu_type = "ppc64/970",
  232. .oprofile_model = &op_model_power4,
  233. #endif
  234. },
  235. { /* Power5 */
  236. .pvr_mask = 0xffff0000,
  237. .pvr_value = 0x003a0000,
  238. .cpu_name = "POWER5 (gr)",
  239. .cpu_features = CPU_FTRS_POWER5,
  240. .cpu_user_features = COMMON_USER_PPC64,
  241. .icache_bsize = 128,
  242. .dcache_bsize = 128,
  243. .num_pmcs = 6,
  244. .cpu_setup = __setup_cpu_power4,
  245. #ifdef CONFIG_OPROFILE
  246. .oprofile_cpu_type = "ppc64/power5",
  247. .oprofile_model = &op_model_power4,
  248. #endif
  249. },
  250. { /* Power5 */
  251. .pvr_mask = 0xffff0000,
  252. .pvr_value = 0x003b0000,
  253. .cpu_name = "POWER5 (gs)",
  254. .cpu_features = CPU_FTRS_POWER5,
  255. .cpu_user_features = COMMON_USER_PPC64,
  256. .icache_bsize = 128,
  257. .dcache_bsize = 128,
  258. .num_pmcs = 6,
  259. .cpu_setup = __setup_cpu_power4,
  260. #ifdef CONFIG_OPROFILE
  261. .oprofile_cpu_type = "ppc64/power5",
  262. .oprofile_model = &op_model_power4,
  263. #endif
  264. },
  265. { /* BE DD1.x */
  266. .pvr_mask = 0xffff0000,
  267. .pvr_value = 0x00700000,
  268. .cpu_name = "Cell Broadband Engine",
  269. .cpu_features = CPU_FTRS_CELL,
  270. .cpu_user_features = COMMON_USER_PPC64 |
  271. PPC_FEATURE_HAS_ALTIVEC_COMP,
  272. .icache_bsize = 128,
  273. .dcache_bsize = 128,
  274. .cpu_setup = __setup_cpu_be,
  275. },
  276. { /* default match */
  277. .pvr_mask = 0x00000000,
  278. .pvr_value = 0x00000000,
  279. .cpu_name = "POWER4 (compatible)",
  280. .cpu_features = CPU_FTRS_COMPATIBLE,
  281. .cpu_user_features = COMMON_USER_PPC64,
  282. .icache_bsize = 128,
  283. .dcache_bsize = 128,
  284. .num_pmcs = 6,
  285. .cpu_setup = __setup_cpu_power4,
  286. }
  287. #endif /* CONFIG_PPC64 */
  288. #ifdef CONFIG_PPC32
  289. #if CLASSIC_PPC
  290. { /* 601 */
  291. .pvr_mask = 0xffff0000,
  292. .pvr_value = 0x00010000,
  293. .cpu_name = "601",
  294. .cpu_features = CPU_FTRS_PPC601,
  295. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  296. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  297. .icache_bsize = 32,
  298. .dcache_bsize = 32,
  299. },
  300. { /* 603 */
  301. .pvr_mask = 0xffff0000,
  302. .pvr_value = 0x00030000,
  303. .cpu_name = "603",
  304. .cpu_features = CPU_FTRS_603,
  305. .cpu_user_features = COMMON_USER,
  306. .icache_bsize = 32,
  307. .dcache_bsize = 32,
  308. .cpu_setup = __setup_cpu_603
  309. },
  310. { /* 603e */
  311. .pvr_mask = 0xffff0000,
  312. .pvr_value = 0x00060000,
  313. .cpu_name = "603e",
  314. .cpu_features = CPU_FTRS_603,
  315. .cpu_user_features = COMMON_USER,
  316. .icache_bsize = 32,
  317. .dcache_bsize = 32,
  318. .cpu_setup = __setup_cpu_603
  319. },
  320. { /* 603ev */
  321. .pvr_mask = 0xffff0000,
  322. .pvr_value = 0x00070000,
  323. .cpu_name = "603ev",
  324. .cpu_features = CPU_FTRS_603,
  325. .cpu_user_features = COMMON_USER,
  326. .icache_bsize = 32,
  327. .dcache_bsize = 32,
  328. .cpu_setup = __setup_cpu_603
  329. },
  330. { /* 604 */
  331. .pvr_mask = 0xffff0000,
  332. .pvr_value = 0x00040000,
  333. .cpu_name = "604",
  334. .cpu_features = CPU_FTRS_604,
  335. .cpu_user_features = COMMON_USER,
  336. .icache_bsize = 32,
  337. .dcache_bsize = 32,
  338. .num_pmcs = 2,
  339. .cpu_setup = __setup_cpu_604
  340. },
  341. { /* 604e */
  342. .pvr_mask = 0xfffff000,
  343. .pvr_value = 0x00090000,
  344. .cpu_name = "604e",
  345. .cpu_features = CPU_FTRS_604,
  346. .cpu_user_features = COMMON_USER,
  347. .icache_bsize = 32,
  348. .dcache_bsize = 32,
  349. .num_pmcs = 4,
  350. .cpu_setup = __setup_cpu_604
  351. },
  352. { /* 604r */
  353. .pvr_mask = 0xffff0000,
  354. .pvr_value = 0x00090000,
  355. .cpu_name = "604r",
  356. .cpu_features = CPU_FTRS_604,
  357. .cpu_user_features = COMMON_USER,
  358. .icache_bsize = 32,
  359. .dcache_bsize = 32,
  360. .num_pmcs = 4,
  361. .cpu_setup = __setup_cpu_604
  362. },
  363. { /* 604ev */
  364. .pvr_mask = 0xffff0000,
  365. .pvr_value = 0x000a0000,
  366. .cpu_name = "604ev",
  367. .cpu_features = CPU_FTRS_604,
  368. .cpu_user_features = COMMON_USER,
  369. .icache_bsize = 32,
  370. .dcache_bsize = 32,
  371. .num_pmcs = 4,
  372. .cpu_setup = __setup_cpu_604
  373. },
  374. { /* 740/750 (0x4202, don't support TAU ?) */
  375. .pvr_mask = 0xffffffff,
  376. .pvr_value = 0x00084202,
  377. .cpu_name = "740/750",
  378. .cpu_features = CPU_FTRS_740_NOTAU,
  379. .cpu_user_features = COMMON_USER,
  380. .icache_bsize = 32,
  381. .dcache_bsize = 32,
  382. .num_pmcs = 4,
  383. .cpu_setup = __setup_cpu_750
  384. },
  385. { /* 750CX (80100 and 8010x?) */
  386. .pvr_mask = 0xfffffff0,
  387. .pvr_value = 0x00080100,
  388. .cpu_name = "750CX",
  389. .cpu_features = CPU_FTRS_750,
  390. .cpu_user_features = COMMON_USER,
  391. .icache_bsize = 32,
  392. .dcache_bsize = 32,
  393. .num_pmcs = 4,
  394. .cpu_setup = __setup_cpu_750cx
  395. },
  396. { /* 750CX (82201 and 82202) */
  397. .pvr_mask = 0xfffffff0,
  398. .pvr_value = 0x00082200,
  399. .cpu_name = "750CX",
  400. .cpu_features = CPU_FTRS_750,
  401. .cpu_user_features = COMMON_USER,
  402. .icache_bsize = 32,
  403. .dcache_bsize = 32,
  404. .num_pmcs = 4,
  405. .cpu_setup = __setup_cpu_750cx
  406. },
  407. { /* 750CXe (82214) */
  408. .pvr_mask = 0xfffffff0,
  409. .pvr_value = 0x00082210,
  410. .cpu_name = "750CXe",
  411. .cpu_features = CPU_FTRS_750,
  412. .cpu_user_features = COMMON_USER,
  413. .icache_bsize = 32,
  414. .dcache_bsize = 32,
  415. .num_pmcs = 4,
  416. .cpu_setup = __setup_cpu_750cx
  417. },
  418. { /* 750CXe "Gekko" (83214) */
  419. .pvr_mask = 0xffffffff,
  420. .pvr_value = 0x00083214,
  421. .cpu_name = "750CXe",
  422. .cpu_features = CPU_FTRS_750,
  423. .cpu_user_features = COMMON_USER,
  424. .icache_bsize = 32,
  425. .dcache_bsize = 32,
  426. .num_pmcs = 4,
  427. .cpu_setup = __setup_cpu_750cx
  428. },
  429. { /* 745/755 */
  430. .pvr_mask = 0xfffff000,
  431. .pvr_value = 0x00083000,
  432. .cpu_name = "745/755",
  433. .cpu_features = CPU_FTRS_750,
  434. .cpu_user_features = COMMON_USER,
  435. .icache_bsize = 32,
  436. .dcache_bsize = 32,
  437. .num_pmcs = 4,
  438. .cpu_setup = __setup_cpu_750
  439. },
  440. { /* 750FX rev 1.x */
  441. .pvr_mask = 0xffffff00,
  442. .pvr_value = 0x70000100,
  443. .cpu_name = "750FX",
  444. .cpu_features = CPU_FTRS_750FX1,
  445. .cpu_user_features = COMMON_USER,
  446. .icache_bsize = 32,
  447. .dcache_bsize = 32,
  448. .num_pmcs = 4,
  449. .cpu_setup = __setup_cpu_750
  450. },
  451. { /* 750FX rev 2.0 must disable HID0[DPM] */
  452. .pvr_mask = 0xffffffff,
  453. .pvr_value = 0x70000200,
  454. .cpu_name = "750FX",
  455. .cpu_features = CPU_FTRS_750FX2,
  456. .cpu_user_features = COMMON_USER,
  457. .icache_bsize = 32,
  458. .dcache_bsize = 32,
  459. .num_pmcs = 4,
  460. .cpu_setup = __setup_cpu_750
  461. },
  462. { /* 750FX (All revs except 2.0) */
  463. .pvr_mask = 0xffff0000,
  464. .pvr_value = 0x70000000,
  465. .cpu_name = "750FX",
  466. .cpu_features = CPU_FTRS_750FX,
  467. .cpu_user_features = COMMON_USER,
  468. .icache_bsize = 32,
  469. .dcache_bsize = 32,
  470. .num_pmcs = 4,
  471. .cpu_setup = __setup_cpu_750fx
  472. },
  473. { /* 750GX */
  474. .pvr_mask = 0xffff0000,
  475. .pvr_value = 0x70020000,
  476. .cpu_name = "750GX",
  477. .cpu_features = CPU_FTRS_750GX,
  478. .cpu_user_features = COMMON_USER,
  479. .icache_bsize = 32,
  480. .dcache_bsize = 32,
  481. .num_pmcs = 4,
  482. .cpu_setup = __setup_cpu_750fx
  483. },
  484. { /* 740/750 (L2CR bit need fixup for 740) */
  485. .pvr_mask = 0xffff0000,
  486. .pvr_value = 0x00080000,
  487. .cpu_name = "740/750",
  488. .cpu_features = CPU_FTRS_740,
  489. .cpu_user_features = COMMON_USER,
  490. .icache_bsize = 32,
  491. .dcache_bsize = 32,
  492. .num_pmcs = 4,
  493. .cpu_setup = __setup_cpu_750
  494. },
  495. { /* 7400 rev 1.1 ? (no TAU) */
  496. .pvr_mask = 0xffffffff,
  497. .pvr_value = 0x000c1101,
  498. .cpu_name = "7400 (1.1)",
  499. .cpu_features = CPU_FTRS_7400_NOTAU,
  500. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  501. .icache_bsize = 32,
  502. .dcache_bsize = 32,
  503. .num_pmcs = 4,
  504. .cpu_setup = __setup_cpu_7400
  505. },
  506. { /* 7400 */
  507. .pvr_mask = 0xffff0000,
  508. .pvr_value = 0x000c0000,
  509. .cpu_name = "7400",
  510. .cpu_features = CPU_FTRS_7400,
  511. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  512. .icache_bsize = 32,
  513. .dcache_bsize = 32,
  514. .num_pmcs = 4,
  515. .cpu_setup = __setup_cpu_7400
  516. },
  517. { /* 7410 */
  518. .pvr_mask = 0xffff0000,
  519. .pvr_value = 0x800c0000,
  520. .cpu_name = "7410",
  521. .cpu_features = CPU_FTRS_7400,
  522. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  523. .icache_bsize = 32,
  524. .dcache_bsize = 32,
  525. .num_pmcs = 4,
  526. .cpu_setup = __setup_cpu_7410
  527. },
  528. { /* 7450 2.0 - no doze/nap */
  529. .pvr_mask = 0xffffffff,
  530. .pvr_value = 0x80000200,
  531. .cpu_name = "7450",
  532. .cpu_features = CPU_FTRS_7450_20,
  533. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  534. .icache_bsize = 32,
  535. .dcache_bsize = 32,
  536. .num_pmcs = 6,
  537. .cpu_setup = __setup_cpu_745x
  538. },
  539. { /* 7450 2.1 */
  540. .pvr_mask = 0xffffffff,
  541. .pvr_value = 0x80000201,
  542. .cpu_name = "7450",
  543. .cpu_features = CPU_FTRS_7450_21,
  544. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  545. .icache_bsize = 32,
  546. .dcache_bsize = 32,
  547. .num_pmcs = 6,
  548. .cpu_setup = __setup_cpu_745x
  549. },
  550. { /* 7450 2.3 and newer */
  551. .pvr_mask = 0xffff0000,
  552. .pvr_value = 0x80000000,
  553. .cpu_name = "7450",
  554. .cpu_features = CPU_FTRS_7450_23,
  555. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  556. .icache_bsize = 32,
  557. .dcache_bsize = 32,
  558. .num_pmcs = 6,
  559. .cpu_setup = __setup_cpu_745x
  560. },
  561. { /* 7455 rev 1.x */
  562. .pvr_mask = 0xffffff00,
  563. .pvr_value = 0x80010100,
  564. .cpu_name = "7455",
  565. .cpu_features = CPU_FTRS_7455_1,
  566. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  567. .icache_bsize = 32,
  568. .dcache_bsize = 32,
  569. .num_pmcs = 6,
  570. .cpu_setup = __setup_cpu_745x
  571. },
  572. { /* 7455 rev 2.0 */
  573. .pvr_mask = 0xffffffff,
  574. .pvr_value = 0x80010200,
  575. .cpu_name = "7455",
  576. .cpu_features = CPU_FTRS_7455_20,
  577. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  578. .icache_bsize = 32,
  579. .dcache_bsize = 32,
  580. .num_pmcs = 6,
  581. .cpu_setup = __setup_cpu_745x
  582. },
  583. { /* 7455 others */
  584. .pvr_mask = 0xffff0000,
  585. .pvr_value = 0x80010000,
  586. .cpu_name = "7455",
  587. .cpu_features = CPU_FTRS_7455,
  588. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  589. .icache_bsize = 32,
  590. .dcache_bsize = 32,
  591. .num_pmcs = 6,
  592. .cpu_setup = __setup_cpu_745x
  593. },
  594. { /* 7447/7457 Rev 1.0 */
  595. .pvr_mask = 0xffffffff,
  596. .pvr_value = 0x80020100,
  597. .cpu_name = "7447/7457",
  598. .cpu_features = CPU_FTRS_7447_10,
  599. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  600. .icache_bsize = 32,
  601. .dcache_bsize = 32,
  602. .num_pmcs = 6,
  603. .cpu_setup = __setup_cpu_745x
  604. },
  605. { /* 7447/7457 Rev 1.1 */
  606. .pvr_mask = 0xffffffff,
  607. .pvr_value = 0x80020101,
  608. .cpu_name = "7447/7457",
  609. .cpu_features = CPU_FTRS_7447_10,
  610. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  611. .icache_bsize = 32,
  612. .dcache_bsize = 32,
  613. .num_pmcs = 6,
  614. .cpu_setup = __setup_cpu_745x
  615. },
  616. { /* 7447/7457 Rev 1.2 and later */
  617. .pvr_mask = 0xffff0000,
  618. .pvr_value = 0x80020000,
  619. .cpu_name = "7447/7457",
  620. .cpu_features = CPU_FTRS_7447,
  621. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  622. .icache_bsize = 32,
  623. .dcache_bsize = 32,
  624. .num_pmcs = 6,
  625. .cpu_setup = __setup_cpu_745x
  626. },
  627. { /* 7447A */
  628. .pvr_mask = 0xffff0000,
  629. .pvr_value = 0x80030000,
  630. .cpu_name = "7447A",
  631. .cpu_features = CPU_FTRS_7447A,
  632. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  633. .icache_bsize = 32,
  634. .dcache_bsize = 32,
  635. .num_pmcs = 6,
  636. .cpu_setup = __setup_cpu_745x
  637. },
  638. { /* 7448 */
  639. .pvr_mask = 0xffff0000,
  640. .pvr_value = 0x80040000,
  641. .cpu_name = "7448",
  642. .cpu_features = CPU_FTRS_7447A,
  643. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
  644. .icache_bsize = 32,
  645. .dcache_bsize = 32,
  646. .num_pmcs = 6,
  647. .cpu_setup = __setup_cpu_745x
  648. },
  649. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  650. .pvr_mask = 0x7fff0000,
  651. .pvr_value = 0x00810000,
  652. .cpu_name = "82xx",
  653. .cpu_features = CPU_FTRS_82XX,
  654. .cpu_user_features = COMMON_USER,
  655. .icache_bsize = 32,
  656. .dcache_bsize = 32,
  657. .cpu_setup = __setup_cpu_603
  658. },
  659. { /* All G2_LE (603e core, plus some) have the same pvr */
  660. .pvr_mask = 0x7fff0000,
  661. .pvr_value = 0x00820000,
  662. .cpu_name = "G2_LE",
  663. .cpu_features = CPU_FTRS_G2_LE,
  664. .cpu_user_features = COMMON_USER,
  665. .icache_bsize = 32,
  666. .dcache_bsize = 32,
  667. .cpu_setup = __setup_cpu_603
  668. },
  669. { /* e300 (a 603e core, plus some) on 83xx */
  670. .pvr_mask = 0x7fff0000,
  671. .pvr_value = 0x00830000,
  672. .cpu_name = "e300",
  673. .cpu_features = CPU_FTRS_E300,
  674. .cpu_user_features = COMMON_USER,
  675. .icache_bsize = 32,
  676. .dcache_bsize = 32,
  677. .cpu_setup = __setup_cpu_603
  678. },
  679. { /* default match, we assume split I/D cache & TB (non-601)... */
  680. .pvr_mask = 0x00000000,
  681. .pvr_value = 0x00000000,
  682. .cpu_name = "(generic PPC)",
  683. .cpu_features = CPU_FTRS_CLASSIC32,
  684. .cpu_user_features = COMMON_USER,
  685. .icache_bsize = 32,
  686. .dcache_bsize = 32,
  687. },
  688. #endif /* CLASSIC_PPC */
  689. #ifdef CONFIG_8xx
  690. { /* 8xx */
  691. .pvr_mask = 0xffff0000,
  692. .pvr_value = 0x00500000,
  693. .cpu_name = "8xx",
  694. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  695. * if the 8xx code is there.... */
  696. .cpu_features = CPU_FTRS_8XX,
  697. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  698. .icache_bsize = 16,
  699. .dcache_bsize = 16,
  700. },
  701. #endif /* CONFIG_8xx */
  702. #ifdef CONFIG_40x
  703. { /* 403GC */
  704. .pvr_mask = 0xffffff00,
  705. .pvr_value = 0x00200200,
  706. .cpu_name = "403GC",
  707. .cpu_features = CPU_FTRS_40X,
  708. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  709. .icache_bsize = 16,
  710. .dcache_bsize = 16,
  711. },
  712. { /* 403GCX */
  713. .pvr_mask = 0xffffff00,
  714. .pvr_value = 0x00201400,
  715. .cpu_name = "403GCX",
  716. .cpu_features = CPU_FTRS_40X,
  717. .cpu_user_features = PPC_FEATURE_32 |
  718. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  719. .icache_bsize = 16,
  720. .dcache_bsize = 16,
  721. },
  722. { /* 403G ?? */
  723. .pvr_mask = 0xffff0000,
  724. .pvr_value = 0x00200000,
  725. .cpu_name = "403G ??",
  726. .cpu_features = CPU_FTRS_40X,
  727. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  728. .icache_bsize = 16,
  729. .dcache_bsize = 16,
  730. },
  731. { /* 405GP */
  732. .pvr_mask = 0xffff0000,
  733. .pvr_value = 0x40110000,
  734. .cpu_name = "405GP",
  735. .cpu_features = CPU_FTRS_40X,
  736. .cpu_user_features = PPC_FEATURE_32 |
  737. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  738. .icache_bsize = 32,
  739. .dcache_bsize = 32,
  740. },
  741. { /* STB 03xxx */
  742. .pvr_mask = 0xffff0000,
  743. .pvr_value = 0x40130000,
  744. .cpu_name = "STB03xxx",
  745. .cpu_features = CPU_FTRS_40X,
  746. .cpu_user_features = PPC_FEATURE_32 |
  747. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  748. .icache_bsize = 32,
  749. .dcache_bsize = 32,
  750. },
  751. { /* STB 04xxx */
  752. .pvr_mask = 0xffff0000,
  753. .pvr_value = 0x41810000,
  754. .cpu_name = "STB04xxx",
  755. .cpu_features = CPU_FTRS_40X,
  756. .cpu_user_features = PPC_FEATURE_32 |
  757. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  758. .icache_bsize = 32,
  759. .dcache_bsize = 32,
  760. },
  761. { /* NP405L */
  762. .pvr_mask = 0xffff0000,
  763. .pvr_value = 0x41610000,
  764. .cpu_name = "NP405L",
  765. .cpu_features = CPU_FTRS_40X,
  766. .cpu_user_features = PPC_FEATURE_32 |
  767. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  768. .icache_bsize = 32,
  769. .dcache_bsize = 32,
  770. },
  771. { /* NP4GS3 */
  772. .pvr_mask = 0xffff0000,
  773. .pvr_value = 0x40B10000,
  774. .cpu_name = "NP4GS3",
  775. .cpu_features = CPU_FTRS_40X,
  776. .cpu_user_features = PPC_FEATURE_32 |
  777. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  778. .icache_bsize = 32,
  779. .dcache_bsize = 32,
  780. },
  781. { /* NP405H */
  782. .pvr_mask = 0xffff0000,
  783. .pvr_value = 0x41410000,
  784. .cpu_name = "NP405H",
  785. .cpu_features = CPU_FTRS_40X,
  786. .cpu_user_features = PPC_FEATURE_32 |
  787. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  788. .icache_bsize = 32,
  789. .dcache_bsize = 32,
  790. },
  791. { /* 405GPr */
  792. .pvr_mask = 0xffff0000,
  793. .pvr_value = 0x50910000,
  794. .cpu_name = "405GPr",
  795. .cpu_features = CPU_FTRS_40X,
  796. .cpu_user_features = PPC_FEATURE_32 |
  797. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  798. .icache_bsize = 32,
  799. .dcache_bsize = 32,
  800. },
  801. { /* STBx25xx */
  802. .pvr_mask = 0xffff0000,
  803. .pvr_value = 0x51510000,
  804. .cpu_name = "STBx25xx",
  805. .cpu_features = CPU_FTRS_40X,
  806. .cpu_user_features = PPC_FEATURE_32 |
  807. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  808. .icache_bsize = 32,
  809. .dcache_bsize = 32,
  810. },
  811. { /* 405LP */
  812. .pvr_mask = 0xffff0000,
  813. .pvr_value = 0x41F10000,
  814. .cpu_name = "405LP",
  815. .cpu_features = CPU_FTRS_40X,
  816. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  817. .icache_bsize = 32,
  818. .dcache_bsize = 32,
  819. },
  820. { /* Xilinx Virtex-II Pro */
  821. .pvr_mask = 0xffff0000,
  822. .pvr_value = 0x20010000,
  823. .cpu_name = "Virtex-II Pro",
  824. .cpu_features = CPU_FTRS_40X,
  825. .cpu_user_features = PPC_FEATURE_32 |
  826. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  827. .icache_bsize = 32,
  828. .dcache_bsize = 32,
  829. },
  830. { /* 405EP */
  831. .pvr_mask = 0xffff0000,
  832. .pvr_value = 0x51210000,
  833. .cpu_name = "405EP",
  834. .cpu_features = CPU_FTRS_40X,
  835. .cpu_user_features = PPC_FEATURE_32 |
  836. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  837. .icache_bsize = 32,
  838. .dcache_bsize = 32,
  839. },
  840. #endif /* CONFIG_40x */
  841. #ifdef CONFIG_44x
  842. {
  843. .pvr_mask = 0xf0000fff,
  844. .pvr_value = 0x40000850,
  845. .cpu_name = "440EP Rev. A",
  846. .cpu_features = CPU_FTRS_44X,
  847. .cpu_user_features = COMMON_USER, /* 440EP has an FPU */
  848. .icache_bsize = 32,
  849. .dcache_bsize = 32,
  850. },
  851. {
  852. .pvr_mask = 0xf0000fff,
  853. .pvr_value = 0x400008d3,
  854. .cpu_name = "440EP Rev. B",
  855. .cpu_features = CPU_FTRS_44X,
  856. .cpu_user_features = COMMON_USER, /* 440EP has an FPU */
  857. .icache_bsize = 32,
  858. .dcache_bsize = 32,
  859. },
  860. { /* 440GP Rev. B */
  861. .pvr_mask = 0xf0000fff,
  862. .pvr_value = 0x40000440,
  863. .cpu_name = "440GP Rev. B",
  864. .cpu_features = CPU_FTRS_44X,
  865. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  866. .icache_bsize = 32,
  867. .dcache_bsize = 32,
  868. },
  869. { /* 440GP Rev. C */
  870. .pvr_mask = 0xf0000fff,
  871. .pvr_value = 0x40000481,
  872. .cpu_name = "440GP Rev. C",
  873. .cpu_features = CPU_FTRS_44X,
  874. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  875. .icache_bsize = 32,
  876. .dcache_bsize = 32,
  877. },
  878. { /* 440GX Rev. A */
  879. .pvr_mask = 0xf0000fff,
  880. .pvr_value = 0x50000850,
  881. .cpu_name = "440GX Rev. A",
  882. .cpu_features = CPU_FTRS_44X,
  883. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  884. .icache_bsize = 32,
  885. .dcache_bsize = 32,
  886. },
  887. { /* 440GX Rev. B */
  888. .pvr_mask = 0xf0000fff,
  889. .pvr_value = 0x50000851,
  890. .cpu_name = "440GX Rev. B",
  891. .cpu_features = CPU_FTRS_44X,
  892. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  893. .icache_bsize = 32,
  894. .dcache_bsize = 32,
  895. },
  896. { /* 440GX Rev. C */
  897. .pvr_mask = 0xf0000fff,
  898. .pvr_value = 0x50000892,
  899. .cpu_name = "440GX Rev. C",
  900. .cpu_features = CPU_FTRS_44X,
  901. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  902. .icache_bsize = 32,
  903. .dcache_bsize = 32,
  904. },
  905. { /* 440GX Rev. F */
  906. .pvr_mask = 0xf0000fff,
  907. .pvr_value = 0x50000894,
  908. .cpu_name = "440GX Rev. F",
  909. .cpu_features = CPU_FTRS_44X,
  910. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  911. .icache_bsize = 32,
  912. .dcache_bsize = 32,
  913. },
  914. { /* 440SP Rev. A */
  915. .pvr_mask = 0xff000fff,
  916. .pvr_value = 0x53000891,
  917. .cpu_name = "440SP Rev. A",
  918. .cpu_features = CPU_FTRS_44X,
  919. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  920. .icache_bsize = 32,
  921. .dcache_bsize = 32,
  922. },
  923. #endif /* CONFIG_44x */
  924. #ifdef CONFIG_FSL_BOOKE
  925. { /* e200z5 */
  926. .pvr_mask = 0xfff00000,
  927. .pvr_value = 0x81000000,
  928. .cpu_name = "e200z5",
  929. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  930. .cpu_features = CPU_FTRS_E200,
  931. .cpu_user_features = PPC_FEATURE_32 |
  932. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
  933. PPC_FEATURE_UNIFIED_CACHE,
  934. .dcache_bsize = 32,
  935. },
  936. { /* e200z6 */
  937. .pvr_mask = 0xfff00000,
  938. .pvr_value = 0x81100000,
  939. .cpu_name = "e200z6",
  940. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  941. .cpu_features = CPU_FTRS_E200,
  942. .cpu_user_features = PPC_FEATURE_32 |
  943. PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
  944. PPC_FEATURE_HAS_EFP_SINGLE |
  945. PPC_FEATURE_UNIFIED_CACHE,
  946. .dcache_bsize = 32,
  947. },
  948. { /* e500 */
  949. .pvr_mask = 0xffff0000,
  950. .pvr_value = 0x80200000,
  951. .cpu_name = "e500",
  952. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  953. .cpu_features = CPU_FTRS_E500,
  954. .cpu_user_features = PPC_FEATURE_32 |
  955. PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
  956. PPC_FEATURE_HAS_EFP_SINGLE,
  957. .icache_bsize = 32,
  958. .dcache_bsize = 32,
  959. .num_pmcs = 4,
  960. },
  961. { /* e500v2 */
  962. .pvr_mask = 0xffff0000,
  963. .pvr_value = 0x80210000,
  964. .cpu_name = "e500v2",
  965. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  966. .cpu_features = CPU_FTRS_E500_2,
  967. .cpu_user_features = PPC_FEATURE_32 |
  968. PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
  969. PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
  970. .icache_bsize = 32,
  971. .dcache_bsize = 32,
  972. .num_pmcs = 4,
  973. },
  974. #endif
  975. #if !CLASSIC_PPC
  976. { /* default match */
  977. .pvr_mask = 0x00000000,
  978. .pvr_value = 0x00000000,
  979. .cpu_name = "(generic PPC)",
  980. .cpu_features = CPU_FTRS_GENERIC_32,
  981. .cpu_user_features = PPC_FEATURE_32,
  982. .icache_bsize = 32,
  983. .dcache_bsize = 32,
  984. }
  985. #endif /* !CLASSIC_PPC */
  986. #endif /* CONFIG_PPC32 */
  987. };