s3c2412-i2s.c 4.7 KB

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  1. /* sound/soc/s3c24xx/s3c2412-i2s.c
  2. *
  3. * ALSA Soc Audio Layer - S3C2412 I2S driver
  4. *
  5. * Copyright (c) 2006 Wolfson Microelectronics PLC.
  6. * Graeme Gregory graeme.gregory@wolfsonmicro.com
  7. * linux@wolfsonmicro.com
  8. *
  9. * Copyright (c) 2007, 2004-2005 Simtec Electronics
  10. * http://armlinux.simtec.co.uk/
  11. * Ben Dooks <ben@simtec.co.uk>
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #include <linux/init.h>
  19. #include <linux/module.h>
  20. #include <linux/device.h>
  21. #include <linux/delay.h>
  22. #include <linux/clk.h>
  23. #include <linux/kernel.h>
  24. #include <linux/io.h>
  25. #include <sound/core.h>
  26. #include <sound/pcm.h>
  27. #include <sound/pcm_params.h>
  28. #include <sound/initval.h>
  29. #include <sound/soc.h>
  30. #include <mach/hardware.h>
  31. #include <plat/regs-s3c2412-iis.h>
  32. #include <plat/regs-gpio.h>
  33. #include <plat/audio.h>
  34. #include <mach/dma.h>
  35. #include "s3c24xx-pcm.h"
  36. #include "s3c2412-i2s.h"
  37. #define S3C2412_I2S_DEBUG 0
  38. #if S3C2412_I2S_DEBUG
  39. #define DBG(x...) printk(KERN_INFO x)
  40. #else
  41. #define DBG(x...) do { } while (0)
  42. #endif
  43. static struct s3c2410_dma_client s3c2412_dma_client_out = {
  44. .name = "I2S PCM Stereo out"
  45. };
  46. static struct s3c2410_dma_client s3c2412_dma_client_in = {
  47. .name = "I2S PCM Stereo in"
  48. };
  49. static struct s3c24xx_pcm_dma_params s3c2412_i2s_pcm_stereo_out = {
  50. .client = &s3c2412_dma_client_out,
  51. .channel = DMACH_I2S_OUT,
  52. .dma_addr = S3C2410_PA_IIS + S3C2412_IISTXD,
  53. .dma_size = 4,
  54. };
  55. static struct s3c24xx_pcm_dma_params s3c2412_i2s_pcm_stereo_in = {
  56. .client = &s3c2412_dma_client_in,
  57. .channel = DMACH_I2S_IN,
  58. .dma_addr = S3C2410_PA_IIS + S3C2412_IISRXD,
  59. .dma_size = 4,
  60. };
  61. static struct s3c_i2sv2_info s3c2412_i2s;
  62. /*
  63. * Set S3C2412 Clock source
  64. */
  65. static int s3c2412_i2s_set_sysclk(struct snd_soc_dai *cpu_dai,
  66. int clk_id, unsigned int freq, int dir)
  67. {
  68. u32 iismod = readl(s3c2412_i2s.regs + S3C2412_IISMOD);
  69. DBG("%s(%p, %d, %u, %d)\n", __func__, cpu_dai, clk_id,
  70. freq, dir);
  71. switch (clk_id) {
  72. case S3C2412_CLKSRC_PCLK:
  73. s3c2412_i2s.master = 1;
  74. iismod &= ~S3C2412_IISMOD_MASTER_MASK;
  75. iismod |= S3C2412_IISMOD_MASTER_INTERNAL;
  76. break;
  77. case S3C2412_CLKSRC_I2SCLK:
  78. s3c2412_i2s.master = 0;
  79. iismod &= ~S3C2412_IISMOD_MASTER_MASK;
  80. iismod |= S3C2412_IISMOD_MASTER_EXTERNAL;
  81. break;
  82. default:
  83. return -EINVAL;
  84. }
  85. writel(iismod, s3c2412_i2s.regs + S3C2412_IISMOD);
  86. return 0;
  87. }
  88. struct clk *s3c2412_get_iisclk(void)
  89. {
  90. return s3c2412_i2s.iis_clk;
  91. }
  92. EXPORT_SYMBOL_GPL(s3c2412_get_iisclk);
  93. static int s3c2412_i2s_probe(struct platform_device *pdev,
  94. struct snd_soc_dai *dai)
  95. {
  96. int ret;
  97. DBG("Entered %s\n", __func__);
  98. ret = s3c_i2sv2_probe(pdev, dai, &s3c2412_i2s, S3C2410_PA_IIS);
  99. if (ret)
  100. return ret;
  101. s3c2412_i2s.dma_capture = &s3c2412_i2s_pcm_stereo_in;
  102. s3c2412_i2s.dma_playback = &s3c2412_i2s_pcm_stereo_out;
  103. s3c2412_i2s.iis_cclk = clk_get(&pdev->dev, "i2sclk");
  104. if (s3c2412_i2s.iis_cclk == NULL) {
  105. DBG("failed to get i2sclk clock\n");
  106. iounmap(s3c2412_i2s.regs);
  107. return -ENODEV;
  108. }
  109. /* Set MPLL as the source for IIS CLK */
  110. clk_set_parent(s3c2412_i2s.iis_cclk, clk_get(NULL, "mpll"));
  111. clk_enable(s3c2412_i2s.iis_cclk);
  112. s3c2412_i2s.iis_cclk = s3c2412_i2s.iis_pclk;
  113. /* Configure the I2S pins in correct mode */
  114. s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
  115. s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
  116. s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
  117. s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
  118. s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
  119. return 0;
  120. }
  121. #define S3C2412_I2S_RATES \
  122. (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
  123. SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
  124. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
  125. struct snd_soc_dai s3c2412_i2s_dai = {
  126. .name = "s3c2412-i2s",
  127. .id = 0,
  128. .probe = s3c2412_i2s_probe,
  129. .playback = {
  130. .channels_min = 2,
  131. .channels_max = 2,
  132. .rates = S3C2412_I2S_RATES,
  133. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
  134. },
  135. .capture = {
  136. .channels_min = 2,
  137. .channels_max = 2,
  138. .rates = S3C2412_I2S_RATES,
  139. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,
  140. },
  141. .ops = {
  142. .set_sysclk = s3c2412_i2s_set_sysclk,
  143. },
  144. };
  145. EXPORT_SYMBOL_GPL(s3c2412_i2s_dai);
  146. static int __init s3c2412_i2s_init(void)
  147. {
  148. return s3c_i2sv2_register_dai(&s3c2412_i2s_dai);
  149. }
  150. module_init(s3c2412_i2s_init);
  151. static void __exit s3c2412_i2s_exit(void)
  152. {
  153. snd_soc_unregister_dai(&s3c2412_i2s_dai);
  154. }
  155. module_exit(s3c2412_i2s_exit);
  156. /* Module information */
  157. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  158. MODULE_DESCRIPTION("S3C2412 I2S SoC Interface");
  159. MODULE_LICENSE("GPL");