iwl3945-base.c 218 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152515351545155515651575158515951605161516251635164516551665167516851695170517151725173517451755176517751785179518051815182518351845185518651875188518951905191519251935194519551965197519851995200520152025203520452055206520752085209521052115212521352145215521652175218521952205221522252235224522552265227522852295230523152325233523452355236523752385239524052415242524352445245524652475248524952505251525252535254525552565257525852595260526152625263526452655266526752685269527052715272527352745275527652775278527952805281528252835284528552865287528852895290529152925293529452955296529752985299530053015302530353045305530653075308530953105311531253135314531553165317531853195320532153225323532453255326532753285329533053315332533353345335533653375338533953405341534253435344534553465347534853495350535153525353535453555356535753585359536053615362536353645365536653675368536953705371537253735374537553765377537853795380538153825383538453855386538753885389539053915392539353945395539653975398539954005401540254035404540554065407540854095410541154125413541454155416541754185419542054215422542354245425542654275428542954305431543254335434543554365437543854395440544154425443544454455446544754485449545054515452545354545455545654575458545954605461546254635464546554665467546854695470547154725473547454755476547754785479548054815482548354845485548654875488548954905491549254935494549554965497549854995500550155025503550455055506550755085509551055115512551355145515551655175518551955205521552255235524552555265527552855295530553155325533553455355536553755385539554055415542554355445545554655475548554955505551555255535554555555565557555855595560556155625563556455655566556755685569557055715572557355745575557655775578557955805581558255835584558555865587558855895590559155925593559455955596559755985599560056015602560356045605560656075608560956105611561256135614561556165617561856195620562156225623562456255626562756285629563056315632563356345635563656375638563956405641564256435644564556465647564856495650565156525653565456555656565756585659566056615662566356645665566656675668566956705671567256735674567556765677567856795680568156825683568456855686568756885689569056915692569356945695569656975698569957005701570257035704570557065707570857095710571157125713571457155716571757185719572057215722572357245725572657275728572957305731573257335734573557365737573857395740574157425743574457455746574757485749575057515752575357545755575657575758575957605761576257635764576557665767576857695770577157725773577457755776577757785779578057815782578357845785578657875788578957905791579257935794579557965797579857995800580158025803580458055806580758085809581058115812581358145815581658175818581958205821582258235824582558265827582858295830583158325833583458355836583758385839584058415842584358445845584658475848584958505851585258535854585558565857585858595860586158625863586458655866586758685869587058715872587358745875587658775878587958805881588258835884588558865887588858895890589158925893589458955896589758985899590059015902590359045905590659075908590959105911591259135914591559165917591859195920592159225923592459255926592759285929593059315932593359345935593659375938593959405941594259435944594559465947594859495950595159525953595459555956595759585959596059615962596359645965596659675968596959705971597259735974597559765977597859795980598159825983598459855986598759885989599059915992599359945995599659975998599960006001600260036004600560066007600860096010601160126013601460156016601760186019602060216022602360246025602660276028602960306031603260336034603560366037603860396040604160426043604460456046604760486049605060516052605360546055605660576058605960606061606260636064606560666067606860696070607160726073607460756076607760786079608060816082608360846085608660876088608960906091609260936094609560966097609860996100610161026103610461056106610761086109611061116112611361146115611661176118611961206121612261236124612561266127612861296130613161326133613461356136613761386139614061416142614361446145614661476148614961506151615261536154615561566157615861596160616161626163616461656166616761686169617061716172617361746175617661776178617961806181618261836184618561866187618861896190619161926193619461956196619761986199620062016202620362046205620662076208620962106211621262136214621562166217621862196220622162226223622462256226622762286229623062316232623362346235623662376238623962406241624262436244624562466247624862496250625162526253625462556256625762586259626062616262626362646265626662676268626962706271627262736274627562766277627862796280628162826283628462856286628762886289629062916292629362946295629662976298629963006301630263036304630563066307630863096310631163126313631463156316631763186319632063216322632363246325632663276328632963306331633263336334633563366337633863396340634163426343634463456346634763486349635063516352635363546355635663576358635963606361636263636364636563666367636863696370637163726373637463756376637763786379638063816382638363846385638663876388638963906391639263936394639563966397639863996400640164026403640464056406640764086409641064116412641364146415641664176418641964206421642264236424642564266427642864296430643164326433643464356436643764386439644064416442644364446445644664476448644964506451645264536454645564566457645864596460646164626463646464656466646764686469647064716472647364746475647664776478647964806481648264836484648564866487648864896490649164926493649464956496649764986499650065016502650365046505650665076508650965106511651265136514651565166517651865196520652165226523652465256526652765286529653065316532653365346535653665376538653965406541654265436544654565466547654865496550655165526553655465556556655765586559656065616562656365646565656665676568656965706571657265736574657565766577657865796580658165826583658465856586658765886589659065916592659365946595659665976598659966006601660266036604660566066607660866096610661166126613661466156616661766186619662066216622662366246625662666276628662966306631663266336634663566366637663866396640664166426643664466456646664766486649665066516652665366546655665666576658665966606661666266636664666566666667666866696670667166726673667466756676667766786679668066816682668366846685668666876688668966906691669266936694669566966697669866996700670167026703670467056706670767086709671067116712671367146715671667176718671967206721672267236724672567266727672867296730673167326733673467356736673767386739674067416742674367446745674667476748674967506751675267536754675567566757675867596760676167626763676467656766676767686769677067716772677367746775677667776778677967806781678267836784678567866787678867896790679167926793679467956796679767986799680068016802680368046805680668076808680968106811681268136814681568166817681868196820682168226823682468256826682768286829683068316832683368346835683668376838683968406841684268436844684568466847684868496850685168526853685468556856685768586859686068616862686368646865686668676868686968706871687268736874687568766877687868796880688168826883688468856886688768886889689068916892689368946895689668976898689969006901690269036904690569066907690869096910691169126913691469156916691769186919692069216922692369246925692669276928692969306931693269336934693569366937693869396940694169426943694469456946694769486949695069516952695369546955695669576958695969606961696269636964696569666967696869696970697169726973697469756976697769786979698069816982698369846985698669876988698969906991699269936994699569966997699869997000700170027003700470057006700770087009701070117012701370147015701670177018701970207021702270237024702570267027702870297030703170327033703470357036703770387039704070417042704370447045704670477048704970507051705270537054705570567057705870597060706170627063706470657066706770687069707070717072707370747075707670777078707970807081708270837084708570867087708870897090709170927093709470957096709770987099710071017102710371047105710671077108710971107111711271137114711571167117711871197120712171227123712471257126712771287129713071317132713371347135713671377138713971407141714271437144714571467147714871497150715171527153715471557156715771587159716071617162716371647165716671677168716971707171717271737174717571767177717871797180718171827183718471857186718771887189719071917192719371947195719671977198719972007201720272037204720572067207720872097210721172127213721472157216721772187219722072217222722372247225722672277228722972307231723272337234723572367237723872397240724172427243724472457246724772487249725072517252725372547255725672577258725972607261726272637264726572667267726872697270727172727273727472757276727772787279728072817282728372847285728672877288728972907291729272937294729572967297729872997300730173027303730473057306730773087309731073117312731373147315731673177318731973207321732273237324732573267327732873297330733173327333733473357336733773387339734073417342734373447345734673477348734973507351735273537354735573567357735873597360736173627363736473657366736773687369737073717372737373747375737673777378737973807381738273837384738573867387738873897390739173927393739473957396739773987399740074017402740374047405740674077408740974107411741274137414741574167417741874197420742174227423742474257426742774287429743074317432743374347435743674377438743974407441744274437444744574467447744874497450745174527453745474557456745774587459746074617462746374647465746674677468746974707471747274737474747574767477747874797480748174827483748474857486748774887489749074917492749374947495749674977498749975007501750275037504750575067507750875097510751175127513751475157516751775187519752075217522752375247525752675277528752975307531753275337534753575367537753875397540754175427543754475457546754775487549755075517552755375547555755675577558755975607561756275637564756575667567756875697570757175727573757475757576757775787579758075817582758375847585758675877588758975907591759275937594759575967597759875997600760176027603760476057606760776087609761076117612761376147615761676177618761976207621762276237624762576267627762876297630763176327633763476357636763776387639764076417642764376447645764676477648764976507651765276537654765576567657765876597660766176627663766476657666766776687669767076717672767376747675767676777678767976807681768276837684768576867687768876897690769176927693769476957696769776987699770077017702770377047705770677077708770977107711771277137714771577167717771877197720772177227723772477257726772777287729773077317732773377347735773677377738773977407741774277437744774577467747774877497750775177527753775477557756775777587759776077617762776377647765776677677768776977707771777277737774777577767777777877797780778177827783778477857786778777887789779077917792779377947795779677977798779978007801780278037804780578067807780878097810781178127813781478157816781778187819782078217822782378247825782678277828782978307831783278337834783578367837783878397840784178427843784478457846784778487849785078517852785378547855785678577858785978607861786278637864786578667867786878697870787178727873787478757876787778787879788078817882788378847885788678877888788978907891789278937894
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/ieee80211_radiotap.h>
  42. #include <net/lib80211.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #define DRV_NAME "iwl3945"
  46. #include "iwl-fh.h"
  47. #include "iwl-3945-fh.h"
  48. #include "iwl-commands.h"
  49. #include "iwl-3945.h"
  50. #include "iwl-helpers.h"
  51. #include "iwl-core.h"
  52. #include "iwl-dev.h"
  53. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  54. struct iwl_tx_queue *txq);
  55. /*
  56. * module name, copyright, version, etc.
  57. */
  58. #define DRV_DESCRIPTION \
  59. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  60. #ifdef CONFIG_IWL3945_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define IWL39_VERSION "1.2.26k" VD VS
  71. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  72. #define DRV_AUTHOR "<ilw@linux.intel.com>"
  73. #define DRV_VERSION IWL39_VERSION
  74. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  75. MODULE_VERSION(DRV_VERSION);
  76. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  77. MODULE_LICENSE("GPL");
  78. /* module parameters */
  79. struct iwl_mod_params iwl3945_mod_params = {
  80. .num_of_queues = IWL39_MAX_NUM_QUEUES,
  81. /* the rest are 0 by default */
  82. };
  83. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  84. * DMA services
  85. *
  86. * Theory of operation
  87. *
  88. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  89. * of buffer descriptors, each of which points to one or more data buffers for
  90. * the device to read from or fill. Driver and device exchange status of each
  91. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  92. * entries in each circular buffer, to protect against confusing empty and full
  93. * queue states.
  94. *
  95. * The device reads or writes the data in the queues via the device's several
  96. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  97. *
  98. * For Tx queue, there are low mark and high mark limits. If, after queuing
  99. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  100. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  101. * Tx queue resumed.
  102. *
  103. * The 3945 operates with six queues: One receive queue, one transmit queue
  104. * (#4) for sending commands to the device firmware, and four transmit queues
  105. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  106. ***************************************************/
  107. int iwl3945_x2_queue_used(const struct iwl_queue *q, int i)
  108. {
  109. return q->write_ptr > q->read_ptr ?
  110. (i >= q->read_ptr && i < q->write_ptr) :
  111. !(i < q->read_ptr && i >= q->write_ptr);
  112. }
  113. /**
  114. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  115. */
  116. static int iwl3945_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
  117. int count, int slots_num, u32 id)
  118. {
  119. q->n_bd = count;
  120. q->n_window = slots_num;
  121. q->id = id;
  122. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  123. * and iwl_queue_dec_wrap are broken. */
  124. BUG_ON(!is_power_of_2(count));
  125. /* slots_num must be power-of-two size, otherwise
  126. * get_cmd_index is broken. */
  127. BUG_ON(!is_power_of_2(slots_num));
  128. q->low_mark = q->n_window / 4;
  129. if (q->low_mark < 4)
  130. q->low_mark = 4;
  131. q->high_mark = q->n_window / 8;
  132. if (q->high_mark < 2)
  133. q->high_mark = 2;
  134. q->write_ptr = q->read_ptr = 0;
  135. return 0;
  136. }
  137. /**
  138. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  139. */
  140. static int iwl3945_tx_queue_alloc(struct iwl_priv *priv,
  141. struct iwl_tx_queue *txq, u32 id)
  142. {
  143. struct pci_dev *dev = priv->pci_dev;
  144. /* Driver private data, only for Tx (not command) queues,
  145. * not shared with device. */
  146. if (id != IWL_CMD_QUEUE_NUM) {
  147. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  148. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  149. if (!txq->txb) {
  150. IWL_ERR(priv, "kmalloc for auxiliary BD "
  151. "structures failed\n");
  152. goto error;
  153. }
  154. } else
  155. txq->txb = NULL;
  156. /* Circular buffer of transmit frame descriptors (TFDs),
  157. * shared with device */
  158. txq->tfds39 = pci_alloc_consistent(dev,
  159. sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX,
  160. &txq->q.dma_addr);
  161. if (!txq->tfds39) {
  162. IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n",
  163. sizeof(txq->tfds39[0]) * TFD_QUEUE_SIZE_MAX);
  164. goto error;
  165. }
  166. txq->q.id = id;
  167. return 0;
  168. error:
  169. kfree(txq->txb);
  170. txq->txb = NULL;
  171. return -ENOMEM;
  172. }
  173. /**
  174. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  175. */
  176. int iwl3945_tx_queue_init(struct iwl_priv *priv,
  177. struct iwl_tx_queue *txq, int slots_num, u32 txq_id)
  178. {
  179. int len, i;
  180. int rc = 0;
  181. /*
  182. * Alloc buffer array for commands (Tx or other types of commands).
  183. * For the command queue (#4), allocate command space + one big
  184. * command for scan, since scan command is very huge; the system will
  185. * not have two scans at the same time, so only one is needed.
  186. * For data Tx queues (all other queues), no super-size command
  187. * space is needed.
  188. */
  189. len = sizeof(struct iwl_cmd);
  190. for (i = 0; i <= slots_num; i++) {
  191. if (i == slots_num) {
  192. if (txq_id == IWL_CMD_QUEUE_NUM)
  193. len += IWL_MAX_SCAN_SIZE;
  194. else
  195. continue;
  196. }
  197. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  198. if (!txq->cmd[i])
  199. goto err;
  200. }
  201. /* Alloc driver data array and TFD circular buffer */
  202. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  203. if (rc)
  204. goto err;
  205. txq->need_update = 0;
  206. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  207. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  208. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  209. /* Initialize queue high/low-water, head/tail indexes */
  210. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  211. /* Tell device where to find queue, enable DMA channel. */
  212. iwl3945_hw_tx_queue_init(priv, txq);
  213. return 0;
  214. err:
  215. for (i = 0; i < slots_num; i++) {
  216. kfree(txq->cmd[i]);
  217. txq->cmd[i] = NULL;
  218. }
  219. if (txq_id == IWL_CMD_QUEUE_NUM) {
  220. kfree(txq->cmd[slots_num]);
  221. txq->cmd[slots_num] = NULL;
  222. }
  223. return -ENOMEM;
  224. }
  225. /**
  226. * iwl3945_tx_queue_free - Deallocate DMA queue.
  227. * @txq: Transmit queue to deallocate.
  228. *
  229. * Empty queue by removing and destroying all BD's.
  230. * Free all buffers.
  231. * 0-fill, but do not free "txq" descriptor structure.
  232. */
  233. void iwl3945_tx_queue_free(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  234. {
  235. struct iwl_queue *q = &txq->q;
  236. struct pci_dev *dev = priv->pci_dev;
  237. int len, i;
  238. if (q->n_bd == 0)
  239. return;
  240. /* first, empty all BD's */
  241. for (; q->write_ptr != q->read_ptr;
  242. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  243. iwl3945_hw_txq_free_tfd(priv, txq);
  244. len = sizeof(struct iwl_cmd) * q->n_window;
  245. if (q->id == IWL_CMD_QUEUE_NUM)
  246. len += IWL_MAX_SCAN_SIZE;
  247. /* De-alloc array of command/tx buffers */
  248. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  249. kfree(txq->cmd[i]);
  250. /* De-alloc circular buffer of TFDs */
  251. if (txq->q.n_bd)
  252. pci_free_consistent(dev, sizeof(struct iwl3945_tfd) *
  253. txq->q.n_bd, txq->tfds39, txq->q.dma_addr);
  254. /* De-alloc array of per-TFD driver data */
  255. kfree(txq->txb);
  256. txq->txb = NULL;
  257. /* 0-fill queue descriptor structure */
  258. memset(txq, 0, sizeof(*txq));
  259. }
  260. /*************** STATION TABLE MANAGEMENT ****
  261. * mac80211 should be examined to determine if sta_info is duplicating
  262. * the functionality provided here
  263. */
  264. /**************************************************************/
  265. #if 0 /* temporary disable till we add real remove station */
  266. /**
  267. * iwl3945_remove_station - Remove driver's knowledge of station.
  268. *
  269. * NOTE: This does not remove station from device's station table.
  270. */
  271. static u8 iwl3945_remove_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
  272. {
  273. int index = IWL_INVALID_STATION;
  274. int i;
  275. unsigned long flags;
  276. spin_lock_irqsave(&priv->sta_lock, flags);
  277. if (is_ap)
  278. index = IWL_AP_ID;
  279. else if (is_broadcast_ether_addr(addr))
  280. index = priv->hw_params.bcast_sta_id;
  281. else
  282. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++)
  283. if (priv->stations_39[i].used &&
  284. !compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  285. addr)) {
  286. index = i;
  287. break;
  288. }
  289. if (unlikely(index == IWL_INVALID_STATION))
  290. goto out;
  291. if (priv->stations_39[index].used) {
  292. priv->stations_39[index].used = 0;
  293. priv->num_stations--;
  294. }
  295. BUG_ON(priv->num_stations < 0);
  296. out:
  297. spin_unlock_irqrestore(&priv->sta_lock, flags);
  298. return 0;
  299. }
  300. #endif
  301. /**
  302. * iwl3945_clear_stations_table - Clear the driver's station table
  303. *
  304. * NOTE: This does not clear or otherwise alter the device's station table.
  305. */
  306. static void iwl3945_clear_stations_table(struct iwl_priv *priv)
  307. {
  308. unsigned long flags;
  309. spin_lock_irqsave(&priv->sta_lock, flags);
  310. priv->num_stations = 0;
  311. memset(priv->stations_39, 0, sizeof(priv->stations_39));
  312. spin_unlock_irqrestore(&priv->sta_lock, flags);
  313. }
  314. /**
  315. * iwl3945_add_station - Add station to station tables in driver and device
  316. */
  317. u8 iwl3945_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap, u8 flags)
  318. {
  319. int i;
  320. int index = IWL_INVALID_STATION;
  321. struct iwl3945_station_entry *station;
  322. unsigned long flags_spin;
  323. u8 rate;
  324. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  325. if (is_ap)
  326. index = IWL_AP_ID;
  327. else if (is_broadcast_ether_addr(addr))
  328. index = priv->hw_params.bcast_sta_id;
  329. else
  330. for (i = IWL_STA_ID; i < priv->hw_params.max_stations; i++) {
  331. if (!compare_ether_addr(priv->stations_39[i].sta.sta.addr,
  332. addr)) {
  333. index = i;
  334. break;
  335. }
  336. if (!priv->stations_39[i].used &&
  337. index == IWL_INVALID_STATION)
  338. index = i;
  339. }
  340. /* These two conditions has the same outcome but keep them separate
  341. since they have different meaning */
  342. if (unlikely(index == IWL_INVALID_STATION)) {
  343. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  344. return index;
  345. }
  346. if (priv->stations_39[index].used &&
  347. !compare_ether_addr(priv->stations_39[index].sta.sta.addr, addr)) {
  348. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  349. return index;
  350. }
  351. IWL_DEBUG_ASSOC("Add STA ID %d: %pM\n", index, addr);
  352. station = &priv->stations_39[index];
  353. station->used = 1;
  354. priv->num_stations++;
  355. /* Set up the REPLY_ADD_STA command to send to device */
  356. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  357. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  358. station->sta.mode = 0;
  359. station->sta.sta.sta_id = index;
  360. station->sta.station_flags = 0;
  361. if (priv->band == IEEE80211_BAND_5GHZ)
  362. rate = IWL_RATE_6M_PLCP;
  363. else
  364. rate = IWL_RATE_1M_PLCP;
  365. /* Turn on both antennas for the station... */
  366. station->sta.rate_n_flags =
  367. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  368. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  369. /* Add station to device's station table */
  370. iwl3945_send_add_station(priv, &station->sta, flags);
  371. return index;
  372. }
  373. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  374. #define IWL_CMD(x) case x: return #x
  375. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  376. /**
  377. * iwl3945_enqueue_hcmd - enqueue a uCode command
  378. * @priv: device private data point
  379. * @cmd: a point to the ucode command structure
  380. *
  381. * The function returns < 0 values to indicate the operation is
  382. * failed. On success, it turns the index (> 0) of command in the
  383. * command queue.
  384. */
  385. static int iwl3945_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  386. {
  387. struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  388. struct iwl_queue *q = &txq->q;
  389. struct iwl3945_tfd *tfd;
  390. struct iwl_cmd *out_cmd;
  391. u32 idx;
  392. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  393. dma_addr_t phys_addr;
  394. int pad;
  395. int ret, len;
  396. unsigned long flags;
  397. /* If any of the command structures end up being larger than
  398. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  399. * we will need to increase the size of the TFD entries */
  400. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  401. !(cmd->meta.flags & CMD_SIZE_HUGE));
  402. if (iwl_is_rfkill(priv)) {
  403. IWL_DEBUG_INFO("Not sending command - RF KILL");
  404. return -EIO;
  405. }
  406. if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  407. IWL_ERR(priv, "No space for Tx\n");
  408. return -ENOSPC;
  409. }
  410. spin_lock_irqsave(&priv->hcmd_lock, flags);
  411. tfd = &txq->tfds39[q->write_ptr];
  412. memset(tfd, 0, sizeof(*tfd));
  413. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  414. out_cmd = txq->cmd[idx];
  415. out_cmd->hdr.cmd = cmd->id;
  416. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  417. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  418. /* At this point, the out_cmd now has all of the incoming cmd
  419. * information */
  420. out_cmd->hdr.flags = 0;
  421. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  422. INDEX_TO_SEQ(q->write_ptr));
  423. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  424. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  425. len = (idx == TFD_CMD_SLOTS) ?
  426. IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
  427. phys_addr = pci_map_single(priv->pci_dev, out_cmd,
  428. len, PCI_DMA_TODEVICE);
  429. pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
  430. pci_unmap_len_set(&out_cmd->meta, len, len);
  431. phys_addr += offsetof(struct iwl_cmd, hdr);
  432. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  433. pad = U32_PAD(cmd->len);
  434. tfd->control_flags |= cpu_to_le32(TFD_CTL_PAD_SET(pad));
  435. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  436. "%d bytes at %d[%d]:%d\n",
  437. get_cmd_string(out_cmd->hdr.cmd),
  438. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  439. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  440. txq->need_update = 1;
  441. /* Increment and update queue's write index */
  442. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  443. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  444. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  445. return ret ? ret : idx;
  446. }
  447. static int iwl3945_send_cmd_async(struct iwl_priv *priv,
  448. struct iwl_host_cmd *cmd)
  449. {
  450. int ret;
  451. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  452. /* An asynchronous command can not expect an SKB to be set. */
  453. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  454. /* An asynchronous command MUST have a callback. */
  455. BUG_ON(!cmd->meta.u.callback);
  456. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  457. return -EBUSY;
  458. ret = iwl3945_enqueue_hcmd(priv, cmd);
  459. if (ret < 0) {
  460. IWL_ERR(priv,
  461. "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  462. get_cmd_string(cmd->id), ret);
  463. return ret;
  464. }
  465. return 0;
  466. }
  467. static int iwl3945_send_cmd_sync(struct iwl_priv *priv,
  468. struct iwl_host_cmd *cmd)
  469. {
  470. int cmd_idx;
  471. int ret;
  472. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  473. /* A synchronous command can not have a callback set. */
  474. BUG_ON(cmd->meta.u.callback != NULL);
  475. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  476. IWL_ERR(priv,
  477. "Error sending %s: Already sending a host command\n",
  478. get_cmd_string(cmd->id));
  479. ret = -EBUSY;
  480. goto out;
  481. }
  482. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  483. if (cmd->meta.flags & CMD_WANT_SKB)
  484. cmd->meta.source = &cmd->meta;
  485. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  486. if (cmd_idx < 0) {
  487. ret = cmd_idx;
  488. IWL_ERR(priv,
  489. "Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  490. get_cmd_string(cmd->id), ret);
  491. goto out;
  492. }
  493. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  494. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  495. HOST_COMPLETE_TIMEOUT);
  496. if (!ret) {
  497. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  498. IWL_ERR(priv, "Error sending %s: time out after %dms\n",
  499. get_cmd_string(cmd->id),
  500. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  501. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  502. ret = -ETIMEDOUT;
  503. goto cancel;
  504. }
  505. }
  506. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  507. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  508. get_cmd_string(cmd->id));
  509. ret = -ECANCELED;
  510. goto fail;
  511. }
  512. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  513. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  514. get_cmd_string(cmd->id));
  515. ret = -EIO;
  516. goto fail;
  517. }
  518. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  519. IWL_ERR(priv, "Error: Response NULL in '%s'\n",
  520. get_cmd_string(cmd->id));
  521. ret = -EIO;
  522. goto cancel;
  523. }
  524. ret = 0;
  525. goto out;
  526. cancel:
  527. if (cmd->meta.flags & CMD_WANT_SKB) {
  528. struct iwl_cmd *qcmd;
  529. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  530. * TX cmd queue. Otherwise in case the cmd comes
  531. * in later, it will possibly set an invalid
  532. * address (cmd->meta.source). */
  533. qcmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  534. qcmd->meta.flags &= ~CMD_WANT_SKB;
  535. }
  536. fail:
  537. if (cmd->meta.u.skb) {
  538. dev_kfree_skb_any(cmd->meta.u.skb);
  539. cmd->meta.u.skb = NULL;
  540. }
  541. out:
  542. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  543. return ret;
  544. }
  545. int iwl3945_send_cmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  546. {
  547. if (cmd->meta.flags & CMD_ASYNC)
  548. return iwl3945_send_cmd_async(priv, cmd);
  549. return iwl3945_send_cmd_sync(priv, cmd);
  550. }
  551. int iwl3945_send_cmd_pdu(struct iwl_priv *priv, u8 id, u16 len, const void *data)
  552. {
  553. struct iwl_host_cmd cmd = {
  554. .id = id,
  555. .len = len,
  556. .data = data,
  557. };
  558. return iwl3945_send_cmd_sync(priv, &cmd);
  559. }
  560. static int __must_check iwl3945_send_cmd_u32(struct iwl_priv *priv, u8 id, u32 val)
  561. {
  562. struct iwl_host_cmd cmd = {
  563. .id = id,
  564. .len = sizeof(val),
  565. .data = &val,
  566. };
  567. return iwl3945_send_cmd_sync(priv, &cmd);
  568. }
  569. int iwl3945_send_statistics_request(struct iwl_priv *priv)
  570. {
  571. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  572. }
  573. /**
  574. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  575. * @band: 2.4 or 5 GHz band
  576. * @channel: Any channel valid for the requested band
  577. * In addition to setting the staging RXON, priv->band is also set.
  578. *
  579. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  580. * in the staging RXON flag structure based on the band
  581. */
  582. static int iwl3945_set_rxon_channel(struct iwl_priv *priv,
  583. enum ieee80211_band band,
  584. u16 channel)
  585. {
  586. if (!iwl3945_get_channel_info(priv, band, channel)) {
  587. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  588. channel, band);
  589. return -EINVAL;
  590. }
  591. if ((le16_to_cpu(priv->staging39_rxon.channel) == channel) &&
  592. (priv->band == band))
  593. return 0;
  594. priv->staging39_rxon.channel = cpu_to_le16(channel);
  595. if (band == IEEE80211_BAND_5GHZ)
  596. priv->staging39_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  597. else
  598. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  599. priv->band = band;
  600. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  601. return 0;
  602. }
  603. /**
  604. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  605. *
  606. * NOTE: This is really only useful during development and can eventually
  607. * be #ifdef'd out once the driver is stable and folks aren't actively
  608. * making changes
  609. */
  610. static int iwl3945_check_rxon_cmd(struct iwl_priv *priv)
  611. {
  612. int error = 0;
  613. int counter = 1;
  614. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  615. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  616. error |= le32_to_cpu(rxon->flags &
  617. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  618. RXON_FLG_RADAR_DETECT_MSK));
  619. if (error)
  620. IWL_WARN(priv, "check 24G fields %d | %d\n",
  621. counter++, error);
  622. } else {
  623. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  624. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  625. if (error)
  626. IWL_WARN(priv, "check 52 fields %d | %d\n",
  627. counter++, error);
  628. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  629. if (error)
  630. IWL_WARN(priv, "check 52 CCK %d | %d\n",
  631. counter++, error);
  632. }
  633. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  634. if (error)
  635. IWL_WARN(priv, "check mac addr %d | %d\n", counter++, error);
  636. /* make sure basic rates 6Mbps and 1Mbps are supported */
  637. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  638. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  639. if (error)
  640. IWL_WARN(priv, "check basic rate %d | %d\n", counter++, error);
  641. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  642. if (error)
  643. IWL_WARN(priv, "check assoc id %d | %d\n", counter++, error);
  644. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  645. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  646. if (error)
  647. IWL_WARN(priv, "check CCK and short slot %d | %d\n",
  648. counter++, error);
  649. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  650. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  651. if (error)
  652. IWL_WARN(priv, "check CCK & auto detect %d | %d\n",
  653. counter++, error);
  654. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  655. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  656. if (error)
  657. IWL_WARN(priv, "check TGG and auto detect %d | %d\n",
  658. counter++, error);
  659. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  660. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  661. RXON_FLG_ANT_A_MSK)) == 0);
  662. if (error)
  663. IWL_WARN(priv, "check antenna %d %d\n", counter++, error);
  664. if (error)
  665. IWL_WARN(priv, "Tuning to channel %d\n",
  666. le16_to_cpu(rxon->channel));
  667. if (error) {
  668. IWL_ERR(priv, "Not a valid rxon_assoc_cmd field values\n");
  669. return -1;
  670. }
  671. return 0;
  672. }
  673. /**
  674. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  675. * @priv: staging_rxon is compared to active_rxon
  676. *
  677. * If the RXON structure is changing enough to require a new tune,
  678. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  679. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  680. */
  681. static int iwl3945_full_rxon_required(struct iwl_priv *priv)
  682. {
  683. /* These items are only settable from the full RXON command */
  684. if (!(iwl3945_is_associated(priv)) ||
  685. compare_ether_addr(priv->staging39_rxon.bssid_addr,
  686. priv->active39_rxon.bssid_addr) ||
  687. compare_ether_addr(priv->staging39_rxon.node_addr,
  688. priv->active39_rxon.node_addr) ||
  689. compare_ether_addr(priv->staging39_rxon.wlap_bssid_addr,
  690. priv->active39_rxon.wlap_bssid_addr) ||
  691. (priv->staging39_rxon.dev_type != priv->active39_rxon.dev_type) ||
  692. (priv->staging39_rxon.channel != priv->active39_rxon.channel) ||
  693. (priv->staging39_rxon.air_propagation !=
  694. priv->active39_rxon.air_propagation) ||
  695. (priv->staging39_rxon.assoc_id != priv->active39_rxon.assoc_id))
  696. return 1;
  697. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  698. * be updated with the RXON_ASSOC command -- however only some
  699. * flag transitions are allowed using RXON_ASSOC */
  700. /* Check if we are not switching bands */
  701. if ((priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  702. (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK))
  703. return 1;
  704. /* Check if we are switching association toggle */
  705. if ((priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  706. (priv->active39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  707. return 1;
  708. return 0;
  709. }
  710. static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
  711. {
  712. int rc = 0;
  713. struct iwl_rx_packet *res = NULL;
  714. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  715. struct iwl_host_cmd cmd = {
  716. .id = REPLY_RXON_ASSOC,
  717. .len = sizeof(rxon_assoc),
  718. .meta.flags = CMD_WANT_SKB,
  719. .data = &rxon_assoc,
  720. };
  721. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging39_rxon;
  722. const struct iwl3945_rxon_cmd *rxon2 = &priv->active39_rxon;
  723. if ((rxon1->flags == rxon2->flags) &&
  724. (rxon1->filter_flags == rxon2->filter_flags) &&
  725. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  726. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  727. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  728. return 0;
  729. }
  730. rxon_assoc.flags = priv->staging39_rxon.flags;
  731. rxon_assoc.filter_flags = priv->staging39_rxon.filter_flags;
  732. rxon_assoc.ofdm_basic_rates = priv->staging39_rxon.ofdm_basic_rates;
  733. rxon_assoc.cck_basic_rates = priv->staging39_rxon.cck_basic_rates;
  734. rxon_assoc.reserved = 0;
  735. rc = iwl3945_send_cmd_sync(priv, &cmd);
  736. if (rc)
  737. return rc;
  738. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  739. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  740. IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
  741. rc = -EIO;
  742. }
  743. priv->alloc_rxb_skb--;
  744. dev_kfree_skb_any(cmd.meta.u.skb);
  745. return rc;
  746. }
  747. /**
  748. * iwl3945_commit_rxon - commit staging_rxon to hardware
  749. *
  750. * The RXON command in staging_rxon is committed to the hardware and
  751. * the active_rxon structure is updated with the new data. This
  752. * function correctly transitions out of the RXON_ASSOC_MSK state if
  753. * a HW tune is required based on the RXON structure changes.
  754. */
  755. static int iwl3945_commit_rxon(struct iwl_priv *priv)
  756. {
  757. /* cast away the const for active_rxon in this function */
  758. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active39_rxon;
  759. int rc = 0;
  760. if (!iwl_is_alive(priv))
  761. return -1;
  762. /* always get timestamp with Rx frame */
  763. priv->staging39_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  764. /* select antenna */
  765. priv->staging39_rxon.flags &=
  766. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  767. priv->staging39_rxon.flags |= iwl3945_get_antenna_flags(priv);
  768. rc = iwl3945_check_rxon_cmd(priv);
  769. if (rc) {
  770. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  771. return -EINVAL;
  772. }
  773. /* If we don't need to send a full RXON, we can use
  774. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  775. * and other flags for the current radio configuration. */
  776. if (!iwl3945_full_rxon_required(priv)) {
  777. rc = iwl3945_send_rxon_assoc(priv);
  778. if (rc) {
  779. IWL_ERR(priv, "Error setting RXON_ASSOC "
  780. "configuration (%d).\n", rc);
  781. return rc;
  782. }
  783. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  784. return 0;
  785. }
  786. /* If we are currently associated and the new config requires
  787. * an RXON_ASSOC and the new config wants the associated mask enabled,
  788. * we must clear the associated from the active configuration
  789. * before we apply the new config */
  790. if (iwl3945_is_associated(priv) &&
  791. (priv->staging39_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  792. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  793. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  794. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  795. sizeof(struct iwl3945_rxon_cmd),
  796. &priv->active39_rxon);
  797. /* If the mask clearing failed then we set
  798. * active_rxon back to what it was previously */
  799. if (rc) {
  800. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  801. IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
  802. "configuration (%d).\n", rc);
  803. return rc;
  804. }
  805. }
  806. IWL_DEBUG_INFO("Sending RXON\n"
  807. "* with%s RXON_FILTER_ASSOC_MSK\n"
  808. "* channel = %d\n"
  809. "* bssid = %pM\n",
  810. ((priv->staging39_rxon.filter_flags &
  811. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  812. le16_to_cpu(priv->staging39_rxon.channel),
  813. priv->staging_rxon.bssid_addr);
  814. /* Apply the new configuration */
  815. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  816. sizeof(struct iwl3945_rxon_cmd), &priv->staging39_rxon);
  817. if (rc) {
  818. IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
  819. return rc;
  820. }
  821. memcpy(active_rxon, &priv->staging39_rxon, sizeof(*active_rxon));
  822. iwl3945_clear_stations_table(priv);
  823. /* If we issue a new RXON command which required a tune then we must
  824. * send a new TXPOWER command or we won't be able to Tx any frames */
  825. rc = iwl3945_hw_reg_send_txpower(priv);
  826. if (rc) {
  827. IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
  828. return rc;
  829. }
  830. /* Add the broadcast address so we can send broadcast frames */
  831. if (iwl3945_add_station(priv, iwl_bcast_addr, 0, 0) ==
  832. IWL_INVALID_STATION) {
  833. IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
  834. return -EIO;
  835. }
  836. /* If we have set the ASSOC_MSK and we are in BSS mode then
  837. * add the IWL_AP_ID to the station rate table */
  838. if (iwl3945_is_associated(priv) &&
  839. (priv->iw_mode == NL80211_IFTYPE_STATION))
  840. if (iwl3945_add_station(priv, priv->active39_rxon.bssid_addr, 1, 0)
  841. == IWL_INVALID_STATION) {
  842. IWL_ERR(priv, "Error adding AP address for transmit\n");
  843. return -EIO;
  844. }
  845. /* Init the hardware's rate fallback order based on the band */
  846. rc = iwl3945_init_hw_rate_table(priv);
  847. if (rc) {
  848. IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
  849. return -EIO;
  850. }
  851. return 0;
  852. }
  853. static int iwl3945_send_bt_config(struct iwl_priv *priv)
  854. {
  855. struct iwl_bt_cmd bt_cmd = {
  856. .flags = 3,
  857. .lead_time = 0xAA,
  858. .max_kill = 1,
  859. .kill_ack_mask = 0,
  860. .kill_cts_mask = 0,
  861. };
  862. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  863. sizeof(bt_cmd), &bt_cmd);
  864. }
  865. static int iwl3945_send_scan_abort(struct iwl_priv *priv)
  866. {
  867. int rc = 0;
  868. struct iwl_rx_packet *res;
  869. struct iwl_host_cmd cmd = {
  870. .id = REPLY_SCAN_ABORT_CMD,
  871. .meta.flags = CMD_WANT_SKB,
  872. };
  873. /* If there isn't a scan actively going on in the hardware
  874. * then we are in between scan bands and not actually
  875. * actively scanning, so don't send the abort command */
  876. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  877. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  878. return 0;
  879. }
  880. rc = iwl3945_send_cmd_sync(priv, &cmd);
  881. if (rc) {
  882. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  883. return rc;
  884. }
  885. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  886. if (res->u.status != CAN_ABORT_STATUS) {
  887. /* The scan abort will return 1 for success or
  888. * 2 for "failure". A failure condition can be
  889. * due to simply not being in an active scan which
  890. * can occur if we send the scan abort before we
  891. * the microcode has notified us that a scan is
  892. * completed. */
  893. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  894. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  895. clear_bit(STATUS_SCAN_HW, &priv->status);
  896. }
  897. dev_kfree_skb_any(cmd.meta.u.skb);
  898. return rc;
  899. }
  900. static int iwl3945_add_sta_sync_callback(struct iwl_priv *priv,
  901. struct iwl_cmd *cmd, struct sk_buff *skb)
  902. {
  903. struct iwl_rx_packet *res = NULL;
  904. if (!skb) {
  905. IWL_ERR(priv, "Error: Response NULL in REPLY_ADD_STA.\n");
  906. return 1;
  907. }
  908. res = (struct iwl_rx_packet *)skb->data;
  909. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  910. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  911. res->hdr.flags);
  912. return 1;
  913. }
  914. switch (res->u.add_sta.status) {
  915. case ADD_STA_SUCCESS_MSK:
  916. break;
  917. default:
  918. break;
  919. }
  920. /* We didn't cache the SKB; let the caller free it */
  921. return 1;
  922. }
  923. int iwl3945_send_add_station(struct iwl_priv *priv,
  924. struct iwl3945_addsta_cmd *sta, u8 flags)
  925. {
  926. struct iwl_rx_packet *res = NULL;
  927. int rc = 0;
  928. struct iwl_host_cmd cmd = {
  929. .id = REPLY_ADD_STA,
  930. .len = sizeof(struct iwl3945_addsta_cmd),
  931. .meta.flags = flags,
  932. .data = sta,
  933. };
  934. if (flags & CMD_ASYNC)
  935. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  936. else
  937. cmd.meta.flags |= CMD_WANT_SKB;
  938. rc = iwl3945_send_cmd(priv, &cmd);
  939. if (rc || (flags & CMD_ASYNC))
  940. return rc;
  941. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  942. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  943. IWL_ERR(priv, "Bad return from REPLY_ADD_STA (0x%08X)\n",
  944. res->hdr.flags);
  945. rc = -EIO;
  946. }
  947. if (rc == 0) {
  948. switch (res->u.add_sta.status) {
  949. case ADD_STA_SUCCESS_MSK:
  950. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  951. break;
  952. default:
  953. rc = -EIO;
  954. IWL_WARN(priv, "REPLY_ADD_STA failed\n");
  955. break;
  956. }
  957. }
  958. priv->alloc_rxb_skb--;
  959. dev_kfree_skb_any(cmd.meta.u.skb);
  960. return rc;
  961. }
  962. static int iwl3945_update_sta_key_info(struct iwl_priv *priv,
  963. struct ieee80211_key_conf *keyconf,
  964. u8 sta_id)
  965. {
  966. unsigned long flags;
  967. __le16 key_flags = 0;
  968. switch (keyconf->alg) {
  969. case ALG_CCMP:
  970. key_flags |= STA_KEY_FLG_CCMP;
  971. key_flags |= cpu_to_le16(
  972. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  973. key_flags &= ~STA_KEY_FLG_INVALID;
  974. break;
  975. case ALG_TKIP:
  976. case ALG_WEP:
  977. default:
  978. return -EINVAL;
  979. }
  980. spin_lock_irqsave(&priv->sta_lock, flags);
  981. priv->stations_39[sta_id].keyinfo.alg = keyconf->alg;
  982. priv->stations_39[sta_id].keyinfo.keylen = keyconf->keylen;
  983. memcpy(priv->stations_39[sta_id].keyinfo.key, keyconf->key,
  984. keyconf->keylen);
  985. memcpy(priv->stations_39[sta_id].sta.key.key, keyconf->key,
  986. keyconf->keylen);
  987. priv->stations_39[sta_id].sta.key.key_flags = key_flags;
  988. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  989. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  990. spin_unlock_irqrestore(&priv->sta_lock, flags);
  991. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  992. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  993. return 0;
  994. }
  995. static int iwl3945_clear_sta_key_info(struct iwl_priv *priv, u8 sta_id)
  996. {
  997. unsigned long flags;
  998. spin_lock_irqsave(&priv->sta_lock, flags);
  999. memset(&priv->stations_39[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1000. memset(&priv->stations_39[sta_id].sta.key, 0,
  1001. sizeof(struct iwl4965_keyinfo));
  1002. priv->stations_39[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1003. priv->stations_39[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1004. priv->stations_39[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1005. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1006. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1007. iwl3945_send_add_station(priv, &priv->stations_39[sta_id].sta, 0);
  1008. return 0;
  1009. }
  1010. static void iwl3945_clear_free_frames(struct iwl_priv *priv)
  1011. {
  1012. struct list_head *element;
  1013. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1014. priv->frames_count);
  1015. while (!list_empty(&priv->free_frames)) {
  1016. element = priv->free_frames.next;
  1017. list_del(element);
  1018. kfree(list_entry(element, struct iwl3945_frame, list));
  1019. priv->frames_count--;
  1020. }
  1021. if (priv->frames_count) {
  1022. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  1023. priv->frames_count);
  1024. priv->frames_count = 0;
  1025. }
  1026. }
  1027. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl_priv *priv)
  1028. {
  1029. struct iwl3945_frame *frame;
  1030. struct list_head *element;
  1031. if (list_empty(&priv->free_frames)) {
  1032. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1033. if (!frame) {
  1034. IWL_ERR(priv, "Could not allocate frame!\n");
  1035. return NULL;
  1036. }
  1037. priv->frames_count++;
  1038. return frame;
  1039. }
  1040. element = priv->free_frames.next;
  1041. list_del(element);
  1042. return list_entry(element, struct iwl3945_frame, list);
  1043. }
  1044. static void iwl3945_free_frame(struct iwl_priv *priv, struct iwl3945_frame *frame)
  1045. {
  1046. memset(frame, 0, sizeof(*frame));
  1047. list_add(&frame->list, &priv->free_frames);
  1048. }
  1049. unsigned int iwl3945_fill_beacon_frame(struct iwl_priv *priv,
  1050. struct ieee80211_hdr *hdr,
  1051. int left)
  1052. {
  1053. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1054. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  1055. (priv->iw_mode != NL80211_IFTYPE_AP)))
  1056. return 0;
  1057. if (priv->ibss_beacon->len > left)
  1058. return 0;
  1059. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1060. return priv->ibss_beacon->len;
  1061. }
  1062. static u8 iwl3945_rate_get_lowest_plcp(struct iwl_priv *priv)
  1063. {
  1064. u8 i;
  1065. int rate_mask;
  1066. /* Set rate mask*/
  1067. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1068. rate_mask = priv->active_rate_basic & IWL_CCK_RATES_MASK;
  1069. else
  1070. rate_mask = priv->active_rate_basic & IWL_OFDM_RATES_MASK;
  1071. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1072. i = iwl3945_rates[i].next_ieee) {
  1073. if (rate_mask & (1 << i))
  1074. return iwl3945_rates[i].plcp;
  1075. }
  1076. /* No valid rate was found. Assign the lowest one */
  1077. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  1078. return IWL_RATE_1M_PLCP;
  1079. else
  1080. return IWL_RATE_6M_PLCP;
  1081. }
  1082. static int iwl3945_send_beacon_cmd(struct iwl_priv *priv)
  1083. {
  1084. struct iwl3945_frame *frame;
  1085. unsigned int frame_size;
  1086. int rc;
  1087. u8 rate;
  1088. frame = iwl3945_get_free_frame(priv);
  1089. if (!frame) {
  1090. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  1091. "command.\n");
  1092. return -ENOMEM;
  1093. }
  1094. rate = iwl3945_rate_get_lowest_plcp(priv);
  1095. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1096. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1097. &frame->u.cmd[0]);
  1098. iwl3945_free_frame(priv, frame);
  1099. return rc;
  1100. }
  1101. /******************************************************************************
  1102. *
  1103. * EEPROM related functions
  1104. *
  1105. ******************************************************************************/
  1106. static void get_eeprom_mac(struct iwl_priv *priv, u8 *mac)
  1107. {
  1108. memcpy(mac, priv->eeprom39.mac_address, 6);
  1109. }
  1110. /*
  1111. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1112. * embedded controller) as EEPROM reader; each read is a series of pulses
  1113. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1114. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1115. * simply claims ownership, which should be safe when this function is called
  1116. * (i.e. before loading uCode!).
  1117. */
  1118. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
  1119. {
  1120. _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1121. return 0;
  1122. }
  1123. /**
  1124. * iwl3945_eeprom_init - read EEPROM contents
  1125. *
  1126. * Load the EEPROM contents from adapter into priv->eeprom39
  1127. *
  1128. * NOTE: This routine uses the non-debug IO access functions.
  1129. */
  1130. int iwl3945_eeprom_init(struct iwl_priv *priv)
  1131. {
  1132. u16 *e = (u16 *)&priv->eeprom39;
  1133. u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
  1134. int sz = sizeof(priv->eeprom39);
  1135. int ret;
  1136. u16 addr;
  1137. /* The EEPROM structure has several padding buffers within it
  1138. * and when adding new EEPROM maps is subject to programmer errors
  1139. * which may be very difficult to identify without explicitly
  1140. * checking the resulting size of the eeprom map. */
  1141. BUILD_BUG_ON(sizeof(priv->eeprom39) != IWL_EEPROM_IMAGE_SIZE);
  1142. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1143. IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
  1144. return -ENOENT;
  1145. }
  1146. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1147. ret = iwl3945_eeprom_acquire_semaphore(priv);
  1148. if (ret < 0) {
  1149. IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
  1150. return -ENOENT;
  1151. }
  1152. /* eeprom is an array of 16bit values */
  1153. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1154. u32 r;
  1155. _iwl_write32(priv, CSR_EEPROM_REG,
  1156. CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
  1157. _iwl_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1158. ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
  1159. CSR_EEPROM_REG_READ_VALID_MSK,
  1160. IWL_EEPROM_ACCESS_TIMEOUT);
  1161. if (ret < 0) {
  1162. IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
  1163. return ret;
  1164. }
  1165. r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
  1166. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1167. }
  1168. return 0;
  1169. }
  1170. static void iwl3945_unset_hw_params(struct iwl_priv *priv)
  1171. {
  1172. if (priv->shared_virt)
  1173. pci_free_consistent(priv->pci_dev,
  1174. sizeof(struct iwl3945_shared),
  1175. priv->shared_virt,
  1176. priv->shared_phys);
  1177. }
  1178. /**
  1179. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1180. *
  1181. * return : set the bit for each supported rate insert in ie
  1182. */
  1183. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1184. u16 basic_rate, int *left)
  1185. {
  1186. u16 ret_rates = 0, bit;
  1187. int i;
  1188. u8 *cnt = ie;
  1189. u8 *rates = ie + 1;
  1190. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1191. if (bit & supported_rate) {
  1192. ret_rates |= bit;
  1193. rates[*cnt] = iwl3945_rates[i].ieee |
  1194. ((bit & basic_rate) ? 0x80 : 0x00);
  1195. (*cnt)++;
  1196. (*left)--;
  1197. if ((*left <= 0) ||
  1198. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1199. break;
  1200. }
  1201. }
  1202. return ret_rates;
  1203. }
  1204. /**
  1205. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1206. */
  1207. static u16 iwl3945_fill_probe_req(struct iwl_priv *priv,
  1208. struct ieee80211_mgmt *frame,
  1209. int left)
  1210. {
  1211. int len = 0;
  1212. u8 *pos = NULL;
  1213. u16 active_rates, ret_rates, cck_rates;
  1214. /* Make sure there is enough space for the probe request,
  1215. * two mandatory IEs and the data */
  1216. left -= 24;
  1217. if (left < 0)
  1218. return 0;
  1219. len += 24;
  1220. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1221. memcpy(frame->da, iwl_bcast_addr, ETH_ALEN);
  1222. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1223. memcpy(frame->bssid, iwl_bcast_addr, ETH_ALEN);
  1224. frame->seq_ctrl = 0;
  1225. /* fill in our indirect SSID IE */
  1226. /* ...next IE... */
  1227. left -= 2;
  1228. if (left < 0)
  1229. return 0;
  1230. len += 2;
  1231. pos = &(frame->u.probe_req.variable[0]);
  1232. *pos++ = WLAN_EID_SSID;
  1233. *pos++ = 0;
  1234. /* fill in supported rate */
  1235. /* ...next IE... */
  1236. left -= 2;
  1237. if (left < 0)
  1238. return 0;
  1239. /* ... fill it in... */
  1240. *pos++ = WLAN_EID_SUPP_RATES;
  1241. *pos = 0;
  1242. priv->active_rate = priv->rates_mask;
  1243. active_rates = priv->active_rate;
  1244. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1245. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1246. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1247. priv->active_rate_basic, &left);
  1248. active_rates &= ~ret_rates;
  1249. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1250. priv->active_rate_basic, &left);
  1251. active_rates &= ~ret_rates;
  1252. len += 2 + *pos;
  1253. pos += (*pos) + 1;
  1254. if (active_rates == 0)
  1255. goto fill_end;
  1256. /* fill in supported extended rate */
  1257. /* ...next IE... */
  1258. left -= 2;
  1259. if (left < 0)
  1260. return 0;
  1261. /* ... fill it in... */
  1262. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1263. *pos = 0;
  1264. iwl3945_supported_rate_to_ie(pos, active_rates,
  1265. priv->active_rate_basic, &left);
  1266. if (*pos > 0)
  1267. len += 2 + *pos;
  1268. fill_end:
  1269. return (u16)len;
  1270. }
  1271. /*
  1272. * QoS support
  1273. */
  1274. static int iwl3945_send_qos_params_command(struct iwl_priv *priv,
  1275. struct iwl_qosparam_cmd *qos)
  1276. {
  1277. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1278. sizeof(struct iwl_qosparam_cmd), qos);
  1279. }
  1280. static void iwl3945_activate_qos(struct iwl_priv *priv, u8 force)
  1281. {
  1282. unsigned long flags;
  1283. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1284. return;
  1285. spin_lock_irqsave(&priv->lock, flags);
  1286. priv->qos_data.def_qos_parm.qos_flags = 0;
  1287. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1288. !priv->qos_data.qos_cap.q_AP.txop_request)
  1289. priv->qos_data.def_qos_parm.qos_flags |=
  1290. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1291. if (priv->qos_data.qos_active)
  1292. priv->qos_data.def_qos_parm.qos_flags |=
  1293. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1294. spin_unlock_irqrestore(&priv->lock, flags);
  1295. if (force || iwl3945_is_associated(priv)) {
  1296. IWL_DEBUG_QOS("send QoS cmd with QoS active %d \n",
  1297. priv->qos_data.qos_active);
  1298. iwl3945_send_qos_params_command(priv,
  1299. &(priv->qos_data.def_qos_parm));
  1300. }
  1301. }
  1302. /*
  1303. * Power management (not Tx power!) functions
  1304. */
  1305. #define MSEC_TO_USEC 1024
  1306. #define NOSLP __constant_cpu_to_le16(0), 0, 0
  1307. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK, 0, 0
  1308. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1309. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1310. __constant_cpu_to_le32(X1), \
  1311. __constant_cpu_to_le32(X2), \
  1312. __constant_cpu_to_le32(X3), \
  1313. __constant_cpu_to_le32(X4)}
  1314. /* default power management (not Tx power) table values */
  1315. /* for TIM 0-10 */
  1316. static struct iwl_power_vec_entry range_0[IWL39_POWER_AC] = {
  1317. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1318. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1319. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1320. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1321. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1322. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1323. };
  1324. /* for TIM > 10 */
  1325. static struct iwl_power_vec_entry range_1[IWL39_POWER_AC] = {
  1326. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1327. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1328. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1329. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1330. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1331. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1332. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1333. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1334. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1335. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1336. };
  1337. int iwl3945_power_init_handle(struct iwl_priv *priv)
  1338. {
  1339. int rc = 0, i;
  1340. struct iwl3945_power_mgr *pow_data;
  1341. int size = sizeof(struct iwl_power_vec_entry) * IWL39_POWER_AC;
  1342. u16 pci_pm;
  1343. IWL_DEBUG_POWER("Initialize power \n");
  1344. pow_data = &(priv->power_data_39);
  1345. memset(pow_data, 0, sizeof(*pow_data));
  1346. pow_data->active_index = IWL_POWER_RANGE_0;
  1347. pow_data->dtim_val = 0xffff;
  1348. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1349. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1350. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1351. if (rc != 0)
  1352. return 0;
  1353. else {
  1354. struct iwl_powertable_cmd *cmd;
  1355. IWL_DEBUG_POWER("adjust power command flags\n");
  1356. for (i = 0; i < IWL39_POWER_AC; i++) {
  1357. cmd = &pow_data->pwr_range_0[i].cmd;
  1358. if (pci_pm & 0x1)
  1359. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1360. else
  1361. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1362. }
  1363. }
  1364. return rc;
  1365. }
  1366. static int iwl3945_update_power_cmd(struct iwl_priv *priv,
  1367. struct iwl_powertable_cmd *cmd, u32 mode)
  1368. {
  1369. int rc = 0, i;
  1370. u8 skip;
  1371. u32 max_sleep = 0;
  1372. struct iwl_power_vec_entry *range;
  1373. u8 period = 0;
  1374. struct iwl3945_power_mgr *pow_data;
  1375. if (mode > IWL_POWER_INDEX_5) {
  1376. IWL_DEBUG_POWER("Error invalid power mode \n");
  1377. return -1;
  1378. }
  1379. pow_data = &(priv->power_data_39);
  1380. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1381. range = &pow_data->pwr_range_0[0];
  1382. else
  1383. range = &pow_data->pwr_range_1[1];
  1384. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1385. #ifdef IWL_MAC80211_DISABLE
  1386. if (priv->assoc_network != NULL) {
  1387. unsigned long flags;
  1388. period = priv->assoc_network->tim.tim_period;
  1389. }
  1390. #endif /*IWL_MAC80211_DISABLE */
  1391. skip = range[mode].no_dtim;
  1392. if (period == 0) {
  1393. period = 1;
  1394. skip = 0;
  1395. }
  1396. if (skip == 0) {
  1397. max_sleep = period;
  1398. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1399. } else {
  1400. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1401. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1402. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1403. }
  1404. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1405. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1406. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1407. }
  1408. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1409. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1410. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1411. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1412. le32_to_cpu(cmd->sleep_interval[0]),
  1413. le32_to_cpu(cmd->sleep_interval[1]),
  1414. le32_to_cpu(cmd->sleep_interval[2]),
  1415. le32_to_cpu(cmd->sleep_interval[3]),
  1416. le32_to_cpu(cmd->sleep_interval[4]));
  1417. return rc;
  1418. }
  1419. static int iwl3945_send_power_mode(struct iwl_priv *priv, u32 mode)
  1420. {
  1421. u32 uninitialized_var(final_mode);
  1422. int rc;
  1423. struct iwl_powertable_cmd cmd;
  1424. /* If on battery, set to 3,
  1425. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1426. * else user level */
  1427. switch (mode) {
  1428. case IWL39_POWER_BATTERY:
  1429. final_mode = IWL_POWER_INDEX_3;
  1430. break;
  1431. case IWL39_POWER_AC:
  1432. final_mode = IWL_POWER_MODE_CAM;
  1433. break;
  1434. default:
  1435. final_mode = mode;
  1436. break;
  1437. }
  1438. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1439. /* FIXME use get_hcmd_size 3945 command is 4 bytes shorter */
  1440. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD,
  1441. sizeof(struct iwl3945_powertable_cmd), &cmd);
  1442. if (final_mode == IWL_POWER_MODE_CAM)
  1443. clear_bit(STATUS_POWER_PMI, &priv->status);
  1444. else
  1445. set_bit(STATUS_POWER_PMI, &priv->status);
  1446. return rc;
  1447. }
  1448. /**
  1449. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1450. *
  1451. * NOTE: priv->mutex is not required before calling this function
  1452. */
  1453. static int iwl3945_scan_cancel(struct iwl_priv *priv)
  1454. {
  1455. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1456. clear_bit(STATUS_SCANNING, &priv->status);
  1457. return 0;
  1458. }
  1459. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1460. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1461. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1462. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1463. queue_work(priv->workqueue, &priv->abort_scan);
  1464. } else
  1465. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1466. return test_bit(STATUS_SCANNING, &priv->status);
  1467. }
  1468. return 0;
  1469. }
  1470. /**
  1471. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1472. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1473. *
  1474. * NOTE: priv->mutex must be held before calling this function
  1475. */
  1476. static int iwl3945_scan_cancel_timeout(struct iwl_priv *priv, unsigned long ms)
  1477. {
  1478. unsigned long now = jiffies;
  1479. int ret;
  1480. ret = iwl3945_scan_cancel(priv);
  1481. if (ret && ms) {
  1482. mutex_unlock(&priv->mutex);
  1483. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1484. test_bit(STATUS_SCANNING, &priv->status))
  1485. msleep(1);
  1486. mutex_lock(&priv->mutex);
  1487. return test_bit(STATUS_SCANNING, &priv->status);
  1488. }
  1489. return ret;
  1490. }
  1491. #define MAX_UCODE_BEACON_INTERVAL 1024
  1492. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1493. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1494. {
  1495. u16 new_val = 0;
  1496. u16 beacon_factor = 0;
  1497. beacon_factor =
  1498. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1499. / MAX_UCODE_BEACON_INTERVAL;
  1500. new_val = beacon_val / beacon_factor;
  1501. return cpu_to_le16(new_val);
  1502. }
  1503. static void iwl3945_setup_rxon_timing(struct iwl_priv *priv)
  1504. {
  1505. u64 interval_tm_unit;
  1506. u64 tsf, result;
  1507. unsigned long flags;
  1508. struct ieee80211_conf *conf = NULL;
  1509. u16 beacon_int = 0;
  1510. conf = ieee80211_get_hw_conf(priv->hw);
  1511. spin_lock_irqsave(&priv->lock, flags);
  1512. priv->rxon_timing.timestamp = cpu_to_le64(priv->timestamp);
  1513. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1514. tsf = priv->timestamp;
  1515. beacon_int = priv->beacon_int;
  1516. spin_unlock_irqrestore(&priv->lock, flags);
  1517. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  1518. if (beacon_int == 0) {
  1519. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1520. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1521. } else {
  1522. priv->rxon_timing.beacon_interval =
  1523. cpu_to_le16(beacon_int);
  1524. priv->rxon_timing.beacon_interval =
  1525. iwl3945_adjust_beacon_interval(
  1526. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1527. }
  1528. priv->rxon_timing.atim_window = 0;
  1529. } else {
  1530. priv->rxon_timing.beacon_interval =
  1531. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1532. /* TODO: we need to get atim_window from upper stack
  1533. * for now we set to 0 */
  1534. priv->rxon_timing.atim_window = 0;
  1535. }
  1536. interval_tm_unit =
  1537. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1538. result = do_div(tsf, interval_tm_unit);
  1539. priv->rxon_timing.beacon_init_val =
  1540. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1541. IWL_DEBUG_ASSOC
  1542. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1543. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1544. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1545. le16_to_cpu(priv->rxon_timing.atim_window));
  1546. }
  1547. static int iwl3945_scan_initiate(struct iwl_priv *priv)
  1548. {
  1549. if (!iwl_is_ready_rf(priv)) {
  1550. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1551. return -EIO;
  1552. }
  1553. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1554. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1555. return -EAGAIN;
  1556. }
  1557. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1558. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1559. "Queuing.\n");
  1560. return -EAGAIN;
  1561. }
  1562. IWL_DEBUG_INFO("Starting scan...\n");
  1563. if (priv->cfg->sku & IWL_SKU_G)
  1564. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1565. if (priv->cfg->sku & IWL_SKU_A)
  1566. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1567. set_bit(STATUS_SCANNING, &priv->status);
  1568. priv->scan_start = jiffies;
  1569. priv->scan_pass_start = priv->scan_start;
  1570. queue_work(priv->workqueue, &priv->request_scan);
  1571. return 0;
  1572. }
  1573. static int iwl3945_set_rxon_hwcrypto(struct iwl_priv *priv, int hw_decrypt)
  1574. {
  1575. struct iwl3945_rxon_cmd *rxon = &priv->staging39_rxon;
  1576. if (hw_decrypt)
  1577. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1578. else
  1579. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1580. return 0;
  1581. }
  1582. static void iwl3945_set_flags_for_phymode(struct iwl_priv *priv,
  1583. enum ieee80211_band band)
  1584. {
  1585. if (band == IEEE80211_BAND_5GHZ) {
  1586. priv->staging39_rxon.flags &=
  1587. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1588. | RXON_FLG_CCK_MSK);
  1589. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1590. } else {
  1591. /* Copied from iwl3945_bg_post_associate() */
  1592. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1593. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1594. else
  1595. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1596. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1597. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1598. priv->staging39_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1599. priv->staging39_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1600. priv->staging39_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1601. }
  1602. }
  1603. /*
  1604. * initialize rxon structure with default values from eeprom
  1605. */
  1606. static void iwl3945_connection_init_rx_config(struct iwl_priv *priv,
  1607. int mode)
  1608. {
  1609. const struct iwl_channel_info *ch_info;
  1610. memset(&priv->staging39_rxon, 0, sizeof(priv->staging39_rxon));
  1611. switch (mode) {
  1612. case NL80211_IFTYPE_AP:
  1613. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_AP;
  1614. break;
  1615. case NL80211_IFTYPE_STATION:
  1616. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1617. priv->staging39_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1618. break;
  1619. case NL80211_IFTYPE_ADHOC:
  1620. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1621. priv->staging39_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1622. priv->staging39_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1623. RXON_FILTER_ACCEPT_GRP_MSK;
  1624. break;
  1625. case NL80211_IFTYPE_MONITOR:
  1626. priv->staging39_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1627. priv->staging39_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1628. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1629. break;
  1630. default:
  1631. IWL_ERR(priv, "Unsupported interface type %d\n", mode);
  1632. break;
  1633. }
  1634. #if 0
  1635. /* TODO: Figure out when short_preamble would be set and cache from
  1636. * that */
  1637. if (!hw_to_local(priv->hw)->short_preamble)
  1638. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1639. else
  1640. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1641. #endif
  1642. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1643. le16_to_cpu(priv->active39_rxon.channel));
  1644. if (!ch_info)
  1645. ch_info = &priv->channel_info[0];
  1646. /*
  1647. * in some case A channels are all non IBSS
  1648. * in this case force B/G channel
  1649. */
  1650. if ((mode == NL80211_IFTYPE_ADHOC) && !(is_channel_ibss(ch_info)))
  1651. ch_info = &priv->channel_info[0];
  1652. priv->staging39_rxon.channel = cpu_to_le16(ch_info->channel);
  1653. if (is_channel_a_band(ch_info))
  1654. priv->band = IEEE80211_BAND_5GHZ;
  1655. else
  1656. priv->band = IEEE80211_BAND_2GHZ;
  1657. iwl3945_set_flags_for_phymode(priv, priv->band);
  1658. priv->staging39_rxon.ofdm_basic_rates =
  1659. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1660. priv->staging39_rxon.cck_basic_rates =
  1661. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1662. }
  1663. static int iwl3945_set_mode(struct iwl_priv *priv, int mode)
  1664. {
  1665. if (mode == NL80211_IFTYPE_ADHOC) {
  1666. const struct iwl_channel_info *ch_info;
  1667. ch_info = iwl3945_get_channel_info(priv,
  1668. priv->band,
  1669. le16_to_cpu(priv->staging39_rxon.channel));
  1670. if (!ch_info || !is_channel_ibss(ch_info)) {
  1671. IWL_ERR(priv, "channel %d not IBSS channel\n",
  1672. le16_to_cpu(priv->staging39_rxon.channel));
  1673. return -EINVAL;
  1674. }
  1675. }
  1676. iwl3945_connection_init_rx_config(priv, mode);
  1677. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1678. iwl3945_clear_stations_table(priv);
  1679. /* don't commit rxon if rf-kill is on*/
  1680. if (!iwl_is_ready_rf(priv))
  1681. return -EAGAIN;
  1682. cancel_delayed_work(&priv->scan_check);
  1683. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1684. IWL_WARN(priv, "Aborted scan still in progress after 100ms\n");
  1685. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1686. return -EAGAIN;
  1687. }
  1688. iwl3945_commit_rxon(priv);
  1689. return 0;
  1690. }
  1691. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl_priv *priv,
  1692. struct ieee80211_tx_info *info,
  1693. struct iwl_cmd *cmd,
  1694. struct sk_buff *skb_frag,
  1695. int last_frag)
  1696. {
  1697. struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  1698. struct iwl3945_hw_key *keyinfo =
  1699. &priv->stations_39[info->control.hw_key->hw_key_idx].keyinfo;
  1700. switch (keyinfo->alg) {
  1701. case ALG_CCMP:
  1702. tx->sec_ctl = TX_CMD_SEC_CCM;
  1703. memcpy(tx->key, keyinfo->key, keyinfo->keylen);
  1704. IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
  1705. break;
  1706. case ALG_TKIP:
  1707. #if 0
  1708. tx->sec_ctl = TX_CMD_SEC_TKIP;
  1709. if (last_frag)
  1710. memcpy(tx->tkip_mic.byte, skb_frag->tail - 8,
  1711. 8);
  1712. else
  1713. memset(tx->tkip_mic.byte, 0, 8);
  1714. #endif
  1715. break;
  1716. case ALG_WEP:
  1717. tx->sec_ctl = TX_CMD_SEC_WEP |
  1718. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  1719. if (keyinfo->keylen == 13)
  1720. tx->sec_ctl |= TX_CMD_SEC_KEY128;
  1721. memcpy(&tx->key[3], keyinfo->key, keyinfo->keylen);
  1722. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  1723. "with key %d\n", info->control.hw_key->hw_key_idx);
  1724. break;
  1725. default:
  1726. IWL_ERR(priv, "Unknown encode alg %d\n", keyinfo->alg);
  1727. break;
  1728. }
  1729. }
  1730. /*
  1731. * handle build REPLY_TX command notification.
  1732. */
  1733. static void iwl3945_build_tx_cmd_basic(struct iwl_priv *priv,
  1734. struct iwl_cmd *cmd,
  1735. struct ieee80211_tx_info *info,
  1736. struct ieee80211_hdr *hdr, u8 std_id)
  1737. {
  1738. struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
  1739. __le32 tx_flags = tx->tx_flags;
  1740. __le16 fc = hdr->frame_control;
  1741. u8 rc_flags = info->control.rates[0].flags;
  1742. tx->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1743. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  1744. tx_flags |= TX_CMD_FLG_ACK_MSK;
  1745. if (ieee80211_is_mgmt(fc))
  1746. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1747. if (ieee80211_is_probe_resp(fc) &&
  1748. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  1749. tx_flags |= TX_CMD_FLG_TSF_MSK;
  1750. } else {
  1751. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  1752. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1753. }
  1754. tx->sta_id = std_id;
  1755. if (ieee80211_has_morefrags(fc))
  1756. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  1757. if (ieee80211_is_data_qos(fc)) {
  1758. u8 *qc = ieee80211_get_qos_ctl(hdr);
  1759. tx->tid_tspec = qc[0] & 0xf;
  1760. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  1761. } else {
  1762. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  1763. }
  1764. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1765. tx_flags |= TX_CMD_FLG_RTS_MSK;
  1766. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  1767. } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1768. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  1769. tx_flags |= TX_CMD_FLG_CTS_MSK;
  1770. }
  1771. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  1772. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  1773. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  1774. if (ieee80211_is_mgmt(fc)) {
  1775. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  1776. tx->timeout.pm_frame_timeout = cpu_to_le16(3);
  1777. else
  1778. tx->timeout.pm_frame_timeout = cpu_to_le16(2);
  1779. } else {
  1780. tx->timeout.pm_frame_timeout = 0;
  1781. #ifdef CONFIG_IWL3945_LEDS
  1782. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  1783. #endif
  1784. }
  1785. tx->driver_txop = 0;
  1786. tx->tx_flags = tx_flags;
  1787. tx->next_frame_len = 0;
  1788. }
  1789. /**
  1790. * iwl3945_get_sta_id - Find station's index within station table
  1791. */
  1792. static int iwl3945_get_sta_id(struct iwl_priv *priv, struct ieee80211_hdr *hdr)
  1793. {
  1794. int sta_id;
  1795. u16 fc = le16_to_cpu(hdr->frame_control);
  1796. /* If this frame is broadcast or management, use broadcast station id */
  1797. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  1798. is_multicast_ether_addr(hdr->addr1))
  1799. return priv->hw_params.bcast_sta_id;
  1800. switch (priv->iw_mode) {
  1801. /* If we are a client station in a BSS network, use the special
  1802. * AP station entry (that's the only station we communicate with) */
  1803. case NL80211_IFTYPE_STATION:
  1804. return IWL_AP_ID;
  1805. /* If we are an AP, then find the station, or use BCAST */
  1806. case NL80211_IFTYPE_AP:
  1807. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1808. if (sta_id != IWL_INVALID_STATION)
  1809. return sta_id;
  1810. return priv->hw_params.bcast_sta_id;
  1811. /* If this frame is going out to an IBSS network, find the station,
  1812. * or create a new station table entry */
  1813. case NL80211_IFTYPE_ADHOC: {
  1814. /* Create new station table entry */
  1815. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  1816. if (sta_id != IWL_INVALID_STATION)
  1817. return sta_id;
  1818. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  1819. if (sta_id != IWL_INVALID_STATION)
  1820. return sta_id;
  1821. IWL_DEBUG_DROP("Station %pM not in station map. "
  1822. "Defaulting to broadcast...\n",
  1823. hdr->addr1);
  1824. iwl_print_hex_dump(priv, IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  1825. return priv->hw_params.bcast_sta_id;
  1826. }
  1827. /* If we are in monitor mode, use BCAST. This is required for
  1828. * packet injection. */
  1829. case NL80211_IFTYPE_MONITOR:
  1830. return priv->hw_params.bcast_sta_id;
  1831. default:
  1832. IWL_WARN(priv, "Unknown mode of operation: %d\n",
  1833. priv->iw_mode);
  1834. return priv->hw_params.bcast_sta_id;
  1835. }
  1836. }
  1837. /*
  1838. * start REPLY_TX command process
  1839. */
  1840. static int iwl3945_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
  1841. {
  1842. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1843. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1844. struct iwl3945_tfd *tfd;
  1845. struct iwl3945_tx_cmd *tx;
  1846. struct iwl_tx_queue *txq = NULL;
  1847. struct iwl_queue *q = NULL;
  1848. struct iwl_cmd *out_cmd = NULL;
  1849. dma_addr_t phys_addr;
  1850. dma_addr_t txcmd_phys;
  1851. int txq_id = skb_get_queue_mapping(skb);
  1852. u16 len, idx, len_org, hdr_len;
  1853. u8 id;
  1854. u8 unicast;
  1855. u8 sta_id;
  1856. u8 tid = 0;
  1857. u16 seq_number = 0;
  1858. __le16 fc;
  1859. u8 wait_write_ptr = 0;
  1860. u8 *qc = NULL;
  1861. unsigned long flags;
  1862. int rc;
  1863. spin_lock_irqsave(&priv->lock, flags);
  1864. if (iwl_is_rfkill(priv)) {
  1865. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  1866. goto drop_unlock;
  1867. }
  1868. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  1869. IWL_ERR(priv, "ERROR: No TX rate available.\n");
  1870. goto drop_unlock;
  1871. }
  1872. unicast = !is_multicast_ether_addr(hdr->addr1);
  1873. id = 0;
  1874. fc = hdr->frame_control;
  1875. #ifdef CONFIG_IWL3945_DEBUG
  1876. if (ieee80211_is_auth(fc))
  1877. IWL_DEBUG_TX("Sending AUTH frame\n");
  1878. else if (ieee80211_is_assoc_req(fc))
  1879. IWL_DEBUG_TX("Sending ASSOC frame\n");
  1880. else if (ieee80211_is_reassoc_req(fc))
  1881. IWL_DEBUG_TX("Sending REASSOC frame\n");
  1882. #endif
  1883. /* drop all data frame if we are not associated */
  1884. if (ieee80211_is_data(fc) &&
  1885. (priv->iw_mode != NL80211_IFTYPE_MONITOR) && /* packet injection */
  1886. (!iwl3945_is_associated(priv) ||
  1887. ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id))) {
  1888. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  1889. goto drop_unlock;
  1890. }
  1891. spin_unlock_irqrestore(&priv->lock, flags);
  1892. hdr_len = ieee80211_hdrlen(fc);
  1893. /* Find (or create) index into station table for destination station */
  1894. sta_id = iwl3945_get_sta_id(priv, hdr);
  1895. if (sta_id == IWL_INVALID_STATION) {
  1896. IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
  1897. hdr->addr1);
  1898. goto drop;
  1899. }
  1900. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  1901. if (ieee80211_is_data_qos(fc)) {
  1902. qc = ieee80211_get_qos_ctl(hdr);
  1903. tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
  1904. seq_number = priv->stations_39[sta_id].tid[tid].seq_number &
  1905. IEEE80211_SCTL_SEQ;
  1906. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  1907. (hdr->seq_ctrl &
  1908. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  1909. seq_number += 0x10;
  1910. }
  1911. /* Descriptor for chosen Tx queue */
  1912. txq = &priv->txq[txq_id];
  1913. q = &txq->q;
  1914. spin_lock_irqsave(&priv->lock, flags);
  1915. /* Set up first empty TFD within this queue's circular TFD buffer */
  1916. tfd = &txq->tfds39[q->write_ptr];
  1917. memset(tfd, 0, sizeof(*tfd));
  1918. idx = get_cmd_index(q, q->write_ptr, 0);
  1919. /* Set up driver data for this TFD */
  1920. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
  1921. txq->txb[q->write_ptr].skb[0] = skb;
  1922. /* Init first empty entry in queue's array of Tx/cmd buffers */
  1923. out_cmd = txq->cmd[idx];
  1924. tx = (struct iwl3945_tx_cmd *)out_cmd->cmd.payload;
  1925. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  1926. memset(tx, 0, sizeof(*tx));
  1927. /*
  1928. * Set up the Tx-command (not MAC!) header.
  1929. * Store the chosen Tx queue and TFD index within the sequence field;
  1930. * after Tx, uCode's Tx response will return this value so driver can
  1931. * locate the frame within the tx queue and do post-tx processing.
  1932. */
  1933. out_cmd->hdr.cmd = REPLY_TX;
  1934. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  1935. INDEX_TO_SEQ(q->write_ptr)));
  1936. /* Copy MAC header from skb into command buffer */
  1937. memcpy(tx->hdr, hdr, hdr_len);
  1938. /*
  1939. * Use the first empty entry in this queue's command buffer array
  1940. * to contain the Tx command and MAC header concatenated together
  1941. * (payload data will be in another buffer).
  1942. * Size of this varies, due to varying MAC header length.
  1943. * If end is not dword aligned, we'll have 2 extra bytes at the end
  1944. * of the MAC header (device reads on dword boundaries).
  1945. * We'll tell device about this padding later.
  1946. */
  1947. len = sizeof(struct iwl3945_tx_cmd) +
  1948. sizeof(struct iwl_cmd_header) + hdr_len;
  1949. len_org = len;
  1950. len = (len + 3) & ~3;
  1951. if (len_org != len)
  1952. len_org = 1;
  1953. else
  1954. len_org = 0;
  1955. /* Physical address of this Tx command's header (not MAC header!),
  1956. * within command buffer array. */
  1957. txcmd_phys = pci_map_single(priv->pci_dev,
  1958. out_cmd, sizeof(struct iwl_cmd),
  1959. PCI_DMA_TODEVICE);
  1960. pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
  1961. pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
  1962. /* Add buffer containing Tx command and MAC(!) header to TFD's
  1963. * first entry */
  1964. txcmd_phys += offsetof(struct iwl_cmd, hdr);
  1965. /* Add buffer containing Tx command and MAC(!) header to TFD's
  1966. * first entry */
  1967. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  1968. if (info->control.hw_key)
  1969. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  1970. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  1971. * if any (802.11 null frames have no payload). */
  1972. len = skb->len - hdr_len;
  1973. if (len) {
  1974. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  1975. len, PCI_DMA_TODEVICE);
  1976. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  1977. }
  1978. if (!len)
  1979. /* If there is no payload, then we use only one Tx buffer */
  1980. tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(1));
  1981. else
  1982. /* Else use 2 buffers.
  1983. * Tell 3945 about any padding after MAC header */
  1984. tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(2) |
  1985. TFD_CTL_PAD_SET(U32_PAD(len)));
  1986. /* Total # bytes to be transmitted */
  1987. len = (u16)skb->len;
  1988. tx->len = cpu_to_le16(len);
  1989. /* TODO need this for burst mode later on */
  1990. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, sta_id);
  1991. /* set is_hcca to 0; it probably will never be implemented */
  1992. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  1993. tx->tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  1994. tx->tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  1995. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  1996. txq->need_update = 1;
  1997. if (qc)
  1998. priv->stations_39[sta_id].tid[tid].seq_number = seq_number;
  1999. } else {
  2000. wait_write_ptr = 1;
  2001. txq->need_update = 0;
  2002. }
  2003. iwl_print_hex_dump(priv, IWL_DL_TX, tx, sizeof(*tx));
  2004. iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx->hdr,
  2005. ieee80211_hdrlen(fc));
  2006. /* Tell device the write index *just past* this latest filled TFD */
  2007. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2008. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2009. spin_unlock_irqrestore(&priv->lock, flags);
  2010. if (rc)
  2011. return rc;
  2012. if ((iwl_queue_space(q) < q->high_mark)
  2013. && priv->mac80211_registered) {
  2014. if (wait_write_ptr) {
  2015. spin_lock_irqsave(&priv->lock, flags);
  2016. txq->need_update = 1;
  2017. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2018. spin_unlock_irqrestore(&priv->lock, flags);
  2019. }
  2020. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2021. }
  2022. return 0;
  2023. drop_unlock:
  2024. spin_unlock_irqrestore(&priv->lock, flags);
  2025. drop:
  2026. return -1;
  2027. }
  2028. static void iwl3945_set_rate(struct iwl_priv *priv)
  2029. {
  2030. const struct ieee80211_supported_band *sband = NULL;
  2031. struct ieee80211_rate *rate;
  2032. int i;
  2033. sband = iwl_get_hw_mode(priv, priv->band);
  2034. if (!sband) {
  2035. IWL_ERR(priv, "Failed to set rate: unable to get hw mode\n");
  2036. return;
  2037. }
  2038. priv->active_rate = 0;
  2039. priv->active_rate_basic = 0;
  2040. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2041. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2042. for (i = 0; i < sband->n_bitrates; i++) {
  2043. rate = &sband->bitrates[i];
  2044. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2045. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2046. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2047. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2048. priv->active_rate |= (1 << rate->hw_value);
  2049. }
  2050. }
  2051. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2052. priv->active_rate, priv->active_rate_basic);
  2053. /*
  2054. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2055. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2056. * OFDM
  2057. */
  2058. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2059. priv->staging39_rxon.cck_basic_rates =
  2060. ((priv->active_rate_basic &
  2061. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2062. else
  2063. priv->staging39_rxon.cck_basic_rates =
  2064. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2065. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2066. priv->staging39_rxon.ofdm_basic_rates =
  2067. ((priv->active_rate_basic &
  2068. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2069. IWL_FIRST_OFDM_RATE) & 0xFF;
  2070. else
  2071. priv->staging39_rxon.ofdm_basic_rates =
  2072. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2073. }
  2074. static void iwl3945_radio_kill_sw(struct iwl_priv *priv, int disable_radio)
  2075. {
  2076. unsigned long flags;
  2077. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2078. return;
  2079. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2080. disable_radio ? "OFF" : "ON");
  2081. if (disable_radio) {
  2082. iwl3945_scan_cancel(priv);
  2083. /* FIXME: This is a workaround for AP */
  2084. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  2085. spin_lock_irqsave(&priv->lock, flags);
  2086. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2087. CSR_UCODE_SW_BIT_RFKILL);
  2088. spin_unlock_irqrestore(&priv->lock, flags);
  2089. iwl_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2090. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2091. }
  2092. return;
  2093. }
  2094. spin_lock_irqsave(&priv->lock, flags);
  2095. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2096. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2097. spin_unlock_irqrestore(&priv->lock, flags);
  2098. /* wake up ucode */
  2099. msleep(10);
  2100. spin_lock_irqsave(&priv->lock, flags);
  2101. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2102. if (!iwl_grab_nic_access(priv))
  2103. iwl_release_nic_access(priv);
  2104. spin_unlock_irqrestore(&priv->lock, flags);
  2105. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2106. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2107. "disabled by HW switch\n");
  2108. return;
  2109. }
  2110. if (priv->is_open)
  2111. queue_work(priv->workqueue, &priv->restart);
  2112. return;
  2113. }
  2114. void iwl3945_set_decrypted_flag(struct iwl_priv *priv, struct sk_buff *skb,
  2115. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2116. {
  2117. u16 fc =
  2118. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2119. if (priv->active39_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2120. return;
  2121. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2122. return;
  2123. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2124. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2125. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2126. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2127. RX_RES_STATUS_BAD_ICV_MIC)
  2128. stats->flag |= RX_FLAG_MMIC_ERROR;
  2129. case RX_RES_STATUS_SEC_TYPE_WEP:
  2130. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2131. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2132. RX_RES_STATUS_DECRYPT_OK) {
  2133. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2134. stats->flag |= RX_FLAG_DECRYPTED;
  2135. }
  2136. break;
  2137. default:
  2138. break;
  2139. }
  2140. }
  2141. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2142. #include "iwl-spectrum.h"
  2143. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2144. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2145. #define TIME_UNIT 1024
  2146. /*
  2147. * extended beacon time format
  2148. * time in usec will be changed into a 32-bit value in 8:24 format
  2149. * the high 1 byte is the beacon counts
  2150. * the lower 3 bytes is the time in usec within one beacon interval
  2151. */
  2152. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2153. {
  2154. u32 quot;
  2155. u32 rem;
  2156. u32 interval = beacon_interval * 1024;
  2157. if (!interval || !usec)
  2158. return 0;
  2159. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2160. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2161. return (quot << 24) + rem;
  2162. }
  2163. /* base is usually what we get from ucode with each received frame,
  2164. * the same as HW timer counter counting down
  2165. */
  2166. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2167. {
  2168. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2169. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2170. u32 interval = beacon_interval * TIME_UNIT;
  2171. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2172. (addon & BEACON_TIME_MASK_HIGH);
  2173. if (base_low > addon_low)
  2174. res += base_low - addon_low;
  2175. else if (base_low < addon_low) {
  2176. res += interval + base_low - addon_low;
  2177. res += (1 << 24);
  2178. } else
  2179. res += (1 << 24);
  2180. return cpu_to_le32(res);
  2181. }
  2182. static int iwl3945_get_measurement(struct iwl_priv *priv,
  2183. struct ieee80211_measurement_params *params,
  2184. u8 type)
  2185. {
  2186. struct iwl_spectrum_cmd spectrum;
  2187. struct iwl_rx_packet *res;
  2188. struct iwl_host_cmd cmd = {
  2189. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2190. .data = (void *)&spectrum,
  2191. .meta.flags = CMD_WANT_SKB,
  2192. };
  2193. u32 add_time = le64_to_cpu(params->start_time);
  2194. int rc;
  2195. int spectrum_resp_status;
  2196. int duration = le16_to_cpu(params->duration);
  2197. if (iwl3945_is_associated(priv))
  2198. add_time =
  2199. iwl3945_usecs_to_beacons(
  2200. le64_to_cpu(params->start_time) - priv->last_tsf,
  2201. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2202. memset(&spectrum, 0, sizeof(spectrum));
  2203. spectrum.channel_count = cpu_to_le16(1);
  2204. spectrum.flags =
  2205. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2206. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2207. cmd.len = sizeof(spectrum);
  2208. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2209. if (iwl3945_is_associated(priv))
  2210. spectrum.start_time =
  2211. iwl3945_add_beacon_time(priv->last_beacon_time,
  2212. add_time,
  2213. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2214. else
  2215. spectrum.start_time = 0;
  2216. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2217. spectrum.channels[0].channel = params->channel;
  2218. spectrum.channels[0].type = type;
  2219. if (priv->active39_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2220. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2221. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2222. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2223. if (rc)
  2224. return rc;
  2225. res = (struct iwl_rx_packet *)cmd.meta.u.skb->data;
  2226. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2227. IWL_ERR(priv, "Bad return from REPLY_RX_ON_ASSOC command\n");
  2228. rc = -EIO;
  2229. }
  2230. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2231. switch (spectrum_resp_status) {
  2232. case 0: /* Command will be handled */
  2233. if (res->u.spectrum.id != 0xff) {
  2234. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2235. res->u.spectrum.id);
  2236. priv->measurement_status &= ~MEASUREMENT_READY;
  2237. }
  2238. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2239. rc = 0;
  2240. break;
  2241. case 1: /* Command will not be handled */
  2242. rc = -EAGAIN;
  2243. break;
  2244. }
  2245. dev_kfree_skb_any(cmd.meta.u.skb);
  2246. return rc;
  2247. }
  2248. #endif
  2249. static void iwl3945_rx_reply_alive(struct iwl_priv *priv,
  2250. struct iwl_rx_mem_buffer *rxb)
  2251. {
  2252. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2253. struct iwl_alive_resp *palive;
  2254. struct delayed_work *pwork;
  2255. palive = &pkt->u.alive_frame;
  2256. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2257. "0x%01X 0x%01X\n",
  2258. palive->is_valid, palive->ver_type,
  2259. palive->ver_subtype);
  2260. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2261. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2262. memcpy(&priv->card_alive_init, &pkt->u.alive_frame,
  2263. sizeof(struct iwl_alive_resp));
  2264. pwork = &priv->init_alive_start;
  2265. } else {
  2266. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2267. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2268. sizeof(struct iwl_alive_resp));
  2269. pwork = &priv->alive_start;
  2270. iwl3945_disable_events(priv);
  2271. }
  2272. /* We delay the ALIVE response by 5ms to
  2273. * give the HW RF Kill time to activate... */
  2274. if (palive->is_valid == UCODE_VALID_OK)
  2275. queue_delayed_work(priv->workqueue, pwork,
  2276. msecs_to_jiffies(5));
  2277. else
  2278. IWL_WARN(priv, "uCode did not respond OK.\n");
  2279. }
  2280. static void iwl3945_rx_reply_add_sta(struct iwl_priv *priv,
  2281. struct iwl_rx_mem_buffer *rxb)
  2282. {
  2283. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2284. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2285. return;
  2286. }
  2287. static void iwl3945_rx_reply_error(struct iwl_priv *priv,
  2288. struct iwl_rx_mem_buffer *rxb)
  2289. {
  2290. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2291. IWL_ERR(priv, "Error Reply type 0x%08X cmd %s (0x%02X) "
  2292. "seq 0x%04X ser 0x%08X\n",
  2293. le32_to_cpu(pkt->u.err_resp.error_type),
  2294. get_cmd_string(pkt->u.err_resp.cmd_id),
  2295. pkt->u.err_resp.cmd_id,
  2296. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2297. le32_to_cpu(pkt->u.err_resp.error_info));
  2298. }
  2299. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2300. static void iwl3945_rx_csa(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  2301. {
  2302. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2303. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active39_rxon;
  2304. struct iwl_csa_notification *csa = &(pkt->u.csa_notif);
  2305. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2306. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2307. rxon->channel = csa->channel;
  2308. priv->staging39_rxon.channel = csa->channel;
  2309. }
  2310. static void iwl3945_rx_spectrum_measure_notif(struct iwl_priv *priv,
  2311. struct iwl_rx_mem_buffer *rxb)
  2312. {
  2313. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2314. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2315. struct iwl_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2316. if (!report->state) {
  2317. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2318. "Spectrum Measure Notification: Start\n");
  2319. return;
  2320. }
  2321. memcpy(&priv->measure_report, report, sizeof(*report));
  2322. priv->measurement_status |= MEASUREMENT_READY;
  2323. #endif
  2324. }
  2325. static void iwl3945_rx_pm_sleep_notif(struct iwl_priv *priv,
  2326. struct iwl_rx_mem_buffer *rxb)
  2327. {
  2328. #ifdef CONFIG_IWL3945_DEBUG
  2329. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2330. struct iwl_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2331. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2332. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2333. #endif
  2334. }
  2335. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl_priv *priv,
  2336. struct iwl_rx_mem_buffer *rxb)
  2337. {
  2338. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2339. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2340. "notification for %s:\n",
  2341. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2342. iwl_print_hex_dump(priv, IWL_DL_RADIO, pkt->u.raw,
  2343. le32_to_cpu(pkt->len));
  2344. }
  2345. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2346. {
  2347. struct iwl_priv *priv =
  2348. container_of(work, struct iwl_priv, beacon_update);
  2349. struct sk_buff *beacon;
  2350. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2351. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2352. if (!beacon) {
  2353. IWL_ERR(priv, "update beacon failed\n");
  2354. return;
  2355. }
  2356. mutex_lock(&priv->mutex);
  2357. /* new beacon skb is allocated every time; dispose previous.*/
  2358. if (priv->ibss_beacon)
  2359. dev_kfree_skb(priv->ibss_beacon);
  2360. priv->ibss_beacon = beacon;
  2361. mutex_unlock(&priv->mutex);
  2362. iwl3945_send_beacon_cmd(priv);
  2363. }
  2364. static void iwl3945_rx_beacon_notif(struct iwl_priv *priv,
  2365. struct iwl_rx_mem_buffer *rxb)
  2366. {
  2367. #ifdef CONFIG_IWL3945_DEBUG
  2368. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2369. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2370. u8 rate = beacon->beacon_notify_hdr.rate;
  2371. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2372. "tsf %d %d rate %d\n",
  2373. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2374. beacon->beacon_notify_hdr.failure_frame,
  2375. le32_to_cpu(beacon->ibss_mgr_status),
  2376. le32_to_cpu(beacon->high_tsf),
  2377. le32_to_cpu(beacon->low_tsf), rate);
  2378. #endif
  2379. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  2380. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2381. queue_work(priv->workqueue, &priv->beacon_update);
  2382. }
  2383. /* Service response to REPLY_SCAN_CMD (0x80) */
  2384. static void iwl3945_rx_reply_scan(struct iwl_priv *priv,
  2385. struct iwl_rx_mem_buffer *rxb)
  2386. {
  2387. #ifdef CONFIG_IWL3945_DEBUG
  2388. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2389. struct iwl_scanreq_notification *notif =
  2390. (struct iwl_scanreq_notification *)pkt->u.raw;
  2391. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2392. #endif
  2393. }
  2394. /* Service SCAN_START_NOTIFICATION (0x82) */
  2395. static void iwl3945_rx_scan_start_notif(struct iwl_priv *priv,
  2396. struct iwl_rx_mem_buffer *rxb)
  2397. {
  2398. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2399. struct iwl_scanstart_notification *notif =
  2400. (struct iwl_scanstart_notification *)pkt->u.raw;
  2401. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2402. IWL_DEBUG_SCAN("Scan start: "
  2403. "%d [802.11%s] "
  2404. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2405. notif->channel,
  2406. notif->band ? "bg" : "a",
  2407. notif->tsf_high,
  2408. notif->tsf_low, notif->status, notif->beacon_timer);
  2409. }
  2410. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2411. static void iwl3945_rx_scan_results_notif(struct iwl_priv *priv,
  2412. struct iwl_rx_mem_buffer *rxb)
  2413. {
  2414. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2415. struct iwl_scanresults_notification *notif =
  2416. (struct iwl_scanresults_notification *)pkt->u.raw;
  2417. IWL_DEBUG_SCAN("Scan ch.res: "
  2418. "%d [802.11%s] "
  2419. "(TSF: 0x%08X:%08X) - %d "
  2420. "elapsed=%lu usec (%dms since last)\n",
  2421. notif->channel,
  2422. notif->band ? "bg" : "a",
  2423. le32_to_cpu(notif->tsf_high),
  2424. le32_to_cpu(notif->tsf_low),
  2425. le32_to_cpu(notif->statistics[0]),
  2426. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2427. jiffies_to_msecs(elapsed_jiffies
  2428. (priv->last_scan_jiffies, jiffies)));
  2429. priv->last_scan_jiffies = jiffies;
  2430. priv->next_scan_jiffies = 0;
  2431. }
  2432. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2433. static void iwl3945_rx_scan_complete_notif(struct iwl_priv *priv,
  2434. struct iwl_rx_mem_buffer *rxb)
  2435. {
  2436. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2437. struct iwl_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2438. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2439. scan_notif->scanned_channels,
  2440. scan_notif->tsf_low,
  2441. scan_notif->tsf_high, scan_notif->status);
  2442. /* The HW is no longer scanning */
  2443. clear_bit(STATUS_SCAN_HW, &priv->status);
  2444. /* The scan completion notification came in, so kill that timer... */
  2445. cancel_delayed_work(&priv->scan_check);
  2446. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2447. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2448. "2.4" : "5.2",
  2449. jiffies_to_msecs(elapsed_jiffies
  2450. (priv->scan_pass_start, jiffies)));
  2451. /* Remove this scanned band from the list of pending
  2452. * bands to scan, band G precedes A in order of scanning
  2453. * as seen in iwl3945_bg_request_scan */
  2454. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2455. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2456. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2457. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2458. /* If a request to abort was given, or the scan did not succeed
  2459. * then we reset the scan state machine and terminate,
  2460. * re-queuing another scan if one has been requested */
  2461. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2462. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2463. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2464. } else {
  2465. /* If there are more bands on this scan pass reschedule */
  2466. if (priv->scan_bands > 0)
  2467. goto reschedule;
  2468. }
  2469. priv->last_scan_jiffies = jiffies;
  2470. priv->next_scan_jiffies = 0;
  2471. IWL_DEBUG_INFO("Setting scan to off\n");
  2472. clear_bit(STATUS_SCANNING, &priv->status);
  2473. IWL_DEBUG_INFO("Scan took %dms\n",
  2474. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2475. queue_work(priv->workqueue, &priv->scan_completed);
  2476. return;
  2477. reschedule:
  2478. priv->scan_pass_start = jiffies;
  2479. queue_work(priv->workqueue, &priv->request_scan);
  2480. }
  2481. /* Handle notification from uCode that card's power state is changing
  2482. * due to software, hardware, or critical temperature RFKILL */
  2483. static void iwl3945_rx_card_state_notif(struct iwl_priv *priv,
  2484. struct iwl_rx_mem_buffer *rxb)
  2485. {
  2486. struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
  2487. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2488. unsigned long status = priv->status;
  2489. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2490. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2491. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2492. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2493. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2494. if (flags & HW_CARD_DISABLED)
  2495. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2496. else
  2497. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2498. if (flags & SW_CARD_DISABLED)
  2499. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2500. else
  2501. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2502. iwl3945_scan_cancel(priv);
  2503. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2504. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2505. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2506. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2507. queue_work(priv->workqueue, &priv->rf_kill);
  2508. else
  2509. wake_up_interruptible(&priv->wait_command_queue);
  2510. }
  2511. /**
  2512. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2513. *
  2514. * Setup the RX handlers for each of the reply types sent from the uCode
  2515. * to the host.
  2516. *
  2517. * This function chains into the hardware specific files for them to setup
  2518. * any hardware specific handlers as well.
  2519. */
  2520. static void iwl3945_setup_rx_handlers(struct iwl_priv *priv)
  2521. {
  2522. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2523. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2524. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2525. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2526. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2527. iwl3945_rx_spectrum_measure_notif;
  2528. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2529. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2530. iwl3945_rx_pm_debug_statistics_notif;
  2531. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2532. /*
  2533. * The same handler is used for both the REPLY to a discrete
  2534. * statistics request from the host as well as for the periodic
  2535. * statistics notifications (after received beacons) from the uCode.
  2536. */
  2537. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2538. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2539. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2540. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2541. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2542. iwl3945_rx_scan_results_notif;
  2543. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2544. iwl3945_rx_scan_complete_notif;
  2545. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2546. /* Set up hardware specific Rx handlers */
  2547. iwl3945_hw_rx_handler_setup(priv);
  2548. }
  2549. /**
  2550. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2551. * When FW advances 'R' index, all entries between old and new 'R' index
  2552. * need to be reclaimed.
  2553. */
  2554. static void iwl3945_cmd_queue_reclaim(struct iwl_priv *priv,
  2555. int txq_id, int index)
  2556. {
  2557. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  2558. struct iwl_queue *q = &txq->q;
  2559. int nfreed = 0;
  2560. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2561. IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
  2562. "is out of range [0-%d] %d %d.\n", txq_id,
  2563. index, q->n_bd, q->write_ptr, q->read_ptr);
  2564. return;
  2565. }
  2566. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2567. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2568. if (nfreed > 1) {
  2569. IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", index,
  2570. q->write_ptr, q->read_ptr);
  2571. queue_work(priv->workqueue, &priv->restart);
  2572. break;
  2573. }
  2574. nfreed++;
  2575. }
  2576. }
  2577. /**
  2578. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2579. * @rxb: Rx buffer to reclaim
  2580. *
  2581. * If an Rx buffer has an async callback associated with it the callback
  2582. * will be executed. The attached skb (if present) will only be freed
  2583. * if the callback returns 1
  2584. */
  2585. static void iwl3945_tx_cmd_complete(struct iwl_priv *priv,
  2586. struct iwl_rx_mem_buffer *rxb)
  2587. {
  2588. struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2589. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2590. int txq_id = SEQ_TO_QUEUE(sequence);
  2591. int index = SEQ_TO_INDEX(sequence);
  2592. int huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  2593. int cmd_index;
  2594. struct iwl_cmd *cmd;
  2595. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2596. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2597. cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2598. /* Input error checking is done when commands are added to queue. */
  2599. if (cmd->meta.flags & CMD_WANT_SKB) {
  2600. cmd->meta.source->u.skb = rxb->skb;
  2601. rxb->skb = NULL;
  2602. } else if (cmd->meta.u.callback &&
  2603. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2604. rxb->skb = NULL;
  2605. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2606. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2607. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2608. wake_up_interruptible(&priv->wait_command_queue);
  2609. }
  2610. }
  2611. /************************** RX-FUNCTIONS ****************************/
  2612. /*
  2613. * Rx theory of operation
  2614. *
  2615. * The host allocates 32 DMA target addresses and passes the host address
  2616. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2617. * 0 to 31
  2618. *
  2619. * Rx Queue Indexes
  2620. * The host/firmware share two index registers for managing the Rx buffers.
  2621. *
  2622. * The READ index maps to the first position that the firmware may be writing
  2623. * to -- the driver can read up to (but not including) this position and get
  2624. * good data.
  2625. * The READ index is managed by the firmware once the card is enabled.
  2626. *
  2627. * The WRITE index maps to the last position the driver has read from -- the
  2628. * position preceding WRITE is the last slot the firmware can place a packet.
  2629. *
  2630. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2631. * WRITE = READ.
  2632. *
  2633. * During initialization, the host sets up the READ queue position to the first
  2634. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2635. *
  2636. * When the firmware places a packet in a buffer, it will advance the READ index
  2637. * and fire the RX interrupt. The driver can then query the READ index and
  2638. * process as many packets as possible, moving the WRITE index forward as it
  2639. * resets the Rx queue buffers with new memory.
  2640. *
  2641. * The management in the driver is as follows:
  2642. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2643. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2644. * to replenish the iwl->rxq->rx_free.
  2645. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2646. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2647. * 'processed' and 'read' driver indexes as well)
  2648. * + A received packet is processed and handed to the kernel network stack,
  2649. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2650. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2651. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  2652. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  2653. * were enough free buffers and RX_STALLED is set it is cleared.
  2654. *
  2655. *
  2656. * Driver sequence:
  2657. *
  2658. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  2659. * iwl3945_rx_queue_restock
  2660. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  2661. * queue, updates firmware pointers, and updates
  2662. * the WRITE index. If insufficient rx_free buffers
  2663. * are available, schedules iwl3945_rx_replenish
  2664. *
  2665. * -- enable interrupts --
  2666. * ISR - iwl3945_rx() Detach iwl_rx_mem_buffers from pool up to the
  2667. * READ INDEX, detaching the SKB from the pool.
  2668. * Moves the packet buffer from queue to rx_used.
  2669. * Calls iwl3945_rx_queue_restock to refill any empty
  2670. * slots.
  2671. * ...
  2672. *
  2673. */
  2674. /**
  2675. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  2676. */
  2677. static int iwl3945_rx_queue_space(const struct iwl_rx_queue *q)
  2678. {
  2679. int s = q->read - q->write;
  2680. if (s <= 0)
  2681. s += RX_QUEUE_SIZE;
  2682. /* keep some buffer to not confuse full and empty queue */
  2683. s -= 2;
  2684. if (s < 0)
  2685. s = 0;
  2686. return s;
  2687. }
  2688. /**
  2689. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  2690. */
  2691. int iwl3945_rx_queue_update_write_ptr(struct iwl_priv *priv, struct iwl_rx_queue *q)
  2692. {
  2693. u32 reg = 0;
  2694. int rc = 0;
  2695. unsigned long flags;
  2696. spin_lock_irqsave(&q->lock, flags);
  2697. if (q->need_update == 0)
  2698. goto exit_unlock;
  2699. /* If power-saving is in use, make sure device is awake */
  2700. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  2701. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  2702. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  2703. iwl_set_bit(priv, CSR_GP_CNTRL,
  2704. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2705. goto exit_unlock;
  2706. }
  2707. rc = iwl_grab_nic_access(priv);
  2708. if (rc)
  2709. goto exit_unlock;
  2710. /* Device expects a multiple of 8 */
  2711. iwl_write_direct32(priv, FH39_RSCSR_CHNL0_WPTR,
  2712. q->write & ~0x7);
  2713. iwl_release_nic_access(priv);
  2714. /* Else device is assumed to be awake */
  2715. } else
  2716. /* Device expects a multiple of 8 */
  2717. iwl_write32(priv, FH39_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  2718. q->need_update = 0;
  2719. exit_unlock:
  2720. spin_unlock_irqrestore(&q->lock, flags);
  2721. return rc;
  2722. }
  2723. /**
  2724. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  2725. */
  2726. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl_priv *priv,
  2727. dma_addr_t dma_addr)
  2728. {
  2729. return cpu_to_le32((u32)dma_addr);
  2730. }
  2731. /**
  2732. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  2733. *
  2734. * If there are slots in the RX queue that need to be restocked,
  2735. * and we have free pre-allocated buffers, fill the ranks as much
  2736. * as we can, pulling from rx_free.
  2737. *
  2738. * This moves the 'write' index forward to catch up with 'processed', and
  2739. * also updates the memory address in the firmware to reference the new
  2740. * target buffer.
  2741. */
  2742. static int iwl3945_rx_queue_restock(struct iwl_priv *priv)
  2743. {
  2744. struct iwl_rx_queue *rxq = &priv->rxq;
  2745. struct list_head *element;
  2746. struct iwl_rx_mem_buffer *rxb;
  2747. unsigned long flags;
  2748. int write, rc;
  2749. spin_lock_irqsave(&rxq->lock, flags);
  2750. write = rxq->write & ~0x7;
  2751. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  2752. /* Get next free Rx buffer, remove from free list */
  2753. element = rxq->rx_free.next;
  2754. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2755. list_del(element);
  2756. /* Point to Rx buffer via next RBD in circular buffer */
  2757. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->real_dma_addr);
  2758. rxq->queue[rxq->write] = rxb;
  2759. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  2760. rxq->free_count--;
  2761. }
  2762. spin_unlock_irqrestore(&rxq->lock, flags);
  2763. /* If the pre-allocated buffer pool is dropping low, schedule to
  2764. * refill it */
  2765. if (rxq->free_count <= RX_LOW_WATERMARK)
  2766. queue_work(priv->workqueue, &priv->rx_replenish);
  2767. /* If we've added more space for the firmware to place data, tell it.
  2768. * Increment device's write pointer in multiples of 8. */
  2769. if ((write != (rxq->write & ~0x7))
  2770. || (abs(rxq->write - rxq->read) > 7)) {
  2771. spin_lock_irqsave(&rxq->lock, flags);
  2772. rxq->need_update = 1;
  2773. spin_unlock_irqrestore(&rxq->lock, flags);
  2774. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  2775. if (rc)
  2776. return rc;
  2777. }
  2778. return 0;
  2779. }
  2780. /**
  2781. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  2782. *
  2783. * When moving to rx_free an SKB is allocated for the slot.
  2784. *
  2785. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  2786. * This is called as a scheduled work item (except for during initialization)
  2787. */
  2788. static void iwl3945_rx_allocate(struct iwl_priv *priv)
  2789. {
  2790. struct iwl_rx_queue *rxq = &priv->rxq;
  2791. struct list_head *element;
  2792. struct iwl_rx_mem_buffer *rxb;
  2793. unsigned long flags;
  2794. spin_lock_irqsave(&rxq->lock, flags);
  2795. while (!list_empty(&rxq->rx_used)) {
  2796. element = rxq->rx_used.next;
  2797. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  2798. /* Alloc a new receive buffer */
  2799. rxb->skb =
  2800. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  2801. if (!rxb->skb) {
  2802. if (net_ratelimit())
  2803. IWL_CRIT(priv, ": Can not allocate SKB buffers\n");
  2804. /* We don't reschedule replenish work here -- we will
  2805. * call the restock method and if it still needs
  2806. * more buffers it will schedule replenish */
  2807. break;
  2808. }
  2809. /* If radiotap head is required, reserve some headroom here.
  2810. * The physical head count is a variable rx_stats->phy_count.
  2811. * We reserve 4 bytes here. Plus these extra bytes, the
  2812. * headroom of the physical head should be enough for the
  2813. * radiotap head that iwl3945 supported. See iwl3945_rt.
  2814. */
  2815. skb_reserve(rxb->skb, 4);
  2816. priv->alloc_rxb_skb++;
  2817. list_del(element);
  2818. /* Get physical address of RB/SKB */
  2819. rxb->real_dma_addr =
  2820. pci_map_single(priv->pci_dev, rxb->skb->data,
  2821. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2822. list_add_tail(&rxb->list, &rxq->rx_free);
  2823. rxq->free_count++;
  2824. }
  2825. spin_unlock_irqrestore(&rxq->lock, flags);
  2826. }
  2827. /*
  2828. * this should be called while priv->lock is locked
  2829. */
  2830. static void __iwl3945_rx_replenish(void *data)
  2831. {
  2832. struct iwl_priv *priv = data;
  2833. iwl3945_rx_allocate(priv);
  2834. iwl3945_rx_queue_restock(priv);
  2835. }
  2836. void iwl3945_rx_replenish(void *data)
  2837. {
  2838. struct iwl_priv *priv = data;
  2839. unsigned long flags;
  2840. iwl3945_rx_allocate(priv);
  2841. spin_lock_irqsave(&priv->lock, flags);
  2842. iwl3945_rx_queue_restock(priv);
  2843. spin_unlock_irqrestore(&priv->lock, flags);
  2844. }
  2845. /* Convert linear signal-to-noise ratio into dB */
  2846. static u8 ratio2dB[100] = {
  2847. /* 0 1 2 3 4 5 6 7 8 9 */
  2848. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  2849. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  2850. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  2851. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  2852. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  2853. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  2854. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  2855. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  2856. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  2857. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  2858. };
  2859. /* Calculates a relative dB value from a ratio of linear
  2860. * (i.e. not dB) signal levels.
  2861. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  2862. int iwl3945_calc_db_from_ratio(int sig_ratio)
  2863. {
  2864. /* 1000:1 or higher just report as 60 dB */
  2865. if (sig_ratio >= 1000)
  2866. return 60;
  2867. /* 100:1 or higher, divide by 10 and use table,
  2868. * add 20 dB to make up for divide by 10 */
  2869. if (sig_ratio >= 100)
  2870. return 20 + (int)ratio2dB[sig_ratio/10];
  2871. /* We shouldn't see this */
  2872. if (sig_ratio < 1)
  2873. return 0;
  2874. /* Use table for ratios 1:1 - 99:1 */
  2875. return (int)ratio2dB[sig_ratio];
  2876. }
  2877. #define PERFECT_RSSI (-20) /* dBm */
  2878. #define WORST_RSSI (-95) /* dBm */
  2879. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  2880. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  2881. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  2882. * about formulas used below. */
  2883. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  2884. {
  2885. int sig_qual;
  2886. int degradation = PERFECT_RSSI - rssi_dbm;
  2887. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  2888. * as indicator; formula is (signal dbm - noise dbm).
  2889. * SNR at or above 40 is a great signal (100%).
  2890. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  2891. * Weakest usable signal is usually 10 - 15 dB SNR. */
  2892. if (noise_dbm) {
  2893. if (rssi_dbm - noise_dbm >= 40)
  2894. return 100;
  2895. else if (rssi_dbm < noise_dbm)
  2896. return 0;
  2897. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  2898. /* Else use just the signal level.
  2899. * This formula is a least squares fit of data points collected and
  2900. * compared with a reference system that had a percentage (%) display
  2901. * for signal quality. */
  2902. } else
  2903. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  2904. (15 * RSSI_RANGE + 62 * degradation)) /
  2905. (RSSI_RANGE * RSSI_RANGE);
  2906. if (sig_qual > 100)
  2907. sig_qual = 100;
  2908. else if (sig_qual < 1)
  2909. sig_qual = 0;
  2910. return sig_qual;
  2911. }
  2912. /**
  2913. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  2914. *
  2915. * Uses the priv->rx_handlers callback function array to invoke
  2916. * the appropriate handlers, including command responses,
  2917. * frame-received notifications, and other notifications.
  2918. */
  2919. static void iwl3945_rx_handle(struct iwl_priv *priv)
  2920. {
  2921. struct iwl_rx_mem_buffer *rxb;
  2922. struct iwl_rx_packet *pkt;
  2923. struct iwl_rx_queue *rxq = &priv->rxq;
  2924. u32 r, i;
  2925. int reclaim;
  2926. unsigned long flags;
  2927. u8 fill_rx = 0;
  2928. u32 count = 8;
  2929. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  2930. * buffer that the driver may process (last buffer filled by ucode). */
  2931. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  2932. i = rxq->read;
  2933. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  2934. fill_rx = 1;
  2935. /* Rx interrupt, but nothing sent from uCode */
  2936. if (i == r)
  2937. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  2938. while (i != r) {
  2939. rxb = rxq->queue[i];
  2940. /* If an RXB doesn't have a Rx queue slot associated with it,
  2941. * then a bug has been introduced in the queue refilling
  2942. * routines -- catch it here */
  2943. BUG_ON(rxb == NULL);
  2944. rxq->queue[i] = NULL;
  2945. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->real_dma_addr,
  2946. IWL_RX_BUF_SIZE,
  2947. PCI_DMA_FROMDEVICE);
  2948. pkt = (struct iwl_rx_packet *)rxb->skb->data;
  2949. /* Reclaim a command buffer only if this packet is a response
  2950. * to a (driver-originated) command.
  2951. * If the packet (e.g. Rx frame) originated from uCode,
  2952. * there is no command buffer to reclaim.
  2953. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  2954. * but apparently a few don't get set; catch them here. */
  2955. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  2956. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  2957. (pkt->hdr.cmd != REPLY_TX);
  2958. /* Based on type of command response or notification,
  2959. * handle those that need handling via function in
  2960. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  2961. if (priv->rx_handlers[pkt->hdr.cmd]) {
  2962. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  2963. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  2964. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  2965. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  2966. } else {
  2967. /* No handling needed */
  2968. IWL_DEBUG(IWL_DL_HCMD | IWL_DL_RX | IWL_DL_ISR,
  2969. "r %d i %d No handler needed for %s, 0x%02x\n",
  2970. r, i, get_cmd_string(pkt->hdr.cmd),
  2971. pkt->hdr.cmd);
  2972. }
  2973. if (reclaim) {
  2974. /* Invoke any callbacks, transfer the skb to caller, and
  2975. * fire off the (possibly) blocking iwl3945_send_cmd()
  2976. * as we reclaim the driver command queue */
  2977. if (rxb && rxb->skb)
  2978. iwl3945_tx_cmd_complete(priv, rxb);
  2979. else
  2980. IWL_WARN(priv, "Claim null rxb?\n");
  2981. }
  2982. /* For now we just don't re-use anything. We can tweak this
  2983. * later to try and re-use notification packets and SKBs that
  2984. * fail to Rx correctly */
  2985. if (rxb->skb != NULL) {
  2986. priv->alloc_rxb_skb--;
  2987. dev_kfree_skb_any(rxb->skb);
  2988. rxb->skb = NULL;
  2989. }
  2990. pci_unmap_single(priv->pci_dev, rxb->real_dma_addr,
  2991. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  2992. spin_lock_irqsave(&rxq->lock, flags);
  2993. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  2994. spin_unlock_irqrestore(&rxq->lock, flags);
  2995. i = (i + 1) & RX_QUEUE_MASK;
  2996. /* If there are a lot of unused frames,
  2997. * restock the Rx queue so ucode won't assert. */
  2998. if (fill_rx) {
  2999. count++;
  3000. if (count >= 8) {
  3001. priv->rxq.read = i;
  3002. __iwl3945_rx_replenish(priv);
  3003. count = 0;
  3004. }
  3005. }
  3006. }
  3007. /* Backtrack one entry */
  3008. priv->rxq.read = i;
  3009. iwl3945_rx_queue_restock(priv);
  3010. }
  3011. /**
  3012. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3013. */
  3014. static int iwl3945_tx_queue_update_write_ptr(struct iwl_priv *priv,
  3015. struct iwl_tx_queue *txq)
  3016. {
  3017. u32 reg = 0;
  3018. int rc = 0;
  3019. int txq_id = txq->q.id;
  3020. if (txq->need_update == 0)
  3021. return rc;
  3022. /* if we're trying to save power */
  3023. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3024. /* wake up nic if it's powered down ...
  3025. * uCode will wake up, and interrupt us again, so next
  3026. * time we'll skip this part. */
  3027. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  3028. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3029. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3030. iwl_set_bit(priv, CSR_GP_CNTRL,
  3031. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3032. return rc;
  3033. }
  3034. /* restore this queue's parameters in nic hardware. */
  3035. rc = iwl_grab_nic_access(priv);
  3036. if (rc)
  3037. return rc;
  3038. iwl_write_direct32(priv, HBUS_TARG_WRPTR,
  3039. txq->q.write_ptr | (txq_id << 8));
  3040. iwl_release_nic_access(priv);
  3041. /* else not in power-save mode, uCode will never sleep when we're
  3042. * trying to tx (during RFKILL, we're not trying to tx). */
  3043. } else
  3044. iwl_write32(priv, HBUS_TARG_WRPTR,
  3045. txq->q.write_ptr | (txq_id << 8));
  3046. txq->need_update = 0;
  3047. return rc;
  3048. }
  3049. #ifdef CONFIG_IWL3945_DEBUG
  3050. static void iwl3945_print_rx_config_cmd(struct iwl_priv *priv,
  3051. struct iwl3945_rxon_cmd *rxon)
  3052. {
  3053. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3054. iwl_print_hex_dump(priv, IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3055. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3056. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3057. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3058. le32_to_cpu(rxon->filter_flags));
  3059. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3060. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3061. rxon->ofdm_basic_rates);
  3062. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3063. IWL_DEBUG_RADIO("u8[6] node_addr: %pM\n", rxon->node_addr);
  3064. IWL_DEBUG_RADIO("u8[6] bssid_addr: %pM\n", rxon->bssid_addr);
  3065. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3066. }
  3067. #endif
  3068. static void iwl3945_enable_interrupts(struct iwl_priv *priv)
  3069. {
  3070. IWL_DEBUG_ISR("Enabling interrupts\n");
  3071. set_bit(STATUS_INT_ENABLED, &priv->status);
  3072. iwl_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3073. }
  3074. /* call this function to flush any scheduled tasklet */
  3075. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  3076. {
  3077. /* wait to make sure we flush pending tasklet*/
  3078. synchronize_irq(priv->pci_dev->irq);
  3079. tasklet_kill(&priv->irq_tasklet);
  3080. }
  3081. static inline void iwl3945_disable_interrupts(struct iwl_priv *priv)
  3082. {
  3083. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3084. /* disable interrupts from uCode/NIC to host */
  3085. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3086. /* acknowledge/clear/reset any interrupts still pending
  3087. * from uCode or flow handler (Rx/Tx DMA) */
  3088. iwl_write32(priv, CSR_INT, 0xffffffff);
  3089. iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3090. IWL_DEBUG_ISR("Disabled interrupts\n");
  3091. }
  3092. static const char *desc_lookup(int i)
  3093. {
  3094. switch (i) {
  3095. case 1:
  3096. return "FAIL";
  3097. case 2:
  3098. return "BAD_PARAM";
  3099. case 3:
  3100. return "BAD_CHECKSUM";
  3101. case 4:
  3102. return "NMI_INTERRUPT";
  3103. case 5:
  3104. return "SYSASSERT";
  3105. case 6:
  3106. return "FATAL_ERROR";
  3107. }
  3108. return "UNKNOWN";
  3109. }
  3110. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3111. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3112. static void iwl3945_dump_nic_error_log(struct iwl_priv *priv)
  3113. {
  3114. u32 i;
  3115. u32 desc, time, count, base, data1;
  3116. u32 blink1, blink2, ilink1, ilink2;
  3117. int rc;
  3118. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3119. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3120. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  3121. return;
  3122. }
  3123. rc = iwl_grab_nic_access(priv);
  3124. if (rc) {
  3125. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  3126. return;
  3127. }
  3128. count = iwl_read_targ_mem(priv, base);
  3129. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3130. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  3131. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  3132. priv->status, count);
  3133. }
  3134. IWL_ERR(priv, "Desc Time asrtPC blink2 "
  3135. "ilink1 nmiPC Line\n");
  3136. for (i = ERROR_START_OFFSET;
  3137. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3138. i += ERROR_ELEM_SIZE) {
  3139. desc = iwl_read_targ_mem(priv, base + i);
  3140. time =
  3141. iwl_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3142. blink1 =
  3143. iwl_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3144. blink2 =
  3145. iwl_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3146. ilink1 =
  3147. iwl_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3148. ilink2 =
  3149. iwl_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3150. data1 =
  3151. iwl_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3152. IWL_ERR(priv,
  3153. "%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3154. desc_lookup(desc), desc, time, blink1, blink2,
  3155. ilink1, ilink2, data1);
  3156. }
  3157. iwl_release_nic_access(priv);
  3158. }
  3159. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3160. /**
  3161. * iwl3945_print_event_log - Dump error event log to syslog
  3162. *
  3163. * NOTE: Must be called with iwl_grab_nic_access() already obtained!
  3164. */
  3165. static void iwl3945_print_event_log(struct iwl_priv *priv, u32 start_idx,
  3166. u32 num_events, u32 mode)
  3167. {
  3168. u32 i;
  3169. u32 base; /* SRAM byte address of event log header */
  3170. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3171. u32 ptr; /* SRAM byte address of log data */
  3172. u32 ev, time, data; /* event log data */
  3173. if (num_events == 0)
  3174. return;
  3175. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3176. if (mode == 0)
  3177. event_size = 2 * sizeof(u32);
  3178. else
  3179. event_size = 3 * sizeof(u32);
  3180. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3181. /* "time" is actually "data" for mode 0 (no timestamp).
  3182. * place event id # at far right for easier visual parsing. */
  3183. for (i = 0; i < num_events; i++) {
  3184. ev = iwl_read_targ_mem(priv, ptr);
  3185. ptr += sizeof(u32);
  3186. time = iwl_read_targ_mem(priv, ptr);
  3187. ptr += sizeof(u32);
  3188. if (mode == 0) {
  3189. /* data, ev */
  3190. IWL_ERR(priv, "0x%08x\t%04u\n", time, ev);
  3191. } else {
  3192. data = iwl_read_targ_mem(priv, ptr);
  3193. ptr += sizeof(u32);
  3194. IWL_ERR(priv, "%010u\t0x%08x\t%04u\n", time, data, ev);
  3195. }
  3196. }
  3197. }
  3198. static void iwl3945_dump_nic_event_log(struct iwl_priv *priv)
  3199. {
  3200. int rc;
  3201. u32 base; /* SRAM byte address of event log header */
  3202. u32 capacity; /* event log capacity in # entries */
  3203. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3204. u32 num_wraps; /* # times uCode wrapped to top of log */
  3205. u32 next_entry; /* index of next entry to be written by uCode */
  3206. u32 size; /* # entries that we'll print */
  3207. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3208. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3209. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  3210. return;
  3211. }
  3212. rc = iwl_grab_nic_access(priv);
  3213. if (rc) {
  3214. IWL_WARN(priv, "Can not read from adapter at this time.\n");
  3215. return;
  3216. }
  3217. /* event log header */
  3218. capacity = iwl_read_targ_mem(priv, base);
  3219. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3220. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3221. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3222. size = num_wraps ? capacity : next_entry;
  3223. /* bail out if nothing in log */
  3224. if (size == 0) {
  3225. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  3226. iwl_release_nic_access(priv);
  3227. return;
  3228. }
  3229. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  3230. size, num_wraps);
  3231. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3232. * i.e the next one that uCode would fill. */
  3233. if (num_wraps)
  3234. iwl3945_print_event_log(priv, next_entry,
  3235. capacity - next_entry, mode);
  3236. /* (then/else) start at top of log */
  3237. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3238. iwl_release_nic_access(priv);
  3239. }
  3240. /**
  3241. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3242. */
  3243. static void iwl3945_irq_handle_error(struct iwl_priv *priv)
  3244. {
  3245. /* Set the FW error flag -- cleared on iwl3945_down */
  3246. set_bit(STATUS_FW_ERROR, &priv->status);
  3247. /* Cancel currently queued command. */
  3248. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3249. #ifdef CONFIG_IWL3945_DEBUG
  3250. if (priv->debug_level & IWL_DL_FW_ERRORS) {
  3251. iwl3945_dump_nic_error_log(priv);
  3252. iwl3945_dump_nic_event_log(priv);
  3253. iwl3945_print_rx_config_cmd(priv, &priv->staging39_rxon);
  3254. }
  3255. #endif
  3256. wake_up_interruptible(&priv->wait_command_queue);
  3257. /* Keep the restart process from trying to send host
  3258. * commands by clearing the INIT status bit */
  3259. clear_bit(STATUS_READY, &priv->status);
  3260. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3261. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3262. "Restarting adapter due to uCode error.\n");
  3263. if (iwl3945_is_associated(priv)) {
  3264. memcpy(&priv->recovery39_rxon, &priv->active39_rxon,
  3265. sizeof(priv->recovery39_rxon));
  3266. priv->error_recovering = 1;
  3267. }
  3268. queue_work(priv->workqueue, &priv->restart);
  3269. }
  3270. }
  3271. static void iwl3945_error_recovery(struct iwl_priv *priv)
  3272. {
  3273. unsigned long flags;
  3274. memcpy(&priv->staging39_rxon, &priv->recovery39_rxon,
  3275. sizeof(priv->staging39_rxon));
  3276. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3277. iwl3945_commit_rxon(priv);
  3278. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3279. spin_lock_irqsave(&priv->lock, flags);
  3280. priv->assoc_id = le16_to_cpu(priv->staging39_rxon.assoc_id);
  3281. priv->error_recovering = 0;
  3282. spin_unlock_irqrestore(&priv->lock, flags);
  3283. }
  3284. static void iwl3945_irq_tasklet(struct iwl_priv *priv)
  3285. {
  3286. u32 inta, handled = 0;
  3287. u32 inta_fh;
  3288. unsigned long flags;
  3289. #ifdef CONFIG_IWL3945_DEBUG
  3290. u32 inta_mask;
  3291. #endif
  3292. spin_lock_irqsave(&priv->lock, flags);
  3293. /* Ack/clear/reset pending uCode interrupts.
  3294. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3295. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3296. inta = iwl_read32(priv, CSR_INT);
  3297. iwl_write32(priv, CSR_INT, inta);
  3298. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3299. * Any new interrupts that happen after this, either while we're
  3300. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3301. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3302. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3303. #ifdef CONFIG_IWL3945_DEBUG
  3304. if (priv->debug_level & IWL_DL_ISR) {
  3305. /* just for debug */
  3306. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3307. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3308. inta, inta_mask, inta_fh);
  3309. }
  3310. #endif
  3311. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3312. * atomic, make sure that inta covers all the interrupts that
  3313. * we've discovered, even if FH interrupt came in just after
  3314. * reading CSR_INT. */
  3315. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3316. inta |= CSR_INT_BIT_FH_RX;
  3317. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3318. inta |= CSR_INT_BIT_FH_TX;
  3319. /* Now service all interrupt bits discovered above. */
  3320. if (inta & CSR_INT_BIT_HW_ERR) {
  3321. IWL_ERR(priv, "Microcode HW error detected. Restarting.\n");
  3322. /* Tell the device to stop sending interrupts */
  3323. iwl3945_disable_interrupts(priv);
  3324. iwl3945_irq_handle_error(priv);
  3325. handled |= CSR_INT_BIT_HW_ERR;
  3326. spin_unlock_irqrestore(&priv->lock, flags);
  3327. return;
  3328. }
  3329. #ifdef CONFIG_IWL3945_DEBUG
  3330. if (priv->debug_level & (IWL_DL_ISR)) {
  3331. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3332. if (inta & CSR_INT_BIT_SCD)
  3333. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3334. "the frame/frames.\n");
  3335. /* Alive notification via Rx interrupt will do the real work */
  3336. if (inta & CSR_INT_BIT_ALIVE)
  3337. IWL_DEBUG_ISR("Alive interrupt\n");
  3338. }
  3339. #endif
  3340. /* Safely ignore these bits for debug checks below */
  3341. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3342. /* Error detected by uCode */
  3343. if (inta & CSR_INT_BIT_SW_ERR) {
  3344. IWL_ERR(priv, "Microcode SW error detected. "
  3345. "Restarting 0x%X.\n", inta);
  3346. iwl3945_irq_handle_error(priv);
  3347. handled |= CSR_INT_BIT_SW_ERR;
  3348. }
  3349. /* uCode wakes up after power-down sleep */
  3350. if (inta & CSR_INT_BIT_WAKEUP) {
  3351. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3352. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3353. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3354. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3355. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3356. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3357. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3358. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3359. handled |= CSR_INT_BIT_WAKEUP;
  3360. }
  3361. /* All uCode command responses, including Tx command responses,
  3362. * Rx "responses" (frame-received notification), and other
  3363. * notifications from uCode come through here*/
  3364. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3365. iwl3945_rx_handle(priv);
  3366. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3367. }
  3368. if (inta & CSR_INT_BIT_FH_TX) {
  3369. IWL_DEBUG_ISR("Tx interrupt\n");
  3370. iwl_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3371. if (!iwl_grab_nic_access(priv)) {
  3372. iwl_write_direct32(priv, FH39_TCSR_CREDIT
  3373. (FH39_SRVC_CHNL), 0x0);
  3374. iwl_release_nic_access(priv);
  3375. }
  3376. handled |= CSR_INT_BIT_FH_TX;
  3377. }
  3378. if (inta & ~handled)
  3379. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3380. if (inta & ~CSR_INI_SET_MASK) {
  3381. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  3382. inta & ~CSR_INI_SET_MASK);
  3383. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  3384. }
  3385. /* Re-enable all interrupts */
  3386. /* only Re-enable if disabled by irq */
  3387. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3388. iwl3945_enable_interrupts(priv);
  3389. #ifdef CONFIG_IWL3945_DEBUG
  3390. if (priv->debug_level & (IWL_DL_ISR)) {
  3391. inta = iwl_read32(priv, CSR_INT);
  3392. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  3393. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3394. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3395. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3396. }
  3397. #endif
  3398. spin_unlock_irqrestore(&priv->lock, flags);
  3399. }
  3400. static irqreturn_t iwl3945_isr(int irq, void *data)
  3401. {
  3402. struct iwl_priv *priv = data;
  3403. u32 inta, inta_mask;
  3404. u32 inta_fh;
  3405. if (!priv)
  3406. return IRQ_NONE;
  3407. spin_lock(&priv->lock);
  3408. /* Disable (but don't clear!) interrupts here to avoid
  3409. * back-to-back ISRs and sporadic interrupts from our NIC.
  3410. * If we have something to service, the tasklet will re-enable ints.
  3411. * If we *don't* have something, we'll re-enable before leaving here. */
  3412. inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
  3413. iwl_write32(priv, CSR_INT_MASK, 0x00000000);
  3414. /* Discover which interrupts are active/pending */
  3415. inta = iwl_read32(priv, CSR_INT);
  3416. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  3417. /* Ignore interrupt if there's nothing in NIC to service.
  3418. * This may be due to IRQ shared with another device,
  3419. * or due to sporadic interrupts thrown from our NIC. */
  3420. if (!inta && !inta_fh) {
  3421. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3422. goto none;
  3423. }
  3424. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3425. /* Hardware disappeared */
  3426. IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
  3427. goto unplugged;
  3428. }
  3429. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3430. inta, inta_mask, inta_fh);
  3431. inta &= ~CSR_INT_BIT_SCD;
  3432. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3433. if (likely(inta || inta_fh))
  3434. tasklet_schedule(&priv->irq_tasklet);
  3435. unplugged:
  3436. spin_unlock(&priv->lock);
  3437. return IRQ_HANDLED;
  3438. none:
  3439. /* re-enable interrupts here since we don't have anything to service. */
  3440. /* only Re-enable if disabled by irq */
  3441. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3442. iwl3945_enable_interrupts(priv);
  3443. spin_unlock(&priv->lock);
  3444. return IRQ_NONE;
  3445. }
  3446. /************************** EEPROM BANDS ****************************
  3447. *
  3448. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3449. * EEPROM contents to the specific channel number supported for each
  3450. * band.
  3451. *
  3452. * For example, iwl3945_priv->eeprom39.band_3_channels[4] from the band_3
  3453. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3454. * The specific geography and calibration information for that channel
  3455. * is contained in the eeprom map itself.
  3456. *
  3457. * During init, we copy the eeprom information and channel map
  3458. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3459. *
  3460. * channel_map_24/52 provides the index in the channel_info array for a
  3461. * given channel. We have to have two separate maps as there is channel
  3462. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3463. * band_2
  3464. *
  3465. * A value of 0xff stored in the channel_map indicates that the channel
  3466. * is not supported by the hardware at all.
  3467. *
  3468. * A value of 0xfe in the channel_map indicates that the channel is not
  3469. * valid for Tx with the current hardware. This means that
  3470. * while the system can tune and receive on a given channel, it may not
  3471. * be able to associate or transmit any frames on that
  3472. * channel. There is no corresponding channel information for that
  3473. * entry.
  3474. *
  3475. *********************************************************************/
  3476. /* 2.4 GHz */
  3477. static const u8 iwl3945_eeprom_band_1[14] = {
  3478. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3479. };
  3480. /* 5.2 GHz bands */
  3481. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3482. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3483. };
  3484. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3485. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3486. };
  3487. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3488. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3489. };
  3490. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3491. 145, 149, 153, 157, 161, 165
  3492. };
  3493. static void iwl3945_init_band_reference(const struct iwl_priv *priv, int band,
  3494. int *eeprom_ch_count,
  3495. const struct iwl_eeprom_channel
  3496. **eeprom_ch_info,
  3497. const u8 **eeprom_ch_index)
  3498. {
  3499. switch (band) {
  3500. case 1: /* 2.4GHz band */
  3501. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3502. *eeprom_ch_info = priv->eeprom39.band_1_channels;
  3503. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3504. break;
  3505. case 2: /* 4.9GHz band */
  3506. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3507. *eeprom_ch_info = priv->eeprom39.band_2_channels;
  3508. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3509. break;
  3510. case 3: /* 5.2GHz band */
  3511. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3512. *eeprom_ch_info = priv->eeprom39.band_3_channels;
  3513. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3514. break;
  3515. case 4: /* 5.5GHz band */
  3516. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3517. *eeprom_ch_info = priv->eeprom39.band_4_channels;
  3518. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3519. break;
  3520. case 5: /* 5.7GHz band */
  3521. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3522. *eeprom_ch_info = priv->eeprom39.band_5_channels;
  3523. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3524. break;
  3525. default:
  3526. BUG();
  3527. return;
  3528. }
  3529. }
  3530. /**
  3531. * iwl3945_get_channel_info - Find driver's private channel info
  3532. *
  3533. * Based on band and channel number.
  3534. */
  3535. const struct iwl_channel_info *
  3536. iwl3945_get_channel_info(const struct iwl_priv *priv,
  3537. enum ieee80211_band band, u16 channel)
  3538. {
  3539. int i;
  3540. switch (band) {
  3541. case IEEE80211_BAND_5GHZ:
  3542. for (i = 14; i < priv->channel_count; i++) {
  3543. if (priv->channel_info[i].channel == channel)
  3544. return &priv->channel_info[i];
  3545. }
  3546. break;
  3547. case IEEE80211_BAND_2GHZ:
  3548. if (channel >= 1 && channel <= 14)
  3549. return &priv->channel_info[channel - 1];
  3550. break;
  3551. case IEEE80211_NUM_BANDS:
  3552. WARN_ON(1);
  3553. }
  3554. return NULL;
  3555. }
  3556. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  3557. ? # x " " : "")
  3558. /**
  3559. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  3560. */
  3561. static int iwl3945_init_channel_map(struct iwl_priv *priv)
  3562. {
  3563. int eeprom_ch_count = 0;
  3564. const u8 *eeprom_ch_index = NULL;
  3565. const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
  3566. int band, ch;
  3567. struct iwl_channel_info *ch_info;
  3568. if (priv->channel_count) {
  3569. IWL_DEBUG_INFO("Channel map already initialized.\n");
  3570. return 0;
  3571. }
  3572. if (priv->eeprom39.version < 0x2f) {
  3573. IWL_WARN(priv, "Unsupported EEPROM version: 0x%04X\n",
  3574. priv->eeprom39.version);
  3575. return -EINVAL;
  3576. }
  3577. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  3578. priv->channel_count =
  3579. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  3580. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  3581. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  3582. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  3583. ARRAY_SIZE(iwl3945_eeprom_band_5);
  3584. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  3585. priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
  3586. priv->channel_count, GFP_KERNEL);
  3587. if (!priv->channel_info) {
  3588. IWL_ERR(priv, "Could not allocate channel_info\n");
  3589. priv->channel_count = 0;
  3590. return -ENOMEM;
  3591. }
  3592. ch_info = priv->channel_info;
  3593. /* Loop through the 5 EEPROM bands adding them in order to the
  3594. * channel map we maintain (that contains additional information than
  3595. * what just in the EEPROM) */
  3596. for (band = 1; band <= 5; band++) {
  3597. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  3598. &eeprom_ch_info, &eeprom_ch_index);
  3599. /* Loop through each band adding each of the channels */
  3600. for (ch = 0; ch < eeprom_ch_count; ch++) {
  3601. ch_info->channel = eeprom_ch_index[ch];
  3602. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  3603. IEEE80211_BAND_5GHZ;
  3604. /* permanently store EEPROM's channel regulatory flags
  3605. * and max power in channel info database. */
  3606. ch_info->eeprom = eeprom_ch_info[ch];
  3607. /* Copy the run-time flags so they are there even on
  3608. * invalid channels */
  3609. ch_info->flags = eeprom_ch_info[ch].flags;
  3610. if (!(is_channel_valid(ch_info))) {
  3611. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  3612. "No traffic\n",
  3613. ch_info->channel,
  3614. ch_info->flags,
  3615. is_channel_a_band(ch_info) ?
  3616. "5.2" : "2.4");
  3617. ch_info++;
  3618. continue;
  3619. }
  3620. /* Initialize regulatory-based run-time data */
  3621. ch_info->max_power_avg = ch_info->curr_txpow =
  3622. eeprom_ch_info[ch].max_power_avg;
  3623. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  3624. ch_info->min_power = 0;
  3625. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  3626. " %ddBm): Ad-Hoc %ssupported\n",
  3627. ch_info->channel,
  3628. is_channel_a_band(ch_info) ?
  3629. "5.2" : "2.4",
  3630. CHECK_AND_PRINT(VALID),
  3631. CHECK_AND_PRINT(IBSS),
  3632. CHECK_AND_PRINT(ACTIVE),
  3633. CHECK_AND_PRINT(RADAR),
  3634. CHECK_AND_PRINT(WIDE),
  3635. CHECK_AND_PRINT(DFS),
  3636. eeprom_ch_info[ch].flags,
  3637. eeprom_ch_info[ch].max_power_avg,
  3638. ((eeprom_ch_info[ch].
  3639. flags & EEPROM_CHANNEL_IBSS)
  3640. && !(eeprom_ch_info[ch].
  3641. flags & EEPROM_CHANNEL_RADAR))
  3642. ? "" : "not ");
  3643. /* Set the user_txpower_limit to the highest power
  3644. * supported by any channel */
  3645. if (eeprom_ch_info[ch].max_power_avg >
  3646. priv->user_txpower_limit)
  3647. priv->user_txpower_limit =
  3648. eeprom_ch_info[ch].max_power_avg;
  3649. ch_info++;
  3650. }
  3651. }
  3652. /* Set up txpower settings in driver for all channels */
  3653. if (iwl3945_txpower_set_from_eeprom(priv))
  3654. return -EIO;
  3655. return 0;
  3656. }
  3657. /*
  3658. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  3659. */
  3660. static void iwl3945_free_channel_map(struct iwl_priv *priv)
  3661. {
  3662. kfree(priv->channel_info);
  3663. priv->channel_count = 0;
  3664. }
  3665. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  3666. * sending probe req. This should be set long enough to hear probe responses
  3667. * from more than one AP. */
  3668. #define IWL_ACTIVE_DWELL_TIME_24 (30) /* all times in msec */
  3669. #define IWL_ACTIVE_DWELL_TIME_52 (20)
  3670. #define IWL_ACTIVE_DWELL_FACTOR_24GHZ (3)
  3671. #define IWL_ACTIVE_DWELL_FACTOR_52GHZ (2)
  3672. /* For faster active scanning, scan will move to the next channel if fewer than
  3673. * PLCP_QUIET_THRESH packets are heard on this channel within
  3674. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  3675. * time if it's a quiet channel (nothing responded to our probe, and there's
  3676. * no other traffic).
  3677. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  3678. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  3679. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(10) /* msec */
  3680. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  3681. * Must be set longer than active dwell time.
  3682. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  3683. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  3684. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  3685. #define IWL_PASSIVE_DWELL_BASE (100)
  3686. #define IWL_CHANNEL_TUNE_TIME 5
  3687. #define IWL_SCAN_PROBE_MASK(n) (BIT(n) | (BIT(n) - BIT(1)))
  3688. static inline u16 iwl3945_get_active_dwell_time(struct iwl_priv *priv,
  3689. enum ieee80211_band band,
  3690. u8 n_probes)
  3691. {
  3692. if (band == IEEE80211_BAND_5GHZ)
  3693. return IWL_ACTIVE_DWELL_TIME_52 +
  3694. IWL_ACTIVE_DWELL_FACTOR_52GHZ * (n_probes + 1);
  3695. else
  3696. return IWL_ACTIVE_DWELL_TIME_24 +
  3697. IWL_ACTIVE_DWELL_FACTOR_24GHZ * (n_probes + 1);
  3698. }
  3699. static u16 iwl3945_get_passive_dwell_time(struct iwl_priv *priv,
  3700. enum ieee80211_band band)
  3701. {
  3702. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  3703. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  3704. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  3705. if (iwl3945_is_associated(priv)) {
  3706. /* If we're associated, we clamp the maximum passive
  3707. * dwell time to be 98% of the beacon interval (minus
  3708. * 2 * channel tune time) */
  3709. passive = priv->beacon_int;
  3710. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  3711. passive = IWL_PASSIVE_DWELL_BASE;
  3712. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  3713. }
  3714. return passive;
  3715. }
  3716. static int iwl3945_get_channels_for_scan(struct iwl_priv *priv,
  3717. enum ieee80211_band band,
  3718. u8 is_active, u8 n_probes,
  3719. struct iwl3945_scan_channel *scan_ch)
  3720. {
  3721. const struct ieee80211_channel *channels = NULL;
  3722. const struct ieee80211_supported_band *sband;
  3723. const struct iwl_channel_info *ch_info;
  3724. u16 passive_dwell = 0;
  3725. u16 active_dwell = 0;
  3726. int added, i;
  3727. sband = iwl_get_hw_mode(priv, band);
  3728. if (!sband)
  3729. return 0;
  3730. channels = sband->channels;
  3731. active_dwell = iwl3945_get_active_dwell_time(priv, band, n_probes);
  3732. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  3733. if (passive_dwell <= active_dwell)
  3734. passive_dwell = active_dwell + 1;
  3735. for (i = 0, added = 0; i < sband->n_channels; i++) {
  3736. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  3737. continue;
  3738. scan_ch->channel = channels[i].hw_value;
  3739. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  3740. if (!is_channel_valid(ch_info)) {
  3741. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  3742. scan_ch->channel);
  3743. continue;
  3744. }
  3745. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  3746. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  3747. /* If passive , set up for auto-switch
  3748. * and use long active_dwell time.
  3749. */
  3750. if (!is_active || is_channel_passive(ch_info) ||
  3751. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN)) {
  3752. scan_ch->type = 0; /* passive */
  3753. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  3754. scan_ch->active_dwell = cpu_to_le16(passive_dwell - 1);
  3755. } else {
  3756. scan_ch->type = 1; /* active */
  3757. }
  3758. /* Set direct probe bits. These may be used both for active
  3759. * scan channels (probes gets sent right away),
  3760. * or for passive channels (probes get se sent only after
  3761. * hearing clear Rx packet).*/
  3762. if (IWL_UCODE_API(priv->ucode_ver) >= 2) {
  3763. if (n_probes)
  3764. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3765. } else {
  3766. /* uCode v1 does not allow setting direct probe bits on
  3767. * passive channel. */
  3768. if ((scan_ch->type & 1) && n_probes)
  3769. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  3770. }
  3771. /* Set txpower levels to defaults */
  3772. scan_ch->tpc.dsp_atten = 110;
  3773. /* scan_pwr_info->tpc.dsp_atten; */
  3774. /*scan_pwr_info->tpc.tx_gain; */
  3775. if (band == IEEE80211_BAND_5GHZ)
  3776. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  3777. else {
  3778. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  3779. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  3780. * power level:
  3781. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  3782. */
  3783. }
  3784. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  3785. scan_ch->channel,
  3786. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  3787. (scan_ch->type & 1) ?
  3788. active_dwell : passive_dwell);
  3789. scan_ch++;
  3790. added++;
  3791. }
  3792. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  3793. return added;
  3794. }
  3795. static void iwl3945_init_hw_rates(struct iwl_priv *priv,
  3796. struct ieee80211_rate *rates)
  3797. {
  3798. int i;
  3799. for (i = 0; i < IWL_RATE_COUNT; i++) {
  3800. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  3801. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  3802. rates[i].hw_value_short = i;
  3803. rates[i].flags = 0;
  3804. if ((i > IWL39_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  3805. /*
  3806. * If CCK != 1M then set short preamble rate flag.
  3807. */
  3808. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  3809. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  3810. }
  3811. }
  3812. }
  3813. /**
  3814. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  3815. */
  3816. static int iwl3945_init_geos(struct iwl_priv *priv)
  3817. {
  3818. struct iwl_channel_info *ch;
  3819. struct ieee80211_supported_band *sband;
  3820. struct ieee80211_channel *channels;
  3821. struct ieee80211_channel *geo_ch;
  3822. struct ieee80211_rate *rates;
  3823. int i = 0;
  3824. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  3825. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  3826. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  3827. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3828. return 0;
  3829. }
  3830. channels = kzalloc(sizeof(struct ieee80211_channel) *
  3831. priv->channel_count, GFP_KERNEL);
  3832. if (!channels)
  3833. return -ENOMEM;
  3834. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  3835. GFP_KERNEL);
  3836. if (!rates) {
  3837. kfree(channels);
  3838. return -ENOMEM;
  3839. }
  3840. /* 5.2GHz channels start after the 2.4GHz channels */
  3841. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3842. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  3843. /* just OFDM */
  3844. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  3845. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  3846. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3847. sband->channels = channels;
  3848. /* OFDM & CCK */
  3849. sband->bitrates = rates;
  3850. sband->n_bitrates = IWL_RATE_COUNT;
  3851. priv->ieee_channels = channels;
  3852. priv->ieee_rates = rates;
  3853. iwl3945_init_hw_rates(priv, rates);
  3854. for (i = 0; i < priv->channel_count; i++) {
  3855. ch = &priv->channel_info[i];
  3856. /* FIXME: might be removed if scan is OK*/
  3857. if (!is_channel_valid(ch))
  3858. continue;
  3859. if (is_channel_a_band(ch))
  3860. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  3861. else
  3862. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  3863. geo_ch = &sband->channels[sband->n_channels++];
  3864. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  3865. geo_ch->max_power = ch->max_power_avg;
  3866. geo_ch->max_antenna_gain = 0xff;
  3867. geo_ch->hw_value = ch->channel;
  3868. if (is_channel_valid(ch)) {
  3869. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  3870. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  3871. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  3872. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  3873. if (ch->flags & EEPROM_CHANNEL_RADAR)
  3874. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  3875. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  3876. priv->max_channel_txpower_limit =
  3877. ch->max_power_avg;
  3878. } else {
  3879. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  3880. }
  3881. /* Save flags for reg domain usage */
  3882. geo_ch->orig_flags = geo_ch->flags;
  3883. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  3884. ch->channel, geo_ch->center_freq,
  3885. is_channel_a_band(ch) ? "5.2" : "2.4",
  3886. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  3887. "restricted" : "valid",
  3888. geo_ch->flags);
  3889. }
  3890. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  3891. priv->cfg->sku & IWL_SKU_A) {
  3892. IWL_INFO(priv, "Incorrectly detected BG card as ABG. "
  3893. "Please send your PCI ID 0x%04X:0x%04X to maintainer.\n",
  3894. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  3895. priv->cfg->sku &= ~IWL_SKU_A;
  3896. }
  3897. IWL_INFO(priv, "Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  3898. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  3899. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  3900. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  3901. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  3902. &priv->bands[IEEE80211_BAND_2GHZ];
  3903. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  3904. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  3905. &priv->bands[IEEE80211_BAND_5GHZ];
  3906. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3907. return 0;
  3908. }
  3909. /*
  3910. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  3911. */
  3912. static void iwl3945_free_geos(struct iwl_priv *priv)
  3913. {
  3914. kfree(priv->ieee_channels);
  3915. kfree(priv->ieee_rates);
  3916. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  3917. }
  3918. /******************************************************************************
  3919. *
  3920. * uCode download functions
  3921. *
  3922. ******************************************************************************/
  3923. static void iwl3945_dealloc_ucode_pci(struct iwl_priv *priv)
  3924. {
  3925. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  3926. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  3927. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  3928. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  3929. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  3930. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  3931. }
  3932. /**
  3933. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  3934. * looking at all data.
  3935. */
  3936. static int iwl3945_verify_inst_full(struct iwl_priv *priv, __le32 *image, u32 len)
  3937. {
  3938. u32 val;
  3939. u32 save_len = len;
  3940. int rc = 0;
  3941. u32 errcnt;
  3942. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  3943. rc = iwl_grab_nic_access(priv);
  3944. if (rc)
  3945. return rc;
  3946. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  3947. IWL39_RTC_INST_LOWER_BOUND);
  3948. errcnt = 0;
  3949. for (; len > 0; len -= sizeof(u32), image++) {
  3950. /* read data comes through single port, auto-incr addr */
  3951. /* NOTE: Use the debugless read so we don't flood kernel log
  3952. * if IWL_DL_IO is set */
  3953. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  3954. if (val != le32_to_cpu(*image)) {
  3955. IWL_ERR(priv, "uCode INST section is invalid at "
  3956. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  3957. save_len - len, val, le32_to_cpu(*image));
  3958. rc = -EIO;
  3959. errcnt++;
  3960. if (errcnt >= 20)
  3961. break;
  3962. }
  3963. }
  3964. iwl_release_nic_access(priv);
  3965. if (!errcnt)
  3966. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  3967. return rc;
  3968. }
  3969. /**
  3970. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  3971. * using sample data 100 bytes apart. If these sample points are good,
  3972. * it's a pretty good bet that everything between them is good, too.
  3973. */
  3974. static int iwl3945_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
  3975. {
  3976. u32 val;
  3977. int rc = 0;
  3978. u32 errcnt = 0;
  3979. u32 i;
  3980. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  3981. rc = iwl_grab_nic_access(priv);
  3982. if (rc)
  3983. return rc;
  3984. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  3985. /* read data comes through single port, auto-incr addr */
  3986. /* NOTE: Use the debugless read so we don't flood kernel log
  3987. * if IWL_DL_IO is set */
  3988. iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  3989. i + IWL39_RTC_INST_LOWER_BOUND);
  3990. val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  3991. if (val != le32_to_cpu(*image)) {
  3992. #if 0 /* Enable this if you want to see details */
  3993. IWL_ERR(priv, "uCode INST section is invalid at "
  3994. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  3995. i, val, *image);
  3996. #endif
  3997. rc = -EIO;
  3998. errcnt++;
  3999. if (errcnt >= 3)
  4000. break;
  4001. }
  4002. }
  4003. iwl_release_nic_access(priv);
  4004. return rc;
  4005. }
  4006. /**
  4007. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4008. * and verify its contents
  4009. */
  4010. static int iwl3945_verify_ucode(struct iwl_priv *priv)
  4011. {
  4012. __le32 *image;
  4013. u32 len;
  4014. int rc = 0;
  4015. /* Try bootstrap */
  4016. image = (__le32 *)priv->ucode_boot.v_addr;
  4017. len = priv->ucode_boot.len;
  4018. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4019. if (rc == 0) {
  4020. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4021. return 0;
  4022. }
  4023. /* Try initialize */
  4024. image = (__le32 *)priv->ucode_init.v_addr;
  4025. len = priv->ucode_init.len;
  4026. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4027. if (rc == 0) {
  4028. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4029. return 0;
  4030. }
  4031. /* Try runtime/protocol */
  4032. image = (__le32 *)priv->ucode_code.v_addr;
  4033. len = priv->ucode_code.len;
  4034. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4035. if (rc == 0) {
  4036. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4037. return 0;
  4038. }
  4039. IWL_ERR(priv, "NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4040. /* Since nothing seems to match, show first several data entries in
  4041. * instruction SRAM, so maybe visual inspection will give a clue.
  4042. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4043. image = (__le32 *)priv->ucode_boot.v_addr;
  4044. len = priv->ucode_boot.len;
  4045. rc = iwl3945_verify_inst_full(priv, image, len);
  4046. return rc;
  4047. }
  4048. static void iwl3945_nic_start(struct iwl_priv *priv)
  4049. {
  4050. /* Remove all resets to allow NIC to operate */
  4051. iwl_write32(priv, CSR_RESET, 0);
  4052. }
  4053. /**
  4054. * iwl3945_read_ucode - Read uCode images from disk file.
  4055. *
  4056. * Copy into buffers for card to fetch via bus-mastering
  4057. */
  4058. static int iwl3945_read_ucode(struct iwl_priv *priv)
  4059. {
  4060. struct iwl_ucode *ucode;
  4061. int ret = -EINVAL, index;
  4062. const struct firmware *ucode_raw;
  4063. /* firmware file name contains uCode/driver compatibility version */
  4064. const char *name_pre = priv->cfg->fw_name_pre;
  4065. const unsigned int api_max = priv->cfg->ucode_api_max;
  4066. const unsigned int api_min = priv->cfg->ucode_api_min;
  4067. char buf[25];
  4068. u8 *src;
  4069. size_t len;
  4070. u32 api_ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4071. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4072. * request_firmware() is synchronous, file is in memory on return. */
  4073. for (index = api_max; index >= api_min; index--) {
  4074. sprintf(buf, "%s%u%s", name_pre, index, ".ucode");
  4075. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  4076. if (ret < 0) {
  4077. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  4078. buf, ret);
  4079. if (ret == -ENOENT)
  4080. continue;
  4081. else
  4082. goto error;
  4083. } else {
  4084. if (index < api_max)
  4085. IWL_ERR(priv, "Loaded firmware %s, "
  4086. "which is deprecated. "
  4087. " Please use API v%u instead.\n",
  4088. buf, api_max);
  4089. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4090. buf, ucode_raw->size);
  4091. break;
  4092. }
  4093. }
  4094. if (ret < 0)
  4095. goto error;
  4096. /* Make sure that we got at least our header! */
  4097. if (ucode_raw->size < sizeof(*ucode)) {
  4098. IWL_ERR(priv, "File size way too small!\n");
  4099. ret = -EINVAL;
  4100. goto err_release;
  4101. }
  4102. /* Data from ucode file: header followed by uCode images */
  4103. ucode = (void *)ucode_raw->data;
  4104. priv->ucode_ver = le32_to_cpu(ucode->ver);
  4105. api_ver = IWL_UCODE_API(priv->ucode_ver);
  4106. inst_size = le32_to_cpu(ucode->inst_size);
  4107. data_size = le32_to_cpu(ucode->data_size);
  4108. init_size = le32_to_cpu(ucode->init_size);
  4109. init_data_size = le32_to_cpu(ucode->init_data_size);
  4110. boot_size = le32_to_cpu(ucode->boot_size);
  4111. /* api_ver should match the api version forming part of the
  4112. * firmware filename ... but we don't check for that and only rely
  4113. * on the API version read from firware header from here on forward */
  4114. if (api_ver < api_min || api_ver > api_max) {
  4115. IWL_ERR(priv, "Driver unable to support your firmware API. "
  4116. "Driver supports v%u, firmware is v%u.\n",
  4117. api_max, api_ver);
  4118. priv->ucode_ver = 0;
  4119. ret = -EINVAL;
  4120. goto err_release;
  4121. }
  4122. if (api_ver != api_max)
  4123. IWL_ERR(priv, "Firmware has old API version. Expected %u, "
  4124. "got %u. New firmware can be obtained "
  4125. "from http://www.intellinuxwireless.org.\n",
  4126. api_max, api_ver);
  4127. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  4128. IWL_UCODE_MAJOR(priv->ucode_ver),
  4129. IWL_UCODE_MINOR(priv->ucode_ver),
  4130. IWL_UCODE_API(priv->ucode_ver),
  4131. IWL_UCODE_SERIAL(priv->ucode_ver));
  4132. IWL_DEBUG_INFO("f/w package hdr ucode version raw = 0x%x\n",
  4133. priv->ucode_ver);
  4134. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4135. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4136. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4137. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4138. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4139. /* Verify size of file vs. image size info in file's header */
  4140. if (ucode_raw->size < sizeof(*ucode) +
  4141. inst_size + data_size + init_size +
  4142. init_data_size + boot_size) {
  4143. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4144. (int)ucode_raw->size);
  4145. ret = -EINVAL;
  4146. goto err_release;
  4147. }
  4148. /* Verify that uCode images will fit in card's SRAM */
  4149. if (inst_size > IWL39_MAX_INST_SIZE) {
  4150. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4151. inst_size);
  4152. ret = -EINVAL;
  4153. goto err_release;
  4154. }
  4155. if (data_size > IWL39_MAX_DATA_SIZE) {
  4156. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4157. data_size);
  4158. ret = -EINVAL;
  4159. goto err_release;
  4160. }
  4161. if (init_size > IWL39_MAX_INST_SIZE) {
  4162. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4163. init_size);
  4164. ret = -EINVAL;
  4165. goto err_release;
  4166. }
  4167. if (init_data_size > IWL39_MAX_DATA_SIZE) {
  4168. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4169. init_data_size);
  4170. ret = -EINVAL;
  4171. goto err_release;
  4172. }
  4173. if (boot_size > IWL39_MAX_BSM_SIZE) {
  4174. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4175. boot_size);
  4176. ret = -EINVAL;
  4177. goto err_release;
  4178. }
  4179. /* Allocate ucode buffers for card's bus-master loading ... */
  4180. /* Runtime instructions and 2 copies of data:
  4181. * 1) unmodified from disk
  4182. * 2) backup cache for save/restore during power-downs */
  4183. priv->ucode_code.len = inst_size;
  4184. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4185. priv->ucode_data.len = data_size;
  4186. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4187. priv->ucode_data_backup.len = data_size;
  4188. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4189. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4190. !priv->ucode_data_backup.v_addr)
  4191. goto err_pci_alloc;
  4192. /* Initialization instructions and data */
  4193. if (init_size && init_data_size) {
  4194. priv->ucode_init.len = init_size;
  4195. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4196. priv->ucode_init_data.len = init_data_size;
  4197. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4198. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4199. goto err_pci_alloc;
  4200. }
  4201. /* Bootstrap (instructions only, no data) */
  4202. if (boot_size) {
  4203. priv->ucode_boot.len = boot_size;
  4204. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4205. if (!priv->ucode_boot.v_addr)
  4206. goto err_pci_alloc;
  4207. }
  4208. /* Copy images into buffers for card's bus-master reads ... */
  4209. /* Runtime instructions (first block of data in file) */
  4210. src = &ucode->data[0];
  4211. len = priv->ucode_code.len;
  4212. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4213. memcpy(priv->ucode_code.v_addr, src, len);
  4214. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4215. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4216. /* Runtime data (2nd block)
  4217. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4218. src = &ucode->data[inst_size];
  4219. len = priv->ucode_data.len;
  4220. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4221. memcpy(priv->ucode_data.v_addr, src, len);
  4222. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4223. /* Initialization instructions (3rd block) */
  4224. if (init_size) {
  4225. src = &ucode->data[inst_size + data_size];
  4226. len = priv->ucode_init.len;
  4227. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4228. len);
  4229. memcpy(priv->ucode_init.v_addr, src, len);
  4230. }
  4231. /* Initialization data (4th block) */
  4232. if (init_data_size) {
  4233. src = &ucode->data[inst_size + data_size + init_size];
  4234. len = priv->ucode_init_data.len;
  4235. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4236. (int)len);
  4237. memcpy(priv->ucode_init_data.v_addr, src, len);
  4238. }
  4239. /* Bootstrap instructions (5th block) */
  4240. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4241. len = priv->ucode_boot.len;
  4242. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4243. (int)len);
  4244. memcpy(priv->ucode_boot.v_addr, src, len);
  4245. /* We have our copies now, allow OS release its copies */
  4246. release_firmware(ucode_raw);
  4247. return 0;
  4248. err_pci_alloc:
  4249. IWL_ERR(priv, "failed to allocate pci memory\n");
  4250. ret = -ENOMEM;
  4251. iwl3945_dealloc_ucode_pci(priv);
  4252. err_release:
  4253. release_firmware(ucode_raw);
  4254. error:
  4255. return ret;
  4256. }
  4257. /**
  4258. * iwl3945_set_ucode_ptrs - Set uCode address location
  4259. *
  4260. * Tell initialization uCode where to find runtime uCode.
  4261. *
  4262. * BSM registers initially contain pointers to initialization uCode.
  4263. * We need to replace them to load runtime uCode inst and data,
  4264. * and to save runtime data when powering down.
  4265. */
  4266. static int iwl3945_set_ucode_ptrs(struct iwl_priv *priv)
  4267. {
  4268. dma_addr_t pinst;
  4269. dma_addr_t pdata;
  4270. int rc = 0;
  4271. unsigned long flags;
  4272. /* bits 31:0 for 3945 */
  4273. pinst = priv->ucode_code.p_addr;
  4274. pdata = priv->ucode_data_backup.p_addr;
  4275. spin_lock_irqsave(&priv->lock, flags);
  4276. rc = iwl_grab_nic_access(priv);
  4277. if (rc) {
  4278. spin_unlock_irqrestore(&priv->lock, flags);
  4279. return rc;
  4280. }
  4281. /* Tell bootstrap uCode where to find image to load */
  4282. iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4283. iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4284. iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4285. priv->ucode_data.len);
  4286. /* Inst byte count must be last to set up, bit 31 signals uCode
  4287. * that all new ptr/size info is in place */
  4288. iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4289. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4290. iwl_release_nic_access(priv);
  4291. spin_unlock_irqrestore(&priv->lock, flags);
  4292. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4293. return rc;
  4294. }
  4295. /**
  4296. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4297. *
  4298. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4299. *
  4300. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4301. */
  4302. static void iwl3945_init_alive_start(struct iwl_priv *priv)
  4303. {
  4304. /* Check alive response for "valid" sign from uCode */
  4305. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4306. /* We had an error bringing up the hardware, so take it
  4307. * all the way back down so we can try again */
  4308. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4309. goto restart;
  4310. }
  4311. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4312. * This is a paranoid check, because we would not have gotten the
  4313. * "initialize" alive if code weren't properly loaded. */
  4314. if (iwl3945_verify_ucode(priv)) {
  4315. /* Runtime instruction load was bad;
  4316. * take it all the way back down so we can try again */
  4317. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4318. goto restart;
  4319. }
  4320. /* Send pointers to protocol/runtime uCode image ... init code will
  4321. * load and launch runtime uCode, which will send us another "Alive"
  4322. * notification. */
  4323. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4324. if (iwl3945_set_ucode_ptrs(priv)) {
  4325. /* Runtime instruction load won't happen;
  4326. * take it all the way back down so we can try again */
  4327. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4328. goto restart;
  4329. }
  4330. return;
  4331. restart:
  4332. queue_work(priv->workqueue, &priv->restart);
  4333. }
  4334. /* temporary */
  4335. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw,
  4336. struct sk_buff *skb);
  4337. /**
  4338. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4339. * from protocol/runtime uCode (initialization uCode's
  4340. * Alive gets handled by iwl3945_init_alive_start()).
  4341. */
  4342. static void iwl3945_alive_start(struct iwl_priv *priv)
  4343. {
  4344. int rc = 0;
  4345. int thermal_spin = 0;
  4346. u32 rfkill;
  4347. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4348. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4349. /* We had an error bringing up the hardware, so take it
  4350. * all the way back down so we can try again */
  4351. IWL_DEBUG_INFO("Alive failed.\n");
  4352. goto restart;
  4353. }
  4354. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4355. * This is a paranoid check, because we would not have gotten the
  4356. * "runtime" alive if code weren't properly loaded. */
  4357. if (iwl3945_verify_ucode(priv)) {
  4358. /* Runtime instruction load was bad;
  4359. * take it all the way back down so we can try again */
  4360. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4361. goto restart;
  4362. }
  4363. iwl3945_clear_stations_table(priv);
  4364. rc = iwl_grab_nic_access(priv);
  4365. if (rc) {
  4366. IWL_WARN(priv, "Can not read RFKILL status from adapter\n");
  4367. return;
  4368. }
  4369. rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
  4370. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4371. iwl_release_nic_access(priv);
  4372. if (rfkill & 0x1) {
  4373. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4374. /* if RFKILL is not on, then wait for thermal
  4375. * sensor in adapter to kick in */
  4376. while (iwl3945_hw_get_temperature(priv) == 0) {
  4377. thermal_spin++;
  4378. udelay(10);
  4379. }
  4380. if (thermal_spin)
  4381. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4382. thermal_spin * 10);
  4383. } else
  4384. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4385. /* After the ALIVE response, we can send commands to 3945 uCode */
  4386. set_bit(STATUS_ALIVE, &priv->status);
  4387. /* Clear out the uCode error bit if it is set */
  4388. clear_bit(STATUS_FW_ERROR, &priv->status);
  4389. if (iwl_is_rfkill(priv))
  4390. return;
  4391. ieee80211_wake_queues(priv->hw);
  4392. priv->active_rate = priv->rates_mask;
  4393. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4394. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4395. if (iwl3945_is_associated(priv)) {
  4396. struct iwl3945_rxon_cmd *active_rxon =
  4397. (struct iwl3945_rxon_cmd *)(&priv->active39_rxon);
  4398. memcpy(&priv->staging39_rxon, &priv->active39_rxon,
  4399. sizeof(priv->staging39_rxon));
  4400. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4401. } else {
  4402. /* Initialize our rx_config data */
  4403. iwl3945_connection_init_rx_config(priv, priv->iw_mode);
  4404. memcpy(priv->staging39_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4405. }
  4406. /* Configure Bluetooth device coexistence support */
  4407. iwl3945_send_bt_config(priv);
  4408. /* Configure the adapter for unassociated operation */
  4409. iwl3945_commit_rxon(priv);
  4410. iwl3945_reg_txpower_periodic(priv);
  4411. iwl3945_led_register(priv);
  4412. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4413. set_bit(STATUS_READY, &priv->status);
  4414. wake_up_interruptible(&priv->wait_command_queue);
  4415. if (priv->error_recovering)
  4416. iwl3945_error_recovery(priv);
  4417. /* reassociate for ADHOC mode */
  4418. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  4419. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  4420. priv->vif);
  4421. if (beacon)
  4422. iwl3945_mac_beacon_update(priv->hw, beacon);
  4423. }
  4424. return;
  4425. restart:
  4426. queue_work(priv->workqueue, &priv->restart);
  4427. }
  4428. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv);
  4429. static void __iwl3945_down(struct iwl_priv *priv)
  4430. {
  4431. unsigned long flags;
  4432. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4433. struct ieee80211_conf *conf = NULL;
  4434. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4435. conf = ieee80211_get_hw_conf(priv->hw);
  4436. if (!exit_pending)
  4437. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4438. iwl3945_led_unregister(priv);
  4439. iwl3945_clear_stations_table(priv);
  4440. /* Unblock any waiting calls */
  4441. wake_up_interruptible_all(&priv->wait_command_queue);
  4442. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4443. * exiting the module */
  4444. if (!exit_pending)
  4445. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4446. /* stop and reset the on-board processor */
  4447. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4448. /* tell the device to stop sending interrupts */
  4449. spin_lock_irqsave(&priv->lock, flags);
  4450. iwl3945_disable_interrupts(priv);
  4451. spin_unlock_irqrestore(&priv->lock, flags);
  4452. iwl_synchronize_irq(priv);
  4453. if (priv->mac80211_registered)
  4454. ieee80211_stop_queues(priv->hw);
  4455. /* If we have not previously called iwl3945_init() then
  4456. * clear all bits but the RF Kill and SUSPEND bits and return */
  4457. if (!iwl_is_init(priv)) {
  4458. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4459. STATUS_RF_KILL_HW |
  4460. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4461. STATUS_RF_KILL_SW |
  4462. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4463. STATUS_GEO_CONFIGURED |
  4464. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4465. STATUS_IN_SUSPEND |
  4466. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4467. STATUS_EXIT_PENDING;
  4468. goto exit;
  4469. }
  4470. /* ...otherwise clear out all the status bits but the RF Kill and
  4471. * SUSPEND bits and continue taking the NIC down. */
  4472. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4473. STATUS_RF_KILL_HW |
  4474. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4475. STATUS_RF_KILL_SW |
  4476. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4477. STATUS_GEO_CONFIGURED |
  4478. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4479. STATUS_IN_SUSPEND |
  4480. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4481. STATUS_FW_ERROR |
  4482. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  4483. STATUS_EXIT_PENDING;
  4484. spin_lock_irqsave(&priv->lock, flags);
  4485. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4486. spin_unlock_irqrestore(&priv->lock, flags);
  4487. iwl3945_hw_txq_ctx_stop(priv);
  4488. iwl3945_hw_rxq_stop(priv);
  4489. spin_lock_irqsave(&priv->lock, flags);
  4490. if (!iwl_grab_nic_access(priv)) {
  4491. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  4492. APMG_CLK_VAL_DMA_CLK_RQT);
  4493. iwl_release_nic_access(priv);
  4494. }
  4495. spin_unlock_irqrestore(&priv->lock, flags);
  4496. udelay(5);
  4497. priv->cfg->ops->lib->apm_ops.reset(priv);
  4498. exit:
  4499. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  4500. if (priv->ibss_beacon)
  4501. dev_kfree_skb(priv->ibss_beacon);
  4502. priv->ibss_beacon = NULL;
  4503. /* clear out any free frames */
  4504. iwl3945_clear_free_frames(priv);
  4505. }
  4506. static void iwl3945_down(struct iwl_priv *priv)
  4507. {
  4508. mutex_lock(&priv->mutex);
  4509. __iwl3945_down(priv);
  4510. mutex_unlock(&priv->mutex);
  4511. iwl3945_cancel_deferred_work(priv);
  4512. }
  4513. #define MAX_HW_RESTARTS 5
  4514. static int __iwl3945_up(struct iwl_priv *priv)
  4515. {
  4516. int rc, i;
  4517. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4518. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  4519. return -EIO;
  4520. }
  4521. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  4522. IWL_WARN(priv, "Radio disabled by SW RF kill (module "
  4523. "parameter)\n");
  4524. return -ENODEV;
  4525. }
  4526. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  4527. IWL_ERR(priv, "ucode not available for device bring up\n");
  4528. return -EIO;
  4529. }
  4530. /* If platform's RF_KILL switch is NOT set to KILL */
  4531. if (iwl_read32(priv, CSR_GP_CNTRL) &
  4532. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  4533. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4534. else {
  4535. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4536. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  4537. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  4538. return -ENODEV;
  4539. }
  4540. }
  4541. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4542. rc = iwl3945_hw_nic_init(priv);
  4543. if (rc) {
  4544. IWL_ERR(priv, "Unable to int nic\n");
  4545. return rc;
  4546. }
  4547. /* make sure rfkill handshake bits are cleared */
  4548. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4549. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  4550. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  4551. /* clear (again), then enable host interrupts */
  4552. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  4553. iwl3945_enable_interrupts(priv);
  4554. /* really make sure rfkill handshake bits are cleared */
  4555. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4556. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  4557. /* Copy original ucode data image from disk into backup cache.
  4558. * This will be used to initialize the on-board processor's
  4559. * data SRAM for a clean start when the runtime program first loads. */
  4560. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  4561. priv->ucode_data.len);
  4562. /* We return success when we resume from suspend and rf_kill is on. */
  4563. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  4564. return 0;
  4565. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  4566. iwl3945_clear_stations_table(priv);
  4567. /* load bootstrap state machine,
  4568. * load bootstrap program into processor's memory,
  4569. * prepare to load the "initialize" uCode */
  4570. priv->cfg->ops->lib->load_ucode(priv);
  4571. if (rc) {
  4572. IWL_ERR(priv,
  4573. "Unable to set up bootstrap uCode: %d\n", rc);
  4574. continue;
  4575. }
  4576. /* start card; "initialize" will load runtime ucode */
  4577. iwl3945_nic_start(priv);
  4578. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  4579. return 0;
  4580. }
  4581. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4582. __iwl3945_down(priv);
  4583. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4584. /* tried to restart and config the device for as long as our
  4585. * patience could withstand */
  4586. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  4587. return -EIO;
  4588. }
  4589. /*****************************************************************************
  4590. *
  4591. * Workqueue callbacks
  4592. *
  4593. *****************************************************************************/
  4594. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  4595. {
  4596. struct iwl_priv *priv =
  4597. container_of(data, struct iwl_priv, init_alive_start.work);
  4598. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4599. return;
  4600. mutex_lock(&priv->mutex);
  4601. iwl3945_init_alive_start(priv);
  4602. mutex_unlock(&priv->mutex);
  4603. }
  4604. static void iwl3945_bg_alive_start(struct work_struct *data)
  4605. {
  4606. struct iwl_priv *priv =
  4607. container_of(data, struct iwl_priv, alive_start.work);
  4608. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4609. return;
  4610. mutex_lock(&priv->mutex);
  4611. iwl3945_alive_start(priv);
  4612. mutex_unlock(&priv->mutex);
  4613. }
  4614. static void iwl3945_bg_rf_kill(struct work_struct *work)
  4615. {
  4616. struct iwl_priv *priv = container_of(work, struct iwl_priv, rf_kill);
  4617. wake_up_interruptible(&priv->wait_command_queue);
  4618. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4619. return;
  4620. mutex_lock(&priv->mutex);
  4621. if (!iwl_is_rfkill(priv)) {
  4622. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  4623. "HW and/or SW RF Kill no longer active, restarting "
  4624. "device\n");
  4625. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4626. queue_work(priv->workqueue, &priv->restart);
  4627. } else {
  4628. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  4629. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  4630. "disabled by SW switch\n");
  4631. else
  4632. IWL_WARN(priv, "Radio Frequency Kill Switch is On:\n"
  4633. "Kill switch must be turned off for "
  4634. "wireless networking to work.\n");
  4635. }
  4636. mutex_unlock(&priv->mutex);
  4637. iwl3945_rfkill_set_hw_state(priv);
  4638. }
  4639. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  4640. static void iwl3945_bg_scan_check(struct work_struct *data)
  4641. {
  4642. struct iwl_priv *priv =
  4643. container_of(data, struct iwl_priv, scan_check.work);
  4644. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4645. return;
  4646. mutex_lock(&priv->mutex);
  4647. if (test_bit(STATUS_SCANNING, &priv->status) ||
  4648. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4649. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  4650. "Scan completion watchdog resetting adapter (%dms)\n",
  4651. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  4652. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  4653. iwl3945_send_scan_abort(priv);
  4654. }
  4655. mutex_unlock(&priv->mutex);
  4656. }
  4657. static void iwl3945_bg_request_scan(struct work_struct *data)
  4658. {
  4659. struct iwl_priv *priv =
  4660. container_of(data, struct iwl_priv, request_scan);
  4661. struct iwl_host_cmd cmd = {
  4662. .id = REPLY_SCAN_CMD,
  4663. .len = sizeof(struct iwl3945_scan_cmd),
  4664. .meta.flags = CMD_SIZE_HUGE,
  4665. };
  4666. int rc = 0;
  4667. struct iwl3945_scan_cmd *scan;
  4668. struct ieee80211_conf *conf = NULL;
  4669. u8 n_probes = 2;
  4670. enum ieee80211_band band;
  4671. DECLARE_SSID_BUF(ssid);
  4672. conf = ieee80211_get_hw_conf(priv->hw);
  4673. mutex_lock(&priv->mutex);
  4674. if (!iwl_is_ready(priv)) {
  4675. IWL_WARN(priv, "request scan called when driver not ready.\n");
  4676. goto done;
  4677. }
  4678. /* Make sure the scan wasn't canceled before this queued work
  4679. * was given the chance to run... */
  4680. if (!test_bit(STATUS_SCANNING, &priv->status))
  4681. goto done;
  4682. /* This should never be called or scheduled if there is currently
  4683. * a scan active in the hardware. */
  4684. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  4685. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  4686. "Ignoring second request.\n");
  4687. rc = -EIO;
  4688. goto done;
  4689. }
  4690. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  4691. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  4692. goto done;
  4693. }
  4694. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  4695. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  4696. goto done;
  4697. }
  4698. if (iwl_is_rfkill(priv)) {
  4699. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  4700. goto done;
  4701. }
  4702. if (!test_bit(STATUS_READY, &priv->status)) {
  4703. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  4704. goto done;
  4705. }
  4706. if (!priv->scan_bands) {
  4707. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  4708. goto done;
  4709. }
  4710. if (!priv->scan39) {
  4711. priv->scan39 = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  4712. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  4713. if (!priv->scan39) {
  4714. rc = -ENOMEM;
  4715. goto done;
  4716. }
  4717. }
  4718. scan = priv->scan39;
  4719. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  4720. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  4721. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  4722. if (iwl3945_is_associated(priv)) {
  4723. u16 interval = 0;
  4724. u32 extra;
  4725. u32 suspend_time = 100;
  4726. u32 scan_suspend_time = 100;
  4727. unsigned long flags;
  4728. IWL_DEBUG_INFO("Scanning while associated...\n");
  4729. spin_lock_irqsave(&priv->lock, flags);
  4730. interval = priv->beacon_int;
  4731. spin_unlock_irqrestore(&priv->lock, flags);
  4732. scan->suspend_time = 0;
  4733. scan->max_out_time = cpu_to_le32(200 * 1024);
  4734. if (!interval)
  4735. interval = suspend_time;
  4736. /*
  4737. * suspend time format:
  4738. * 0-19: beacon interval in usec (time before exec.)
  4739. * 20-23: 0
  4740. * 24-31: number of beacons (suspend between channels)
  4741. */
  4742. extra = (suspend_time / interval) << 24;
  4743. scan_suspend_time = 0xFF0FFFFF &
  4744. (extra | ((suspend_time % interval) * 1024));
  4745. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  4746. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  4747. scan_suspend_time, interval);
  4748. }
  4749. /* We should add the ability for user to lock to PASSIVE ONLY */
  4750. if (priv->one_direct_scan) {
  4751. IWL_DEBUG_SCAN
  4752. ("Kicking off one direct scan for '%s'\n",
  4753. print_ssid(ssid, priv->direct_ssid,
  4754. priv->direct_ssid_len));
  4755. scan->direct_scan[0].id = WLAN_EID_SSID;
  4756. scan->direct_scan[0].len = priv->direct_ssid_len;
  4757. memcpy(scan->direct_scan[0].ssid,
  4758. priv->direct_ssid, priv->direct_ssid_len);
  4759. n_probes++;
  4760. } else
  4761. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  4762. /* We don't build a direct scan probe request; the uCode will do
  4763. * that based on the direct_mask added to each channel entry */
  4764. scan->tx_cmd.len = cpu_to_le16(
  4765. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  4766. IWL_MAX_SCAN_SIZE - sizeof(*scan)));
  4767. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  4768. scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
  4769. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  4770. /* flags + rate selection */
  4771. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  4772. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  4773. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  4774. scan->good_CRC_th = 0;
  4775. band = IEEE80211_BAND_2GHZ;
  4776. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  4777. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  4778. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  4779. band = IEEE80211_BAND_5GHZ;
  4780. } else {
  4781. IWL_WARN(priv, "Invalid scan band count\n");
  4782. goto done;
  4783. }
  4784. /* select Rx antennas */
  4785. scan->flags |= iwl3945_get_antenna_flags(priv);
  4786. if (priv->iw_mode == NL80211_IFTYPE_MONITOR)
  4787. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  4788. scan->channel_count =
  4789. iwl3945_get_channels_for_scan(priv, band, 1, /* active */
  4790. n_probes,
  4791. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  4792. if (scan->channel_count == 0) {
  4793. IWL_DEBUG_SCAN("channel count %d\n", scan->channel_count);
  4794. goto done;
  4795. }
  4796. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  4797. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  4798. cmd.data = scan;
  4799. scan->len = cpu_to_le16(cmd.len);
  4800. set_bit(STATUS_SCAN_HW, &priv->status);
  4801. rc = iwl3945_send_cmd_sync(priv, &cmd);
  4802. if (rc)
  4803. goto done;
  4804. queue_delayed_work(priv->workqueue, &priv->scan_check,
  4805. IWL_SCAN_CHECK_WATCHDOG);
  4806. mutex_unlock(&priv->mutex);
  4807. return;
  4808. done:
  4809. /* can not perform scan make sure we clear scanning
  4810. * bits from status so next scan request can be performed.
  4811. * if we dont clear scanning status bit here all next scan
  4812. * will fail
  4813. */
  4814. clear_bit(STATUS_SCAN_HW, &priv->status);
  4815. clear_bit(STATUS_SCANNING, &priv->status);
  4816. /* inform mac80211 scan aborted */
  4817. queue_work(priv->workqueue, &priv->scan_completed);
  4818. mutex_unlock(&priv->mutex);
  4819. }
  4820. static void iwl3945_bg_up(struct work_struct *data)
  4821. {
  4822. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  4823. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4824. return;
  4825. mutex_lock(&priv->mutex);
  4826. __iwl3945_up(priv);
  4827. mutex_unlock(&priv->mutex);
  4828. iwl3945_rfkill_set_hw_state(priv);
  4829. }
  4830. static void iwl3945_bg_restart(struct work_struct *data)
  4831. {
  4832. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  4833. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4834. return;
  4835. iwl3945_down(priv);
  4836. queue_work(priv->workqueue, &priv->up);
  4837. }
  4838. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  4839. {
  4840. struct iwl_priv *priv =
  4841. container_of(data, struct iwl_priv, rx_replenish);
  4842. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4843. return;
  4844. mutex_lock(&priv->mutex);
  4845. iwl3945_rx_replenish(priv);
  4846. mutex_unlock(&priv->mutex);
  4847. }
  4848. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  4849. static void iwl3945_post_associate(struct iwl_priv *priv)
  4850. {
  4851. int rc = 0;
  4852. struct ieee80211_conf *conf = NULL;
  4853. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  4854. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  4855. return;
  4856. }
  4857. IWL_DEBUG_ASSOC("Associated as %d to: %pM\n",
  4858. priv->assoc_id, priv->active39_rxon.bssid_addr);
  4859. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4860. return;
  4861. if (!priv->vif || !priv->is_open)
  4862. return;
  4863. iwl3945_scan_cancel_timeout(priv, 200);
  4864. conf = ieee80211_get_hw_conf(priv->hw);
  4865. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4866. iwl3945_commit_rxon(priv);
  4867. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  4868. iwl3945_setup_rxon_timing(priv);
  4869. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  4870. sizeof(priv->rxon_timing), &priv->rxon_timing);
  4871. if (rc)
  4872. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  4873. "Attempting to continue.\n");
  4874. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  4875. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  4876. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  4877. priv->assoc_id, priv->beacon_int);
  4878. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  4879. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  4880. else
  4881. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  4882. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  4883. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  4884. priv->staging39_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  4885. else
  4886. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4887. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  4888. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  4889. }
  4890. iwl3945_commit_rxon(priv);
  4891. switch (priv->iw_mode) {
  4892. case NL80211_IFTYPE_STATION:
  4893. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  4894. break;
  4895. case NL80211_IFTYPE_ADHOC:
  4896. priv->assoc_id = 1;
  4897. iwl3945_add_station(priv, priv->bssid, 0, 0);
  4898. iwl3945_sync_sta(priv, IWL_STA_ID,
  4899. (priv->band == IEEE80211_BAND_5GHZ) ?
  4900. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  4901. CMD_ASYNC);
  4902. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  4903. iwl3945_send_beacon_cmd(priv);
  4904. break;
  4905. default:
  4906. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  4907. __func__, priv->iw_mode);
  4908. break;
  4909. }
  4910. iwl3945_activate_qos(priv, 0);
  4911. /* we have just associated, don't start scan too early */
  4912. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  4913. }
  4914. static void iwl3945_bg_abort_scan(struct work_struct *work)
  4915. {
  4916. struct iwl_priv *priv = container_of(work, struct iwl_priv, abort_scan);
  4917. if (!iwl_is_ready(priv))
  4918. return;
  4919. mutex_lock(&priv->mutex);
  4920. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  4921. iwl3945_send_scan_abort(priv);
  4922. mutex_unlock(&priv->mutex);
  4923. }
  4924. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed);
  4925. static void iwl3945_bg_scan_completed(struct work_struct *work)
  4926. {
  4927. struct iwl_priv *priv =
  4928. container_of(work, struct iwl_priv, scan_completed);
  4929. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  4930. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  4931. return;
  4932. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  4933. iwl3945_mac_config(priv->hw, 0);
  4934. ieee80211_scan_completed(priv->hw);
  4935. /* Since setting the TXPOWER may have been deferred while
  4936. * performing the scan, fire one off */
  4937. mutex_lock(&priv->mutex);
  4938. iwl3945_hw_reg_send_txpower(priv);
  4939. mutex_unlock(&priv->mutex);
  4940. }
  4941. /*****************************************************************************
  4942. *
  4943. * mac80211 entry point functions
  4944. *
  4945. *****************************************************************************/
  4946. #define UCODE_READY_TIMEOUT (2 * HZ)
  4947. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  4948. {
  4949. struct iwl_priv *priv = hw->priv;
  4950. int ret;
  4951. IWL_DEBUG_MAC80211("enter\n");
  4952. if (pci_enable_device(priv->pci_dev)) {
  4953. IWL_ERR(priv, "Fail to pci_enable_device\n");
  4954. return -ENODEV;
  4955. }
  4956. pci_restore_state(priv->pci_dev);
  4957. pci_enable_msi(priv->pci_dev);
  4958. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  4959. DRV_NAME, priv);
  4960. if (ret) {
  4961. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  4962. goto out_disable_msi;
  4963. }
  4964. /* we should be verifying the device is ready to be opened */
  4965. mutex_lock(&priv->mutex);
  4966. memset(&priv->staging39_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  4967. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  4968. * ucode filename and max sizes are card-specific. */
  4969. if (!priv->ucode_code.len) {
  4970. ret = iwl3945_read_ucode(priv);
  4971. if (ret) {
  4972. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  4973. mutex_unlock(&priv->mutex);
  4974. goto out_release_irq;
  4975. }
  4976. }
  4977. ret = __iwl3945_up(priv);
  4978. mutex_unlock(&priv->mutex);
  4979. iwl3945_rfkill_set_hw_state(priv);
  4980. if (ret)
  4981. goto out_release_irq;
  4982. IWL_DEBUG_INFO("Start UP work.\n");
  4983. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  4984. return 0;
  4985. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  4986. * mac80211 will not be run successfully. */
  4987. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  4988. test_bit(STATUS_READY, &priv->status),
  4989. UCODE_READY_TIMEOUT);
  4990. if (!ret) {
  4991. if (!test_bit(STATUS_READY, &priv->status)) {
  4992. IWL_ERR(priv,
  4993. "Wait for START_ALIVE timeout after %dms.\n",
  4994. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  4995. ret = -ETIMEDOUT;
  4996. goto out_release_irq;
  4997. }
  4998. }
  4999. priv->is_open = 1;
  5000. IWL_DEBUG_MAC80211("leave\n");
  5001. return 0;
  5002. out_release_irq:
  5003. free_irq(priv->pci_dev->irq, priv);
  5004. out_disable_msi:
  5005. pci_disable_msi(priv->pci_dev);
  5006. pci_disable_device(priv->pci_dev);
  5007. priv->is_open = 0;
  5008. IWL_DEBUG_MAC80211("leave - failed\n");
  5009. return ret;
  5010. }
  5011. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5012. {
  5013. struct iwl_priv *priv = hw->priv;
  5014. IWL_DEBUG_MAC80211("enter\n");
  5015. if (!priv->is_open) {
  5016. IWL_DEBUG_MAC80211("leave - skip\n");
  5017. return;
  5018. }
  5019. priv->is_open = 0;
  5020. if (iwl_is_ready_rf(priv)) {
  5021. /* stop mac, cancel any scan request and clear
  5022. * RXON_FILTER_ASSOC_MSK BIT
  5023. */
  5024. mutex_lock(&priv->mutex);
  5025. iwl3945_scan_cancel_timeout(priv, 100);
  5026. mutex_unlock(&priv->mutex);
  5027. }
  5028. iwl3945_down(priv);
  5029. flush_workqueue(priv->workqueue);
  5030. free_irq(priv->pci_dev->irq, priv);
  5031. pci_disable_msi(priv->pci_dev);
  5032. pci_save_state(priv->pci_dev);
  5033. pci_disable_device(priv->pci_dev);
  5034. IWL_DEBUG_MAC80211("leave\n");
  5035. }
  5036. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5037. {
  5038. struct iwl_priv *priv = hw->priv;
  5039. IWL_DEBUG_MAC80211("enter\n");
  5040. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5041. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5042. if (iwl3945_tx_skb(priv, skb))
  5043. dev_kfree_skb_any(skb);
  5044. IWL_DEBUG_MAC80211("leave\n");
  5045. return NETDEV_TX_OK;
  5046. }
  5047. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5048. struct ieee80211_if_init_conf *conf)
  5049. {
  5050. struct iwl_priv *priv = hw->priv;
  5051. unsigned long flags;
  5052. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5053. if (priv->vif) {
  5054. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5055. return -EOPNOTSUPP;
  5056. }
  5057. spin_lock_irqsave(&priv->lock, flags);
  5058. priv->vif = conf->vif;
  5059. priv->iw_mode = conf->type;
  5060. spin_unlock_irqrestore(&priv->lock, flags);
  5061. mutex_lock(&priv->mutex);
  5062. if (conf->mac_addr) {
  5063. IWL_DEBUG_MAC80211("Set: %pM\n", conf->mac_addr);
  5064. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5065. }
  5066. if (iwl_is_ready(priv))
  5067. iwl3945_set_mode(priv, conf->type);
  5068. mutex_unlock(&priv->mutex);
  5069. IWL_DEBUG_MAC80211("leave\n");
  5070. return 0;
  5071. }
  5072. /**
  5073. * iwl3945_mac_config - mac80211 config callback
  5074. *
  5075. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5076. * be set inappropriately and the driver currently sets the hardware up to
  5077. * use it whenever needed.
  5078. */
  5079. static int iwl3945_mac_config(struct ieee80211_hw *hw, u32 changed)
  5080. {
  5081. struct iwl_priv *priv = hw->priv;
  5082. const struct iwl_channel_info *ch_info;
  5083. struct ieee80211_conf *conf = &hw->conf;
  5084. unsigned long flags;
  5085. int ret = 0;
  5086. mutex_lock(&priv->mutex);
  5087. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5088. if (!iwl_is_ready(priv)) {
  5089. IWL_DEBUG_MAC80211("leave - not ready\n");
  5090. ret = -EIO;
  5091. goto out;
  5092. }
  5093. if (unlikely(!iwl3945_mod_params.disable_hw_scan &&
  5094. test_bit(STATUS_SCANNING, &priv->status))) {
  5095. IWL_DEBUG_MAC80211("leave - scanning\n");
  5096. set_bit(STATUS_CONF_PENDING, &priv->status);
  5097. mutex_unlock(&priv->mutex);
  5098. return 0;
  5099. }
  5100. spin_lock_irqsave(&priv->lock, flags);
  5101. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5102. conf->channel->hw_value);
  5103. if (!is_channel_valid(ch_info)) {
  5104. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5105. conf->channel->hw_value, conf->channel->band);
  5106. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5107. spin_unlock_irqrestore(&priv->lock, flags);
  5108. ret = -EINVAL;
  5109. goto out;
  5110. }
  5111. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5112. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5113. /* The list of supported rates and rate mask can be different
  5114. * for each phymode; since the phymode may have changed, reset
  5115. * the rate mask to what mac80211 lists */
  5116. iwl3945_set_rate(priv);
  5117. spin_unlock_irqrestore(&priv->lock, flags);
  5118. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5119. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5120. iwl3945_hw_channel_switch(priv, conf->channel);
  5121. goto out;
  5122. }
  5123. #endif
  5124. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5125. if (!conf->radio_enabled) {
  5126. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5127. goto out;
  5128. }
  5129. if (iwl_is_rfkill(priv)) {
  5130. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5131. ret = -EIO;
  5132. goto out;
  5133. }
  5134. iwl3945_set_rate(priv);
  5135. if (memcmp(&priv->active39_rxon,
  5136. &priv->staging39_rxon, sizeof(priv->staging39_rxon)))
  5137. iwl3945_commit_rxon(priv);
  5138. else
  5139. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5140. IWL_DEBUG_MAC80211("leave\n");
  5141. out:
  5142. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5143. mutex_unlock(&priv->mutex);
  5144. return ret;
  5145. }
  5146. static void iwl3945_config_ap(struct iwl_priv *priv)
  5147. {
  5148. int rc = 0;
  5149. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5150. return;
  5151. /* The following should be done only at AP bring up */
  5152. if (!(iwl3945_is_associated(priv))) {
  5153. /* RXON - unassoc (to set timing command) */
  5154. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5155. iwl3945_commit_rxon(priv);
  5156. /* RXON Timing */
  5157. memset(&priv->rxon_timing, 0, sizeof(struct iwl_rxon_time_cmd));
  5158. iwl3945_setup_rxon_timing(priv);
  5159. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5160. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5161. if (rc)
  5162. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  5163. "Attempting to continue.\n");
  5164. /* FIXME: what should be the assoc_id for AP? */
  5165. priv->staging39_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5166. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5167. priv->staging39_rxon.flags |=
  5168. RXON_FLG_SHORT_PREAMBLE_MSK;
  5169. else
  5170. priv->staging39_rxon.flags &=
  5171. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5172. if (priv->staging39_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5173. if (priv->assoc_capability &
  5174. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5175. priv->staging39_rxon.flags |=
  5176. RXON_FLG_SHORT_SLOT_MSK;
  5177. else
  5178. priv->staging39_rxon.flags &=
  5179. ~RXON_FLG_SHORT_SLOT_MSK;
  5180. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  5181. priv->staging39_rxon.flags &=
  5182. ~RXON_FLG_SHORT_SLOT_MSK;
  5183. }
  5184. /* restore RXON assoc */
  5185. priv->staging39_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5186. iwl3945_commit_rxon(priv);
  5187. iwl3945_add_station(priv, iwl_bcast_addr, 0, 0);
  5188. }
  5189. iwl3945_send_beacon_cmd(priv);
  5190. /* FIXME - we need to add code here to detect a totally new
  5191. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5192. * clear sta table, add BCAST sta... */
  5193. }
  5194. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5195. struct ieee80211_vif *vif,
  5196. struct ieee80211_if_conf *conf)
  5197. {
  5198. struct iwl_priv *priv = hw->priv;
  5199. int rc;
  5200. if (conf == NULL)
  5201. return -EIO;
  5202. if (priv->vif != vif) {
  5203. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5204. return 0;
  5205. }
  5206. /* handle this temporarily here */
  5207. if (priv->iw_mode == NL80211_IFTYPE_ADHOC &&
  5208. conf->changed & IEEE80211_IFCC_BEACON) {
  5209. struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
  5210. if (!beacon)
  5211. return -ENOMEM;
  5212. mutex_lock(&priv->mutex);
  5213. rc = iwl3945_mac_beacon_update(hw, beacon);
  5214. mutex_unlock(&priv->mutex);
  5215. if (rc)
  5216. return rc;
  5217. }
  5218. if (!iwl_is_alive(priv))
  5219. return -EAGAIN;
  5220. mutex_lock(&priv->mutex);
  5221. if (conf->bssid)
  5222. IWL_DEBUG_MAC80211("bssid: %pM\n", conf->bssid);
  5223. /*
  5224. * very dubious code was here; the probe filtering flag is never set:
  5225. *
  5226. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5227. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5228. */
  5229. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  5230. if (!conf->bssid) {
  5231. conf->bssid = priv->mac_addr;
  5232. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5233. IWL_DEBUG_MAC80211("bssid was set to: %pM\n",
  5234. conf->bssid);
  5235. }
  5236. if (priv->ibss_beacon)
  5237. dev_kfree_skb(priv->ibss_beacon);
  5238. priv->ibss_beacon = ieee80211_beacon_get(hw, vif);
  5239. }
  5240. if (iwl_is_rfkill(priv))
  5241. goto done;
  5242. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5243. !is_multicast_ether_addr(conf->bssid)) {
  5244. /* If there is currently a HW scan going on in the background
  5245. * then we need to cancel it else the RXON below will fail. */
  5246. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5247. IWL_WARN(priv, "Aborted scan still in progress "
  5248. "after 100ms\n");
  5249. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5250. mutex_unlock(&priv->mutex);
  5251. return -EAGAIN;
  5252. }
  5253. memcpy(priv->staging39_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5254. /* TODO: Audit driver for usage of these members and see
  5255. * if mac80211 deprecates them (priv->bssid looks like it
  5256. * shouldn't be there, but I haven't scanned the IBSS code
  5257. * to verify) - jpk */
  5258. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5259. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5260. iwl3945_config_ap(priv);
  5261. else {
  5262. rc = iwl3945_commit_rxon(priv);
  5263. if ((priv->iw_mode == NL80211_IFTYPE_STATION) && rc)
  5264. iwl3945_add_station(priv,
  5265. priv->active39_rxon.bssid_addr, 1, 0);
  5266. }
  5267. } else {
  5268. iwl3945_scan_cancel_timeout(priv, 100);
  5269. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5270. iwl3945_commit_rxon(priv);
  5271. }
  5272. done:
  5273. IWL_DEBUG_MAC80211("leave\n");
  5274. mutex_unlock(&priv->mutex);
  5275. return 0;
  5276. }
  5277. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5278. unsigned int changed_flags,
  5279. unsigned int *total_flags,
  5280. int mc_count, struct dev_addr_list *mc_list)
  5281. {
  5282. struct iwl_priv *priv = hw->priv;
  5283. __le32 *filter_flags = &priv->staging39_rxon.filter_flags;
  5284. IWL_DEBUG_MAC80211("Enter: changed: 0x%x, total: 0x%x\n",
  5285. changed_flags, *total_flags);
  5286. if (changed_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS)) {
  5287. if (*total_flags & (FIF_OTHER_BSS | FIF_PROMISC_IN_BSS))
  5288. *filter_flags |= RXON_FILTER_PROMISC_MSK;
  5289. else
  5290. *filter_flags &= ~RXON_FILTER_PROMISC_MSK;
  5291. }
  5292. if (changed_flags & FIF_ALLMULTI) {
  5293. if (*total_flags & FIF_ALLMULTI)
  5294. *filter_flags |= RXON_FILTER_ACCEPT_GRP_MSK;
  5295. else
  5296. *filter_flags &= ~RXON_FILTER_ACCEPT_GRP_MSK;
  5297. }
  5298. if (changed_flags & FIF_CONTROL) {
  5299. if (*total_flags & FIF_CONTROL)
  5300. *filter_flags |= RXON_FILTER_CTL2HOST_MSK;
  5301. else
  5302. *filter_flags &= ~RXON_FILTER_CTL2HOST_MSK;
  5303. }
  5304. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  5305. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  5306. *filter_flags |= RXON_FILTER_BCON_AWARE_MSK;
  5307. else
  5308. *filter_flags &= ~RXON_FILTER_BCON_AWARE_MSK;
  5309. }
  5310. /* We avoid iwl_commit_rxon here to commit the new filter flags
  5311. * since mac80211 will call ieee80211_hw_config immediately.
  5312. * (mc_list is not supported at this time). Otherwise, we need to
  5313. * queue a background iwl_commit_rxon work.
  5314. */
  5315. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  5316. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  5317. }
  5318. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5319. struct ieee80211_if_init_conf *conf)
  5320. {
  5321. struct iwl_priv *priv = hw->priv;
  5322. IWL_DEBUG_MAC80211("enter\n");
  5323. mutex_lock(&priv->mutex);
  5324. if (iwl_is_ready_rf(priv)) {
  5325. iwl3945_scan_cancel_timeout(priv, 100);
  5326. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5327. iwl3945_commit_rxon(priv);
  5328. }
  5329. if (priv->vif == conf->vif) {
  5330. priv->vif = NULL;
  5331. memset(priv->bssid, 0, ETH_ALEN);
  5332. }
  5333. mutex_unlock(&priv->mutex);
  5334. IWL_DEBUG_MAC80211("leave\n");
  5335. }
  5336. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  5337. static void iwl3945_bss_info_changed(struct ieee80211_hw *hw,
  5338. struct ieee80211_vif *vif,
  5339. struct ieee80211_bss_conf *bss_conf,
  5340. u32 changes)
  5341. {
  5342. struct iwl_priv *priv = hw->priv;
  5343. IWL_DEBUG_MAC80211("changes = 0x%X\n", changes);
  5344. if (changes & BSS_CHANGED_ERP_PREAMBLE) {
  5345. IWL_DEBUG_MAC80211("ERP_PREAMBLE %d\n",
  5346. bss_conf->use_short_preamble);
  5347. if (bss_conf->use_short_preamble)
  5348. priv->staging39_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5349. else
  5350. priv->staging39_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5351. }
  5352. if (changes & BSS_CHANGED_ERP_CTS_PROT) {
  5353. IWL_DEBUG_MAC80211("ERP_CTS %d\n", bss_conf->use_cts_prot);
  5354. if (bss_conf->use_cts_prot && (priv->band != IEEE80211_BAND_5GHZ))
  5355. priv->staging39_rxon.flags |= RXON_FLG_TGG_PROTECT_MSK;
  5356. else
  5357. priv->staging39_rxon.flags &= ~RXON_FLG_TGG_PROTECT_MSK;
  5358. }
  5359. if (changes & BSS_CHANGED_ASSOC) {
  5360. IWL_DEBUG_MAC80211("ASSOC %d\n", bss_conf->assoc);
  5361. /* This should never happen as this function should
  5362. * never be called from interrupt context. */
  5363. if (WARN_ON_ONCE(in_interrupt()))
  5364. return;
  5365. if (bss_conf->assoc) {
  5366. priv->assoc_id = bss_conf->aid;
  5367. priv->beacon_int = bss_conf->beacon_int;
  5368. priv->timestamp = bss_conf->timestamp;
  5369. priv->assoc_capability = bss_conf->assoc_capability;
  5370. priv->next_scan_jiffies = jiffies +
  5371. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  5372. mutex_lock(&priv->mutex);
  5373. iwl3945_post_associate(priv);
  5374. mutex_unlock(&priv->mutex);
  5375. } else {
  5376. priv->assoc_id = 0;
  5377. IWL_DEBUG_MAC80211("DISASSOC %d\n", bss_conf->assoc);
  5378. }
  5379. } else if (changes && iwl3945_is_associated(priv) && priv->assoc_id) {
  5380. IWL_DEBUG_MAC80211("Associated Changes %d\n", changes);
  5381. iwl3945_send_rxon_assoc(priv);
  5382. }
  5383. }
  5384. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5385. {
  5386. int rc = 0;
  5387. unsigned long flags;
  5388. struct iwl_priv *priv = hw->priv;
  5389. DECLARE_SSID_BUF(ssid_buf);
  5390. IWL_DEBUG_MAC80211("enter\n");
  5391. mutex_lock(&priv->mutex);
  5392. spin_lock_irqsave(&priv->lock, flags);
  5393. if (!iwl_is_ready_rf(priv)) {
  5394. rc = -EIO;
  5395. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5396. goto out_unlock;
  5397. }
  5398. /* we don't schedule scan within next_scan_jiffies period */
  5399. if (priv->next_scan_jiffies &&
  5400. time_after(priv->next_scan_jiffies, jiffies)) {
  5401. rc = -EAGAIN;
  5402. goto out_unlock;
  5403. }
  5404. /* if we just finished scan ask for delay for a broadcast scan */
  5405. if ((len == 0) && priv->last_scan_jiffies &&
  5406. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5407. jiffies)) {
  5408. rc = -EAGAIN;
  5409. goto out_unlock;
  5410. }
  5411. if (len) {
  5412. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5413. print_ssid(ssid_buf, ssid, len), (int)len);
  5414. priv->one_direct_scan = 1;
  5415. priv->direct_ssid_len = (u8)
  5416. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5417. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5418. } else
  5419. priv->one_direct_scan = 0;
  5420. rc = iwl3945_scan_initiate(priv);
  5421. IWL_DEBUG_MAC80211("leave\n");
  5422. out_unlock:
  5423. spin_unlock_irqrestore(&priv->lock, flags);
  5424. mutex_unlock(&priv->mutex);
  5425. return rc;
  5426. }
  5427. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5428. struct ieee80211_vif *vif,
  5429. struct ieee80211_sta *sta,
  5430. struct ieee80211_key_conf *key)
  5431. {
  5432. struct iwl_priv *priv = hw->priv;
  5433. const u8 *addr;
  5434. int rc = 0;
  5435. u8 sta_id;
  5436. static const u8 bcast_addr[ETH_ALEN] =
  5437. { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  5438. IWL_DEBUG_MAC80211("enter\n");
  5439. if (iwl3945_mod_params.sw_crypto) {
  5440. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5441. return -EOPNOTSUPP;
  5442. }
  5443. addr = sta ? sta->addr : bcast_addr;
  5444. sta_id = iwl3945_hw_find_station(priv, addr);
  5445. if (sta_id == IWL_INVALID_STATION) {
  5446. IWL_DEBUG_MAC80211("leave - %pM not in station map.\n",
  5447. addr);
  5448. return -EINVAL;
  5449. }
  5450. mutex_lock(&priv->mutex);
  5451. iwl3945_scan_cancel_timeout(priv, 100);
  5452. switch (cmd) {
  5453. case SET_KEY:
  5454. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5455. if (!rc) {
  5456. iwl3945_set_rxon_hwcrypto(priv, 1);
  5457. iwl3945_commit_rxon(priv);
  5458. key->hw_key_idx = sta_id;
  5459. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5460. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5461. }
  5462. break;
  5463. case DISABLE_KEY:
  5464. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5465. if (!rc) {
  5466. iwl3945_set_rxon_hwcrypto(priv, 0);
  5467. iwl3945_commit_rxon(priv);
  5468. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5469. }
  5470. break;
  5471. default:
  5472. rc = -EINVAL;
  5473. }
  5474. IWL_DEBUG_MAC80211("leave\n");
  5475. mutex_unlock(&priv->mutex);
  5476. return rc;
  5477. }
  5478. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5479. const struct ieee80211_tx_queue_params *params)
  5480. {
  5481. struct iwl_priv *priv = hw->priv;
  5482. unsigned long flags;
  5483. int q;
  5484. IWL_DEBUG_MAC80211("enter\n");
  5485. if (!iwl_is_ready_rf(priv)) {
  5486. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5487. return -EIO;
  5488. }
  5489. if (queue >= AC_NUM) {
  5490. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5491. return 0;
  5492. }
  5493. q = AC_NUM - 1 - queue;
  5494. spin_lock_irqsave(&priv->lock, flags);
  5495. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5496. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5497. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5498. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5499. cpu_to_le16((params->txop * 32));
  5500. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5501. priv->qos_data.qos_active = 1;
  5502. spin_unlock_irqrestore(&priv->lock, flags);
  5503. mutex_lock(&priv->mutex);
  5504. if (priv->iw_mode == NL80211_IFTYPE_AP)
  5505. iwl3945_activate_qos(priv, 1);
  5506. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5507. iwl3945_activate_qos(priv, 0);
  5508. mutex_unlock(&priv->mutex);
  5509. IWL_DEBUG_MAC80211("leave\n");
  5510. return 0;
  5511. }
  5512. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5513. struct ieee80211_tx_queue_stats *stats)
  5514. {
  5515. struct iwl_priv *priv = hw->priv;
  5516. int i, avail;
  5517. struct iwl_tx_queue *txq;
  5518. struct iwl_queue *q;
  5519. unsigned long flags;
  5520. IWL_DEBUG_MAC80211("enter\n");
  5521. if (!iwl_is_ready_rf(priv)) {
  5522. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5523. return -EIO;
  5524. }
  5525. spin_lock_irqsave(&priv->lock, flags);
  5526. for (i = 0; i < AC_NUM; i++) {
  5527. txq = &priv->txq[i];
  5528. q = &txq->q;
  5529. avail = iwl_queue_space(q);
  5530. stats[i].len = q->n_window - avail;
  5531. stats[i].limit = q->n_window - q->high_mark;
  5532. stats[i].count = q->n_window;
  5533. }
  5534. spin_unlock_irqrestore(&priv->lock, flags);
  5535. IWL_DEBUG_MAC80211("leave\n");
  5536. return 0;
  5537. }
  5538. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  5539. {
  5540. struct iwl_priv *priv = hw->priv;
  5541. unsigned long flags;
  5542. mutex_lock(&priv->mutex);
  5543. IWL_DEBUG_MAC80211("enter\n");
  5544. iwl_reset_qos(priv);
  5545. spin_lock_irqsave(&priv->lock, flags);
  5546. priv->assoc_id = 0;
  5547. priv->assoc_capability = 0;
  5548. priv->call_post_assoc_from_beacon = 0;
  5549. /* new association get rid of ibss beacon skb */
  5550. if (priv->ibss_beacon)
  5551. dev_kfree_skb(priv->ibss_beacon);
  5552. priv->ibss_beacon = NULL;
  5553. priv->beacon_int = priv->hw->conf.beacon_int;
  5554. priv->timestamp = 0;
  5555. if ((priv->iw_mode == NL80211_IFTYPE_STATION))
  5556. priv->beacon_int = 0;
  5557. spin_unlock_irqrestore(&priv->lock, flags);
  5558. if (!iwl_is_ready_rf(priv)) {
  5559. IWL_DEBUG_MAC80211("leave - not ready\n");
  5560. mutex_unlock(&priv->mutex);
  5561. return;
  5562. }
  5563. /* we are restarting association process
  5564. * clear RXON_FILTER_ASSOC_MSK bit
  5565. */
  5566. if (priv->iw_mode != NL80211_IFTYPE_AP) {
  5567. iwl3945_scan_cancel_timeout(priv, 100);
  5568. priv->staging39_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5569. iwl3945_commit_rxon(priv);
  5570. }
  5571. /* Per mac80211.h: This is only used in IBSS mode... */
  5572. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5573. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  5574. mutex_unlock(&priv->mutex);
  5575. return;
  5576. }
  5577. iwl3945_set_rate(priv);
  5578. mutex_unlock(&priv->mutex);
  5579. IWL_DEBUG_MAC80211("leave\n");
  5580. }
  5581. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  5582. {
  5583. struct iwl_priv *priv = hw->priv;
  5584. unsigned long flags;
  5585. IWL_DEBUG_MAC80211("enter\n");
  5586. if (!iwl_is_ready_rf(priv)) {
  5587. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5588. return -EIO;
  5589. }
  5590. if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
  5591. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  5592. return -EIO;
  5593. }
  5594. spin_lock_irqsave(&priv->lock, flags);
  5595. if (priv->ibss_beacon)
  5596. dev_kfree_skb(priv->ibss_beacon);
  5597. priv->ibss_beacon = skb;
  5598. priv->assoc_id = 0;
  5599. IWL_DEBUG_MAC80211("leave\n");
  5600. spin_unlock_irqrestore(&priv->lock, flags);
  5601. iwl_reset_qos(priv);
  5602. iwl3945_post_associate(priv);
  5603. return 0;
  5604. }
  5605. /*****************************************************************************
  5606. *
  5607. * sysfs attributes
  5608. *
  5609. *****************************************************************************/
  5610. #ifdef CONFIG_IWL3945_DEBUG
  5611. /*
  5612. * The following adds a new attribute to the sysfs representation
  5613. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  5614. * used for controlling the debug level.
  5615. *
  5616. * See the level definitions in iwl for details.
  5617. */
  5618. static ssize_t show_debug_level(struct device *d,
  5619. struct device_attribute *attr, char *buf)
  5620. {
  5621. struct iwl_priv *priv = d->driver_data;
  5622. return sprintf(buf, "0x%08X\n", priv->debug_level);
  5623. }
  5624. static ssize_t store_debug_level(struct device *d,
  5625. struct device_attribute *attr,
  5626. const char *buf, size_t count)
  5627. {
  5628. struct iwl_priv *priv = d->driver_data;
  5629. unsigned long val;
  5630. int ret;
  5631. ret = strict_strtoul(buf, 0, &val);
  5632. if (ret)
  5633. IWL_INFO(priv, "%s is not in hex or decimal form.\n", buf);
  5634. else
  5635. priv->debug_level = val;
  5636. return strnlen(buf, count);
  5637. }
  5638. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  5639. show_debug_level, store_debug_level);
  5640. #endif /* CONFIG_IWL3945_DEBUG */
  5641. static ssize_t show_temperature(struct device *d,
  5642. struct device_attribute *attr, char *buf)
  5643. {
  5644. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5645. if (!iwl_is_alive(priv))
  5646. return -EAGAIN;
  5647. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  5648. }
  5649. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  5650. static ssize_t show_tx_power(struct device *d,
  5651. struct device_attribute *attr, char *buf)
  5652. {
  5653. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5654. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  5655. }
  5656. static ssize_t store_tx_power(struct device *d,
  5657. struct device_attribute *attr,
  5658. const char *buf, size_t count)
  5659. {
  5660. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5661. char *p = (char *)buf;
  5662. u32 val;
  5663. val = simple_strtoul(p, &p, 10);
  5664. if (p == buf)
  5665. IWL_INFO(priv, ": %s is not in decimal form.\n", buf);
  5666. else
  5667. iwl3945_hw_reg_set_txpower(priv, val);
  5668. return count;
  5669. }
  5670. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  5671. static ssize_t show_flags(struct device *d,
  5672. struct device_attribute *attr, char *buf)
  5673. {
  5674. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5675. return sprintf(buf, "0x%04X\n", priv->active39_rxon.flags);
  5676. }
  5677. static ssize_t store_flags(struct device *d,
  5678. struct device_attribute *attr,
  5679. const char *buf, size_t count)
  5680. {
  5681. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5682. u32 flags = simple_strtoul(buf, NULL, 0);
  5683. mutex_lock(&priv->mutex);
  5684. if (le32_to_cpu(priv->staging39_rxon.flags) != flags) {
  5685. /* Cancel any currently running scans... */
  5686. if (iwl3945_scan_cancel_timeout(priv, 100))
  5687. IWL_WARN(priv, "Could not cancel scan.\n");
  5688. else {
  5689. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  5690. flags);
  5691. priv->staging39_rxon.flags = cpu_to_le32(flags);
  5692. iwl3945_commit_rxon(priv);
  5693. }
  5694. }
  5695. mutex_unlock(&priv->mutex);
  5696. return count;
  5697. }
  5698. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  5699. static ssize_t show_filter_flags(struct device *d,
  5700. struct device_attribute *attr, char *buf)
  5701. {
  5702. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5703. return sprintf(buf, "0x%04X\n",
  5704. le32_to_cpu(priv->active39_rxon.filter_flags));
  5705. }
  5706. static ssize_t store_filter_flags(struct device *d,
  5707. struct device_attribute *attr,
  5708. const char *buf, size_t count)
  5709. {
  5710. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5711. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  5712. mutex_lock(&priv->mutex);
  5713. if (le32_to_cpu(priv->staging39_rxon.filter_flags) != filter_flags) {
  5714. /* Cancel any currently running scans... */
  5715. if (iwl3945_scan_cancel_timeout(priv, 100))
  5716. IWL_WARN(priv, "Could not cancel scan.\n");
  5717. else {
  5718. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  5719. "0x%04X\n", filter_flags);
  5720. priv->staging39_rxon.filter_flags =
  5721. cpu_to_le32(filter_flags);
  5722. iwl3945_commit_rxon(priv);
  5723. }
  5724. }
  5725. mutex_unlock(&priv->mutex);
  5726. return count;
  5727. }
  5728. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  5729. store_filter_flags);
  5730. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  5731. static ssize_t show_measurement(struct device *d,
  5732. struct device_attribute *attr, char *buf)
  5733. {
  5734. struct iwl_priv *priv = dev_get_drvdata(d);
  5735. struct iwl_spectrum_notification measure_report;
  5736. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  5737. u8 *data = (u8 *)&measure_report;
  5738. unsigned long flags;
  5739. spin_lock_irqsave(&priv->lock, flags);
  5740. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  5741. spin_unlock_irqrestore(&priv->lock, flags);
  5742. return 0;
  5743. }
  5744. memcpy(&measure_report, &priv->measure_report, size);
  5745. priv->measurement_status = 0;
  5746. spin_unlock_irqrestore(&priv->lock, flags);
  5747. while (size && (PAGE_SIZE - len)) {
  5748. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5749. PAGE_SIZE - len, 1);
  5750. len = strlen(buf);
  5751. if (PAGE_SIZE - len)
  5752. buf[len++] = '\n';
  5753. ofs += 16;
  5754. size -= min(size, 16U);
  5755. }
  5756. return len;
  5757. }
  5758. static ssize_t store_measurement(struct device *d,
  5759. struct device_attribute *attr,
  5760. const char *buf, size_t count)
  5761. {
  5762. struct iwl_priv *priv = dev_get_drvdata(d);
  5763. struct ieee80211_measurement_params params = {
  5764. .channel = le16_to_cpu(priv->active39_rxon.channel),
  5765. .start_time = cpu_to_le64(priv->last_tsf),
  5766. .duration = cpu_to_le16(1),
  5767. };
  5768. u8 type = IWL_MEASURE_BASIC;
  5769. u8 buffer[32];
  5770. u8 channel;
  5771. if (count) {
  5772. char *p = buffer;
  5773. strncpy(buffer, buf, min(sizeof(buffer), count));
  5774. channel = simple_strtoul(p, NULL, 0);
  5775. if (channel)
  5776. params.channel = channel;
  5777. p = buffer;
  5778. while (*p && *p != ' ')
  5779. p++;
  5780. if (*p)
  5781. type = simple_strtoul(p + 1, NULL, 0);
  5782. }
  5783. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  5784. "channel %d (for '%s')\n", type, params.channel, buf);
  5785. iwl3945_get_measurement(priv, &params, type);
  5786. return count;
  5787. }
  5788. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  5789. show_measurement, store_measurement);
  5790. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  5791. static ssize_t store_retry_rate(struct device *d,
  5792. struct device_attribute *attr,
  5793. const char *buf, size_t count)
  5794. {
  5795. struct iwl_priv *priv = dev_get_drvdata(d);
  5796. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  5797. if (priv->retry_rate <= 0)
  5798. priv->retry_rate = 1;
  5799. return count;
  5800. }
  5801. static ssize_t show_retry_rate(struct device *d,
  5802. struct device_attribute *attr, char *buf)
  5803. {
  5804. struct iwl_priv *priv = dev_get_drvdata(d);
  5805. return sprintf(buf, "%d", priv->retry_rate);
  5806. }
  5807. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  5808. store_retry_rate);
  5809. static ssize_t store_power_level(struct device *d,
  5810. struct device_attribute *attr,
  5811. const char *buf, size_t count)
  5812. {
  5813. struct iwl_priv *priv = dev_get_drvdata(d);
  5814. int rc;
  5815. int mode;
  5816. mode = simple_strtoul(buf, NULL, 0);
  5817. mutex_lock(&priv->mutex);
  5818. if (!iwl_is_ready(priv)) {
  5819. rc = -EAGAIN;
  5820. goto out;
  5821. }
  5822. if ((mode < 1) || (mode > IWL39_POWER_LIMIT) ||
  5823. (mode == IWL39_POWER_AC))
  5824. mode = IWL39_POWER_AC;
  5825. else
  5826. mode |= IWL_POWER_ENABLED;
  5827. if (mode != priv->power_mode) {
  5828. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  5829. if (rc) {
  5830. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  5831. goto out;
  5832. }
  5833. priv->power_mode = mode;
  5834. }
  5835. rc = count;
  5836. out:
  5837. mutex_unlock(&priv->mutex);
  5838. return rc;
  5839. }
  5840. #define MAX_WX_STRING 80
  5841. /* Values are in microsecond */
  5842. static const s32 timeout_duration[] = {
  5843. 350000,
  5844. 250000,
  5845. 75000,
  5846. 37000,
  5847. 25000,
  5848. };
  5849. static const s32 period_duration[] = {
  5850. 400000,
  5851. 700000,
  5852. 1000000,
  5853. 1000000,
  5854. 1000000
  5855. };
  5856. static ssize_t show_power_level(struct device *d,
  5857. struct device_attribute *attr, char *buf)
  5858. {
  5859. struct iwl_priv *priv = dev_get_drvdata(d);
  5860. int level = IWL_POWER_LEVEL(priv->power_mode);
  5861. char *p = buf;
  5862. p += sprintf(p, "%d ", level);
  5863. switch (level) {
  5864. case IWL_POWER_MODE_CAM:
  5865. case IWL39_POWER_AC:
  5866. p += sprintf(p, "(AC)");
  5867. break;
  5868. case IWL39_POWER_BATTERY:
  5869. p += sprintf(p, "(BATTERY)");
  5870. break;
  5871. default:
  5872. p += sprintf(p,
  5873. "(Timeout %dms, Period %dms)",
  5874. timeout_duration[level - 1] / 1000,
  5875. period_duration[level - 1] / 1000);
  5876. }
  5877. if (!(priv->power_mode & IWL_POWER_ENABLED))
  5878. p += sprintf(p, " OFF\n");
  5879. else
  5880. p += sprintf(p, " \n");
  5881. return p - buf + 1;
  5882. }
  5883. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  5884. store_power_level);
  5885. static ssize_t show_channels(struct device *d,
  5886. struct device_attribute *attr, char *buf)
  5887. {
  5888. /* all this shit doesn't belong into sysfs anyway */
  5889. return 0;
  5890. }
  5891. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  5892. static ssize_t show_statistics(struct device *d,
  5893. struct device_attribute *attr, char *buf)
  5894. {
  5895. struct iwl_priv *priv = dev_get_drvdata(d);
  5896. u32 size = sizeof(struct iwl3945_notif_statistics);
  5897. u32 len = 0, ofs = 0;
  5898. u8 *data = (u8 *)&priv->statistics_39;
  5899. int rc = 0;
  5900. if (!iwl_is_alive(priv))
  5901. return -EAGAIN;
  5902. mutex_lock(&priv->mutex);
  5903. rc = iwl3945_send_statistics_request(priv);
  5904. mutex_unlock(&priv->mutex);
  5905. if (rc) {
  5906. len = sprintf(buf,
  5907. "Error sending statistics request: 0x%08X\n", rc);
  5908. return len;
  5909. }
  5910. while (size && (PAGE_SIZE - len)) {
  5911. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  5912. PAGE_SIZE - len, 1);
  5913. len = strlen(buf);
  5914. if (PAGE_SIZE - len)
  5915. buf[len++] = '\n';
  5916. ofs += 16;
  5917. size -= min(size, 16U);
  5918. }
  5919. return len;
  5920. }
  5921. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  5922. static ssize_t show_antenna(struct device *d,
  5923. struct device_attribute *attr, char *buf)
  5924. {
  5925. struct iwl_priv *priv = dev_get_drvdata(d);
  5926. if (!iwl_is_alive(priv))
  5927. return -EAGAIN;
  5928. return sprintf(buf, "%d\n", priv->antenna);
  5929. }
  5930. static ssize_t store_antenna(struct device *d,
  5931. struct device_attribute *attr,
  5932. const char *buf, size_t count)
  5933. {
  5934. int ant;
  5935. struct iwl_priv *priv = dev_get_drvdata(d);
  5936. if (count == 0)
  5937. return 0;
  5938. if (sscanf(buf, "%1i", &ant) != 1) {
  5939. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  5940. return count;
  5941. }
  5942. if ((ant >= 0) && (ant <= 2)) {
  5943. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  5944. priv->antenna = (enum iwl3945_antenna)ant;
  5945. } else
  5946. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  5947. return count;
  5948. }
  5949. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  5950. static ssize_t show_status(struct device *d,
  5951. struct device_attribute *attr, char *buf)
  5952. {
  5953. struct iwl_priv *priv = (struct iwl_priv *)d->driver_data;
  5954. if (!iwl_is_alive(priv))
  5955. return -EAGAIN;
  5956. return sprintf(buf, "0x%08x\n", (int)priv->status);
  5957. }
  5958. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  5959. static ssize_t dump_error_log(struct device *d,
  5960. struct device_attribute *attr,
  5961. const char *buf, size_t count)
  5962. {
  5963. char *p = (char *)buf;
  5964. if (p[0] == '1')
  5965. iwl3945_dump_nic_error_log((struct iwl_priv *)d->driver_data);
  5966. return strnlen(buf, count);
  5967. }
  5968. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  5969. static ssize_t dump_event_log(struct device *d,
  5970. struct device_attribute *attr,
  5971. const char *buf, size_t count)
  5972. {
  5973. char *p = (char *)buf;
  5974. if (p[0] == '1')
  5975. iwl3945_dump_nic_event_log((struct iwl_priv *)d->driver_data);
  5976. return strnlen(buf, count);
  5977. }
  5978. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  5979. /*****************************************************************************
  5980. *
  5981. * driver setup and tear down
  5982. *
  5983. *****************************************************************************/
  5984. static void iwl3945_setup_deferred_work(struct iwl_priv *priv)
  5985. {
  5986. priv->workqueue = create_workqueue(DRV_NAME);
  5987. init_waitqueue_head(&priv->wait_command_queue);
  5988. INIT_WORK(&priv->up, iwl3945_bg_up);
  5989. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  5990. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  5991. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  5992. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  5993. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  5994. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  5995. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  5996. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  5997. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  5998. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  5999. iwl3945_hw_setup_deferred_work(priv);
  6000. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6001. iwl3945_irq_tasklet, (unsigned long)priv);
  6002. }
  6003. static void iwl3945_cancel_deferred_work(struct iwl_priv *priv)
  6004. {
  6005. iwl3945_hw_cancel_deferred_work(priv);
  6006. cancel_delayed_work_sync(&priv->init_alive_start);
  6007. cancel_delayed_work(&priv->scan_check);
  6008. cancel_delayed_work(&priv->alive_start);
  6009. cancel_work_sync(&priv->beacon_update);
  6010. }
  6011. static struct attribute *iwl3945_sysfs_entries[] = {
  6012. &dev_attr_antenna.attr,
  6013. &dev_attr_channels.attr,
  6014. &dev_attr_dump_errors.attr,
  6015. &dev_attr_dump_events.attr,
  6016. &dev_attr_flags.attr,
  6017. &dev_attr_filter_flags.attr,
  6018. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6019. &dev_attr_measurement.attr,
  6020. #endif
  6021. &dev_attr_power_level.attr,
  6022. &dev_attr_retry_rate.attr,
  6023. &dev_attr_statistics.attr,
  6024. &dev_attr_status.attr,
  6025. &dev_attr_temperature.attr,
  6026. &dev_attr_tx_power.attr,
  6027. #ifdef CONFIG_IWL3945_DEBUG
  6028. &dev_attr_debug_level.attr,
  6029. #endif
  6030. NULL
  6031. };
  6032. static struct attribute_group iwl3945_attribute_group = {
  6033. .name = NULL, /* put in device directory */
  6034. .attrs = iwl3945_sysfs_entries,
  6035. };
  6036. static struct ieee80211_ops iwl3945_hw_ops = {
  6037. .tx = iwl3945_mac_tx,
  6038. .start = iwl3945_mac_start,
  6039. .stop = iwl3945_mac_stop,
  6040. .add_interface = iwl3945_mac_add_interface,
  6041. .remove_interface = iwl3945_mac_remove_interface,
  6042. .config = iwl3945_mac_config,
  6043. .config_interface = iwl3945_mac_config_interface,
  6044. .configure_filter = iwl3945_configure_filter,
  6045. .set_key = iwl3945_mac_set_key,
  6046. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6047. .conf_tx = iwl3945_mac_conf_tx,
  6048. .reset_tsf = iwl3945_mac_reset_tsf,
  6049. .bss_info_changed = iwl3945_bss_info_changed,
  6050. .hw_scan = iwl3945_mac_hw_scan
  6051. };
  6052. static int iwl3945_init_drv(struct iwl_priv *priv)
  6053. {
  6054. int ret;
  6055. priv->retry_rate = 1;
  6056. priv->ibss_beacon = NULL;
  6057. spin_lock_init(&priv->lock);
  6058. spin_lock_init(&priv->power_data.lock);
  6059. spin_lock_init(&priv->sta_lock);
  6060. spin_lock_init(&priv->hcmd_lock);
  6061. INIT_LIST_HEAD(&priv->free_frames);
  6062. mutex_init(&priv->mutex);
  6063. /* Clear the driver's (not device's) station table */
  6064. iwl3945_clear_stations_table(priv);
  6065. priv->data_retry_limit = -1;
  6066. priv->ieee_channels = NULL;
  6067. priv->ieee_rates = NULL;
  6068. priv->band = IEEE80211_BAND_2GHZ;
  6069. priv->iw_mode = NL80211_IFTYPE_STATION;
  6070. iwl_reset_qos(priv);
  6071. priv->qos_data.qos_active = 0;
  6072. priv->qos_data.qos_cap.val = 0;
  6073. priv->rates_mask = IWL_RATES_MASK;
  6074. /* If power management is turned on, default to AC mode */
  6075. priv->power_mode = IWL_POWER_AC;
  6076. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6077. ret = iwl3945_init_channel_map(priv);
  6078. if (ret) {
  6079. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  6080. goto err;
  6081. }
  6082. ret = iwl3945_init_geos(priv);
  6083. if (ret) {
  6084. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  6085. goto err_free_channel_map;
  6086. }
  6087. return 0;
  6088. err_free_channel_map:
  6089. iwl3945_free_channel_map(priv);
  6090. err:
  6091. return ret;
  6092. }
  6093. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6094. {
  6095. int err = 0;
  6096. struct iwl_priv *priv;
  6097. struct ieee80211_hw *hw;
  6098. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  6099. unsigned long flags;
  6100. /***********************
  6101. * 1. Allocating HW data
  6102. * ********************/
  6103. /* mac80211 allocates memory for this device instance, including
  6104. * space for this driver's private structure */
  6105. hw = iwl_alloc_all(cfg, &iwl3945_hw_ops);
  6106. if (hw == NULL) {
  6107. printk(KERN_ERR DRV_NAME "Can not allocate network device\n");
  6108. err = -ENOMEM;
  6109. goto out;
  6110. }
  6111. priv = hw->priv;
  6112. SET_IEEE80211_DEV(hw, &pdev->dev);
  6113. if ((iwl3945_mod_params.num_of_queues > IWL39_MAX_NUM_QUEUES) ||
  6114. (iwl3945_mod_params.num_of_queues < IWL_MIN_NUM_QUEUES)) {
  6115. IWL_ERR(priv,
  6116. "invalid queues_num, should be between %d and %d\n",
  6117. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6118. err = -EINVAL;
  6119. goto out;
  6120. }
  6121. /*
  6122. * Disabling hardware scan means that mac80211 will perform scans
  6123. * "the hard way", rather than using device's scan.
  6124. */
  6125. if (iwl3945_mod_params.disable_hw_scan) {
  6126. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6127. iwl3945_hw_ops.hw_scan = NULL;
  6128. }
  6129. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6130. priv->cfg = cfg;
  6131. priv->pci_dev = pdev;
  6132. #ifdef CONFIG_IWL3945_DEBUG
  6133. priv->debug_level = iwl3945_mod_params.debug;
  6134. atomic_set(&priv->restrict_refcnt, 0);
  6135. #endif
  6136. hw->rate_control_algorithm = "iwl-3945-rs";
  6137. hw->sta_data_size = sizeof(struct iwl3945_sta_priv);
  6138. /* Select antenna (may be helpful if only one antenna is connected) */
  6139. priv->antenna = (enum iwl3945_antenna)iwl3945_mod_params.antenna;
  6140. /* Tell mac80211 our characteristics */
  6141. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  6142. IEEE80211_HW_NOISE_DBM;
  6143. hw->wiphy->interface_modes =
  6144. BIT(NL80211_IFTYPE_STATION) |
  6145. BIT(NL80211_IFTYPE_ADHOC);
  6146. hw->wiphy->fw_handles_regulatory = true;
  6147. /* 4 EDCA QOS priorities */
  6148. hw->queues = 4;
  6149. /***************************
  6150. * 2. Initializing PCI bus
  6151. * *************************/
  6152. if (pci_enable_device(pdev)) {
  6153. err = -ENODEV;
  6154. goto out_ieee80211_free_hw;
  6155. }
  6156. pci_set_master(pdev);
  6157. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6158. if (!err)
  6159. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6160. if (err) {
  6161. IWL_WARN(priv, "No suitable DMA available.\n");
  6162. goto out_pci_disable_device;
  6163. }
  6164. pci_set_drvdata(pdev, priv);
  6165. err = pci_request_regions(pdev, DRV_NAME);
  6166. if (err)
  6167. goto out_pci_disable_device;
  6168. /***********************
  6169. * 3. Read REV Register
  6170. * ********************/
  6171. priv->hw_base = pci_iomap(pdev, 0, 0);
  6172. if (!priv->hw_base) {
  6173. err = -ENODEV;
  6174. goto out_pci_release_regions;
  6175. }
  6176. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6177. (unsigned long long) pci_resource_len(pdev, 0));
  6178. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6179. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6180. * PCI Tx retries from interfering with C3 CPU state */
  6181. pci_write_config_byte(pdev, 0x41, 0x00);
  6182. /* amp init */
  6183. err = priv->cfg->ops->lib->apm_ops.init(priv);
  6184. if (err < 0) {
  6185. IWL_DEBUG_INFO("Failed to init APMG\n");
  6186. goto out_iounmap;
  6187. }
  6188. /***********************
  6189. * 4. Read EEPROM
  6190. * ********************/
  6191. /* Read the EEPROM */
  6192. err = iwl3945_eeprom_init(priv);
  6193. if (err) {
  6194. IWL_ERR(priv, "Unable to init EEPROM\n");
  6195. goto out_remove_sysfs;
  6196. }
  6197. /* MAC Address location in EEPROM same for 3945/4965 */
  6198. get_eeprom_mac(priv, priv->mac_addr);
  6199. IWL_DEBUG_INFO("MAC address: %pM\n", priv->mac_addr);
  6200. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6201. /***********************
  6202. * 5. Setup HW Constants
  6203. * ********************/
  6204. /* Device-specific setup */
  6205. if (iwl3945_hw_set_hw_params(priv)) {
  6206. IWL_ERR(priv, "failed to set hw settings\n");
  6207. goto out_iounmap;
  6208. }
  6209. /***********************
  6210. * 6. Setup priv
  6211. * ********************/
  6212. err = iwl3945_init_drv(priv);
  6213. if (err) {
  6214. IWL_ERR(priv, "initializing driver failed\n");
  6215. goto out_free_geos;
  6216. }
  6217. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s\n",
  6218. priv->cfg->name);
  6219. /***********************************
  6220. * 7. Initialize Module Parameters
  6221. * **********************************/
  6222. /* Initialize module parameter values here */
  6223. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6224. if (iwl3945_mod_params.disable) {
  6225. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6226. IWL_DEBUG_INFO("Radio disabled.\n");
  6227. }
  6228. /***********************
  6229. * 8. Setup Services
  6230. * ********************/
  6231. spin_lock_irqsave(&priv->lock, flags);
  6232. iwl3945_disable_interrupts(priv);
  6233. spin_unlock_irqrestore(&priv->lock, flags);
  6234. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6235. if (err) {
  6236. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  6237. goto out_release_irq;
  6238. }
  6239. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6240. iwl3945_setup_deferred_work(priv);
  6241. iwl3945_setup_rx_handlers(priv);
  6242. /***********************
  6243. * 9. Conclude
  6244. * ********************/
  6245. pci_save_state(pdev);
  6246. pci_disable_device(pdev);
  6247. /*********************************
  6248. * 10. Setup and Register mac80211
  6249. * *******************************/
  6250. err = ieee80211_register_hw(priv->hw);
  6251. if (err) {
  6252. IWL_ERR(priv, "Failed to register network device: %d\n", err);
  6253. goto out_remove_sysfs;
  6254. }
  6255. priv->hw->conf.beacon_int = 100;
  6256. priv->mac80211_registered = 1;
  6257. err = iwl3945_rfkill_init(priv);
  6258. if (err)
  6259. IWL_ERR(priv, "Unable to initialize RFKILL system. "
  6260. "Ignoring error: %d\n", err);
  6261. return 0;
  6262. out_remove_sysfs:
  6263. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6264. out_free_geos:
  6265. iwl3945_free_geos(priv);
  6266. out_release_irq:
  6267. destroy_workqueue(priv->workqueue);
  6268. priv->workqueue = NULL;
  6269. iwl3945_unset_hw_params(priv);
  6270. out_iounmap:
  6271. pci_iounmap(pdev, priv->hw_base);
  6272. out_pci_release_regions:
  6273. pci_release_regions(pdev);
  6274. out_pci_disable_device:
  6275. pci_disable_device(pdev);
  6276. pci_set_drvdata(pdev, NULL);
  6277. out_ieee80211_free_hw:
  6278. ieee80211_free_hw(priv->hw);
  6279. out:
  6280. return err;
  6281. }
  6282. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6283. {
  6284. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6285. unsigned long flags;
  6286. if (!priv)
  6287. return;
  6288. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6289. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6290. if (priv->mac80211_registered) {
  6291. ieee80211_unregister_hw(priv->hw);
  6292. priv->mac80211_registered = 0;
  6293. } else {
  6294. iwl3945_down(priv);
  6295. }
  6296. /* make sure we flush any pending irq or
  6297. * tasklet for the driver
  6298. */
  6299. spin_lock_irqsave(&priv->lock, flags);
  6300. iwl3945_disable_interrupts(priv);
  6301. spin_unlock_irqrestore(&priv->lock, flags);
  6302. iwl_synchronize_irq(priv);
  6303. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6304. iwl3945_rfkill_unregister(priv);
  6305. iwl3945_dealloc_ucode_pci(priv);
  6306. if (priv->rxq.bd)
  6307. iwl_rx_queue_free(priv, &priv->rxq);
  6308. iwl3945_hw_txq_ctx_free(priv);
  6309. iwl3945_unset_hw_params(priv);
  6310. iwl3945_clear_stations_table(priv);
  6311. /*netif_stop_queue(dev); */
  6312. flush_workqueue(priv->workqueue);
  6313. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6314. * priv->workqueue... so we can't take down the workqueue
  6315. * until now... */
  6316. destroy_workqueue(priv->workqueue);
  6317. priv->workqueue = NULL;
  6318. pci_iounmap(pdev, priv->hw_base);
  6319. pci_release_regions(pdev);
  6320. pci_disable_device(pdev);
  6321. pci_set_drvdata(pdev, NULL);
  6322. iwl3945_free_channel_map(priv);
  6323. iwl3945_free_geos(priv);
  6324. kfree(priv->scan39);
  6325. if (priv->ibss_beacon)
  6326. dev_kfree_skb(priv->ibss_beacon);
  6327. ieee80211_free_hw(priv->hw);
  6328. }
  6329. #ifdef CONFIG_PM
  6330. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6331. {
  6332. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6333. if (priv->is_open) {
  6334. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6335. iwl3945_mac_stop(priv->hw);
  6336. priv->is_open = 1;
  6337. }
  6338. pci_set_power_state(pdev, PCI_D3hot);
  6339. return 0;
  6340. }
  6341. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6342. {
  6343. struct iwl_priv *priv = pci_get_drvdata(pdev);
  6344. pci_set_power_state(pdev, PCI_D0);
  6345. if (priv->is_open)
  6346. iwl3945_mac_start(priv->hw);
  6347. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6348. return 0;
  6349. }
  6350. #endif /* CONFIG_PM */
  6351. /*************** RFKILL FUNCTIONS **********/
  6352. #ifdef CONFIG_IWL3945_RFKILL
  6353. /* software rf-kill from user */
  6354. static int iwl3945_rfkill_soft_rf_kill(void *data, enum rfkill_state state)
  6355. {
  6356. struct iwl_priv *priv = data;
  6357. int err = 0;
  6358. if (!priv->rfkill)
  6359. return 0;
  6360. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  6361. return 0;
  6362. IWL_DEBUG_RF_KILL("we received soft RFKILL set to state %d\n", state);
  6363. mutex_lock(&priv->mutex);
  6364. switch (state) {
  6365. case RFKILL_STATE_UNBLOCKED:
  6366. if (iwl_is_rfkill_hw(priv)) {
  6367. err = -EBUSY;
  6368. goto out_unlock;
  6369. }
  6370. iwl3945_radio_kill_sw(priv, 0);
  6371. break;
  6372. case RFKILL_STATE_SOFT_BLOCKED:
  6373. iwl3945_radio_kill_sw(priv, 1);
  6374. break;
  6375. default:
  6376. IWL_WARN(priv, "received unexpected RFKILL state %d\n", state);
  6377. break;
  6378. }
  6379. out_unlock:
  6380. mutex_unlock(&priv->mutex);
  6381. return err;
  6382. }
  6383. int iwl3945_rfkill_init(struct iwl_priv *priv)
  6384. {
  6385. struct device *device = wiphy_dev(priv->hw->wiphy);
  6386. int ret = 0;
  6387. BUG_ON(device == NULL);
  6388. IWL_DEBUG_RF_KILL("Initializing RFKILL.\n");
  6389. priv->rfkill = rfkill_allocate(device, RFKILL_TYPE_WLAN);
  6390. if (!priv->rfkill) {
  6391. IWL_ERR(priv, "Unable to allocate rfkill device.\n");
  6392. ret = -ENOMEM;
  6393. goto error;
  6394. }
  6395. priv->rfkill->name = priv->cfg->name;
  6396. priv->rfkill->data = priv;
  6397. priv->rfkill->state = RFKILL_STATE_UNBLOCKED;
  6398. priv->rfkill->toggle_radio = iwl3945_rfkill_soft_rf_kill;
  6399. priv->rfkill->user_claim_unsupported = 1;
  6400. priv->rfkill->dev.class->suspend = NULL;
  6401. priv->rfkill->dev.class->resume = NULL;
  6402. ret = rfkill_register(priv->rfkill);
  6403. if (ret) {
  6404. IWL_ERR(priv, "Unable to register rfkill: %d\n", ret);
  6405. goto freed_rfkill;
  6406. }
  6407. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6408. return ret;
  6409. freed_rfkill:
  6410. if (priv->rfkill != NULL)
  6411. rfkill_free(priv->rfkill);
  6412. priv->rfkill = NULL;
  6413. error:
  6414. IWL_DEBUG_RF_KILL("RFKILL initialization complete.\n");
  6415. return ret;
  6416. }
  6417. void iwl3945_rfkill_unregister(struct iwl_priv *priv)
  6418. {
  6419. if (priv->rfkill)
  6420. rfkill_unregister(priv->rfkill);
  6421. priv->rfkill = NULL;
  6422. }
  6423. /* set rf-kill to the right state. */
  6424. void iwl3945_rfkill_set_hw_state(struct iwl_priv *priv)
  6425. {
  6426. if (!priv->rfkill)
  6427. return;
  6428. if (iwl_is_rfkill_hw(priv)) {
  6429. rfkill_force_state(priv->rfkill, RFKILL_STATE_HARD_BLOCKED);
  6430. return;
  6431. }
  6432. if (!iwl_is_rfkill_sw(priv))
  6433. rfkill_force_state(priv->rfkill, RFKILL_STATE_UNBLOCKED);
  6434. else
  6435. rfkill_force_state(priv->rfkill, RFKILL_STATE_SOFT_BLOCKED);
  6436. }
  6437. #endif
  6438. /*****************************************************************************
  6439. *
  6440. * driver and module entry point
  6441. *
  6442. *****************************************************************************/
  6443. static struct pci_driver iwl3945_driver = {
  6444. .name = DRV_NAME,
  6445. .id_table = iwl3945_hw_card_ids,
  6446. .probe = iwl3945_pci_probe,
  6447. .remove = __devexit_p(iwl3945_pci_remove),
  6448. #ifdef CONFIG_PM
  6449. .suspend = iwl3945_pci_suspend,
  6450. .resume = iwl3945_pci_resume,
  6451. #endif
  6452. };
  6453. static int __init iwl3945_init(void)
  6454. {
  6455. int ret;
  6456. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6457. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6458. ret = iwl3945_rate_control_register();
  6459. if (ret) {
  6460. printk(KERN_ERR DRV_NAME
  6461. "Unable to register rate control algorithm: %d\n", ret);
  6462. return ret;
  6463. }
  6464. ret = pci_register_driver(&iwl3945_driver);
  6465. if (ret) {
  6466. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  6467. goto error_register;
  6468. }
  6469. return ret;
  6470. error_register:
  6471. iwl3945_rate_control_unregister();
  6472. return ret;
  6473. }
  6474. static void __exit iwl3945_exit(void)
  6475. {
  6476. pci_unregister_driver(&iwl3945_driver);
  6477. iwl3945_rate_control_unregister();
  6478. }
  6479. MODULE_FIRMWARE(IWL3945_MODULE_FIRMWARE(IWL3945_UCODE_API_MAX));
  6480. module_param_named(antenna, iwl3945_mod_params.antenna, int, 0444);
  6481. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6482. module_param_named(disable, iwl3945_mod_params.disable, int, 0444);
  6483. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6484. module_param_named(hwcrypto, iwl3945_mod_params.sw_crypto, int, 0444);
  6485. MODULE_PARM_DESC(hwcrypto,
  6486. "using hardware crypto engine (default 0 [software])\n");
  6487. module_param_named(debug, iwl3945_mod_params.debug, uint, 0444);
  6488. MODULE_PARM_DESC(debug, "debug output mask");
  6489. module_param_named(disable_hw_scan, iwl3945_mod_params.disable_hw_scan, int, 0444);
  6490. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6491. module_param_named(queues_num, iwl3945_mod_params.num_of_queues, int, 0444);
  6492. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6493. module_exit(iwl3945_exit);
  6494. module_init(iwl3945_init);