omap_hsmmc.c 54 KB

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  1. /*
  2. * drivers/mmc/host/omap_hsmmc.c
  3. *
  4. * Driver for OMAP2430/3430 MMC controller.
  5. *
  6. * Copyright (C) 2007 Texas Instruments.
  7. *
  8. * Authors:
  9. * Syed Mohammed Khasim <x0khasim@ti.com>
  10. * Madhusudhan <madhu.cr@ti.com>
  11. * Mohit Jalori <mjalori@ti.com>
  12. *
  13. * This file is licensed under the terms of the GNU General Public License
  14. * version 2. This program is licensed "as is" without any warranty of any
  15. * kind, whether express or implied.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/kernel.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/dmaengine.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/timer.h>
  28. #include <linux/clk.h>
  29. #include <linux/of.h>
  30. #include <linux/of_gpio.h>
  31. #include <linux/of_device.h>
  32. #include <linux/omap-dma.h>
  33. #include <linux/mmc/host.h>
  34. #include <linux/mmc/core.h>
  35. #include <linux/mmc/mmc.h>
  36. #include <linux/io.h>
  37. #include <linux/gpio.h>
  38. #include <linux/regulator/consumer.h>
  39. #include <linux/pinctrl/consumer.h>
  40. #include <linux/pm_runtime.h>
  41. #include <linux/platform_data/mmc-omap.h>
  42. /* OMAP HSMMC Host Controller Registers */
  43. #define OMAP_HSMMC_SYSSTATUS 0x0014
  44. #define OMAP_HSMMC_CON 0x002C
  45. #define OMAP_HSMMC_BLK 0x0104
  46. #define OMAP_HSMMC_ARG 0x0108
  47. #define OMAP_HSMMC_CMD 0x010C
  48. #define OMAP_HSMMC_RSP10 0x0110
  49. #define OMAP_HSMMC_RSP32 0x0114
  50. #define OMAP_HSMMC_RSP54 0x0118
  51. #define OMAP_HSMMC_RSP76 0x011C
  52. #define OMAP_HSMMC_DATA 0x0120
  53. #define OMAP_HSMMC_HCTL 0x0128
  54. #define OMAP_HSMMC_SYSCTL 0x012C
  55. #define OMAP_HSMMC_STAT 0x0130
  56. #define OMAP_HSMMC_IE 0x0134
  57. #define OMAP_HSMMC_ISE 0x0138
  58. #define OMAP_HSMMC_CAPA 0x0140
  59. #define VS18 (1 << 26)
  60. #define VS30 (1 << 25)
  61. #define HSS (1 << 21)
  62. #define SDVS18 (0x5 << 9)
  63. #define SDVS30 (0x6 << 9)
  64. #define SDVS33 (0x7 << 9)
  65. #define SDVS_MASK 0x00000E00
  66. #define SDVSCLR 0xFFFFF1FF
  67. #define SDVSDET 0x00000400
  68. #define AUTOIDLE 0x1
  69. #define SDBP (1 << 8)
  70. #define DTO 0xe
  71. #define ICE 0x1
  72. #define ICS 0x2
  73. #define CEN (1 << 2)
  74. #define CLKD_MASK 0x0000FFC0
  75. #define CLKD_SHIFT 6
  76. #define DTO_MASK 0x000F0000
  77. #define DTO_SHIFT 16
  78. #define INIT_STREAM (1 << 1)
  79. #define DP_SELECT (1 << 21)
  80. #define DDIR (1 << 4)
  81. #define DMAE 0x1
  82. #define MSBS (1 << 5)
  83. #define BCE (1 << 1)
  84. #define FOUR_BIT (1 << 1)
  85. #define HSPE (1 << 2)
  86. #define DDR (1 << 19)
  87. #define DW8 (1 << 5)
  88. #define OD 0x1
  89. #define STAT_CLEAR 0xFFFFFFFF
  90. #define INIT_STREAM_CMD 0x00000000
  91. #define DUAL_VOLT_OCR_BIT 7
  92. #define SRC (1 << 25)
  93. #define SRD (1 << 26)
  94. #define SOFTRESET (1 << 1)
  95. #define RESETDONE (1 << 0)
  96. /* Interrupt masks for IE and ISE register */
  97. #define CC_EN (1 << 0)
  98. #define TC_EN (1 << 1)
  99. #define BWR_EN (1 << 4)
  100. #define BRR_EN (1 << 5)
  101. #define ERR_EN (1 << 15)
  102. #define CTO_EN (1 << 16)
  103. #define CCRC_EN (1 << 17)
  104. #define CEB_EN (1 << 18)
  105. #define CIE_EN (1 << 19)
  106. #define DTO_EN (1 << 20)
  107. #define DCRC_EN (1 << 21)
  108. #define DEB_EN (1 << 22)
  109. #define CERR_EN (1 << 28)
  110. #define BADA_EN (1 << 29)
  111. #define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\
  112. DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
  113. BRR_EN | BWR_EN | TC_EN | CC_EN)
  114. #define MMC_AUTOSUSPEND_DELAY 100
  115. #define MMC_TIMEOUT_MS 20
  116. #define OMAP_MMC_MIN_CLOCK 400000
  117. #define OMAP_MMC_MAX_CLOCK 52000000
  118. #define DRIVER_NAME "omap_hsmmc"
  119. /*
  120. * One controller can have multiple slots, like on some omap boards using
  121. * omap.c controller driver. Luckily this is not currently done on any known
  122. * omap_hsmmc.c device.
  123. */
  124. #define mmc_slot(host) (host->pdata->slots[host->slot_id])
  125. /*
  126. * MMC Host controller read/write API's
  127. */
  128. #define OMAP_HSMMC_READ(base, reg) \
  129. __raw_readl((base) + OMAP_HSMMC_##reg)
  130. #define OMAP_HSMMC_WRITE(base, reg, val) \
  131. __raw_writel((val), (base) + OMAP_HSMMC_##reg)
  132. struct omap_hsmmc_next {
  133. unsigned int dma_len;
  134. s32 cookie;
  135. };
  136. struct omap_hsmmc_host {
  137. struct device *dev;
  138. struct mmc_host *mmc;
  139. struct mmc_request *mrq;
  140. struct mmc_command *cmd;
  141. struct mmc_data *data;
  142. struct clk *fclk;
  143. struct clk *dbclk;
  144. /*
  145. * vcc == configured supply
  146. * vcc_aux == optional
  147. * - MMC1, supply for DAT4..DAT7
  148. * - MMC2/MMC2, external level shifter voltage supply, for
  149. * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
  150. */
  151. struct regulator *vcc;
  152. struct regulator *vcc_aux;
  153. void __iomem *base;
  154. resource_size_t mapbase;
  155. spinlock_t irq_lock; /* Prevent races with irq handler */
  156. unsigned int dma_len;
  157. unsigned int dma_sg_idx;
  158. unsigned char bus_mode;
  159. unsigned char power_mode;
  160. int suspended;
  161. int irq;
  162. int use_dma, dma_ch;
  163. struct dma_chan *tx_chan;
  164. struct dma_chan *rx_chan;
  165. int slot_id;
  166. int response_busy;
  167. int context_loss;
  168. int protect_card;
  169. int reqs_blocked;
  170. int use_reg;
  171. int req_in_progress;
  172. struct omap_hsmmc_next next_data;
  173. struct omap_mmc_platform_data *pdata;
  174. };
  175. static int omap_hsmmc_card_detect(struct device *dev, int slot)
  176. {
  177. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  178. struct omap_mmc_platform_data *mmc = host->pdata;
  179. /* NOTE: assumes card detect signal is active-low */
  180. return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
  181. }
  182. static int omap_hsmmc_get_wp(struct device *dev, int slot)
  183. {
  184. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  185. struct omap_mmc_platform_data *mmc = host->pdata;
  186. /* NOTE: assumes write protect signal is active-high */
  187. return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
  188. }
  189. static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
  190. {
  191. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  192. struct omap_mmc_platform_data *mmc = host->pdata;
  193. /* NOTE: assumes card detect signal is active-low */
  194. return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
  195. }
  196. #ifdef CONFIG_PM
  197. static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
  198. {
  199. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  200. struct omap_mmc_platform_data *mmc = host->pdata;
  201. disable_irq(mmc->slots[0].card_detect_irq);
  202. return 0;
  203. }
  204. static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
  205. {
  206. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  207. struct omap_mmc_platform_data *mmc = host->pdata;
  208. enable_irq(mmc->slots[0].card_detect_irq);
  209. return 0;
  210. }
  211. #else
  212. #define omap_hsmmc_suspend_cdirq NULL
  213. #define omap_hsmmc_resume_cdirq NULL
  214. #endif
  215. #ifdef CONFIG_REGULATOR
  216. static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
  217. int vdd)
  218. {
  219. struct omap_hsmmc_host *host =
  220. platform_get_drvdata(to_platform_device(dev));
  221. int ret = 0;
  222. /*
  223. * If we don't see a Vcc regulator, assume it's a fixed
  224. * voltage always-on regulator.
  225. */
  226. if (!host->vcc)
  227. return 0;
  228. /*
  229. * With DT, never turn OFF the regulator. This is because
  230. * the pbias cell programming support is still missing when
  231. * booting with Device tree
  232. */
  233. if (dev->of_node && !vdd)
  234. return 0;
  235. if (mmc_slot(host).before_set_reg)
  236. mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
  237. /*
  238. * Assume Vcc regulator is used only to power the card ... OMAP
  239. * VDDS is used to power the pins, optionally with a transceiver to
  240. * support cards using voltages other than VDDS (1.8V nominal). When a
  241. * transceiver is used, DAT3..7 are muxed as transceiver control pins.
  242. *
  243. * In some cases this regulator won't support enable/disable;
  244. * e.g. it's a fixed rail for a WLAN chip.
  245. *
  246. * In other cases vcc_aux switches interface power. Example, for
  247. * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
  248. * chips/cards need an interface voltage rail too.
  249. */
  250. if (power_on) {
  251. ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
  252. /* Enable interface voltage rail, if needed */
  253. if (ret == 0 && host->vcc_aux) {
  254. ret = regulator_enable(host->vcc_aux);
  255. if (ret < 0)
  256. ret = mmc_regulator_set_ocr(host->mmc,
  257. host->vcc, 0);
  258. }
  259. } else {
  260. /* Shut down the rail */
  261. if (host->vcc_aux)
  262. ret = regulator_disable(host->vcc_aux);
  263. if (!ret) {
  264. /* Then proceed to shut down the local regulator */
  265. ret = mmc_regulator_set_ocr(host->mmc,
  266. host->vcc, 0);
  267. }
  268. }
  269. if (mmc_slot(host).after_set_reg)
  270. mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
  271. return ret;
  272. }
  273. static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
  274. {
  275. struct regulator *reg;
  276. int ocr_value = 0;
  277. reg = regulator_get(host->dev, "vmmc");
  278. if (IS_ERR(reg)) {
  279. dev_err(host->dev, "vmmc regulator missing\n");
  280. return PTR_ERR(reg);
  281. } else {
  282. mmc_slot(host).set_power = omap_hsmmc_set_power;
  283. host->vcc = reg;
  284. ocr_value = mmc_regulator_get_ocrmask(reg);
  285. if (!mmc_slot(host).ocr_mask) {
  286. mmc_slot(host).ocr_mask = ocr_value;
  287. } else {
  288. if (!(mmc_slot(host).ocr_mask & ocr_value)) {
  289. dev_err(host->dev, "ocrmask %x is not supported\n",
  290. mmc_slot(host).ocr_mask);
  291. mmc_slot(host).ocr_mask = 0;
  292. return -EINVAL;
  293. }
  294. }
  295. /* Allow an aux regulator */
  296. reg = regulator_get(host->dev, "vmmc_aux");
  297. host->vcc_aux = IS_ERR(reg) ? NULL : reg;
  298. /* For eMMC do not power off when not in sleep state */
  299. if (mmc_slot(host).no_regulator_off_init)
  300. return 0;
  301. /*
  302. * UGLY HACK: workaround regulator framework bugs.
  303. * When the bootloader leaves a supply active, it's
  304. * initialized with zero usecount ... and we can't
  305. * disable it without first enabling it. Until the
  306. * framework is fixed, we need a workaround like this
  307. * (which is safe for MMC, but not in general).
  308. */
  309. if (regulator_is_enabled(host->vcc) > 0 ||
  310. (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
  311. int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
  312. mmc_slot(host).set_power(host->dev, host->slot_id,
  313. 1, vdd);
  314. mmc_slot(host).set_power(host->dev, host->slot_id,
  315. 0, 0);
  316. }
  317. }
  318. return 0;
  319. }
  320. static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
  321. {
  322. regulator_put(host->vcc);
  323. regulator_put(host->vcc_aux);
  324. mmc_slot(host).set_power = NULL;
  325. }
  326. static inline int omap_hsmmc_have_reg(void)
  327. {
  328. return 1;
  329. }
  330. #else
  331. static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
  332. {
  333. return -EINVAL;
  334. }
  335. static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
  336. {
  337. }
  338. static inline int omap_hsmmc_have_reg(void)
  339. {
  340. return 0;
  341. }
  342. #endif
  343. static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
  344. {
  345. int ret;
  346. if (gpio_is_valid(pdata->slots[0].switch_pin)) {
  347. if (pdata->slots[0].cover)
  348. pdata->slots[0].get_cover_state =
  349. omap_hsmmc_get_cover_state;
  350. else
  351. pdata->slots[0].card_detect = omap_hsmmc_card_detect;
  352. pdata->slots[0].card_detect_irq =
  353. gpio_to_irq(pdata->slots[0].switch_pin);
  354. ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
  355. if (ret)
  356. return ret;
  357. ret = gpio_direction_input(pdata->slots[0].switch_pin);
  358. if (ret)
  359. goto err_free_sp;
  360. } else
  361. pdata->slots[0].switch_pin = -EINVAL;
  362. if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
  363. pdata->slots[0].get_ro = omap_hsmmc_get_wp;
  364. ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
  365. if (ret)
  366. goto err_free_cd;
  367. ret = gpio_direction_input(pdata->slots[0].gpio_wp);
  368. if (ret)
  369. goto err_free_wp;
  370. } else
  371. pdata->slots[0].gpio_wp = -EINVAL;
  372. return 0;
  373. err_free_wp:
  374. gpio_free(pdata->slots[0].gpio_wp);
  375. err_free_cd:
  376. if (gpio_is_valid(pdata->slots[0].switch_pin))
  377. err_free_sp:
  378. gpio_free(pdata->slots[0].switch_pin);
  379. return ret;
  380. }
  381. static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
  382. {
  383. if (gpio_is_valid(pdata->slots[0].gpio_wp))
  384. gpio_free(pdata->slots[0].gpio_wp);
  385. if (gpio_is_valid(pdata->slots[0].switch_pin))
  386. gpio_free(pdata->slots[0].switch_pin);
  387. }
  388. /*
  389. * Start clock to the card
  390. */
  391. static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
  392. {
  393. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  394. OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
  395. }
  396. /*
  397. * Stop clock to the card
  398. */
  399. static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
  400. {
  401. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  402. OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
  403. if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
  404. dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
  405. }
  406. static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
  407. struct mmc_command *cmd)
  408. {
  409. unsigned int irq_mask;
  410. if (host->use_dma)
  411. irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN);
  412. else
  413. irq_mask = INT_EN_MASK;
  414. /* Disable timeout for erases */
  415. if (cmd->opcode == MMC_ERASE)
  416. irq_mask &= ~DTO_EN;
  417. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  418. OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
  419. OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
  420. }
  421. static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
  422. {
  423. OMAP_HSMMC_WRITE(host->base, ISE, 0);
  424. OMAP_HSMMC_WRITE(host->base, IE, 0);
  425. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  426. }
  427. /* Calculate divisor for the given clock frequency */
  428. static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
  429. {
  430. u16 dsor = 0;
  431. if (ios->clock) {
  432. dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
  433. if (dsor > 250)
  434. dsor = 250;
  435. }
  436. return dsor;
  437. }
  438. static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
  439. {
  440. struct mmc_ios *ios = &host->mmc->ios;
  441. unsigned long regval;
  442. unsigned long timeout;
  443. unsigned long clkdiv;
  444. dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
  445. omap_hsmmc_stop_clock(host);
  446. regval = OMAP_HSMMC_READ(host->base, SYSCTL);
  447. regval = regval & ~(CLKD_MASK | DTO_MASK);
  448. clkdiv = calc_divisor(host, ios);
  449. regval = regval | (clkdiv << 6) | (DTO << 16);
  450. OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
  451. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  452. OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
  453. /* Wait till the ICS bit is set */
  454. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  455. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
  456. && time_before(jiffies, timeout))
  457. cpu_relax();
  458. /*
  459. * Enable High-Speed Support
  460. * Pre-Requisites
  461. * - Controller should support High-Speed-Enable Bit
  462. * - Controller should not be using DDR Mode
  463. * - Controller should advertise that it supports High Speed
  464. * in capabilities register
  465. * - MMC/SD clock coming out of controller > 25MHz
  466. */
  467. if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) &&
  468. (ios->timing != MMC_TIMING_UHS_DDR50) &&
  469. ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
  470. regval = OMAP_HSMMC_READ(host->base, HCTL);
  471. if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
  472. regval |= HSPE;
  473. else
  474. regval &= ~HSPE;
  475. OMAP_HSMMC_WRITE(host->base, HCTL, regval);
  476. }
  477. omap_hsmmc_start_clock(host);
  478. }
  479. static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
  480. {
  481. struct mmc_ios *ios = &host->mmc->ios;
  482. u32 con;
  483. con = OMAP_HSMMC_READ(host->base, CON);
  484. if (ios->timing == MMC_TIMING_UHS_DDR50)
  485. con |= DDR; /* configure in DDR mode */
  486. else
  487. con &= ~DDR;
  488. switch (ios->bus_width) {
  489. case MMC_BUS_WIDTH_8:
  490. OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
  491. break;
  492. case MMC_BUS_WIDTH_4:
  493. OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
  494. OMAP_HSMMC_WRITE(host->base, HCTL,
  495. OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
  496. break;
  497. case MMC_BUS_WIDTH_1:
  498. OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
  499. OMAP_HSMMC_WRITE(host->base, HCTL,
  500. OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
  501. break;
  502. }
  503. }
  504. static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
  505. {
  506. struct mmc_ios *ios = &host->mmc->ios;
  507. u32 con;
  508. con = OMAP_HSMMC_READ(host->base, CON);
  509. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  510. OMAP_HSMMC_WRITE(host->base, CON, con | OD);
  511. else
  512. OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
  513. }
  514. #ifdef CONFIG_PM
  515. /*
  516. * Restore the MMC host context, if it was lost as result of a
  517. * power state change.
  518. */
  519. static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
  520. {
  521. struct mmc_ios *ios = &host->mmc->ios;
  522. struct omap_mmc_platform_data *pdata = host->pdata;
  523. int context_loss = 0;
  524. u32 hctl, capa;
  525. unsigned long timeout;
  526. if (pdata->get_context_loss_count) {
  527. context_loss = pdata->get_context_loss_count(host->dev);
  528. if (context_loss < 0)
  529. return 1;
  530. }
  531. dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
  532. context_loss == host->context_loss ? "not " : "");
  533. if (host->context_loss == context_loss)
  534. return 1;
  535. if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
  536. return 1;
  537. if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  538. if (host->power_mode != MMC_POWER_OFF &&
  539. (1 << ios->vdd) <= MMC_VDD_23_24)
  540. hctl = SDVS18;
  541. else
  542. hctl = SDVS30;
  543. capa = VS30 | VS18;
  544. } else {
  545. hctl = SDVS18;
  546. capa = VS18;
  547. }
  548. OMAP_HSMMC_WRITE(host->base, HCTL,
  549. OMAP_HSMMC_READ(host->base, HCTL) | hctl);
  550. OMAP_HSMMC_WRITE(host->base, CAPA,
  551. OMAP_HSMMC_READ(host->base, CAPA) | capa);
  552. OMAP_HSMMC_WRITE(host->base, HCTL,
  553. OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
  554. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  555. while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
  556. && time_before(jiffies, timeout))
  557. ;
  558. omap_hsmmc_disable_irq(host);
  559. /* Do not initialize card-specific things if the power is off */
  560. if (host->power_mode == MMC_POWER_OFF)
  561. goto out;
  562. omap_hsmmc_set_bus_width(host);
  563. omap_hsmmc_set_clock(host);
  564. omap_hsmmc_set_bus_mode(host);
  565. out:
  566. host->context_loss = context_loss;
  567. dev_dbg(mmc_dev(host->mmc), "context is restored\n");
  568. return 0;
  569. }
  570. /*
  571. * Save the MMC host context (store the number of power state changes so far).
  572. */
  573. static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
  574. {
  575. struct omap_mmc_platform_data *pdata = host->pdata;
  576. int context_loss;
  577. if (pdata->get_context_loss_count) {
  578. context_loss = pdata->get_context_loss_count(host->dev);
  579. if (context_loss < 0)
  580. return;
  581. host->context_loss = context_loss;
  582. }
  583. }
  584. #else
  585. static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
  586. {
  587. return 0;
  588. }
  589. static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
  590. {
  591. }
  592. #endif
  593. /*
  594. * Send init stream sequence to card
  595. * before sending IDLE command
  596. */
  597. static void send_init_stream(struct omap_hsmmc_host *host)
  598. {
  599. int reg = 0;
  600. unsigned long timeout;
  601. if (host->protect_card)
  602. return;
  603. disable_irq(host->irq);
  604. OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
  605. OMAP_HSMMC_WRITE(host->base, CON,
  606. OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
  607. OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
  608. timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
  609. while ((reg != CC_EN) && time_before(jiffies, timeout))
  610. reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
  611. OMAP_HSMMC_WRITE(host->base, CON,
  612. OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
  613. OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
  614. OMAP_HSMMC_READ(host->base, STAT);
  615. enable_irq(host->irq);
  616. }
  617. static inline
  618. int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
  619. {
  620. int r = 1;
  621. if (mmc_slot(host).get_cover_state)
  622. r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
  623. return r;
  624. }
  625. static ssize_t
  626. omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
  627. char *buf)
  628. {
  629. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  630. struct omap_hsmmc_host *host = mmc_priv(mmc);
  631. return sprintf(buf, "%s\n",
  632. omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
  633. }
  634. static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
  635. static ssize_t
  636. omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
  637. char *buf)
  638. {
  639. struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
  640. struct omap_hsmmc_host *host = mmc_priv(mmc);
  641. return sprintf(buf, "%s\n", mmc_slot(host).name);
  642. }
  643. static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
  644. /*
  645. * Configure the response type and send the cmd.
  646. */
  647. static void
  648. omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
  649. struct mmc_data *data)
  650. {
  651. int cmdreg = 0, resptype = 0, cmdtype = 0;
  652. dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
  653. mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
  654. host->cmd = cmd;
  655. omap_hsmmc_enable_irq(host, cmd);
  656. host->response_busy = 0;
  657. if (cmd->flags & MMC_RSP_PRESENT) {
  658. if (cmd->flags & MMC_RSP_136)
  659. resptype = 1;
  660. else if (cmd->flags & MMC_RSP_BUSY) {
  661. resptype = 3;
  662. host->response_busy = 1;
  663. } else
  664. resptype = 2;
  665. }
  666. /*
  667. * Unlike OMAP1 controller, the cmdtype does not seem to be based on
  668. * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
  669. * a val of 0x3, rest 0x0.
  670. */
  671. if (cmd == host->mrq->stop)
  672. cmdtype = 0x3;
  673. cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
  674. if (data) {
  675. cmdreg |= DP_SELECT | MSBS | BCE;
  676. if (data->flags & MMC_DATA_READ)
  677. cmdreg |= DDIR;
  678. else
  679. cmdreg &= ~(DDIR);
  680. }
  681. if (host->use_dma)
  682. cmdreg |= DMAE;
  683. host->req_in_progress = 1;
  684. OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
  685. OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
  686. }
  687. static int
  688. omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
  689. {
  690. if (data->flags & MMC_DATA_WRITE)
  691. return DMA_TO_DEVICE;
  692. else
  693. return DMA_FROM_DEVICE;
  694. }
  695. static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
  696. struct mmc_data *data)
  697. {
  698. return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
  699. }
  700. static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
  701. {
  702. int dma_ch;
  703. unsigned long flags;
  704. spin_lock_irqsave(&host->irq_lock, flags);
  705. host->req_in_progress = 0;
  706. dma_ch = host->dma_ch;
  707. spin_unlock_irqrestore(&host->irq_lock, flags);
  708. omap_hsmmc_disable_irq(host);
  709. /* Do not complete the request if DMA is still in progress */
  710. if (mrq->data && host->use_dma && dma_ch != -1)
  711. return;
  712. host->mrq = NULL;
  713. mmc_request_done(host->mmc, mrq);
  714. }
  715. /*
  716. * Notify the transfer complete to MMC core
  717. */
  718. static void
  719. omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
  720. {
  721. if (!data) {
  722. struct mmc_request *mrq = host->mrq;
  723. /* TC before CC from CMD6 - don't know why, but it happens */
  724. if (host->cmd && host->cmd->opcode == 6 &&
  725. host->response_busy) {
  726. host->response_busy = 0;
  727. return;
  728. }
  729. omap_hsmmc_request_done(host, mrq);
  730. return;
  731. }
  732. host->data = NULL;
  733. if (!data->error)
  734. data->bytes_xfered += data->blocks * (data->blksz);
  735. else
  736. data->bytes_xfered = 0;
  737. if (!data->stop) {
  738. omap_hsmmc_request_done(host, data->mrq);
  739. return;
  740. }
  741. omap_hsmmc_start_command(host, data->stop, NULL);
  742. }
  743. /*
  744. * Notify the core about command completion
  745. */
  746. static void
  747. omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
  748. {
  749. host->cmd = NULL;
  750. if (cmd->flags & MMC_RSP_PRESENT) {
  751. if (cmd->flags & MMC_RSP_136) {
  752. /* response type 2 */
  753. cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
  754. cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
  755. cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
  756. cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
  757. } else {
  758. /* response types 1, 1b, 3, 4, 5, 6 */
  759. cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
  760. }
  761. }
  762. if ((host->data == NULL && !host->response_busy) || cmd->error)
  763. omap_hsmmc_request_done(host, cmd->mrq);
  764. }
  765. /*
  766. * DMA clean up for command errors
  767. */
  768. static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
  769. {
  770. int dma_ch;
  771. unsigned long flags;
  772. host->data->error = errno;
  773. spin_lock_irqsave(&host->irq_lock, flags);
  774. dma_ch = host->dma_ch;
  775. host->dma_ch = -1;
  776. spin_unlock_irqrestore(&host->irq_lock, flags);
  777. if (host->use_dma && dma_ch != -1) {
  778. struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
  779. dmaengine_terminate_all(chan);
  780. dma_unmap_sg(chan->device->dev,
  781. host->data->sg, host->data->sg_len,
  782. omap_hsmmc_get_dma_dir(host, host->data));
  783. host->data->host_cookie = 0;
  784. }
  785. host->data = NULL;
  786. }
  787. /*
  788. * Readable error output
  789. */
  790. #ifdef CONFIG_MMC_DEBUG
  791. static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
  792. {
  793. /* --- means reserved bit without definition at documentation */
  794. static const char *omap_hsmmc_status_bits[] = {
  795. "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
  796. "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
  797. "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
  798. "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
  799. };
  800. char res[256];
  801. char *buf = res;
  802. int len, i;
  803. len = sprintf(buf, "MMC IRQ 0x%x :", status);
  804. buf += len;
  805. for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
  806. if (status & (1 << i)) {
  807. len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
  808. buf += len;
  809. }
  810. dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
  811. }
  812. #else
  813. static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
  814. u32 status)
  815. {
  816. }
  817. #endif /* CONFIG_MMC_DEBUG */
  818. /*
  819. * MMC controller internal state machines reset
  820. *
  821. * Used to reset command or data internal state machines, using respectively
  822. * SRC or SRD bit of SYSCTL register
  823. * Can be called from interrupt context
  824. */
  825. static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
  826. unsigned long bit)
  827. {
  828. unsigned long i = 0;
  829. unsigned long limit = (loops_per_jiffy *
  830. msecs_to_jiffies(MMC_TIMEOUT_MS));
  831. OMAP_HSMMC_WRITE(host->base, SYSCTL,
  832. OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
  833. /*
  834. * OMAP4 ES2 and greater has an updated reset logic.
  835. * Monitor a 0->1 transition first
  836. */
  837. if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
  838. while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
  839. && (i++ < limit))
  840. cpu_relax();
  841. }
  842. i = 0;
  843. while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
  844. (i++ < limit))
  845. cpu_relax();
  846. if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
  847. dev_err(mmc_dev(host->mmc),
  848. "Timeout waiting on controller reset in %s\n",
  849. __func__);
  850. }
  851. static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
  852. int err, int end_cmd)
  853. {
  854. if (end_cmd) {
  855. omap_hsmmc_reset_controller_fsm(host, SRC);
  856. if (host->cmd)
  857. host->cmd->error = err;
  858. }
  859. if (host->data) {
  860. omap_hsmmc_reset_controller_fsm(host, SRD);
  861. omap_hsmmc_dma_cleanup(host, err);
  862. } else if (host->mrq && host->mrq->cmd)
  863. host->mrq->cmd->error = err;
  864. }
  865. static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
  866. {
  867. struct mmc_data *data;
  868. int end_cmd = 0, end_trans = 0;
  869. data = host->data;
  870. dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
  871. if (status & ERR_EN) {
  872. omap_hsmmc_dbg_report_irq(host, status);
  873. if (status & (CTO_EN | CCRC_EN))
  874. end_cmd = 1;
  875. if (status & (CTO_EN | DTO_EN))
  876. hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
  877. else if (status & (CCRC_EN | DCRC_EN))
  878. hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
  879. if (host->data || host->response_busy) {
  880. end_trans = !end_cmd;
  881. host->response_busy = 0;
  882. }
  883. }
  884. if (end_cmd || ((status & CC_EN) && host->cmd))
  885. omap_hsmmc_cmd_done(host, host->cmd);
  886. if ((end_trans || (status & TC_EN)) && host->mrq)
  887. omap_hsmmc_xfer_done(host, data);
  888. }
  889. /*
  890. * MMC controller IRQ handler
  891. */
  892. static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
  893. {
  894. struct omap_hsmmc_host *host = dev_id;
  895. int status;
  896. status = OMAP_HSMMC_READ(host->base, STAT);
  897. while (status & INT_EN_MASK && host->req_in_progress) {
  898. omap_hsmmc_do_irq(host, status);
  899. /* Flush posted write */
  900. OMAP_HSMMC_WRITE(host->base, STAT, status);
  901. status = OMAP_HSMMC_READ(host->base, STAT);
  902. }
  903. return IRQ_HANDLED;
  904. }
  905. static void set_sd_bus_power(struct omap_hsmmc_host *host)
  906. {
  907. unsigned long i;
  908. OMAP_HSMMC_WRITE(host->base, HCTL,
  909. OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
  910. for (i = 0; i < loops_per_jiffy; i++) {
  911. if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
  912. break;
  913. cpu_relax();
  914. }
  915. }
  916. /*
  917. * Switch MMC interface voltage ... only relevant for MMC1.
  918. *
  919. * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
  920. * The MMC2 transceiver controls are used instead of DAT4..DAT7.
  921. * Some chips, like eMMC ones, use internal transceivers.
  922. */
  923. static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
  924. {
  925. u32 reg_val = 0;
  926. int ret;
  927. /* Disable the clocks */
  928. pm_runtime_put_sync(host->dev);
  929. if (host->dbclk)
  930. clk_disable_unprepare(host->dbclk);
  931. /* Turn the power off */
  932. ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
  933. /* Turn the power ON with given VDD 1.8 or 3.0v */
  934. if (!ret)
  935. ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
  936. vdd);
  937. pm_runtime_get_sync(host->dev);
  938. if (host->dbclk)
  939. clk_prepare_enable(host->dbclk);
  940. if (ret != 0)
  941. goto err;
  942. OMAP_HSMMC_WRITE(host->base, HCTL,
  943. OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
  944. reg_val = OMAP_HSMMC_READ(host->base, HCTL);
  945. /*
  946. * If a MMC dual voltage card is detected, the set_ios fn calls
  947. * this fn with VDD bit set for 1.8V. Upon card removal from the
  948. * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
  949. *
  950. * Cope with a bit of slop in the range ... per data sheets:
  951. * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
  952. * but recommended values are 1.71V to 1.89V
  953. * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
  954. * but recommended values are 2.7V to 3.3V
  955. *
  956. * Board setup code shouldn't permit anything very out-of-range.
  957. * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
  958. * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
  959. */
  960. if ((1 << vdd) <= MMC_VDD_23_24)
  961. reg_val |= SDVS18;
  962. else
  963. reg_val |= SDVS30;
  964. OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
  965. set_sd_bus_power(host);
  966. return 0;
  967. err:
  968. dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
  969. return ret;
  970. }
  971. /* Protect the card while the cover is open */
  972. static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
  973. {
  974. if (!mmc_slot(host).get_cover_state)
  975. return;
  976. host->reqs_blocked = 0;
  977. if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
  978. if (host->protect_card) {
  979. dev_info(host->dev, "%s: cover is closed, "
  980. "card is now accessible\n",
  981. mmc_hostname(host->mmc));
  982. host->protect_card = 0;
  983. }
  984. } else {
  985. if (!host->protect_card) {
  986. dev_info(host->dev, "%s: cover is open, "
  987. "card is now inaccessible\n",
  988. mmc_hostname(host->mmc));
  989. host->protect_card = 1;
  990. }
  991. }
  992. }
  993. /*
  994. * irq handler to notify the core about card insertion/removal
  995. */
  996. static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
  997. {
  998. struct omap_hsmmc_host *host = dev_id;
  999. struct omap_mmc_slot_data *slot = &mmc_slot(host);
  1000. int carddetect;
  1001. if (host->suspended)
  1002. return IRQ_HANDLED;
  1003. sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
  1004. if (slot->card_detect)
  1005. carddetect = slot->card_detect(host->dev, host->slot_id);
  1006. else {
  1007. omap_hsmmc_protect_card(host);
  1008. carddetect = -ENOSYS;
  1009. }
  1010. if (carddetect)
  1011. mmc_detect_change(host->mmc, (HZ * 200) / 1000);
  1012. else
  1013. mmc_detect_change(host->mmc, (HZ * 50) / 1000);
  1014. return IRQ_HANDLED;
  1015. }
  1016. static void omap_hsmmc_dma_callback(void *param)
  1017. {
  1018. struct omap_hsmmc_host *host = param;
  1019. struct dma_chan *chan;
  1020. struct mmc_data *data;
  1021. int req_in_progress;
  1022. spin_lock_irq(&host->irq_lock);
  1023. if (host->dma_ch < 0) {
  1024. spin_unlock_irq(&host->irq_lock);
  1025. return;
  1026. }
  1027. data = host->mrq->data;
  1028. chan = omap_hsmmc_get_dma_chan(host, data);
  1029. if (!data->host_cookie)
  1030. dma_unmap_sg(chan->device->dev,
  1031. data->sg, data->sg_len,
  1032. omap_hsmmc_get_dma_dir(host, data));
  1033. req_in_progress = host->req_in_progress;
  1034. host->dma_ch = -1;
  1035. spin_unlock_irq(&host->irq_lock);
  1036. /* If DMA has finished after TC, complete the request */
  1037. if (!req_in_progress) {
  1038. struct mmc_request *mrq = host->mrq;
  1039. host->mrq = NULL;
  1040. mmc_request_done(host->mmc, mrq);
  1041. }
  1042. }
  1043. static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
  1044. struct mmc_data *data,
  1045. struct omap_hsmmc_next *next,
  1046. struct dma_chan *chan)
  1047. {
  1048. int dma_len;
  1049. if (!next && data->host_cookie &&
  1050. data->host_cookie != host->next_data.cookie) {
  1051. dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
  1052. " host->next_data.cookie %d\n",
  1053. __func__, data->host_cookie, host->next_data.cookie);
  1054. data->host_cookie = 0;
  1055. }
  1056. /* Check if next job is already prepared */
  1057. if (next ||
  1058. (!next && data->host_cookie != host->next_data.cookie)) {
  1059. dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
  1060. omap_hsmmc_get_dma_dir(host, data));
  1061. } else {
  1062. dma_len = host->next_data.dma_len;
  1063. host->next_data.dma_len = 0;
  1064. }
  1065. if (dma_len == 0)
  1066. return -EINVAL;
  1067. if (next) {
  1068. next->dma_len = dma_len;
  1069. data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
  1070. } else
  1071. host->dma_len = dma_len;
  1072. return 0;
  1073. }
  1074. /*
  1075. * Routine to configure and start DMA for the MMC card
  1076. */
  1077. static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
  1078. struct mmc_request *req)
  1079. {
  1080. struct dma_slave_config cfg;
  1081. struct dma_async_tx_descriptor *tx;
  1082. int ret = 0, i;
  1083. struct mmc_data *data = req->data;
  1084. struct dma_chan *chan;
  1085. /* Sanity check: all the SG entries must be aligned by block size. */
  1086. for (i = 0; i < data->sg_len; i++) {
  1087. struct scatterlist *sgl;
  1088. sgl = data->sg + i;
  1089. if (sgl->length % data->blksz)
  1090. return -EINVAL;
  1091. }
  1092. if ((data->blksz % 4) != 0)
  1093. /* REVISIT: The MMC buffer increments only when MSB is written.
  1094. * Return error for blksz which is non multiple of four.
  1095. */
  1096. return -EINVAL;
  1097. BUG_ON(host->dma_ch != -1);
  1098. chan = omap_hsmmc_get_dma_chan(host, data);
  1099. cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
  1100. cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
  1101. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1102. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1103. cfg.src_maxburst = data->blksz / 4;
  1104. cfg.dst_maxburst = data->blksz / 4;
  1105. ret = dmaengine_slave_config(chan, &cfg);
  1106. if (ret)
  1107. return ret;
  1108. ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
  1109. if (ret)
  1110. return ret;
  1111. tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
  1112. data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
  1113. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  1114. if (!tx) {
  1115. dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
  1116. /* FIXME: cleanup */
  1117. return -1;
  1118. }
  1119. tx->callback = omap_hsmmc_dma_callback;
  1120. tx->callback_param = host;
  1121. /* Does not fail */
  1122. dmaengine_submit(tx);
  1123. host->dma_ch = 1;
  1124. dma_async_issue_pending(chan);
  1125. return 0;
  1126. }
  1127. static void set_data_timeout(struct omap_hsmmc_host *host,
  1128. unsigned int timeout_ns,
  1129. unsigned int timeout_clks)
  1130. {
  1131. unsigned int timeout, cycle_ns;
  1132. uint32_t reg, clkd, dto = 0;
  1133. reg = OMAP_HSMMC_READ(host->base, SYSCTL);
  1134. clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
  1135. if (clkd == 0)
  1136. clkd = 1;
  1137. cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
  1138. timeout = timeout_ns / cycle_ns;
  1139. timeout += timeout_clks;
  1140. if (timeout) {
  1141. while ((timeout & 0x80000000) == 0) {
  1142. dto += 1;
  1143. timeout <<= 1;
  1144. }
  1145. dto = 31 - dto;
  1146. timeout <<= 1;
  1147. if (timeout && dto)
  1148. dto += 1;
  1149. if (dto >= 13)
  1150. dto -= 13;
  1151. else
  1152. dto = 0;
  1153. if (dto > 14)
  1154. dto = 14;
  1155. }
  1156. reg &= ~DTO_MASK;
  1157. reg |= dto << DTO_SHIFT;
  1158. OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
  1159. }
  1160. /*
  1161. * Configure block length for MMC/SD cards and initiate the transfer.
  1162. */
  1163. static int
  1164. omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
  1165. {
  1166. int ret;
  1167. host->data = req->data;
  1168. if (req->data == NULL) {
  1169. OMAP_HSMMC_WRITE(host->base, BLK, 0);
  1170. /*
  1171. * Set an arbitrary 100ms data timeout for commands with
  1172. * busy signal.
  1173. */
  1174. if (req->cmd->flags & MMC_RSP_BUSY)
  1175. set_data_timeout(host, 100000000U, 0);
  1176. return 0;
  1177. }
  1178. OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
  1179. | (req->data->blocks << 16));
  1180. set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
  1181. if (host->use_dma) {
  1182. ret = omap_hsmmc_start_dma_transfer(host, req);
  1183. if (ret != 0) {
  1184. dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
  1185. return ret;
  1186. }
  1187. }
  1188. return 0;
  1189. }
  1190. static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
  1191. int err)
  1192. {
  1193. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1194. struct mmc_data *data = mrq->data;
  1195. if (host->use_dma && data->host_cookie) {
  1196. struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
  1197. dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
  1198. omap_hsmmc_get_dma_dir(host, data));
  1199. data->host_cookie = 0;
  1200. }
  1201. }
  1202. static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
  1203. bool is_first_req)
  1204. {
  1205. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1206. if (mrq->data->host_cookie) {
  1207. mrq->data->host_cookie = 0;
  1208. return ;
  1209. }
  1210. if (host->use_dma) {
  1211. struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
  1212. if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
  1213. &host->next_data, c))
  1214. mrq->data->host_cookie = 0;
  1215. }
  1216. }
  1217. /*
  1218. * Request function. for read/write operation
  1219. */
  1220. static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
  1221. {
  1222. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1223. int err;
  1224. BUG_ON(host->req_in_progress);
  1225. BUG_ON(host->dma_ch != -1);
  1226. if (host->protect_card) {
  1227. if (host->reqs_blocked < 3) {
  1228. /*
  1229. * Ensure the controller is left in a consistent
  1230. * state by resetting the command and data state
  1231. * machines.
  1232. */
  1233. omap_hsmmc_reset_controller_fsm(host, SRD);
  1234. omap_hsmmc_reset_controller_fsm(host, SRC);
  1235. host->reqs_blocked += 1;
  1236. }
  1237. req->cmd->error = -EBADF;
  1238. if (req->data)
  1239. req->data->error = -EBADF;
  1240. req->cmd->retries = 0;
  1241. mmc_request_done(mmc, req);
  1242. return;
  1243. } else if (host->reqs_blocked)
  1244. host->reqs_blocked = 0;
  1245. WARN_ON(host->mrq != NULL);
  1246. host->mrq = req;
  1247. err = omap_hsmmc_prepare_data(host, req);
  1248. if (err) {
  1249. req->cmd->error = err;
  1250. if (req->data)
  1251. req->data->error = err;
  1252. host->mrq = NULL;
  1253. mmc_request_done(mmc, req);
  1254. return;
  1255. }
  1256. omap_hsmmc_start_command(host, req->cmd, req->data);
  1257. }
  1258. /* Routine to configure clock values. Exposed API to core */
  1259. static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1260. {
  1261. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1262. int do_send_init_stream = 0;
  1263. pm_runtime_get_sync(host->dev);
  1264. if (ios->power_mode != host->power_mode) {
  1265. switch (ios->power_mode) {
  1266. case MMC_POWER_OFF:
  1267. mmc_slot(host).set_power(host->dev, host->slot_id,
  1268. 0, 0);
  1269. break;
  1270. case MMC_POWER_UP:
  1271. mmc_slot(host).set_power(host->dev, host->slot_id,
  1272. 1, ios->vdd);
  1273. break;
  1274. case MMC_POWER_ON:
  1275. do_send_init_stream = 1;
  1276. break;
  1277. }
  1278. host->power_mode = ios->power_mode;
  1279. }
  1280. /* FIXME: set registers based only on changes to ios */
  1281. omap_hsmmc_set_bus_width(host);
  1282. if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  1283. /* Only MMC1 can interface at 3V without some flavor
  1284. * of external transceiver; but they all handle 1.8V.
  1285. */
  1286. if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
  1287. (ios->vdd == DUAL_VOLT_OCR_BIT) &&
  1288. /*
  1289. * With pbias cell programming missing, this
  1290. * can't be allowed when booting with device
  1291. * tree.
  1292. */
  1293. !host->dev->of_node) {
  1294. /*
  1295. * The mmc_select_voltage fn of the core does
  1296. * not seem to set the power_mode to
  1297. * MMC_POWER_UP upon recalculating the voltage.
  1298. * vdd 1.8v.
  1299. */
  1300. if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
  1301. dev_dbg(mmc_dev(host->mmc),
  1302. "Switch operation failed\n");
  1303. }
  1304. }
  1305. omap_hsmmc_set_clock(host);
  1306. if (do_send_init_stream)
  1307. send_init_stream(host);
  1308. omap_hsmmc_set_bus_mode(host);
  1309. pm_runtime_put_autosuspend(host->dev);
  1310. }
  1311. static int omap_hsmmc_get_cd(struct mmc_host *mmc)
  1312. {
  1313. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1314. if (!mmc_slot(host).card_detect)
  1315. return -ENOSYS;
  1316. return mmc_slot(host).card_detect(host->dev, host->slot_id);
  1317. }
  1318. static int omap_hsmmc_get_ro(struct mmc_host *mmc)
  1319. {
  1320. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1321. if (!mmc_slot(host).get_ro)
  1322. return -ENOSYS;
  1323. return mmc_slot(host).get_ro(host->dev, 0);
  1324. }
  1325. static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
  1326. {
  1327. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1328. if (mmc_slot(host).init_card)
  1329. mmc_slot(host).init_card(card);
  1330. }
  1331. static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
  1332. {
  1333. u32 hctl, capa, value;
  1334. /* Only MMC1 supports 3.0V */
  1335. if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
  1336. hctl = SDVS30;
  1337. capa = VS30 | VS18;
  1338. } else {
  1339. hctl = SDVS18;
  1340. capa = VS18;
  1341. }
  1342. value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
  1343. OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
  1344. value = OMAP_HSMMC_READ(host->base, CAPA);
  1345. OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
  1346. /* Set SD bus power bit */
  1347. set_sd_bus_power(host);
  1348. }
  1349. static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
  1350. {
  1351. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1352. pm_runtime_get_sync(host->dev);
  1353. return 0;
  1354. }
  1355. static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
  1356. {
  1357. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1358. pm_runtime_mark_last_busy(host->dev);
  1359. pm_runtime_put_autosuspend(host->dev);
  1360. return 0;
  1361. }
  1362. static const struct mmc_host_ops omap_hsmmc_ops = {
  1363. .enable = omap_hsmmc_enable_fclk,
  1364. .disable = omap_hsmmc_disable_fclk,
  1365. .post_req = omap_hsmmc_post_req,
  1366. .pre_req = omap_hsmmc_pre_req,
  1367. .request = omap_hsmmc_request,
  1368. .set_ios = omap_hsmmc_set_ios,
  1369. .get_cd = omap_hsmmc_get_cd,
  1370. .get_ro = omap_hsmmc_get_ro,
  1371. .init_card = omap_hsmmc_init_card,
  1372. /* NYET -- enable_sdio_irq */
  1373. };
  1374. #ifdef CONFIG_DEBUG_FS
  1375. static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
  1376. {
  1377. struct mmc_host *mmc = s->private;
  1378. struct omap_hsmmc_host *host = mmc_priv(mmc);
  1379. int context_loss = 0;
  1380. if (host->pdata->get_context_loss_count)
  1381. context_loss = host->pdata->get_context_loss_count(host->dev);
  1382. seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
  1383. mmc->index, host->context_loss, context_loss);
  1384. if (host->suspended) {
  1385. seq_printf(s, "host suspended, can't read registers\n");
  1386. return 0;
  1387. }
  1388. pm_runtime_get_sync(host->dev);
  1389. seq_printf(s, "CON:\t\t0x%08x\n",
  1390. OMAP_HSMMC_READ(host->base, CON));
  1391. seq_printf(s, "HCTL:\t\t0x%08x\n",
  1392. OMAP_HSMMC_READ(host->base, HCTL));
  1393. seq_printf(s, "SYSCTL:\t\t0x%08x\n",
  1394. OMAP_HSMMC_READ(host->base, SYSCTL));
  1395. seq_printf(s, "IE:\t\t0x%08x\n",
  1396. OMAP_HSMMC_READ(host->base, IE));
  1397. seq_printf(s, "ISE:\t\t0x%08x\n",
  1398. OMAP_HSMMC_READ(host->base, ISE));
  1399. seq_printf(s, "CAPA:\t\t0x%08x\n",
  1400. OMAP_HSMMC_READ(host->base, CAPA));
  1401. pm_runtime_mark_last_busy(host->dev);
  1402. pm_runtime_put_autosuspend(host->dev);
  1403. return 0;
  1404. }
  1405. static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
  1406. {
  1407. return single_open(file, omap_hsmmc_regs_show, inode->i_private);
  1408. }
  1409. static const struct file_operations mmc_regs_fops = {
  1410. .open = omap_hsmmc_regs_open,
  1411. .read = seq_read,
  1412. .llseek = seq_lseek,
  1413. .release = single_release,
  1414. };
  1415. static void omap_hsmmc_debugfs(struct mmc_host *mmc)
  1416. {
  1417. if (mmc->debugfs_root)
  1418. debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
  1419. mmc, &mmc_regs_fops);
  1420. }
  1421. #else
  1422. static void omap_hsmmc_debugfs(struct mmc_host *mmc)
  1423. {
  1424. }
  1425. #endif
  1426. #ifdef CONFIG_OF
  1427. static u16 omap4_reg_offset = 0x100;
  1428. static const struct of_device_id omap_mmc_of_match[] = {
  1429. {
  1430. .compatible = "ti,omap2-hsmmc",
  1431. },
  1432. {
  1433. .compatible = "ti,omap3-hsmmc",
  1434. },
  1435. {
  1436. .compatible = "ti,omap4-hsmmc",
  1437. .data = &omap4_reg_offset,
  1438. },
  1439. {},
  1440. };
  1441. MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
  1442. static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
  1443. {
  1444. struct omap_mmc_platform_data *pdata;
  1445. struct device_node *np = dev->of_node;
  1446. u32 bus_width, max_freq;
  1447. int cd_gpio, wp_gpio;
  1448. cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
  1449. wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
  1450. if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER)
  1451. return ERR_PTR(-EPROBE_DEFER);
  1452. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  1453. if (!pdata)
  1454. return NULL; /* out of memory */
  1455. if (of_find_property(np, "ti,dual-volt", NULL))
  1456. pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
  1457. /* This driver only supports 1 slot */
  1458. pdata->nr_slots = 1;
  1459. pdata->slots[0].switch_pin = cd_gpio;
  1460. pdata->slots[0].gpio_wp = wp_gpio;
  1461. if (of_find_property(np, "ti,non-removable", NULL)) {
  1462. pdata->slots[0].nonremovable = true;
  1463. pdata->slots[0].no_regulator_off_init = true;
  1464. }
  1465. of_property_read_u32(np, "bus-width", &bus_width);
  1466. if (bus_width == 4)
  1467. pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
  1468. else if (bus_width == 8)
  1469. pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
  1470. if (of_find_property(np, "ti,needs-special-reset", NULL))
  1471. pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
  1472. if (!of_property_read_u32(np, "max-frequency", &max_freq))
  1473. pdata->max_freq = max_freq;
  1474. if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
  1475. pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT;
  1476. return pdata;
  1477. }
  1478. #else
  1479. static inline struct omap_mmc_platform_data
  1480. *of_get_hsmmc_pdata(struct device *dev)
  1481. {
  1482. return NULL;
  1483. }
  1484. #endif
  1485. static int omap_hsmmc_probe(struct platform_device *pdev)
  1486. {
  1487. struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
  1488. struct mmc_host *mmc;
  1489. struct omap_hsmmc_host *host = NULL;
  1490. struct resource *res;
  1491. int ret, irq;
  1492. const struct of_device_id *match;
  1493. dma_cap_mask_t mask;
  1494. unsigned tx_req, rx_req;
  1495. struct pinctrl *pinctrl;
  1496. match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
  1497. if (match) {
  1498. pdata = of_get_hsmmc_pdata(&pdev->dev);
  1499. if (IS_ERR(pdata))
  1500. return PTR_ERR(pdata);
  1501. if (match->data) {
  1502. const u16 *offsetp = match->data;
  1503. pdata->reg_offset = *offsetp;
  1504. }
  1505. }
  1506. if (pdata == NULL) {
  1507. dev_err(&pdev->dev, "Platform Data is missing\n");
  1508. return -ENXIO;
  1509. }
  1510. if (pdata->nr_slots == 0) {
  1511. dev_err(&pdev->dev, "No Slots\n");
  1512. return -ENXIO;
  1513. }
  1514. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1515. irq = platform_get_irq(pdev, 0);
  1516. if (res == NULL || irq < 0)
  1517. return -ENXIO;
  1518. res = request_mem_region(res->start, resource_size(res), pdev->name);
  1519. if (res == NULL)
  1520. return -EBUSY;
  1521. ret = omap_hsmmc_gpio_init(pdata);
  1522. if (ret)
  1523. goto err;
  1524. mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
  1525. if (!mmc) {
  1526. ret = -ENOMEM;
  1527. goto err_alloc;
  1528. }
  1529. host = mmc_priv(mmc);
  1530. host->mmc = mmc;
  1531. host->pdata = pdata;
  1532. host->dev = &pdev->dev;
  1533. host->use_dma = 1;
  1534. host->dma_ch = -1;
  1535. host->irq = irq;
  1536. host->slot_id = 0;
  1537. host->mapbase = res->start + pdata->reg_offset;
  1538. host->base = ioremap(host->mapbase, SZ_4K);
  1539. host->power_mode = MMC_POWER_OFF;
  1540. host->next_data.cookie = 1;
  1541. platform_set_drvdata(pdev, host);
  1542. mmc->ops = &omap_hsmmc_ops;
  1543. /*
  1544. * If regulator_disable can only put vcc_aux to sleep then there is
  1545. * no off state.
  1546. */
  1547. if (mmc_slot(host).vcc_aux_disable_is_sleep)
  1548. mmc_slot(host).no_off = 1;
  1549. mmc->f_min = OMAP_MMC_MIN_CLOCK;
  1550. if (pdata->max_freq > 0)
  1551. mmc->f_max = pdata->max_freq;
  1552. else
  1553. mmc->f_max = OMAP_MMC_MAX_CLOCK;
  1554. spin_lock_init(&host->irq_lock);
  1555. host->fclk = clk_get(&pdev->dev, "fck");
  1556. if (IS_ERR(host->fclk)) {
  1557. ret = PTR_ERR(host->fclk);
  1558. host->fclk = NULL;
  1559. goto err1;
  1560. }
  1561. if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
  1562. dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
  1563. mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
  1564. }
  1565. pm_runtime_enable(host->dev);
  1566. pm_runtime_get_sync(host->dev);
  1567. pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
  1568. pm_runtime_use_autosuspend(host->dev);
  1569. omap_hsmmc_context_save(host);
  1570. host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
  1571. /*
  1572. * MMC can still work without debounce clock.
  1573. */
  1574. if (IS_ERR(host->dbclk)) {
  1575. host->dbclk = NULL;
  1576. } else if (clk_prepare_enable(host->dbclk) != 0) {
  1577. dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
  1578. clk_put(host->dbclk);
  1579. host->dbclk = NULL;
  1580. }
  1581. /* Since we do only SG emulation, we can have as many segs
  1582. * as we want. */
  1583. mmc->max_segs = 1024;
  1584. mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
  1585. mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
  1586. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  1587. mmc->max_seg_size = mmc->max_req_size;
  1588. mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
  1589. MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
  1590. mmc->caps |= mmc_slot(host).caps;
  1591. if (mmc->caps & MMC_CAP_8_BIT_DATA)
  1592. mmc->caps |= MMC_CAP_4_BIT_DATA;
  1593. if (mmc_slot(host).nonremovable)
  1594. mmc->caps |= MMC_CAP_NONREMOVABLE;
  1595. mmc->pm_caps = mmc_slot(host).pm_caps;
  1596. omap_hsmmc_conf_bus_power(host);
  1597. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
  1598. if (!res) {
  1599. dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
  1600. ret = -ENXIO;
  1601. goto err_irq;
  1602. }
  1603. tx_req = res->start;
  1604. res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
  1605. if (!res) {
  1606. dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
  1607. ret = -ENXIO;
  1608. goto err_irq;
  1609. }
  1610. rx_req = res->start;
  1611. dma_cap_zero(mask);
  1612. dma_cap_set(DMA_SLAVE, mask);
  1613. host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
  1614. if (!host->rx_chan) {
  1615. dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
  1616. ret = -ENXIO;
  1617. goto err_irq;
  1618. }
  1619. host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
  1620. if (!host->tx_chan) {
  1621. dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
  1622. ret = -ENXIO;
  1623. goto err_irq;
  1624. }
  1625. /* Request IRQ for MMC operations */
  1626. ret = request_irq(host->irq, omap_hsmmc_irq, 0,
  1627. mmc_hostname(mmc), host);
  1628. if (ret) {
  1629. dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
  1630. goto err_irq;
  1631. }
  1632. if (pdata->init != NULL) {
  1633. if (pdata->init(&pdev->dev) != 0) {
  1634. dev_err(mmc_dev(host->mmc),
  1635. "Unable to configure MMC IRQs\n");
  1636. goto err_irq_cd_init;
  1637. }
  1638. }
  1639. if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
  1640. ret = omap_hsmmc_reg_get(host);
  1641. if (ret)
  1642. goto err_reg;
  1643. host->use_reg = 1;
  1644. }
  1645. mmc->ocr_avail = mmc_slot(host).ocr_mask;
  1646. /* Request IRQ for card detect */
  1647. if ((mmc_slot(host).card_detect_irq)) {
  1648. ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
  1649. NULL,
  1650. omap_hsmmc_detect,
  1651. IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
  1652. mmc_hostname(mmc), host);
  1653. if (ret) {
  1654. dev_err(mmc_dev(host->mmc),
  1655. "Unable to grab MMC CD IRQ\n");
  1656. goto err_irq_cd;
  1657. }
  1658. pdata->suspend = omap_hsmmc_suspend_cdirq;
  1659. pdata->resume = omap_hsmmc_resume_cdirq;
  1660. }
  1661. omap_hsmmc_disable_irq(host);
  1662. pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
  1663. if (IS_ERR(pinctrl))
  1664. dev_warn(&pdev->dev,
  1665. "pins are not configured from the driver\n");
  1666. omap_hsmmc_protect_card(host);
  1667. mmc_add_host(mmc);
  1668. if (mmc_slot(host).name != NULL) {
  1669. ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
  1670. if (ret < 0)
  1671. goto err_slot_name;
  1672. }
  1673. if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
  1674. ret = device_create_file(&mmc->class_dev,
  1675. &dev_attr_cover_switch);
  1676. if (ret < 0)
  1677. goto err_slot_name;
  1678. }
  1679. omap_hsmmc_debugfs(mmc);
  1680. pm_runtime_mark_last_busy(host->dev);
  1681. pm_runtime_put_autosuspend(host->dev);
  1682. return 0;
  1683. err_slot_name:
  1684. mmc_remove_host(mmc);
  1685. free_irq(mmc_slot(host).card_detect_irq, host);
  1686. err_irq_cd:
  1687. if (host->use_reg)
  1688. omap_hsmmc_reg_put(host);
  1689. err_reg:
  1690. if (host->pdata->cleanup)
  1691. host->pdata->cleanup(&pdev->dev);
  1692. err_irq_cd_init:
  1693. free_irq(host->irq, host);
  1694. err_irq:
  1695. if (host->tx_chan)
  1696. dma_release_channel(host->tx_chan);
  1697. if (host->rx_chan)
  1698. dma_release_channel(host->rx_chan);
  1699. pm_runtime_put_sync(host->dev);
  1700. pm_runtime_disable(host->dev);
  1701. clk_put(host->fclk);
  1702. if (host->dbclk) {
  1703. clk_disable_unprepare(host->dbclk);
  1704. clk_put(host->dbclk);
  1705. }
  1706. err1:
  1707. iounmap(host->base);
  1708. platform_set_drvdata(pdev, NULL);
  1709. mmc_free_host(mmc);
  1710. err_alloc:
  1711. omap_hsmmc_gpio_free(pdata);
  1712. err:
  1713. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1714. if (res)
  1715. release_mem_region(res->start, resource_size(res));
  1716. return ret;
  1717. }
  1718. static int omap_hsmmc_remove(struct platform_device *pdev)
  1719. {
  1720. struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
  1721. struct resource *res;
  1722. pm_runtime_get_sync(host->dev);
  1723. mmc_remove_host(host->mmc);
  1724. if (host->use_reg)
  1725. omap_hsmmc_reg_put(host);
  1726. if (host->pdata->cleanup)
  1727. host->pdata->cleanup(&pdev->dev);
  1728. free_irq(host->irq, host);
  1729. if (mmc_slot(host).card_detect_irq)
  1730. free_irq(mmc_slot(host).card_detect_irq, host);
  1731. if (host->tx_chan)
  1732. dma_release_channel(host->tx_chan);
  1733. if (host->rx_chan)
  1734. dma_release_channel(host->rx_chan);
  1735. pm_runtime_put_sync(host->dev);
  1736. pm_runtime_disable(host->dev);
  1737. clk_put(host->fclk);
  1738. if (host->dbclk) {
  1739. clk_disable_unprepare(host->dbclk);
  1740. clk_put(host->dbclk);
  1741. }
  1742. omap_hsmmc_gpio_free(host->pdata);
  1743. iounmap(host->base);
  1744. mmc_free_host(host->mmc);
  1745. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1746. if (res)
  1747. release_mem_region(res->start, resource_size(res));
  1748. platform_set_drvdata(pdev, NULL);
  1749. return 0;
  1750. }
  1751. #ifdef CONFIG_PM
  1752. static int omap_hsmmc_prepare(struct device *dev)
  1753. {
  1754. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  1755. if (host->pdata->suspend)
  1756. return host->pdata->suspend(dev, host->slot_id);
  1757. return 0;
  1758. }
  1759. static void omap_hsmmc_complete(struct device *dev)
  1760. {
  1761. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  1762. if (host->pdata->resume)
  1763. host->pdata->resume(dev, host->slot_id);
  1764. }
  1765. static int omap_hsmmc_suspend(struct device *dev)
  1766. {
  1767. int ret = 0;
  1768. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  1769. if (!host)
  1770. return 0;
  1771. if (host && host->suspended)
  1772. return 0;
  1773. pm_runtime_get_sync(host->dev);
  1774. host->suspended = 1;
  1775. ret = mmc_suspend_host(host->mmc);
  1776. if (ret) {
  1777. host->suspended = 0;
  1778. goto err;
  1779. }
  1780. if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
  1781. omap_hsmmc_disable_irq(host);
  1782. OMAP_HSMMC_WRITE(host->base, HCTL,
  1783. OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
  1784. }
  1785. if (host->dbclk)
  1786. clk_disable_unprepare(host->dbclk);
  1787. err:
  1788. pm_runtime_put_sync(host->dev);
  1789. return ret;
  1790. }
  1791. /* Routine to resume the MMC device */
  1792. static int omap_hsmmc_resume(struct device *dev)
  1793. {
  1794. int ret = 0;
  1795. struct omap_hsmmc_host *host = dev_get_drvdata(dev);
  1796. if (!host)
  1797. return 0;
  1798. if (host && !host->suspended)
  1799. return 0;
  1800. pm_runtime_get_sync(host->dev);
  1801. if (host->dbclk)
  1802. clk_prepare_enable(host->dbclk);
  1803. if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
  1804. omap_hsmmc_conf_bus_power(host);
  1805. omap_hsmmc_protect_card(host);
  1806. /* Notify the core to resume the host */
  1807. ret = mmc_resume_host(host->mmc);
  1808. if (ret == 0)
  1809. host->suspended = 0;
  1810. pm_runtime_mark_last_busy(host->dev);
  1811. pm_runtime_put_autosuspend(host->dev);
  1812. return ret;
  1813. }
  1814. #else
  1815. #define omap_hsmmc_prepare NULL
  1816. #define omap_hsmmc_complete NULL
  1817. #define omap_hsmmc_suspend NULL
  1818. #define omap_hsmmc_resume NULL
  1819. #endif
  1820. static int omap_hsmmc_runtime_suspend(struct device *dev)
  1821. {
  1822. struct omap_hsmmc_host *host;
  1823. host = platform_get_drvdata(to_platform_device(dev));
  1824. omap_hsmmc_context_save(host);
  1825. dev_dbg(dev, "disabled\n");
  1826. return 0;
  1827. }
  1828. static int omap_hsmmc_runtime_resume(struct device *dev)
  1829. {
  1830. struct omap_hsmmc_host *host;
  1831. host = platform_get_drvdata(to_platform_device(dev));
  1832. omap_hsmmc_context_restore(host);
  1833. dev_dbg(dev, "enabled\n");
  1834. return 0;
  1835. }
  1836. static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
  1837. .suspend = omap_hsmmc_suspend,
  1838. .resume = omap_hsmmc_resume,
  1839. .prepare = omap_hsmmc_prepare,
  1840. .complete = omap_hsmmc_complete,
  1841. .runtime_suspend = omap_hsmmc_runtime_suspend,
  1842. .runtime_resume = omap_hsmmc_runtime_resume,
  1843. };
  1844. static struct platform_driver omap_hsmmc_driver = {
  1845. .probe = omap_hsmmc_probe,
  1846. .remove = omap_hsmmc_remove,
  1847. .driver = {
  1848. .name = DRIVER_NAME,
  1849. .owner = THIS_MODULE,
  1850. .pm = &omap_hsmmc_dev_pm_ops,
  1851. .of_match_table = of_match_ptr(omap_mmc_of_match),
  1852. },
  1853. };
  1854. module_platform_driver(omap_hsmmc_driver);
  1855. MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
  1856. MODULE_LICENSE("GPL");
  1857. MODULE_ALIAS("platform:" DRIVER_NAME);
  1858. MODULE_AUTHOR("Texas Instruments Inc");