gpio-rcar.c 10 KB

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  1. /*
  2. * Renesas R-Car GPIO Support
  3. *
  4. * Copyright (C) 2013 Magnus Damm
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/err.h>
  16. #include <linux/gpio.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/io.h>
  20. #include <linux/ioport.h>
  21. #include <linux/irq.h>
  22. #include <linux/irqdomain.h>
  23. #include <linux/module.h>
  24. #include <linux/pinctrl/consumer.h>
  25. #include <linux/platform_data/gpio-rcar.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/spinlock.h>
  28. #include <linux/slab.h>
  29. struct gpio_rcar_priv {
  30. void __iomem *base;
  31. spinlock_t lock;
  32. struct gpio_rcar_config config;
  33. struct platform_device *pdev;
  34. struct gpio_chip gpio_chip;
  35. struct irq_chip irq_chip;
  36. struct irq_domain *irq_domain;
  37. };
  38. #define IOINTSEL 0x00
  39. #define INOUTSEL 0x04
  40. #define OUTDT 0x08
  41. #define INDT 0x0c
  42. #define INTDT 0x10
  43. #define INTCLR 0x14
  44. #define INTMSK 0x18
  45. #define MSKCLR 0x1c
  46. #define POSNEG 0x20
  47. #define EDGLEVEL 0x24
  48. #define FILONOFF 0x28
  49. static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
  50. {
  51. return ioread32(p->base + offs);
  52. }
  53. static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
  54. u32 value)
  55. {
  56. iowrite32(value, p->base + offs);
  57. }
  58. static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
  59. int bit, bool value)
  60. {
  61. u32 tmp = gpio_rcar_read(p, offs);
  62. if (value)
  63. tmp |= BIT(bit);
  64. else
  65. tmp &= ~BIT(bit);
  66. gpio_rcar_write(p, offs, tmp);
  67. }
  68. static void gpio_rcar_irq_disable(struct irq_data *d)
  69. {
  70. struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
  71. gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
  72. }
  73. static void gpio_rcar_irq_enable(struct irq_data *d)
  74. {
  75. struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
  76. gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
  77. }
  78. static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
  79. unsigned int hwirq,
  80. bool active_high_rising_edge,
  81. bool level_trigger)
  82. {
  83. unsigned long flags;
  84. /* follow steps in the GPIO documentation for
  85. * "Setting Edge-Sensitive Interrupt Input Mode" and
  86. * "Setting Level-Sensitive Interrupt Input Mode"
  87. */
  88. spin_lock_irqsave(&p->lock, flags);
  89. /* Configure postive or negative logic in POSNEG */
  90. gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
  91. /* Configure edge or level trigger in EDGLEVEL */
  92. gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
  93. /* Select "Interrupt Input Mode" in IOINTSEL */
  94. gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
  95. /* Write INTCLR in case of edge trigger */
  96. if (!level_trigger)
  97. gpio_rcar_write(p, INTCLR, BIT(hwirq));
  98. spin_unlock_irqrestore(&p->lock, flags);
  99. }
  100. static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
  101. {
  102. struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
  103. unsigned int hwirq = irqd_to_hwirq(d);
  104. dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
  105. switch (type & IRQ_TYPE_SENSE_MASK) {
  106. case IRQ_TYPE_LEVEL_HIGH:
  107. gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
  108. break;
  109. case IRQ_TYPE_LEVEL_LOW:
  110. gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
  111. break;
  112. case IRQ_TYPE_EDGE_RISING:
  113. gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
  114. break;
  115. case IRQ_TYPE_EDGE_FALLING:
  116. gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
  117. break;
  118. default:
  119. return -EINVAL;
  120. }
  121. return 0;
  122. }
  123. static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
  124. {
  125. struct gpio_rcar_priv *p = dev_id;
  126. u32 pending;
  127. unsigned int offset, irqs_handled = 0;
  128. while ((pending = gpio_rcar_read(p, INTDT))) {
  129. offset = __ffs(pending);
  130. gpio_rcar_write(p, INTCLR, BIT(offset));
  131. generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
  132. irqs_handled++;
  133. }
  134. return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
  135. }
  136. static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
  137. {
  138. return container_of(chip, struct gpio_rcar_priv, gpio_chip);
  139. }
  140. static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
  141. unsigned int gpio,
  142. bool output)
  143. {
  144. struct gpio_rcar_priv *p = gpio_to_priv(chip);
  145. unsigned long flags;
  146. /* follow steps in the GPIO documentation for
  147. * "Setting General Output Mode" and
  148. * "Setting General Input Mode"
  149. */
  150. spin_lock_irqsave(&p->lock, flags);
  151. /* Configure postive logic in POSNEG */
  152. gpio_rcar_modify_bit(p, POSNEG, gpio, false);
  153. /* Select "General Input/Output Mode" in IOINTSEL */
  154. gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
  155. /* Select Input Mode or Output Mode in INOUTSEL */
  156. gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
  157. spin_unlock_irqrestore(&p->lock, flags);
  158. }
  159. static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
  160. {
  161. return pinctrl_request_gpio(chip->base + offset);
  162. }
  163. static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
  164. {
  165. pinctrl_free_gpio(chip->base + offset);
  166. /* Set the GPIO as an input to ensure that the next GPIO request won't
  167. * drive the GPIO pin as an output.
  168. */
  169. gpio_rcar_config_general_input_output_mode(chip, offset, false);
  170. }
  171. static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
  172. {
  173. gpio_rcar_config_general_input_output_mode(chip, offset, false);
  174. return 0;
  175. }
  176. static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
  177. {
  178. return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & BIT(offset));
  179. }
  180. static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
  181. {
  182. struct gpio_rcar_priv *p = gpio_to_priv(chip);
  183. unsigned long flags;
  184. spin_lock_irqsave(&p->lock, flags);
  185. gpio_rcar_modify_bit(p, OUTDT, offset, value);
  186. spin_unlock_irqrestore(&p->lock, flags);
  187. }
  188. static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
  189. int value)
  190. {
  191. /* write GPIO value to output before selecting output mode of pin */
  192. gpio_rcar_set(chip, offset, value);
  193. gpio_rcar_config_general_input_output_mode(chip, offset, true);
  194. return 0;
  195. }
  196. static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
  197. {
  198. return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
  199. }
  200. static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq,
  201. irq_hw_number_t hw)
  202. {
  203. struct gpio_rcar_priv *p = h->host_data;
  204. dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq);
  205. irq_set_chip_data(virq, h->host_data);
  206. irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
  207. set_irq_flags(virq, IRQF_VALID); /* kill me now */
  208. return 0;
  209. }
  210. static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
  211. .map = gpio_rcar_irq_domain_map,
  212. };
  213. static int gpio_rcar_probe(struct platform_device *pdev)
  214. {
  215. struct gpio_rcar_config *pdata = pdev->dev.platform_data;
  216. struct gpio_rcar_priv *p;
  217. struct resource *io, *irq;
  218. struct gpio_chip *gpio_chip;
  219. struct irq_chip *irq_chip;
  220. const char *name = dev_name(&pdev->dev);
  221. int ret;
  222. p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
  223. if (!p) {
  224. dev_err(&pdev->dev, "failed to allocate driver data\n");
  225. ret = -ENOMEM;
  226. goto err0;
  227. }
  228. /* deal with driver instance configuration */
  229. if (pdata)
  230. p->config = *pdata;
  231. p->pdev = pdev;
  232. platform_set_drvdata(pdev, p);
  233. spin_lock_init(&p->lock);
  234. io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  235. irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  236. if (!io || !irq) {
  237. dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
  238. ret = -EINVAL;
  239. goto err0;
  240. }
  241. p->base = devm_ioremap_nocache(&pdev->dev, io->start,
  242. resource_size(io));
  243. if (!p->base) {
  244. dev_err(&pdev->dev, "failed to remap I/O memory\n");
  245. ret = -ENXIO;
  246. goto err0;
  247. }
  248. gpio_chip = &p->gpio_chip;
  249. gpio_chip->request = gpio_rcar_request;
  250. gpio_chip->free = gpio_rcar_free;
  251. gpio_chip->direction_input = gpio_rcar_direction_input;
  252. gpio_chip->get = gpio_rcar_get;
  253. gpio_chip->direction_output = gpio_rcar_direction_output;
  254. gpio_chip->set = gpio_rcar_set;
  255. gpio_chip->to_irq = gpio_rcar_to_irq;
  256. gpio_chip->label = name;
  257. gpio_chip->owner = THIS_MODULE;
  258. gpio_chip->base = p->config.gpio_base;
  259. gpio_chip->ngpio = p->config.number_of_pins;
  260. irq_chip = &p->irq_chip;
  261. irq_chip->name = name;
  262. irq_chip->irq_mask = gpio_rcar_irq_disable;
  263. irq_chip->irq_unmask = gpio_rcar_irq_enable;
  264. irq_chip->irq_enable = gpio_rcar_irq_enable;
  265. irq_chip->irq_disable = gpio_rcar_irq_disable;
  266. irq_chip->irq_set_type = gpio_rcar_irq_set_type;
  267. irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED;
  268. p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
  269. p->config.number_of_pins,
  270. p->config.irq_base,
  271. &gpio_rcar_irq_domain_ops, p);
  272. if (!p->irq_domain) {
  273. ret = -ENXIO;
  274. dev_err(&pdev->dev, "cannot initialize irq domain\n");
  275. goto err1;
  276. }
  277. if (devm_request_irq(&pdev->dev, irq->start,
  278. gpio_rcar_irq_handler, 0, name, p)) {
  279. dev_err(&pdev->dev, "failed to request IRQ\n");
  280. ret = -ENOENT;
  281. goto err1;
  282. }
  283. ret = gpiochip_add(gpio_chip);
  284. if (ret) {
  285. dev_err(&pdev->dev, "failed to add GPIO controller\n");
  286. goto err1;
  287. }
  288. dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);
  289. /* warn in case of mismatch if irq base is specified */
  290. if (p->config.irq_base) {
  291. ret = irq_find_mapping(p->irq_domain, 0);
  292. if (p->config.irq_base != ret)
  293. dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
  294. p->config.irq_base, ret);
  295. }
  296. ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
  297. gpio_chip->base, gpio_chip->ngpio);
  298. if (ret < 0)
  299. dev_warn(&pdev->dev, "failed to add pin range\n");
  300. return 0;
  301. err1:
  302. irq_domain_remove(p->irq_domain);
  303. err0:
  304. return ret;
  305. }
  306. static int gpio_rcar_remove(struct platform_device *pdev)
  307. {
  308. struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
  309. int ret;
  310. ret = gpiochip_remove(&p->gpio_chip);
  311. if (ret)
  312. return ret;
  313. irq_domain_remove(p->irq_domain);
  314. return 0;
  315. }
  316. static struct platform_driver gpio_rcar_device_driver = {
  317. .probe = gpio_rcar_probe,
  318. .remove = gpio_rcar_remove,
  319. .driver = {
  320. .name = "gpio_rcar",
  321. }
  322. };
  323. module_platform_driver(gpio_rcar_device_driver);
  324. MODULE_AUTHOR("Magnus Damm");
  325. MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
  326. MODULE_LICENSE("GPL v2");