netxen_nic_init.c 31 KB

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  1. /*
  2. * Copyright (C) 2003 - 2006 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen,
  26. * 3965 Freedom Circle, Fourth floor,
  27. * Santa Clara, CA 95054
  28. *
  29. *
  30. * Source file for NIC routines to initialize the Phantom Hardware
  31. *
  32. */
  33. #include <linux/netdevice.h>
  34. #include <linux/delay.h>
  35. #include "netxen_nic.h"
  36. #include "netxen_nic_hw.h"
  37. #include "netxen_nic_phan_reg.h"
  38. struct crb_addr_pair {
  39. u32 addr;
  40. u32 data;
  41. };
  42. #define NETXEN_MAX_CRB_XFORM 60
  43. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  44. #define NETXEN_ADDR_ERROR (0xffffffff)
  45. #define crb_addr_transform(name) \
  46. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  47. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  48. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  49. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  50. uint32_t ctx, uint32_t ringid);
  51. static void crb_addr_transform_setup(void)
  52. {
  53. crb_addr_transform(XDMA);
  54. crb_addr_transform(TIMR);
  55. crb_addr_transform(SRE);
  56. crb_addr_transform(SQN3);
  57. crb_addr_transform(SQN2);
  58. crb_addr_transform(SQN1);
  59. crb_addr_transform(SQN0);
  60. crb_addr_transform(SQS3);
  61. crb_addr_transform(SQS2);
  62. crb_addr_transform(SQS1);
  63. crb_addr_transform(SQS0);
  64. crb_addr_transform(RPMX7);
  65. crb_addr_transform(RPMX6);
  66. crb_addr_transform(RPMX5);
  67. crb_addr_transform(RPMX4);
  68. crb_addr_transform(RPMX3);
  69. crb_addr_transform(RPMX2);
  70. crb_addr_transform(RPMX1);
  71. crb_addr_transform(RPMX0);
  72. crb_addr_transform(ROMUSB);
  73. crb_addr_transform(SN);
  74. crb_addr_transform(QMN);
  75. crb_addr_transform(QMS);
  76. crb_addr_transform(PGNI);
  77. crb_addr_transform(PGND);
  78. crb_addr_transform(PGN3);
  79. crb_addr_transform(PGN2);
  80. crb_addr_transform(PGN1);
  81. crb_addr_transform(PGN0);
  82. crb_addr_transform(PGSI);
  83. crb_addr_transform(PGSD);
  84. crb_addr_transform(PGS3);
  85. crb_addr_transform(PGS2);
  86. crb_addr_transform(PGS1);
  87. crb_addr_transform(PGS0);
  88. crb_addr_transform(PS);
  89. crb_addr_transform(PH);
  90. crb_addr_transform(NIU);
  91. crb_addr_transform(I2Q);
  92. crb_addr_transform(EG);
  93. crb_addr_transform(MN);
  94. crb_addr_transform(MS);
  95. crb_addr_transform(CAS2);
  96. crb_addr_transform(CAS1);
  97. crb_addr_transform(CAS0);
  98. crb_addr_transform(CAM);
  99. crb_addr_transform(C2C1);
  100. crb_addr_transform(C2C0);
  101. crb_addr_transform(SMB);
  102. crb_addr_transform(OCM0);
  103. crb_addr_transform(I2C0);
  104. }
  105. int netxen_init_firmware(struct netxen_adapter *adapter)
  106. {
  107. u32 state = 0, loops = 0, err = 0;
  108. /* Window 1 call */
  109. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  110. if (state == PHAN_INITIALIZE_ACK)
  111. return 0;
  112. while (state != PHAN_INITIALIZE_COMPLETE && loops < 2000) {
  113. msleep(1);
  114. /* Window 1 call */
  115. state = adapter->pci_read_normalize(adapter, CRB_CMDPEG_STATE);
  116. loops++;
  117. }
  118. if (loops >= 2000) {
  119. printk(KERN_ERR "Cmd Peg initialization not complete:%x.\n",
  120. state);
  121. err = -EIO;
  122. return err;
  123. }
  124. /* Window 1 call */
  125. adapter->pci_write_normalize(adapter,
  126. CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  127. adapter->pci_write_normalize(adapter,
  128. CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  129. adapter->pci_write_normalize(adapter,
  130. CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  131. adapter->pci_write_normalize(adapter,
  132. CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  133. return err;
  134. }
  135. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  136. {
  137. struct netxen_recv_context *recv_ctx;
  138. struct nx_host_rds_ring *rds_ring;
  139. struct netxen_rx_buffer *rx_buf;
  140. int i, ctxid, ring;
  141. for (ctxid = 0; ctxid < MAX_RCV_CTX; ++ctxid) {
  142. recv_ctx = &adapter->recv_ctx[ctxid];
  143. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  144. rds_ring = &recv_ctx->rds_rings[ring];
  145. for (i = 0; i < rds_ring->max_rx_desc_count; ++i) {
  146. rx_buf = &(rds_ring->rx_buf_arr[i]);
  147. if (rx_buf->state == NETXEN_BUFFER_FREE)
  148. continue;
  149. pci_unmap_single(adapter->pdev,
  150. rx_buf->dma,
  151. rds_ring->dma_size,
  152. PCI_DMA_FROMDEVICE);
  153. if (rx_buf->skb != NULL)
  154. dev_kfree_skb_any(rx_buf->skb);
  155. }
  156. }
  157. }
  158. }
  159. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  160. {
  161. struct netxen_cmd_buffer *cmd_buf;
  162. struct netxen_skb_frag *buffrag;
  163. int i, j;
  164. cmd_buf = adapter->cmd_buf_arr;
  165. for (i = 0; i < adapter->max_tx_desc_count; i++) {
  166. buffrag = cmd_buf->frag_array;
  167. if (buffrag->dma) {
  168. pci_unmap_single(adapter->pdev, buffrag->dma,
  169. buffrag->length, PCI_DMA_TODEVICE);
  170. buffrag->dma = 0ULL;
  171. }
  172. for (j = 0; j < cmd_buf->frag_count; j++) {
  173. buffrag++;
  174. if (buffrag->dma) {
  175. pci_unmap_page(adapter->pdev, buffrag->dma,
  176. buffrag->length,
  177. PCI_DMA_TODEVICE);
  178. buffrag->dma = 0ULL;
  179. }
  180. }
  181. /* Free the skb we received in netxen_nic_xmit_frame */
  182. if (cmd_buf->skb) {
  183. dev_kfree_skb_any(cmd_buf->skb);
  184. cmd_buf->skb = NULL;
  185. }
  186. cmd_buf++;
  187. }
  188. }
  189. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  190. {
  191. struct netxen_recv_context *recv_ctx;
  192. struct nx_host_rds_ring *rds_ring;
  193. int ctx, ring;
  194. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  195. recv_ctx = &adapter->recv_ctx[ctx];
  196. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  197. rds_ring = &recv_ctx->rds_rings[ring];
  198. if (rds_ring->rx_buf_arr) {
  199. vfree(rds_ring->rx_buf_arr);
  200. rds_ring->rx_buf_arr = NULL;
  201. }
  202. }
  203. }
  204. if (adapter->cmd_buf_arr)
  205. vfree(adapter->cmd_buf_arr);
  206. return;
  207. }
  208. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  209. {
  210. struct netxen_recv_context *recv_ctx;
  211. struct nx_host_rds_ring *rds_ring;
  212. struct netxen_rx_buffer *rx_buf;
  213. int ctx, ring, i, num_rx_bufs;
  214. struct netxen_cmd_buffer *cmd_buf_arr;
  215. struct net_device *netdev = adapter->netdev;
  216. cmd_buf_arr = (struct netxen_cmd_buffer *)vmalloc(TX_RINGSIZE);
  217. if (cmd_buf_arr == NULL) {
  218. printk(KERN_ERR "%s: Failed to allocate cmd buffer ring\n",
  219. netdev->name);
  220. return -ENOMEM;
  221. }
  222. memset(cmd_buf_arr, 0, TX_RINGSIZE);
  223. adapter->cmd_buf_arr = cmd_buf_arr;
  224. for (ctx = 0; ctx < MAX_RCV_CTX; ctx++) {
  225. recv_ctx = &adapter->recv_ctx[ctx];
  226. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  227. rds_ring = &recv_ctx->rds_rings[ring];
  228. switch (RCV_DESC_TYPE(ring)) {
  229. case RCV_DESC_NORMAL:
  230. rds_ring->max_rx_desc_count =
  231. adapter->max_rx_desc_count;
  232. rds_ring->flags = RCV_DESC_NORMAL;
  233. if (adapter->ahw.cut_through) {
  234. rds_ring->dma_size =
  235. NX_CT_DEFAULT_RX_BUF_LEN;
  236. rds_ring->skb_size =
  237. NX_CT_DEFAULT_RX_BUF_LEN;
  238. } else {
  239. rds_ring->dma_size = RX_DMA_MAP_LEN;
  240. rds_ring->skb_size =
  241. MAX_RX_BUFFER_LENGTH;
  242. }
  243. break;
  244. case RCV_DESC_JUMBO:
  245. rds_ring->max_rx_desc_count =
  246. adapter->max_jumbo_rx_desc_count;
  247. rds_ring->flags = RCV_DESC_JUMBO;
  248. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  249. rds_ring->dma_size =
  250. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  251. else
  252. rds_ring->dma_size =
  253. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  254. rds_ring->skb_size =
  255. rds_ring->dma_size + NET_IP_ALIGN;
  256. break;
  257. case RCV_RING_LRO:
  258. rds_ring->max_rx_desc_count =
  259. adapter->max_lro_rx_desc_count;
  260. rds_ring->flags = RCV_DESC_LRO;
  261. rds_ring->dma_size = RX_LRO_DMA_MAP_LEN;
  262. rds_ring->skb_size = MAX_RX_LRO_BUFFER_LENGTH;
  263. break;
  264. }
  265. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  266. vmalloc(RCV_BUFFSIZE);
  267. if (rds_ring->rx_buf_arr == NULL) {
  268. printk(KERN_ERR "%s: Failed to allocate "
  269. "rx buffer ring %d\n",
  270. netdev->name, ring);
  271. /* free whatever was already allocated */
  272. goto err_out;
  273. }
  274. memset(rds_ring->rx_buf_arr, 0, RCV_BUFFSIZE);
  275. INIT_LIST_HEAD(&rds_ring->free_list);
  276. /*
  277. * Now go through all of them, set reference handles
  278. * and put them in the queues.
  279. */
  280. num_rx_bufs = rds_ring->max_rx_desc_count;
  281. rx_buf = rds_ring->rx_buf_arr;
  282. for (i = 0; i < num_rx_bufs; i++) {
  283. list_add_tail(&rx_buf->list,
  284. &rds_ring->free_list);
  285. rx_buf->ref_handle = i;
  286. rx_buf->state = NETXEN_BUFFER_FREE;
  287. rx_buf++;
  288. }
  289. }
  290. }
  291. return 0;
  292. err_out:
  293. netxen_free_sw_resources(adapter);
  294. return -ENOMEM;
  295. }
  296. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  297. {
  298. switch (adapter->ahw.board_type) {
  299. case NETXEN_NIC_GBE:
  300. adapter->enable_phy_interrupts =
  301. netxen_niu_gbe_enable_phy_interrupts;
  302. adapter->disable_phy_interrupts =
  303. netxen_niu_gbe_disable_phy_interrupts;
  304. adapter->macaddr_set = netxen_niu_macaddr_set;
  305. adapter->set_mtu = netxen_nic_set_mtu_gb;
  306. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  307. adapter->phy_read = netxen_niu_gbe_phy_read;
  308. adapter->phy_write = netxen_niu_gbe_phy_write;
  309. adapter->init_port = netxen_niu_gbe_init_port;
  310. adapter->stop_port = netxen_niu_disable_gbe_port;
  311. break;
  312. case NETXEN_NIC_XGBE:
  313. adapter->enable_phy_interrupts =
  314. netxen_niu_xgbe_enable_phy_interrupts;
  315. adapter->disable_phy_interrupts =
  316. netxen_niu_xgbe_disable_phy_interrupts;
  317. adapter->macaddr_set = netxen_niu_xg_macaddr_set;
  318. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  319. adapter->init_port = netxen_niu_xg_init_port;
  320. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  321. adapter->stop_port = netxen_niu_disable_xg_port;
  322. break;
  323. default:
  324. break;
  325. }
  326. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  327. adapter->set_mtu = nx_fw_cmd_set_mtu;
  328. adapter->set_promisc = netxen_p3_nic_set_promisc;
  329. }
  330. }
  331. /*
  332. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  333. * address to external PCI CRB address.
  334. */
  335. static u32 netxen_decode_crb_addr(u32 addr)
  336. {
  337. int i;
  338. u32 base_addr, offset, pci_base;
  339. crb_addr_transform_setup();
  340. pci_base = NETXEN_ADDR_ERROR;
  341. base_addr = addr & 0xfff00000;
  342. offset = addr & 0x000fffff;
  343. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  344. if (crb_addr_xform[i] == base_addr) {
  345. pci_base = i << 20;
  346. break;
  347. }
  348. }
  349. if (pci_base == NETXEN_ADDR_ERROR)
  350. return pci_base;
  351. else
  352. return (pci_base + offset);
  353. }
  354. static long rom_max_timeout = 100;
  355. static long rom_lock_timeout = 10000;
  356. static int rom_lock(struct netxen_adapter *adapter)
  357. {
  358. int iter;
  359. u32 done = 0;
  360. int timeout = 0;
  361. while (!done) {
  362. /* acquire semaphore2 from PCI HW block */
  363. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK),
  364. &done);
  365. if (done == 1)
  366. break;
  367. if (timeout >= rom_lock_timeout)
  368. return -EIO;
  369. timeout++;
  370. /*
  371. * Yield CPU
  372. */
  373. if (!in_atomic())
  374. schedule();
  375. else {
  376. for (iter = 0; iter < 20; iter++)
  377. cpu_relax(); /*This a nop instr on i386 */
  378. }
  379. }
  380. netxen_nic_reg_write(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  381. return 0;
  382. }
  383. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  384. {
  385. long timeout = 0;
  386. long done = 0;
  387. cond_resched();
  388. while (done == 0) {
  389. done = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_GLB_STATUS);
  390. done &= 2;
  391. timeout++;
  392. if (timeout >= rom_max_timeout) {
  393. printk("Timeout reached waiting for rom done");
  394. return -EIO;
  395. }
  396. }
  397. return 0;
  398. }
  399. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  400. {
  401. u32 val;
  402. /* release semaphore2 */
  403. netxen_nic_read_w0(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK), &val);
  404. }
  405. static int do_rom_fast_read(struct netxen_adapter *adapter,
  406. int addr, int *valp)
  407. {
  408. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  409. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  410. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  411. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  412. if (netxen_wait_rom_done(adapter)) {
  413. printk("Error waiting for rom done\n");
  414. return -EIO;
  415. }
  416. /* reset abyte_cnt and dummy_byte_cnt */
  417. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  418. udelay(10);
  419. netxen_nic_reg_write(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  420. *valp = netxen_nic_reg_read(adapter, NETXEN_ROMUSB_ROM_RDATA);
  421. return 0;
  422. }
  423. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  424. u8 *bytes, size_t size)
  425. {
  426. int addridx;
  427. int ret = 0;
  428. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  429. int v;
  430. ret = do_rom_fast_read(adapter, addridx, &v);
  431. if (ret != 0)
  432. break;
  433. *(__le32 *)bytes = cpu_to_le32(v);
  434. bytes += 4;
  435. }
  436. return ret;
  437. }
  438. int
  439. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  440. u8 *bytes, size_t size)
  441. {
  442. int ret;
  443. ret = rom_lock(adapter);
  444. if (ret < 0)
  445. return ret;
  446. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  447. netxen_rom_unlock(adapter);
  448. return ret;
  449. }
  450. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  451. {
  452. int ret;
  453. if (rom_lock(adapter) != 0)
  454. return -EIO;
  455. ret = do_rom_fast_read(adapter, addr, valp);
  456. netxen_rom_unlock(adapter);
  457. return ret;
  458. }
  459. #define NETXEN_BOARDTYPE 0x4008
  460. #define NETXEN_BOARDNUM 0x400c
  461. #define NETXEN_CHIPNUM 0x4010
  462. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  463. {
  464. int addr, val;
  465. int i, n, init_delay = 0;
  466. struct crb_addr_pair *buf;
  467. unsigned offset;
  468. u32 off;
  469. /* resetall */
  470. rom_lock(adapter);
  471. netxen_crb_writelit_adapter(adapter, NETXEN_ROMUSB_GLB_SW_RESET,
  472. 0xffffffff);
  473. netxen_rom_unlock(adapter);
  474. if (verbose) {
  475. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  476. printk("P2 ROM board type: 0x%08x\n", val);
  477. else
  478. printk("Could not read board type\n");
  479. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  480. printk("P2 ROM board num: 0x%08x\n", val);
  481. else
  482. printk("Could not read board number\n");
  483. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  484. printk("P2 ROM chip num: 0x%08x\n", val);
  485. else
  486. printk("Could not read chip number\n");
  487. }
  488. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  489. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  490. (n != 0xcafecafe) ||
  491. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  492. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  493. "n: %08x\n", netxen_nic_driver_name, n);
  494. return -EIO;
  495. }
  496. offset = n & 0xffffU;
  497. n = (n >> 16) & 0xffffU;
  498. } else {
  499. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  500. !(n & 0x80000000)) {
  501. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  502. "n: %08x\n", netxen_nic_driver_name, n);
  503. return -EIO;
  504. }
  505. offset = 1;
  506. n &= ~0x80000000;
  507. }
  508. if (n < 1024) {
  509. if (verbose)
  510. printk(KERN_DEBUG "%s: %d CRB init values found"
  511. " in ROM.\n", netxen_nic_driver_name, n);
  512. } else {
  513. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  514. " initialized.\n", __func__, n);
  515. return -EIO;
  516. }
  517. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  518. if (buf == NULL) {
  519. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  520. netxen_nic_driver_name);
  521. return -ENOMEM;
  522. }
  523. for (i = 0; i < n; i++) {
  524. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  525. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  526. kfree(buf);
  527. return -EIO;
  528. }
  529. buf[i].addr = addr;
  530. buf[i].data = val;
  531. if (verbose)
  532. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  533. netxen_nic_driver_name,
  534. (u32)netxen_decode_crb_addr(addr), val);
  535. }
  536. for (i = 0; i < n; i++) {
  537. off = netxen_decode_crb_addr(buf[i].addr);
  538. if (off == NETXEN_ADDR_ERROR) {
  539. printk(KERN_ERR"CRB init value out of range %x\n",
  540. buf[i].addr);
  541. continue;
  542. }
  543. off += NETXEN_PCI_CRBSPACE;
  544. /* skipping cold reboot MAGIC */
  545. if (off == NETXEN_CAM_RAM(0x1fc))
  546. continue;
  547. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  548. /* do not reset PCI */
  549. if (off == (ROMUSB_GLB + 0xbc))
  550. continue;
  551. if (off == (ROMUSB_GLB + 0xa8))
  552. continue;
  553. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  554. continue;
  555. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  556. continue;
  557. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  558. continue;
  559. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  560. buf[i].data = 0x1020;
  561. /* skip the function enable register */
  562. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  563. continue;
  564. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  565. continue;
  566. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  567. continue;
  568. }
  569. if (off == NETXEN_ADDR_ERROR) {
  570. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  571. netxen_nic_driver_name, buf[i].addr);
  572. continue;
  573. }
  574. init_delay = 1;
  575. /* After writing this register, HW needs time for CRB */
  576. /* to quiet down (else crb_window returns 0xffffffff) */
  577. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  578. init_delay = 1000;
  579. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  580. /* hold xdma in reset also */
  581. buf[i].data = NETXEN_NIC_XDMA_RESET;
  582. buf[i].data = 0x8000ff;
  583. }
  584. }
  585. adapter->hw_write_wx(adapter, off, &buf[i].data, 4);
  586. msleep(init_delay);
  587. }
  588. kfree(buf);
  589. /* disable_peg_cache_all */
  590. /* unreset_net_cache */
  591. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  592. adapter->hw_read_wx(adapter,
  593. NETXEN_ROMUSB_GLB_SW_RESET, &val, 4);
  594. netxen_crb_writelit_adapter(adapter,
  595. NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  596. }
  597. /* p2dn replyCount */
  598. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  599. /* disable_peg_cache 0 */
  600. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  601. /* disable_peg_cache 1 */
  602. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  603. /* peg_clr_all */
  604. /* peg_clr 0 */
  605. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  606. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  607. /* peg_clr 1 */
  608. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  609. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  610. /* peg_clr 2 */
  611. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  612. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  613. /* peg_clr 3 */
  614. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  615. netxen_crb_writelit_adapter(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  616. return 0;
  617. }
  618. int netxen_initialize_adapter_offload(struct netxen_adapter *adapter)
  619. {
  620. uint64_t addr;
  621. uint32_t hi;
  622. uint32_t lo;
  623. adapter->dummy_dma.addr =
  624. pci_alloc_consistent(adapter->pdev,
  625. NETXEN_HOST_DUMMY_DMA_SIZE,
  626. &adapter->dummy_dma.phys_addr);
  627. if (adapter->dummy_dma.addr == NULL) {
  628. printk("%s: ERROR: Could not allocate dummy DMA memory\n",
  629. __func__);
  630. return -ENOMEM;
  631. }
  632. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  633. hi = (addr >> 32) & 0xffffffff;
  634. lo = addr & 0xffffffff;
  635. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  636. adapter->pci_write_normalize(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  637. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  638. uint32_t temp = 0;
  639. adapter->hw_write_wx(adapter, CRB_HOST_DUMMY_BUF, &temp, 4);
  640. }
  641. return 0;
  642. }
  643. void netxen_free_adapter_offload(struct netxen_adapter *adapter)
  644. {
  645. int i = 100;
  646. if (!adapter->dummy_dma.addr)
  647. return;
  648. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  649. do {
  650. if (dma_watchdog_shutdown_request(adapter) == 1)
  651. break;
  652. msleep(50);
  653. if (dma_watchdog_shutdown_poll_result(adapter) == 1)
  654. break;
  655. } while (--i);
  656. }
  657. if (i) {
  658. pci_free_consistent(adapter->pdev,
  659. NETXEN_HOST_DUMMY_DMA_SIZE,
  660. adapter->dummy_dma.addr,
  661. adapter->dummy_dma.phys_addr);
  662. adapter->dummy_dma.addr = NULL;
  663. } else {
  664. printk(KERN_ERR "%s: dma_watchdog_shutdown failed\n",
  665. adapter->netdev->name);
  666. }
  667. }
  668. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  669. {
  670. u32 val = 0;
  671. int retries = 60;
  672. if (!pegtune_val) {
  673. do {
  674. val = adapter->pci_read_normalize(adapter,
  675. CRB_CMDPEG_STATE);
  676. if (val == PHAN_INITIALIZE_COMPLETE ||
  677. val == PHAN_INITIALIZE_ACK)
  678. return 0;
  679. msleep(500);
  680. } while (--retries);
  681. if (!retries) {
  682. pegtune_val = adapter->pci_read_normalize(adapter,
  683. NETXEN_ROMUSB_GLB_PEGTUNE_DONE);
  684. printk(KERN_WARNING "netxen_phantom_init: init failed, "
  685. "pegtune_val=%x\n", pegtune_val);
  686. return -1;
  687. }
  688. }
  689. return 0;
  690. }
  691. int netxen_receive_peg_ready(struct netxen_adapter *adapter)
  692. {
  693. u32 val = 0;
  694. int retries = 2000;
  695. do {
  696. val = adapter->pci_read_normalize(adapter, CRB_RCVPEG_STATE);
  697. if (val == PHAN_PEG_RCV_INITIALIZED)
  698. return 0;
  699. msleep(10);
  700. } while (--retries);
  701. if (!retries) {
  702. printk(KERN_ERR "Receive Peg initialization not "
  703. "complete, state: 0x%x.\n", val);
  704. return -EIO;
  705. }
  706. return 0;
  707. }
  708. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  709. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  710. {
  711. struct netxen_rx_buffer *buffer;
  712. struct sk_buff *skb;
  713. buffer = &rds_ring->rx_buf_arr[index];
  714. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  715. PCI_DMA_FROMDEVICE);
  716. skb = buffer->skb;
  717. if (!skb)
  718. goto no_skb;
  719. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  720. adapter->stats.csummed++;
  721. skb->ip_summed = CHECKSUM_UNNECESSARY;
  722. } else
  723. skb->ip_summed = CHECKSUM_NONE;
  724. skb->dev = adapter->netdev;
  725. buffer->skb = NULL;
  726. no_skb:
  727. buffer->state = NETXEN_BUFFER_FREE;
  728. buffer->lro_current_frags = 0;
  729. buffer->lro_expected_frags = 0;
  730. list_add_tail(&buffer->list, &rds_ring->free_list);
  731. return skb;
  732. }
  733. /*
  734. * netxen_process_rcv() send the received packet to the protocol stack.
  735. * and if the number of receives exceeds RX_BUFFERS_REFILL, then we
  736. * invoke the routine to send more rx buffers to the Phantom...
  737. */
  738. static void netxen_process_rcv(struct netxen_adapter *adapter, int ctxid,
  739. struct status_desc *desc, struct status_desc *frag_desc)
  740. {
  741. struct net_device *netdev = adapter->netdev;
  742. u64 sts_data = le64_to_cpu(desc->status_desc_data);
  743. int index = netxen_get_sts_refhandle(sts_data);
  744. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  745. struct netxen_rx_buffer *buffer;
  746. struct sk_buff *skb;
  747. u32 length = netxen_get_sts_totallength(sts_data);
  748. u32 desc_ctx;
  749. u16 pkt_offset = 0, cksum;
  750. struct nx_host_rds_ring *rds_ring;
  751. desc_ctx = netxen_get_sts_type(sts_data);
  752. if (unlikely(desc_ctx >= NUM_RCV_DESC_RINGS)) {
  753. printk("%s: %s Bad Rcv descriptor ring\n",
  754. netxen_nic_driver_name, netdev->name);
  755. return;
  756. }
  757. rds_ring = &recv_ctx->rds_rings[desc_ctx];
  758. if (unlikely(index > rds_ring->max_rx_desc_count)) {
  759. DPRINTK(ERR, "Got a buffer index:%x Max is %x\n",
  760. index, rds_ring->max_rx_desc_count);
  761. return;
  762. }
  763. buffer = &rds_ring->rx_buf_arr[index];
  764. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  765. buffer->lro_current_frags++;
  766. if (netxen_get_sts_desc_lro_last_frag(desc)) {
  767. buffer->lro_expected_frags =
  768. netxen_get_sts_desc_lro_cnt(desc);
  769. buffer->lro_length = length;
  770. }
  771. if (buffer->lro_current_frags != buffer->lro_expected_frags) {
  772. if (buffer->lro_expected_frags != 0) {
  773. printk("LRO: (refhandle:%x) recv frag. "
  774. "wait for last. flags: %x expected:%d "
  775. "have:%d\n", index,
  776. netxen_get_sts_desc_lro_last_frag(desc),
  777. buffer->lro_expected_frags,
  778. buffer->lro_current_frags);
  779. }
  780. return;
  781. }
  782. }
  783. cksum = netxen_get_sts_status(sts_data);
  784. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  785. if (!skb)
  786. return;
  787. if (desc_ctx == RCV_DESC_LRO_CTXID) {
  788. /* True length was only available on the last pkt */
  789. skb_put(skb, buffer->lro_length);
  790. } else {
  791. if (length > rds_ring->skb_size)
  792. skb_put(skb, rds_ring->skb_size);
  793. else
  794. skb_put(skb, length);
  795. pkt_offset = netxen_get_sts_pkt_offset(sts_data);
  796. if (pkt_offset)
  797. skb_pull(skb, pkt_offset);
  798. }
  799. skb->protocol = eth_type_trans(skb, netdev);
  800. /*
  801. * rx buffer chaining is disabled, walk and free
  802. * any spurious rx buffer chain.
  803. */
  804. if (frag_desc) {
  805. u16 i, nr_frags = desc->nr_frags;
  806. dev_kfree_skb_any(skb);
  807. for (i = 0; i < nr_frags; i++) {
  808. index = le16_to_cpu(frag_desc->frag_handles[i]);
  809. skb = netxen_process_rxbuf(adapter,
  810. rds_ring, index, cksum);
  811. if (skb)
  812. dev_kfree_skb_any(skb);
  813. }
  814. adapter->stats.rxdropped++;
  815. } else {
  816. netif_receive_skb(skb);
  817. adapter->stats.no_rcv++;
  818. adapter->stats.rxbytes += length;
  819. }
  820. }
  821. /* Process Receive status ring */
  822. u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctxid, int max)
  823. {
  824. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctxid]);
  825. struct status_desc *desc_head = recv_ctx->rcv_status_desc_head;
  826. struct status_desc *desc, *frag_desc;
  827. u32 consumer = recv_ctx->status_rx_consumer;
  828. int count = 0, ring;
  829. u64 sts_data;
  830. u16 opcode;
  831. while (count < max) {
  832. desc = &desc_head[consumer];
  833. if (!(netxen_get_sts_owner(desc) & STATUS_OWNER_HOST)) {
  834. DPRINTK(ERR, "desc %p ownedby %x\n", desc,
  835. netxen_get_sts_owner(desc));
  836. break;
  837. }
  838. sts_data = le64_to_cpu(desc->status_desc_data);
  839. opcode = netxen_get_sts_opcode(sts_data);
  840. frag_desc = NULL;
  841. if (opcode == NETXEN_NIC_RXPKT_DESC) {
  842. if (desc->nr_frags) {
  843. consumer = get_next_index(consumer,
  844. adapter->max_rx_desc_count);
  845. frag_desc = &desc_head[consumer];
  846. netxen_set_sts_owner(frag_desc,
  847. STATUS_OWNER_PHANTOM);
  848. }
  849. }
  850. netxen_process_rcv(adapter, ctxid, desc, frag_desc);
  851. netxen_set_sts_owner(desc, STATUS_OWNER_PHANTOM);
  852. consumer = get_next_index(consumer,
  853. adapter->max_rx_desc_count);
  854. count++;
  855. }
  856. for (ring = 0; ring < adapter->max_rds_rings; ring++)
  857. netxen_post_rx_buffers_nodb(adapter, ctxid, ring);
  858. /* update the consumer index in phantom */
  859. if (count) {
  860. recv_ctx->status_rx_consumer = consumer;
  861. /* Window = 1 */
  862. adapter->pci_write_normalize(adapter,
  863. recv_ctx->crb_sts_consumer, consumer);
  864. }
  865. return count;
  866. }
  867. /* Process Command status ring */
  868. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  869. {
  870. u32 last_consumer, consumer;
  871. int count = 0, i;
  872. struct netxen_cmd_buffer *buffer;
  873. struct pci_dev *pdev = adapter->pdev;
  874. struct net_device *netdev = adapter->netdev;
  875. struct netxen_skb_frag *frag;
  876. int done = 0;
  877. last_consumer = adapter->last_cmd_consumer;
  878. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  879. while (last_consumer != consumer) {
  880. buffer = &adapter->cmd_buf_arr[last_consumer];
  881. if (buffer->skb) {
  882. frag = &buffer->frag_array[0];
  883. pci_unmap_single(pdev, frag->dma, frag->length,
  884. PCI_DMA_TODEVICE);
  885. frag->dma = 0ULL;
  886. for (i = 1; i < buffer->frag_count; i++) {
  887. frag++; /* Get the next frag */
  888. pci_unmap_page(pdev, frag->dma, frag->length,
  889. PCI_DMA_TODEVICE);
  890. frag->dma = 0ULL;
  891. }
  892. adapter->stats.xmitfinished++;
  893. dev_kfree_skb_any(buffer->skb);
  894. buffer->skb = NULL;
  895. }
  896. last_consumer = get_next_index(last_consumer,
  897. adapter->max_tx_desc_count);
  898. if (++count >= MAX_STATUS_HANDLE)
  899. break;
  900. }
  901. if (count) {
  902. adapter->last_cmd_consumer = last_consumer;
  903. smp_mb();
  904. if (netif_queue_stopped(netdev) && netif_running(netdev)) {
  905. netif_tx_lock(netdev);
  906. netif_wake_queue(netdev);
  907. smp_mb();
  908. netif_tx_unlock(netdev);
  909. }
  910. }
  911. /*
  912. * If everything is freed up to consumer then check if the ring is full
  913. * If the ring is full then check if more needs to be freed and
  914. * schedule the call back again.
  915. *
  916. * This happens when there are 2 CPUs. One could be freeing and the
  917. * other filling it. If the ring is full when we get out of here and
  918. * the card has already interrupted the host then the host can miss the
  919. * interrupt.
  920. *
  921. * There is still a possible race condition and the host could miss an
  922. * interrupt. The card has to take care of this.
  923. */
  924. consumer = le32_to_cpu(*(adapter->cmd_consumer));
  925. done = (last_consumer == consumer);
  926. return (done);
  927. }
  928. /*
  929. * netxen_post_rx_buffers puts buffer in the Phantom memory
  930. */
  931. void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx, u32 ringid)
  932. {
  933. struct pci_dev *pdev = adapter->pdev;
  934. struct sk_buff *skb;
  935. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  936. struct nx_host_rds_ring *rds_ring = NULL;
  937. uint producer;
  938. struct rcv_desc *pdesc;
  939. struct netxen_rx_buffer *buffer;
  940. int count = 0;
  941. netxen_ctx_msg msg = 0;
  942. dma_addr_t dma;
  943. struct list_head *head;
  944. rds_ring = &recv_ctx->rds_rings[ringid];
  945. producer = rds_ring->producer;
  946. head = &rds_ring->free_list;
  947. /* We can start writing rx descriptors into the phantom memory. */
  948. while (!list_empty(head)) {
  949. skb = dev_alloc_skb(rds_ring->skb_size);
  950. if (unlikely(!skb)) {
  951. break;
  952. }
  953. if (!adapter->ahw.cut_through)
  954. skb_reserve(skb, 2);
  955. dma = pci_map_single(pdev, skb->data,
  956. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  957. if (pci_dma_mapping_error(pdev, dma)) {
  958. dev_kfree_skb_any(skb);
  959. break;
  960. }
  961. count++;
  962. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  963. list_del(&buffer->list);
  964. buffer->skb = skb;
  965. buffer->state = NETXEN_BUFFER_BUSY;
  966. buffer->dma = dma;
  967. /* make a rcv descriptor */
  968. pdesc = &rds_ring->desc_head[producer];
  969. pdesc->addr_buffer = cpu_to_le64(dma);
  970. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  971. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  972. producer = get_next_index(producer, rds_ring->max_rx_desc_count);
  973. }
  974. /* if we did allocate buffers, then write the count to Phantom */
  975. if (count) {
  976. rds_ring->producer = producer;
  977. /* Window = 1 */
  978. adapter->pci_write_normalize(adapter,
  979. rds_ring->crb_rcv_producer,
  980. (producer-1) & (rds_ring->max_rx_desc_count-1));
  981. if (adapter->fw_major < 4) {
  982. /*
  983. * Write a doorbell msg to tell phanmon of change in
  984. * receive ring producer
  985. * Only for firmware version < 4.0.0
  986. */
  987. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  988. netxen_set_msg_privid(msg);
  989. netxen_set_msg_count(msg,
  990. ((producer -
  991. 1) & (rds_ring->
  992. max_rx_desc_count - 1)));
  993. netxen_set_msg_ctxid(msg, adapter->portnum);
  994. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  995. writel(msg,
  996. DB_NORMALIZE(adapter,
  997. NETXEN_RCV_PRODUCER_OFFSET));
  998. }
  999. }
  1000. }
  1001. static void netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1002. uint32_t ctx, uint32_t ringid)
  1003. {
  1004. struct pci_dev *pdev = adapter->pdev;
  1005. struct sk_buff *skb;
  1006. struct netxen_recv_context *recv_ctx = &(adapter->recv_ctx[ctx]);
  1007. struct nx_host_rds_ring *rds_ring = NULL;
  1008. u32 producer;
  1009. struct rcv_desc *pdesc;
  1010. struct netxen_rx_buffer *buffer;
  1011. int count = 0;
  1012. struct list_head *head;
  1013. dma_addr_t dma;
  1014. rds_ring = &recv_ctx->rds_rings[ringid];
  1015. producer = rds_ring->producer;
  1016. head = &rds_ring->free_list;
  1017. /* We can start writing rx descriptors into the phantom memory. */
  1018. while (!list_empty(head)) {
  1019. skb = dev_alloc_skb(rds_ring->skb_size);
  1020. if (unlikely(!skb)) {
  1021. break;
  1022. }
  1023. if (!adapter->ahw.cut_through)
  1024. skb_reserve(skb, 2);
  1025. dma = pci_map_single(pdev, skb->data,
  1026. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1027. if (pci_dma_mapping_error(pdev, dma)) {
  1028. dev_kfree_skb_any(skb);
  1029. break;
  1030. }
  1031. count++;
  1032. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1033. list_del(&buffer->list);
  1034. buffer->skb = skb;
  1035. buffer->state = NETXEN_BUFFER_BUSY;
  1036. buffer->dma = dma;
  1037. /* make a rcv descriptor */
  1038. pdesc = &rds_ring->desc_head[producer];
  1039. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1040. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1041. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1042. producer = get_next_index(producer, rds_ring->max_rx_desc_count);
  1043. }
  1044. /* if we did allocate buffers, then write the count to Phantom */
  1045. if (count) {
  1046. rds_ring->producer = producer;
  1047. /* Window = 1 */
  1048. adapter->pci_write_normalize(adapter,
  1049. rds_ring->crb_rcv_producer,
  1050. (producer-1) & (rds_ring->max_rx_desc_count-1));
  1051. wmb();
  1052. }
  1053. }
  1054. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1055. {
  1056. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1057. return;
  1058. }