ad5064.c 13 KB

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  1. /*
  2. * AD5024, AD5025, AD5044, AD5045, AD5064, AD5064-1, AD5065, AD5628, AD5648,
  3. * AD5666, AD5668 Digital to analog converters driver
  4. *
  5. * Copyright 2011 Analog Devices Inc.
  6. *
  7. * Licensed under the GPL-2.
  8. */
  9. #include <linux/device.h>
  10. #include <linux/err.h>
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/spi/spi.h>
  14. #include <linux/slab.h>
  15. #include <linux/sysfs.h>
  16. #include <linux/regulator/consumer.h>
  17. #include <linux/iio/iio.h>
  18. #include <linux/iio/sysfs.h>
  19. #define AD5064_MAX_DAC_CHANNELS 8
  20. #define AD5064_MAX_VREFS 4
  21. #define AD5064_ADDR(x) ((x) << 20)
  22. #define AD5064_CMD(x) ((x) << 24)
  23. #define AD5064_ADDR_DAC(chan) (chan)
  24. #define AD5064_ADDR_ALL_DAC 0xF
  25. #define AD5064_CMD_WRITE_INPUT_N 0x0
  26. #define AD5064_CMD_UPDATE_DAC_N 0x1
  27. #define AD5064_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2
  28. #define AD5064_CMD_WRITE_INPUT_N_UPDATE_N 0x3
  29. #define AD5064_CMD_POWERDOWN_DAC 0x4
  30. #define AD5064_CMD_CLEAR 0x5
  31. #define AD5064_CMD_LDAC_MASK 0x6
  32. #define AD5064_CMD_RESET 0x7
  33. #define AD5064_CMD_CONFIG 0x8
  34. #define AD5064_CONFIG_DAISY_CHAIN_ENABLE BIT(1)
  35. #define AD5064_CONFIG_INT_VREF_ENABLE BIT(0)
  36. #define AD5064_LDAC_PWRDN_NONE 0x0
  37. #define AD5064_LDAC_PWRDN_1K 0x1
  38. #define AD5064_LDAC_PWRDN_100K 0x2
  39. #define AD5064_LDAC_PWRDN_3STATE 0x3
  40. /**
  41. * struct ad5064_chip_info - chip specific information
  42. * @shared_vref: whether the vref supply is shared between channels
  43. * @internal_vref: internal reference voltage. 0 if the chip has no internal
  44. * vref.
  45. * @channel: channel specification
  46. * @num_channels: number of channels
  47. */
  48. struct ad5064_chip_info {
  49. bool shared_vref;
  50. unsigned long internal_vref;
  51. const struct iio_chan_spec *channels;
  52. unsigned int num_channels;
  53. };
  54. /**
  55. * struct ad5064_state - driver instance specific data
  56. * @spi: spi_device
  57. * @chip_info: chip model specific constants, available modes etc
  58. * @vref_reg: vref supply regulators
  59. * @pwr_down: whether channel is powered down
  60. * @pwr_down_mode: channel's current power down mode
  61. * @dac_cache: current DAC raw value (chip does not support readback)
  62. * @use_internal_vref: set to true if the internal reference voltage should be
  63. * used.
  64. * @data: spi transfer buffers
  65. */
  66. struct ad5064_state {
  67. struct spi_device *spi;
  68. const struct ad5064_chip_info *chip_info;
  69. struct regulator_bulk_data vref_reg[AD5064_MAX_VREFS];
  70. bool pwr_down[AD5064_MAX_DAC_CHANNELS];
  71. u8 pwr_down_mode[AD5064_MAX_DAC_CHANNELS];
  72. unsigned int dac_cache[AD5064_MAX_DAC_CHANNELS];
  73. bool use_internal_vref;
  74. /*
  75. * DMA (thus cache coherency maintenance) requires the
  76. * transfer buffers to live in their own cache lines.
  77. */
  78. __be32 data ____cacheline_aligned;
  79. };
  80. enum ad5064_type {
  81. ID_AD5024,
  82. ID_AD5025,
  83. ID_AD5044,
  84. ID_AD5045,
  85. ID_AD5064,
  86. ID_AD5064_1,
  87. ID_AD5065,
  88. ID_AD5628_1,
  89. ID_AD5628_2,
  90. ID_AD5648_1,
  91. ID_AD5648_2,
  92. ID_AD5666_1,
  93. ID_AD5666_2,
  94. ID_AD5668_1,
  95. ID_AD5668_2,
  96. };
  97. static int ad5064_spi_write(struct ad5064_state *st, unsigned int cmd,
  98. unsigned int addr, unsigned int val, unsigned int shift)
  99. {
  100. val <<= shift;
  101. st->data = cpu_to_be32(AD5064_CMD(cmd) | AD5064_ADDR(addr) | val);
  102. return spi_write(st->spi, &st->data, sizeof(st->data));
  103. }
  104. static int ad5064_sync_powerdown_mode(struct ad5064_state *st,
  105. unsigned int channel)
  106. {
  107. unsigned int val;
  108. int ret;
  109. val = (0x1 << channel);
  110. if (st->pwr_down[channel])
  111. val |= st->pwr_down_mode[channel] << 8;
  112. ret = ad5064_spi_write(st, AD5064_CMD_POWERDOWN_DAC, 0, val, 0);
  113. return ret;
  114. }
  115. static const char * const ad5064_powerdown_modes[] = {
  116. "1kohm_to_gnd",
  117. "100kohm_to_gnd",
  118. "three_state",
  119. };
  120. static int ad5064_get_powerdown_mode(struct iio_dev *indio_dev,
  121. const struct iio_chan_spec *chan)
  122. {
  123. struct ad5064_state *st = iio_priv(indio_dev);
  124. return st->pwr_down_mode[chan->channel] - 1;
  125. }
  126. static int ad5064_set_powerdown_mode(struct iio_dev *indio_dev,
  127. const struct iio_chan_spec *chan, unsigned int mode)
  128. {
  129. struct ad5064_state *st = iio_priv(indio_dev);
  130. int ret;
  131. mutex_lock(&indio_dev->mlock);
  132. st->pwr_down_mode[chan->channel] = mode + 1;
  133. ret = ad5064_sync_powerdown_mode(st, chan->channel);
  134. mutex_unlock(&indio_dev->mlock);
  135. return ret;
  136. }
  137. static const struct iio_enum ad5064_powerdown_mode_enum = {
  138. .items = ad5064_powerdown_modes,
  139. .num_items = ARRAY_SIZE(ad5064_powerdown_modes),
  140. .get = ad5064_get_powerdown_mode,
  141. .set = ad5064_set_powerdown_mode,
  142. };
  143. static ssize_t ad5064_read_dac_powerdown(struct iio_dev *indio_dev,
  144. uintptr_t private, const struct iio_chan_spec *chan, char *buf)
  145. {
  146. struct ad5064_state *st = iio_priv(indio_dev);
  147. return sprintf(buf, "%d\n", st->pwr_down[chan->channel]);
  148. }
  149. static ssize_t ad5064_write_dac_powerdown(struct iio_dev *indio_dev,
  150. uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
  151. size_t len)
  152. {
  153. struct ad5064_state *st = iio_priv(indio_dev);
  154. bool pwr_down;
  155. int ret;
  156. ret = strtobool(buf, &pwr_down);
  157. if (ret)
  158. return ret;
  159. mutex_lock(&indio_dev->mlock);
  160. st->pwr_down[chan->channel] = pwr_down;
  161. ret = ad5064_sync_powerdown_mode(st, chan->channel);
  162. mutex_unlock(&indio_dev->mlock);
  163. return ret ? ret : len;
  164. }
  165. static int ad5064_get_vref(struct ad5064_state *st,
  166. struct iio_chan_spec const *chan)
  167. {
  168. unsigned int i;
  169. if (st->use_internal_vref)
  170. return st->chip_info->internal_vref;
  171. i = st->chip_info->shared_vref ? 0 : chan->channel;
  172. return regulator_get_voltage(st->vref_reg[i].consumer);
  173. }
  174. static int ad5064_read_raw(struct iio_dev *indio_dev,
  175. struct iio_chan_spec const *chan,
  176. int *val,
  177. int *val2,
  178. long m)
  179. {
  180. struct ad5064_state *st = iio_priv(indio_dev);
  181. int scale_uv;
  182. switch (m) {
  183. case IIO_CHAN_INFO_RAW:
  184. *val = st->dac_cache[chan->channel];
  185. return IIO_VAL_INT;
  186. case IIO_CHAN_INFO_SCALE:
  187. scale_uv = ad5064_get_vref(st, chan);
  188. if (scale_uv < 0)
  189. return scale_uv;
  190. scale_uv = (scale_uv * 100) >> chan->scan_type.realbits;
  191. *val = scale_uv / 100000;
  192. *val2 = (scale_uv % 100000) * 10;
  193. return IIO_VAL_INT_PLUS_MICRO;
  194. default:
  195. break;
  196. }
  197. return -EINVAL;
  198. }
  199. static int ad5064_write_raw(struct iio_dev *indio_dev,
  200. struct iio_chan_spec const *chan, int val, int val2, long mask)
  201. {
  202. struct ad5064_state *st = iio_priv(indio_dev);
  203. int ret;
  204. switch (mask) {
  205. case IIO_CHAN_INFO_RAW:
  206. if (val > (1 << chan->scan_type.realbits) || val < 0)
  207. return -EINVAL;
  208. mutex_lock(&indio_dev->mlock);
  209. ret = ad5064_spi_write(st, AD5064_CMD_WRITE_INPUT_N_UPDATE_N,
  210. chan->address, val, chan->scan_type.shift);
  211. if (ret == 0)
  212. st->dac_cache[chan->channel] = val;
  213. mutex_unlock(&indio_dev->mlock);
  214. break;
  215. default:
  216. ret = -EINVAL;
  217. }
  218. return ret;
  219. }
  220. static const struct iio_info ad5064_info = {
  221. .read_raw = ad5064_read_raw,
  222. .write_raw = ad5064_write_raw,
  223. .driver_module = THIS_MODULE,
  224. };
  225. static const struct iio_chan_spec_ext_info ad5064_ext_info[] = {
  226. {
  227. .name = "powerdown",
  228. .read = ad5064_read_dac_powerdown,
  229. .write = ad5064_write_dac_powerdown,
  230. },
  231. IIO_ENUM("powerdown_mode", false, &ad5064_powerdown_mode_enum),
  232. IIO_ENUM_AVAILABLE("powerdown_mode", &ad5064_powerdown_mode_enum),
  233. { },
  234. };
  235. #define AD5064_CHANNEL(chan, bits) { \
  236. .type = IIO_VOLTAGE, \
  237. .indexed = 1, \
  238. .output = 1, \
  239. .channel = (chan), \
  240. .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \
  241. IIO_CHAN_INFO_SCALE_SEPARATE_BIT, \
  242. .address = AD5064_ADDR_DAC(chan), \
  243. .scan_type = IIO_ST('u', (bits), 16, 20 - (bits)), \
  244. .ext_info = ad5064_ext_info, \
  245. }
  246. #define DECLARE_AD5064_CHANNELS(name, bits) \
  247. const struct iio_chan_spec name[] = { \
  248. AD5064_CHANNEL(0, bits), \
  249. AD5064_CHANNEL(1, bits), \
  250. AD5064_CHANNEL(2, bits), \
  251. AD5064_CHANNEL(3, bits), \
  252. AD5064_CHANNEL(4, bits), \
  253. AD5064_CHANNEL(5, bits), \
  254. AD5064_CHANNEL(6, bits), \
  255. AD5064_CHANNEL(7, bits), \
  256. }
  257. static DECLARE_AD5064_CHANNELS(ad5024_channels, 12);
  258. static DECLARE_AD5064_CHANNELS(ad5044_channels, 14);
  259. static DECLARE_AD5064_CHANNELS(ad5064_channels, 16);
  260. static const struct ad5064_chip_info ad5064_chip_info_tbl[] = {
  261. [ID_AD5024] = {
  262. .shared_vref = false,
  263. .channels = ad5024_channels,
  264. .num_channels = 4,
  265. },
  266. [ID_AD5025] = {
  267. .shared_vref = false,
  268. .channels = ad5024_channels,
  269. .num_channels = 2,
  270. },
  271. [ID_AD5044] = {
  272. .shared_vref = false,
  273. .channels = ad5044_channels,
  274. .num_channels = 4,
  275. },
  276. [ID_AD5045] = {
  277. .shared_vref = false,
  278. .channels = ad5044_channels,
  279. .num_channels = 2,
  280. },
  281. [ID_AD5064] = {
  282. .shared_vref = false,
  283. .channels = ad5064_channels,
  284. .num_channels = 4,
  285. },
  286. [ID_AD5064_1] = {
  287. .shared_vref = true,
  288. .channels = ad5064_channels,
  289. .num_channels = 4,
  290. },
  291. [ID_AD5065] = {
  292. .shared_vref = false,
  293. .channels = ad5064_channels,
  294. .num_channels = 2,
  295. },
  296. [ID_AD5628_1] = {
  297. .shared_vref = true,
  298. .internal_vref = 2500000,
  299. .channels = ad5024_channels,
  300. .num_channels = 8,
  301. },
  302. [ID_AD5628_2] = {
  303. .shared_vref = true,
  304. .internal_vref = 5000000,
  305. .channels = ad5024_channels,
  306. .num_channels = 8,
  307. },
  308. [ID_AD5648_1] = {
  309. .shared_vref = true,
  310. .internal_vref = 2500000,
  311. .channels = ad5044_channels,
  312. .num_channels = 8,
  313. },
  314. [ID_AD5648_2] = {
  315. .shared_vref = true,
  316. .internal_vref = 5000000,
  317. .channels = ad5044_channels,
  318. .num_channels = 8,
  319. },
  320. [ID_AD5666_1] = {
  321. .shared_vref = true,
  322. .internal_vref = 2500000,
  323. .channels = ad5064_channels,
  324. .num_channels = 4,
  325. },
  326. [ID_AD5666_2] = {
  327. .shared_vref = true,
  328. .internal_vref = 5000000,
  329. .channels = ad5064_channels,
  330. .num_channels = 4,
  331. },
  332. [ID_AD5668_1] = {
  333. .shared_vref = true,
  334. .internal_vref = 2500000,
  335. .channels = ad5064_channels,
  336. .num_channels = 8,
  337. },
  338. [ID_AD5668_2] = {
  339. .shared_vref = true,
  340. .internal_vref = 5000000,
  341. .channels = ad5064_channels,
  342. .num_channels = 8,
  343. },
  344. };
  345. static inline unsigned int ad5064_num_vref(struct ad5064_state *st)
  346. {
  347. return st->chip_info->shared_vref ? 1 : st->chip_info->num_channels;
  348. }
  349. static const char * const ad5064_vref_names[] = {
  350. "vrefA",
  351. "vrefB",
  352. "vrefC",
  353. "vrefD",
  354. };
  355. static const char * const ad5064_vref_name(struct ad5064_state *st,
  356. unsigned int vref)
  357. {
  358. return st->chip_info->shared_vref ? "vref" : ad5064_vref_names[vref];
  359. }
  360. static int __devinit ad5064_probe(struct spi_device *spi)
  361. {
  362. enum ad5064_type type = spi_get_device_id(spi)->driver_data;
  363. struct iio_dev *indio_dev;
  364. struct ad5064_state *st;
  365. unsigned int i;
  366. int ret;
  367. indio_dev = iio_device_alloc(sizeof(*st));
  368. if (indio_dev == NULL)
  369. return -ENOMEM;
  370. st = iio_priv(indio_dev);
  371. spi_set_drvdata(spi, indio_dev);
  372. st->chip_info = &ad5064_chip_info_tbl[type];
  373. st->spi = spi;
  374. for (i = 0; i < ad5064_num_vref(st); ++i)
  375. st->vref_reg[i].supply = ad5064_vref_name(st, i);
  376. ret = regulator_bulk_get(&st->spi->dev, ad5064_num_vref(st),
  377. st->vref_reg);
  378. if (ret) {
  379. if (!st->chip_info->internal_vref)
  380. goto error_free;
  381. st->use_internal_vref = true;
  382. ret = ad5064_spi_write(st, AD5064_CMD_CONFIG, 0,
  383. AD5064_CONFIG_INT_VREF_ENABLE, 0);
  384. if (ret) {
  385. dev_err(&spi->dev, "Failed to enable internal vref: %d\n",
  386. ret);
  387. goto error_free;
  388. }
  389. } else {
  390. ret = regulator_bulk_enable(ad5064_num_vref(st), st->vref_reg);
  391. if (ret)
  392. goto error_free_reg;
  393. }
  394. for (i = 0; i < st->chip_info->num_channels; ++i) {
  395. st->pwr_down_mode[i] = AD5064_LDAC_PWRDN_1K;
  396. st->dac_cache[i] = 0x8000;
  397. }
  398. indio_dev->dev.parent = &spi->dev;
  399. indio_dev->name = spi_get_device_id(spi)->name;
  400. indio_dev->info = &ad5064_info;
  401. indio_dev->modes = INDIO_DIRECT_MODE;
  402. indio_dev->channels = st->chip_info->channels;
  403. indio_dev->num_channels = st->chip_info->num_channels;
  404. ret = iio_device_register(indio_dev);
  405. if (ret)
  406. goto error_disable_reg;
  407. return 0;
  408. error_disable_reg:
  409. if (!st->use_internal_vref)
  410. regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
  411. error_free_reg:
  412. if (!st->use_internal_vref)
  413. regulator_bulk_free(ad5064_num_vref(st), st->vref_reg);
  414. error_free:
  415. iio_device_free(indio_dev);
  416. return ret;
  417. }
  418. static int __devexit ad5064_remove(struct spi_device *spi)
  419. {
  420. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  421. struct ad5064_state *st = iio_priv(indio_dev);
  422. iio_device_unregister(indio_dev);
  423. if (!st->use_internal_vref) {
  424. regulator_bulk_disable(ad5064_num_vref(st), st->vref_reg);
  425. regulator_bulk_free(ad5064_num_vref(st), st->vref_reg);
  426. }
  427. iio_device_free(indio_dev);
  428. return 0;
  429. }
  430. static const struct spi_device_id ad5064_id[] = {
  431. {"ad5024", ID_AD5024},
  432. {"ad5025", ID_AD5025},
  433. {"ad5044", ID_AD5044},
  434. {"ad5045", ID_AD5045},
  435. {"ad5064", ID_AD5064},
  436. {"ad5064-1", ID_AD5064_1},
  437. {"ad5065", ID_AD5065},
  438. {"ad5628-1", ID_AD5628_1},
  439. {"ad5628-2", ID_AD5628_2},
  440. {"ad5648-1", ID_AD5648_1},
  441. {"ad5648-2", ID_AD5648_2},
  442. {"ad5666-1", ID_AD5666_1},
  443. {"ad5666-2", ID_AD5666_2},
  444. {"ad5668-1", ID_AD5668_1},
  445. {"ad5668-2", ID_AD5668_2},
  446. {"ad5668-3", ID_AD5668_2}, /* similar enough to ad5668-2 */
  447. {}
  448. };
  449. MODULE_DEVICE_TABLE(spi, ad5064_id);
  450. static struct spi_driver ad5064_driver = {
  451. .driver = {
  452. .name = "ad5064",
  453. .owner = THIS_MODULE,
  454. },
  455. .probe = ad5064_probe,
  456. .remove = __devexit_p(ad5064_remove),
  457. .id_table = ad5064_id,
  458. };
  459. module_spi_driver(ad5064_driver);
  460. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  461. MODULE_DESCRIPTION("Analog Devices AD5024/25/44/45/64/64-1/65, AD5628/48/66/68 DAC");
  462. MODULE_LICENSE("GPL v2");