shpchprm_legacy.c 4.0 KB

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  1. /*
  2. * SHPCHPRM Legacy: PHP Resource Manager for Non-ACPI/Legacy platform
  3. *
  4. * Copyright (C) 1995,2001 Compaq Computer Corporation
  5. * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
  6. * Copyright (C) 2001 IBM Corp.
  7. * Copyright (C) 2003-2004 Intel Corporation
  8. *
  9. * All rights reserved.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or (at
  14. * your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19. * NON INFRINGEMENT. See the GNU General Public License for more
  20. * details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25. *
  26. * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
  27. *
  28. */
  29. #include <linux/config.h>
  30. #include <linux/module.h>
  31. #include <linux/kernel.h>
  32. #include <linux/types.h>
  33. #include <linux/pci.h>
  34. #include <linux/init.h>
  35. #include <asm/uaccess.h>
  36. #include "shpchp.h"
  37. #include "shpchprm.h"
  38. void shpchprm_cleanup(void)
  39. {
  40. }
  41. int shpchprm_get_physical_slot_number(struct controller *ctrl, u32 *sun, u8 busnum, u8 devnum)
  42. {
  43. int offset = devnum - ctrl->slot_device_offset;
  44. *sun = (u8) (ctrl->first_slot + ctrl->slot_num_inc * offset);
  45. return 0;
  46. }
  47. int shpchprm_set_hpp(
  48. struct controller *ctrl,
  49. struct pci_func *func,
  50. u8 card_type)
  51. {
  52. u32 rc;
  53. u8 temp_byte;
  54. struct pci_bus lpci_bus, *pci_bus;
  55. unsigned int devfn;
  56. memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
  57. pci_bus = &lpci_bus;
  58. pci_bus->number = func->bus;
  59. devfn = PCI_DEVFN(func->device, func->function);
  60. temp_byte = 0x40; /* hard coded value for LT */
  61. if (card_type == PCI_HEADER_TYPE_BRIDGE) {
  62. /* set subordinate Latency Timer */
  63. rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_SEC_LATENCY_TIMER, temp_byte);
  64. if (rc) {
  65. dbg("%s: set secondary LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus,
  66. func->device, func->function);
  67. return rc;
  68. }
  69. }
  70. /* set base Latency Timer */
  71. rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_LATENCY_TIMER, temp_byte);
  72. if (rc) {
  73. dbg("%s: set LT error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
  74. return rc;
  75. }
  76. /* set Cache Line size */
  77. temp_byte = 0x08; /* hard coded value for CLS */
  78. rc = pci_bus_write_config_byte(pci_bus, devfn, PCI_CACHE_LINE_SIZE, temp_byte);
  79. if (rc) {
  80. dbg("%s: set CLS error. b:d:f(%02x:%02x:%02x)\n", __FUNCTION__, func->bus, func->device, func->function);
  81. }
  82. /* set enable_perr */
  83. /* set enable_serr */
  84. return rc;
  85. }
  86. void shpchprm_enable_card(
  87. struct controller *ctrl,
  88. struct pci_func *func,
  89. u8 card_type)
  90. {
  91. u16 command, bcommand;
  92. struct pci_bus lpci_bus, *pci_bus;
  93. unsigned int devfn;
  94. int rc;
  95. memcpy(&lpci_bus, ctrl->pci_bus, sizeof(lpci_bus));
  96. pci_bus = &lpci_bus;
  97. pci_bus->number = func->bus;
  98. devfn = PCI_DEVFN(func->device, func->function);
  99. rc = pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &command);
  100. command |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR
  101. | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
  102. | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  103. rc = pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
  104. if (card_type == PCI_HEADER_TYPE_BRIDGE) {
  105. rc = pci_bus_read_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, &bcommand);
  106. bcommand |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR
  107. | PCI_BRIDGE_CTL_NO_ISA;
  108. rc = pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, bcommand);
  109. }
  110. }
  111. static int legacy_shpchprm_init_pci(void)
  112. {
  113. return 0;
  114. }
  115. int shpchprm_init(enum php_ctlr_type ctrl_type)
  116. {
  117. int retval;
  118. switch (ctrl_type) {
  119. case PCI:
  120. retval = legacy_shpchprm_init_pci();
  121. break;
  122. default:
  123. retval = -ENODEV;
  124. break;
  125. }
  126. return retval;
  127. }