main.c 134 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152
  1. /*
  2. Broadcom B43 wireless driver
  3. Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
  4. Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
  5. Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
  6. Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
  7. Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  8. SDIO support
  9. Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
  10. Some parts of the code in this file are derived from the ipw2200
  11. driver Copyright(c) 2003 - 2004 Intel Corporation.
  12. This program is free software; you can redistribute it and/or modify
  13. it under the terms of the GNU General Public License as published by
  14. the Free Software Foundation; either version 2 of the License, or
  15. (at your option) any later version.
  16. This program is distributed in the hope that it will be useful,
  17. but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. GNU General Public License for more details.
  20. You should have received a copy of the GNU General Public License
  21. along with this program; see the file COPYING. If not, write to
  22. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  23. Boston, MA 02110-1301, USA.
  24. */
  25. #include <linux/delay.h>
  26. #include <linux/init.h>
  27. #include <linux/moduleparam.h>
  28. #include <linux/if_arp.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/firmware.h>
  31. #include <linux/wireless.h>
  32. #include <linux/workqueue.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/io.h>
  35. #include <linux/dma-mapping.h>
  36. #include <linux/slab.h>
  37. #include <asm/unaligned.h>
  38. #include "b43.h"
  39. #include "main.h"
  40. #include "debugfs.h"
  41. #include "phy_common.h"
  42. #include "phy_g.h"
  43. #include "phy_n.h"
  44. #include "dma.h"
  45. #include "pio.h"
  46. #include "sysfs.h"
  47. #include "xmit.h"
  48. #include "lo.h"
  49. #include "pcmcia.h"
  50. #include "sdio.h"
  51. #include <linux/mmc/sdio_func.h>
  52. MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  53. MODULE_AUTHOR("Martin Langer");
  54. MODULE_AUTHOR("Stefano Brivio");
  55. MODULE_AUTHOR("Michael Buesch");
  56. MODULE_AUTHOR("Gábor Stefanik");
  57. MODULE_LICENSE("GPL");
  58. MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
  59. MODULE_FIRMWARE("b43/ucode11.fw");
  60. MODULE_FIRMWARE("b43/ucode13.fw");
  61. MODULE_FIRMWARE("b43/ucode14.fw");
  62. MODULE_FIRMWARE("b43/ucode15.fw");
  63. MODULE_FIRMWARE("b43/ucode5.fw");
  64. MODULE_FIRMWARE("b43/ucode9.fw");
  65. static int modparam_bad_frames_preempt;
  66. module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  67. MODULE_PARM_DESC(bad_frames_preempt,
  68. "enable(1) / disable(0) Bad Frames Preemption");
  69. static char modparam_fwpostfix[16];
  70. module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  71. MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  72. static int modparam_hwpctl;
  73. module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  74. MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  75. static int modparam_nohwcrypt;
  76. module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  77. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  78. static int modparam_hwtkip;
  79. module_param_named(hwtkip, modparam_hwtkip, int, 0444);
  80. MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
  81. static int modparam_qos = 1;
  82. module_param_named(qos, modparam_qos, int, 0444);
  83. MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
  84. static int modparam_btcoex = 1;
  85. module_param_named(btcoex, modparam_btcoex, int, 0444);
  86. MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
  87. int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
  88. module_param_named(verbose, b43_modparam_verbose, int, 0644);
  89. MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
  90. static int b43_modparam_pio = B43_PIO_DEFAULT;
  91. module_param_named(pio, b43_modparam_pio, int, 0644);
  92. MODULE_PARM_DESC(pio, "Use PIO accesses by default: 0=DMA, 1=PIO");
  93. static const struct ssb_device_id b43_ssb_tbl[] = {
  94. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
  95. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
  96. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
  97. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
  98. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
  99. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
  100. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 12),
  101. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
  102. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
  103. SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
  104. SSB_DEVTABLE_END
  105. };
  106. MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
  107. /* Channel and ratetables are shared for all devices.
  108. * They can't be const, because ieee80211 puts some precalculated
  109. * data in there. This data is the same for all devices, so we don't
  110. * get concurrency issues */
  111. #define RATETAB_ENT(_rateid, _flags) \
  112. { \
  113. .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
  114. .hw_value = (_rateid), \
  115. .flags = (_flags), \
  116. }
  117. /*
  118. * NOTE: When changing this, sync with xmit.c's
  119. * b43_plcp_get_bitrate_idx_* functions!
  120. */
  121. static struct ieee80211_rate __b43_ratetable[] = {
  122. RATETAB_ENT(B43_CCK_RATE_1MB, 0),
  123. RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
  124. RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
  125. RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
  126. RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
  127. RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
  128. RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
  129. RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
  130. RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
  131. RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
  132. RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
  133. RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
  134. };
  135. #define b43_a_ratetable (__b43_ratetable + 4)
  136. #define b43_a_ratetable_size 8
  137. #define b43_b_ratetable (__b43_ratetable + 0)
  138. #define b43_b_ratetable_size 4
  139. #define b43_g_ratetable (__b43_ratetable + 0)
  140. #define b43_g_ratetable_size 12
  141. #define CHAN4G(_channel, _freq, _flags) { \
  142. .band = IEEE80211_BAND_2GHZ, \
  143. .center_freq = (_freq), \
  144. .hw_value = (_channel), \
  145. .flags = (_flags), \
  146. .max_antenna_gain = 0, \
  147. .max_power = 30, \
  148. }
  149. static struct ieee80211_channel b43_2ghz_chantable[] = {
  150. CHAN4G(1, 2412, 0),
  151. CHAN4G(2, 2417, 0),
  152. CHAN4G(3, 2422, 0),
  153. CHAN4G(4, 2427, 0),
  154. CHAN4G(5, 2432, 0),
  155. CHAN4G(6, 2437, 0),
  156. CHAN4G(7, 2442, 0),
  157. CHAN4G(8, 2447, 0),
  158. CHAN4G(9, 2452, 0),
  159. CHAN4G(10, 2457, 0),
  160. CHAN4G(11, 2462, 0),
  161. CHAN4G(12, 2467, 0),
  162. CHAN4G(13, 2472, 0),
  163. CHAN4G(14, 2484, 0),
  164. };
  165. #undef CHAN4G
  166. #define CHAN5G(_channel, _flags) { \
  167. .band = IEEE80211_BAND_5GHZ, \
  168. .center_freq = 5000 + (5 * (_channel)), \
  169. .hw_value = (_channel), \
  170. .flags = (_flags), \
  171. .max_antenna_gain = 0, \
  172. .max_power = 30, \
  173. }
  174. static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
  175. CHAN5G(32, 0), CHAN5G(34, 0),
  176. CHAN5G(36, 0), CHAN5G(38, 0),
  177. CHAN5G(40, 0), CHAN5G(42, 0),
  178. CHAN5G(44, 0), CHAN5G(46, 0),
  179. CHAN5G(48, 0), CHAN5G(50, 0),
  180. CHAN5G(52, 0), CHAN5G(54, 0),
  181. CHAN5G(56, 0), CHAN5G(58, 0),
  182. CHAN5G(60, 0), CHAN5G(62, 0),
  183. CHAN5G(64, 0), CHAN5G(66, 0),
  184. CHAN5G(68, 0), CHAN5G(70, 0),
  185. CHAN5G(72, 0), CHAN5G(74, 0),
  186. CHAN5G(76, 0), CHAN5G(78, 0),
  187. CHAN5G(80, 0), CHAN5G(82, 0),
  188. CHAN5G(84, 0), CHAN5G(86, 0),
  189. CHAN5G(88, 0), CHAN5G(90, 0),
  190. CHAN5G(92, 0), CHAN5G(94, 0),
  191. CHAN5G(96, 0), CHAN5G(98, 0),
  192. CHAN5G(100, 0), CHAN5G(102, 0),
  193. CHAN5G(104, 0), CHAN5G(106, 0),
  194. CHAN5G(108, 0), CHAN5G(110, 0),
  195. CHAN5G(112, 0), CHAN5G(114, 0),
  196. CHAN5G(116, 0), CHAN5G(118, 0),
  197. CHAN5G(120, 0), CHAN5G(122, 0),
  198. CHAN5G(124, 0), CHAN5G(126, 0),
  199. CHAN5G(128, 0), CHAN5G(130, 0),
  200. CHAN5G(132, 0), CHAN5G(134, 0),
  201. CHAN5G(136, 0), CHAN5G(138, 0),
  202. CHAN5G(140, 0), CHAN5G(142, 0),
  203. CHAN5G(144, 0), CHAN5G(145, 0),
  204. CHAN5G(146, 0), CHAN5G(147, 0),
  205. CHAN5G(148, 0), CHAN5G(149, 0),
  206. CHAN5G(150, 0), CHAN5G(151, 0),
  207. CHAN5G(152, 0), CHAN5G(153, 0),
  208. CHAN5G(154, 0), CHAN5G(155, 0),
  209. CHAN5G(156, 0), CHAN5G(157, 0),
  210. CHAN5G(158, 0), CHAN5G(159, 0),
  211. CHAN5G(160, 0), CHAN5G(161, 0),
  212. CHAN5G(162, 0), CHAN5G(163, 0),
  213. CHAN5G(164, 0), CHAN5G(165, 0),
  214. CHAN5G(166, 0), CHAN5G(168, 0),
  215. CHAN5G(170, 0), CHAN5G(172, 0),
  216. CHAN5G(174, 0), CHAN5G(176, 0),
  217. CHAN5G(178, 0), CHAN5G(180, 0),
  218. CHAN5G(182, 0), CHAN5G(184, 0),
  219. CHAN5G(186, 0), CHAN5G(188, 0),
  220. CHAN5G(190, 0), CHAN5G(192, 0),
  221. CHAN5G(194, 0), CHAN5G(196, 0),
  222. CHAN5G(198, 0), CHAN5G(200, 0),
  223. CHAN5G(202, 0), CHAN5G(204, 0),
  224. CHAN5G(206, 0), CHAN5G(208, 0),
  225. CHAN5G(210, 0), CHAN5G(212, 0),
  226. CHAN5G(214, 0), CHAN5G(216, 0),
  227. CHAN5G(218, 0), CHAN5G(220, 0),
  228. CHAN5G(222, 0), CHAN5G(224, 0),
  229. CHAN5G(226, 0), CHAN5G(228, 0),
  230. };
  231. static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
  232. CHAN5G(34, 0), CHAN5G(36, 0),
  233. CHAN5G(38, 0), CHAN5G(40, 0),
  234. CHAN5G(42, 0), CHAN5G(44, 0),
  235. CHAN5G(46, 0), CHAN5G(48, 0),
  236. CHAN5G(52, 0), CHAN5G(56, 0),
  237. CHAN5G(60, 0), CHAN5G(64, 0),
  238. CHAN5G(100, 0), CHAN5G(104, 0),
  239. CHAN5G(108, 0), CHAN5G(112, 0),
  240. CHAN5G(116, 0), CHAN5G(120, 0),
  241. CHAN5G(124, 0), CHAN5G(128, 0),
  242. CHAN5G(132, 0), CHAN5G(136, 0),
  243. CHAN5G(140, 0), CHAN5G(149, 0),
  244. CHAN5G(153, 0), CHAN5G(157, 0),
  245. CHAN5G(161, 0), CHAN5G(165, 0),
  246. CHAN5G(184, 0), CHAN5G(188, 0),
  247. CHAN5G(192, 0), CHAN5G(196, 0),
  248. CHAN5G(200, 0), CHAN5G(204, 0),
  249. CHAN5G(208, 0), CHAN5G(212, 0),
  250. CHAN5G(216, 0),
  251. };
  252. #undef CHAN5G
  253. static struct ieee80211_supported_band b43_band_5GHz_nphy = {
  254. .band = IEEE80211_BAND_5GHZ,
  255. .channels = b43_5ghz_nphy_chantable,
  256. .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
  257. .bitrates = b43_a_ratetable,
  258. .n_bitrates = b43_a_ratetable_size,
  259. };
  260. static struct ieee80211_supported_band b43_band_5GHz_aphy = {
  261. .band = IEEE80211_BAND_5GHZ,
  262. .channels = b43_5ghz_aphy_chantable,
  263. .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
  264. .bitrates = b43_a_ratetable,
  265. .n_bitrates = b43_a_ratetable_size,
  266. };
  267. static struct ieee80211_supported_band b43_band_2GHz = {
  268. .band = IEEE80211_BAND_2GHZ,
  269. .channels = b43_2ghz_chantable,
  270. .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
  271. .bitrates = b43_g_ratetable,
  272. .n_bitrates = b43_g_ratetable_size,
  273. };
  274. static void b43_wireless_core_exit(struct b43_wldev *dev);
  275. static int b43_wireless_core_init(struct b43_wldev *dev);
  276. static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
  277. static int b43_wireless_core_start(struct b43_wldev *dev);
  278. static int b43_ratelimit(struct b43_wl *wl)
  279. {
  280. if (!wl || !wl->current_dev)
  281. return 1;
  282. if (b43_status(wl->current_dev) < B43_STAT_STARTED)
  283. return 1;
  284. /* We are up and running.
  285. * Ratelimit the messages to avoid DoS over the net. */
  286. return net_ratelimit();
  287. }
  288. void b43info(struct b43_wl *wl, const char *fmt, ...)
  289. {
  290. struct va_format vaf;
  291. va_list args;
  292. if (b43_modparam_verbose < B43_VERBOSITY_INFO)
  293. return;
  294. if (!b43_ratelimit(wl))
  295. return;
  296. va_start(args, fmt);
  297. vaf.fmt = fmt;
  298. vaf.va = &args;
  299. printk(KERN_INFO "b43-%s: %pV",
  300. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
  301. va_end(args);
  302. }
  303. void b43err(struct b43_wl *wl, const char *fmt, ...)
  304. {
  305. struct va_format vaf;
  306. va_list args;
  307. if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
  308. return;
  309. if (!b43_ratelimit(wl))
  310. return;
  311. va_start(args, fmt);
  312. vaf.fmt = fmt;
  313. vaf.va = &args;
  314. printk(KERN_ERR "b43-%s ERROR: %pV",
  315. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
  316. va_end(args);
  317. }
  318. void b43warn(struct b43_wl *wl, const char *fmt, ...)
  319. {
  320. struct va_format vaf;
  321. va_list args;
  322. if (b43_modparam_verbose < B43_VERBOSITY_WARN)
  323. return;
  324. if (!b43_ratelimit(wl))
  325. return;
  326. va_start(args, fmt);
  327. vaf.fmt = fmt;
  328. vaf.va = &args;
  329. printk(KERN_WARNING "b43-%s warning: %pV",
  330. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
  331. va_end(args);
  332. }
  333. void b43dbg(struct b43_wl *wl, const char *fmt, ...)
  334. {
  335. struct va_format vaf;
  336. va_list args;
  337. if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
  338. return;
  339. va_start(args, fmt);
  340. vaf.fmt = fmt;
  341. vaf.va = &args;
  342. printk(KERN_DEBUG "b43-%s debug: %pV",
  343. (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
  344. va_end(args);
  345. }
  346. static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
  347. {
  348. u32 macctl;
  349. B43_WARN_ON(offset % 4 != 0);
  350. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  351. if (macctl & B43_MACCTL_BE)
  352. val = swab32(val);
  353. b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
  354. mmiowb();
  355. b43_write32(dev, B43_MMIO_RAM_DATA, val);
  356. }
  357. static inline void b43_shm_control_word(struct b43_wldev *dev,
  358. u16 routing, u16 offset)
  359. {
  360. u32 control;
  361. /* "offset" is the WORD offset. */
  362. control = routing;
  363. control <<= 16;
  364. control |= offset;
  365. b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
  366. }
  367. u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
  368. {
  369. u32 ret;
  370. if (routing == B43_SHM_SHARED) {
  371. B43_WARN_ON(offset & 0x0001);
  372. if (offset & 0x0003) {
  373. /* Unaligned access */
  374. b43_shm_control_word(dev, routing, offset >> 2);
  375. ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
  376. b43_shm_control_word(dev, routing, (offset >> 2) + 1);
  377. ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
  378. goto out;
  379. }
  380. offset >>= 2;
  381. }
  382. b43_shm_control_word(dev, routing, offset);
  383. ret = b43_read32(dev, B43_MMIO_SHM_DATA);
  384. out:
  385. return ret;
  386. }
  387. u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
  388. {
  389. u16 ret;
  390. if (routing == B43_SHM_SHARED) {
  391. B43_WARN_ON(offset & 0x0001);
  392. if (offset & 0x0003) {
  393. /* Unaligned access */
  394. b43_shm_control_word(dev, routing, offset >> 2);
  395. ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
  396. goto out;
  397. }
  398. offset >>= 2;
  399. }
  400. b43_shm_control_word(dev, routing, offset);
  401. ret = b43_read16(dev, B43_MMIO_SHM_DATA);
  402. out:
  403. return ret;
  404. }
  405. void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
  406. {
  407. if (routing == B43_SHM_SHARED) {
  408. B43_WARN_ON(offset & 0x0001);
  409. if (offset & 0x0003) {
  410. /* Unaligned access */
  411. b43_shm_control_word(dev, routing, offset >> 2);
  412. b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
  413. value & 0xFFFF);
  414. b43_shm_control_word(dev, routing, (offset >> 2) + 1);
  415. b43_write16(dev, B43_MMIO_SHM_DATA,
  416. (value >> 16) & 0xFFFF);
  417. return;
  418. }
  419. offset >>= 2;
  420. }
  421. b43_shm_control_word(dev, routing, offset);
  422. b43_write32(dev, B43_MMIO_SHM_DATA, value);
  423. }
  424. void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
  425. {
  426. if (routing == B43_SHM_SHARED) {
  427. B43_WARN_ON(offset & 0x0001);
  428. if (offset & 0x0003) {
  429. /* Unaligned access */
  430. b43_shm_control_word(dev, routing, offset >> 2);
  431. b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
  432. return;
  433. }
  434. offset >>= 2;
  435. }
  436. b43_shm_control_word(dev, routing, offset);
  437. b43_write16(dev, B43_MMIO_SHM_DATA, value);
  438. }
  439. /* Read HostFlags */
  440. u64 b43_hf_read(struct b43_wldev *dev)
  441. {
  442. u64 ret;
  443. ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
  444. ret <<= 16;
  445. ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
  446. ret <<= 16;
  447. ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
  448. return ret;
  449. }
  450. /* Write HostFlags */
  451. void b43_hf_write(struct b43_wldev *dev, u64 value)
  452. {
  453. u16 lo, mi, hi;
  454. lo = (value & 0x00000000FFFFULL);
  455. mi = (value & 0x0000FFFF0000ULL) >> 16;
  456. hi = (value & 0xFFFF00000000ULL) >> 32;
  457. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
  458. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
  459. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
  460. }
  461. /* Read the firmware capabilities bitmask (Opensource firmware only) */
  462. static u16 b43_fwcapa_read(struct b43_wldev *dev)
  463. {
  464. B43_WARN_ON(!dev->fw.opensource);
  465. return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
  466. }
  467. void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
  468. {
  469. u32 low, high;
  470. B43_WARN_ON(dev->dev->id.revision < 3);
  471. /* The hardware guarantees us an atomic read, if we
  472. * read the low register first. */
  473. low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
  474. high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
  475. *tsf = high;
  476. *tsf <<= 32;
  477. *tsf |= low;
  478. }
  479. static void b43_time_lock(struct b43_wldev *dev)
  480. {
  481. u32 macctl;
  482. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  483. macctl |= B43_MACCTL_TBTTHOLD;
  484. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  485. /* Commit the write */
  486. b43_read32(dev, B43_MMIO_MACCTL);
  487. }
  488. static void b43_time_unlock(struct b43_wldev *dev)
  489. {
  490. u32 macctl;
  491. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  492. macctl &= ~B43_MACCTL_TBTTHOLD;
  493. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  494. /* Commit the write */
  495. b43_read32(dev, B43_MMIO_MACCTL);
  496. }
  497. static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
  498. {
  499. u32 low, high;
  500. B43_WARN_ON(dev->dev->id.revision < 3);
  501. low = tsf;
  502. high = (tsf >> 32);
  503. /* The hardware guarantees us an atomic write, if we
  504. * write the low register first. */
  505. b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
  506. mmiowb();
  507. b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
  508. mmiowb();
  509. }
  510. void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
  511. {
  512. b43_time_lock(dev);
  513. b43_tsf_write_locked(dev, tsf);
  514. b43_time_unlock(dev);
  515. }
  516. static
  517. void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
  518. {
  519. static const u8 zero_addr[ETH_ALEN] = { 0 };
  520. u16 data;
  521. if (!mac)
  522. mac = zero_addr;
  523. offset |= 0x0020;
  524. b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
  525. data = mac[0];
  526. data |= mac[1] << 8;
  527. b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
  528. data = mac[2];
  529. data |= mac[3] << 8;
  530. b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
  531. data = mac[4];
  532. data |= mac[5] << 8;
  533. b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
  534. }
  535. static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
  536. {
  537. const u8 *mac;
  538. const u8 *bssid;
  539. u8 mac_bssid[ETH_ALEN * 2];
  540. int i;
  541. u32 tmp;
  542. bssid = dev->wl->bssid;
  543. mac = dev->wl->mac_addr;
  544. b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
  545. memcpy(mac_bssid, mac, ETH_ALEN);
  546. memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
  547. /* Write our MAC address and BSSID to template ram */
  548. for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
  549. tmp = (u32) (mac_bssid[i + 0]);
  550. tmp |= (u32) (mac_bssid[i + 1]) << 8;
  551. tmp |= (u32) (mac_bssid[i + 2]) << 16;
  552. tmp |= (u32) (mac_bssid[i + 3]) << 24;
  553. b43_ram_write(dev, 0x20 + i, tmp);
  554. }
  555. }
  556. static void b43_upload_card_macaddress(struct b43_wldev *dev)
  557. {
  558. b43_write_mac_bssid_templates(dev);
  559. b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
  560. }
  561. static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
  562. {
  563. /* slot_time is in usec. */
  564. /* This test used to exit for all but a G PHY. */
  565. if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
  566. return;
  567. b43_write16(dev, B43_MMIO_IFSSLOT, 510 + slot_time);
  568. /* Shared memory location 0x0010 is the slot time and should be
  569. * set to slot_time; however, this register is initially 0 and changing
  570. * the value adversely affects the transmit rate for BCM4311
  571. * devices. Until this behavior is unterstood, delete this step
  572. *
  573. * b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
  574. */
  575. }
  576. static void b43_short_slot_timing_enable(struct b43_wldev *dev)
  577. {
  578. b43_set_slot_time(dev, 9);
  579. }
  580. static void b43_short_slot_timing_disable(struct b43_wldev *dev)
  581. {
  582. b43_set_slot_time(dev, 20);
  583. }
  584. /* DummyTransmission function, as documented on
  585. * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
  586. */
  587. void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
  588. {
  589. struct b43_phy *phy = &dev->phy;
  590. unsigned int i, max_loop;
  591. u16 value;
  592. u32 buffer[5] = {
  593. 0x00000000,
  594. 0x00D40000,
  595. 0x00000000,
  596. 0x01000000,
  597. 0x00000000,
  598. };
  599. if (ofdm) {
  600. max_loop = 0x1E;
  601. buffer[0] = 0x000201CC;
  602. } else {
  603. max_loop = 0xFA;
  604. buffer[0] = 0x000B846E;
  605. }
  606. for (i = 0; i < 5; i++)
  607. b43_ram_write(dev, i * 4, buffer[i]);
  608. b43_write16(dev, 0x0568, 0x0000);
  609. if (dev->dev->id.revision < 11)
  610. b43_write16(dev, 0x07C0, 0x0000);
  611. else
  612. b43_write16(dev, 0x07C0, 0x0100);
  613. value = (ofdm ? 0x41 : 0x40);
  614. b43_write16(dev, 0x050C, value);
  615. if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
  616. b43_write16(dev, 0x0514, 0x1A02);
  617. b43_write16(dev, 0x0508, 0x0000);
  618. b43_write16(dev, 0x050A, 0x0000);
  619. b43_write16(dev, 0x054C, 0x0000);
  620. b43_write16(dev, 0x056A, 0x0014);
  621. b43_write16(dev, 0x0568, 0x0826);
  622. b43_write16(dev, 0x0500, 0x0000);
  623. if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
  624. //SPEC TODO
  625. }
  626. switch (phy->type) {
  627. case B43_PHYTYPE_N:
  628. b43_write16(dev, 0x0502, 0x00D0);
  629. break;
  630. case B43_PHYTYPE_LP:
  631. b43_write16(dev, 0x0502, 0x0050);
  632. break;
  633. default:
  634. b43_write16(dev, 0x0502, 0x0030);
  635. }
  636. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  637. b43_radio_write16(dev, 0x0051, 0x0017);
  638. for (i = 0x00; i < max_loop; i++) {
  639. value = b43_read16(dev, 0x050E);
  640. if (value & 0x0080)
  641. break;
  642. udelay(10);
  643. }
  644. for (i = 0x00; i < 0x0A; i++) {
  645. value = b43_read16(dev, 0x050E);
  646. if (value & 0x0400)
  647. break;
  648. udelay(10);
  649. }
  650. for (i = 0x00; i < 0x19; i++) {
  651. value = b43_read16(dev, 0x0690);
  652. if (!(value & 0x0100))
  653. break;
  654. udelay(10);
  655. }
  656. if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
  657. b43_radio_write16(dev, 0x0051, 0x0037);
  658. }
  659. static void key_write(struct b43_wldev *dev,
  660. u8 index, u8 algorithm, const u8 *key)
  661. {
  662. unsigned int i;
  663. u32 offset;
  664. u16 value;
  665. u16 kidx;
  666. /* Key index/algo block */
  667. kidx = b43_kidx_to_fw(dev, index);
  668. value = ((kidx << 4) | algorithm);
  669. b43_shm_write16(dev, B43_SHM_SHARED,
  670. B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
  671. /* Write the key to the Key Table Pointer offset */
  672. offset = dev->ktp + (index * B43_SEC_KEYSIZE);
  673. for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
  674. value = key[i];
  675. value |= (u16) (key[i + 1]) << 8;
  676. b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
  677. }
  678. }
  679. static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
  680. {
  681. u32 addrtmp[2] = { 0, 0, };
  682. u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
  683. if (b43_new_kidx_api(dev))
  684. pairwise_keys_start = B43_NR_GROUP_KEYS;
  685. B43_WARN_ON(index < pairwise_keys_start);
  686. /* We have four default TX keys and possibly four default RX keys.
  687. * Physical mac 0 is mapped to physical key 4 or 8, depending
  688. * on the firmware version.
  689. * So we must adjust the index here.
  690. */
  691. index -= pairwise_keys_start;
  692. B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
  693. if (addr) {
  694. addrtmp[0] = addr[0];
  695. addrtmp[0] |= ((u32) (addr[1]) << 8);
  696. addrtmp[0] |= ((u32) (addr[2]) << 16);
  697. addrtmp[0] |= ((u32) (addr[3]) << 24);
  698. addrtmp[1] = addr[4];
  699. addrtmp[1] |= ((u32) (addr[5]) << 8);
  700. }
  701. /* Receive match transmitter address (RCMTA) mechanism */
  702. b43_shm_write32(dev, B43_SHM_RCMTA,
  703. (index * 2) + 0, addrtmp[0]);
  704. b43_shm_write16(dev, B43_SHM_RCMTA,
  705. (index * 2) + 1, addrtmp[1]);
  706. }
  707. /* The ucode will use phase1 key with TEK key to decrypt rx packets.
  708. * When a packet is received, the iv32 is checked.
  709. * - if it doesn't the packet is returned without modification (and software
  710. * decryption can be done). That's what happen when iv16 wrap.
  711. * - if it does, the rc4 key is computed, and decryption is tried.
  712. * Either it will success and B43_RX_MAC_DEC is returned,
  713. * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
  714. * and the packet is not usable (it got modified by the ucode).
  715. * So in order to never have B43_RX_MAC_DECERR, we should provide
  716. * a iv32 and phase1key that match. Because we drop packets in case of
  717. * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
  718. * packets will be lost without higher layer knowing (ie no resync possible
  719. * until next wrap).
  720. *
  721. * NOTE : this should support 50 key like RCMTA because
  722. * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
  723. */
  724. static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
  725. u16 *phase1key)
  726. {
  727. unsigned int i;
  728. u32 offset;
  729. u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
  730. if (!modparam_hwtkip)
  731. return;
  732. if (b43_new_kidx_api(dev))
  733. pairwise_keys_start = B43_NR_GROUP_KEYS;
  734. B43_WARN_ON(index < pairwise_keys_start);
  735. /* We have four default TX keys and possibly four default RX keys.
  736. * Physical mac 0 is mapped to physical key 4 or 8, depending
  737. * on the firmware version.
  738. * So we must adjust the index here.
  739. */
  740. index -= pairwise_keys_start;
  741. B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
  742. if (b43_debug(dev, B43_DBG_KEYS)) {
  743. b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
  744. index, iv32);
  745. }
  746. /* Write the key to the RX tkip shared mem */
  747. offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
  748. for (i = 0; i < 10; i += 2) {
  749. b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
  750. phase1key ? phase1key[i / 2] : 0);
  751. }
  752. b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
  753. b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
  754. }
  755. static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
  756. struct ieee80211_vif *vif,
  757. struct ieee80211_key_conf *keyconf,
  758. struct ieee80211_sta *sta,
  759. u32 iv32, u16 *phase1key)
  760. {
  761. struct b43_wl *wl = hw_to_b43_wl(hw);
  762. struct b43_wldev *dev;
  763. int index = keyconf->hw_key_idx;
  764. if (B43_WARN_ON(!modparam_hwtkip))
  765. return;
  766. /* This is only called from the RX path through mac80211, where
  767. * our mutex is already locked. */
  768. B43_WARN_ON(!mutex_is_locked(&wl->mutex));
  769. dev = wl->current_dev;
  770. B43_WARN_ON(!dev || b43_status(dev) < B43_STAT_INITIALIZED);
  771. keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
  772. rx_tkip_phase1_write(dev, index, iv32, phase1key);
  773. /* only pairwise TKIP keys are supported right now */
  774. if (WARN_ON(!sta))
  775. return;
  776. keymac_write(dev, index, sta->addr);
  777. }
  778. static void do_key_write(struct b43_wldev *dev,
  779. u8 index, u8 algorithm,
  780. const u8 *key, size_t key_len, const u8 *mac_addr)
  781. {
  782. u8 buf[B43_SEC_KEYSIZE] = { 0, };
  783. u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
  784. if (b43_new_kidx_api(dev))
  785. pairwise_keys_start = B43_NR_GROUP_KEYS;
  786. B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
  787. B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
  788. if (index >= pairwise_keys_start)
  789. keymac_write(dev, index, NULL); /* First zero out mac. */
  790. if (algorithm == B43_SEC_ALGO_TKIP) {
  791. /*
  792. * We should provide an initial iv32, phase1key pair.
  793. * We could start with iv32=0 and compute the corresponding
  794. * phase1key, but this means calling ieee80211_get_tkip_key
  795. * with a fake skb (or export other tkip function).
  796. * Because we are lazy we hope iv32 won't start with
  797. * 0xffffffff and let's b43_op_update_tkip_key provide a
  798. * correct pair.
  799. */
  800. rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
  801. } else if (index >= pairwise_keys_start) /* clear it */
  802. rx_tkip_phase1_write(dev, index, 0, NULL);
  803. if (key)
  804. memcpy(buf, key, key_len);
  805. key_write(dev, index, algorithm, buf);
  806. if (index >= pairwise_keys_start)
  807. keymac_write(dev, index, mac_addr);
  808. dev->key[index].algorithm = algorithm;
  809. }
  810. static int b43_key_write(struct b43_wldev *dev,
  811. int index, u8 algorithm,
  812. const u8 *key, size_t key_len,
  813. const u8 *mac_addr,
  814. struct ieee80211_key_conf *keyconf)
  815. {
  816. int i;
  817. int pairwise_keys_start;
  818. /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
  819. * - Temporal Encryption Key (128 bits)
  820. * - Temporal Authenticator Tx MIC Key (64 bits)
  821. * - Temporal Authenticator Rx MIC Key (64 bits)
  822. *
  823. * Hardware only store TEK
  824. */
  825. if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
  826. key_len = 16;
  827. if (key_len > B43_SEC_KEYSIZE)
  828. return -EINVAL;
  829. for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
  830. /* Check that we don't already have this key. */
  831. B43_WARN_ON(dev->key[i].keyconf == keyconf);
  832. }
  833. if (index < 0) {
  834. /* Pairwise key. Get an empty slot for the key. */
  835. if (b43_new_kidx_api(dev))
  836. pairwise_keys_start = B43_NR_GROUP_KEYS;
  837. else
  838. pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
  839. for (i = pairwise_keys_start;
  840. i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
  841. i++) {
  842. B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
  843. if (!dev->key[i].keyconf) {
  844. /* found empty */
  845. index = i;
  846. break;
  847. }
  848. }
  849. if (index < 0) {
  850. b43warn(dev->wl, "Out of hardware key memory\n");
  851. return -ENOSPC;
  852. }
  853. } else
  854. B43_WARN_ON(index > 3);
  855. do_key_write(dev, index, algorithm, key, key_len, mac_addr);
  856. if ((index <= 3) && !b43_new_kidx_api(dev)) {
  857. /* Default RX key */
  858. B43_WARN_ON(mac_addr);
  859. do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
  860. }
  861. keyconf->hw_key_idx = index;
  862. dev->key[index].keyconf = keyconf;
  863. return 0;
  864. }
  865. static int b43_key_clear(struct b43_wldev *dev, int index)
  866. {
  867. if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
  868. return -EINVAL;
  869. do_key_write(dev, index, B43_SEC_ALGO_NONE,
  870. NULL, B43_SEC_KEYSIZE, NULL);
  871. if ((index <= 3) && !b43_new_kidx_api(dev)) {
  872. do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
  873. NULL, B43_SEC_KEYSIZE, NULL);
  874. }
  875. dev->key[index].keyconf = NULL;
  876. return 0;
  877. }
  878. static void b43_clear_keys(struct b43_wldev *dev)
  879. {
  880. int i, count;
  881. if (b43_new_kidx_api(dev))
  882. count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
  883. else
  884. count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
  885. for (i = 0; i < count; i++)
  886. b43_key_clear(dev, i);
  887. }
  888. static void b43_dump_keymemory(struct b43_wldev *dev)
  889. {
  890. unsigned int i, index, count, offset, pairwise_keys_start;
  891. u8 mac[ETH_ALEN];
  892. u16 algo;
  893. u32 rcmta0;
  894. u16 rcmta1;
  895. u64 hf;
  896. struct b43_key *key;
  897. if (!b43_debug(dev, B43_DBG_KEYS))
  898. return;
  899. hf = b43_hf_read(dev);
  900. b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
  901. !!(hf & B43_HF_USEDEFKEYS));
  902. if (b43_new_kidx_api(dev)) {
  903. pairwise_keys_start = B43_NR_GROUP_KEYS;
  904. count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
  905. } else {
  906. pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
  907. count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
  908. }
  909. for (index = 0; index < count; index++) {
  910. key = &(dev->key[index]);
  911. printk(KERN_DEBUG "Key slot %02u: %s",
  912. index, (key->keyconf == NULL) ? " " : "*");
  913. offset = dev->ktp + (index * B43_SEC_KEYSIZE);
  914. for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
  915. u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
  916. printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
  917. }
  918. algo = b43_shm_read16(dev, B43_SHM_SHARED,
  919. B43_SHM_SH_KEYIDXBLOCK + (index * 2));
  920. printk(" Algo: %04X/%02X", algo, key->algorithm);
  921. if (index >= pairwise_keys_start) {
  922. if (key->algorithm == B43_SEC_ALGO_TKIP) {
  923. printk(" TKIP: ");
  924. offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
  925. for (i = 0; i < 14; i += 2) {
  926. u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
  927. printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
  928. }
  929. }
  930. rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
  931. ((index - pairwise_keys_start) * 2) + 0);
  932. rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
  933. ((index - pairwise_keys_start) * 2) + 1);
  934. *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
  935. *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
  936. printk(" MAC: %pM", mac);
  937. } else
  938. printk(" DEFAULT KEY");
  939. printk("\n");
  940. }
  941. }
  942. void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
  943. {
  944. u32 macctl;
  945. u16 ucstat;
  946. bool hwps;
  947. bool awake;
  948. int i;
  949. B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
  950. (ps_flags & B43_PS_DISABLED));
  951. B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
  952. if (ps_flags & B43_PS_ENABLED) {
  953. hwps = 1;
  954. } else if (ps_flags & B43_PS_DISABLED) {
  955. hwps = 0;
  956. } else {
  957. //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
  958. // and thus is not an AP and we are associated, set bit 25
  959. }
  960. if (ps_flags & B43_PS_AWAKE) {
  961. awake = 1;
  962. } else if (ps_flags & B43_PS_ASLEEP) {
  963. awake = 0;
  964. } else {
  965. //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
  966. // or we are associated, or FIXME, or the latest PS-Poll packet sent was
  967. // successful, set bit26
  968. }
  969. /* FIXME: For now we force awake-on and hwps-off */
  970. hwps = 0;
  971. awake = 1;
  972. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  973. if (hwps)
  974. macctl |= B43_MACCTL_HWPS;
  975. else
  976. macctl &= ~B43_MACCTL_HWPS;
  977. if (awake)
  978. macctl |= B43_MACCTL_AWAKE;
  979. else
  980. macctl &= ~B43_MACCTL_AWAKE;
  981. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  982. /* Commit write */
  983. b43_read32(dev, B43_MMIO_MACCTL);
  984. if (awake && dev->dev->id.revision >= 5) {
  985. /* Wait for the microcode to wake up. */
  986. for (i = 0; i < 100; i++) {
  987. ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
  988. B43_SHM_SH_UCODESTAT);
  989. if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
  990. break;
  991. udelay(10);
  992. }
  993. }
  994. }
  995. void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
  996. {
  997. u32 tmslow;
  998. u32 macctl;
  999. flags |= B43_TMSLOW_PHYCLKEN;
  1000. flags |= B43_TMSLOW_PHYRESET;
  1001. if (dev->phy.type == B43_PHYTYPE_N) {
  1002. if (b43_channel_type_is_40mhz(dev->phy.channel_type))
  1003. flags |= B43_TMSLOW_PHYCLKSPEED_160MHZ;
  1004. else
  1005. flags |= B43_TMSLOW_PHYCLKSPEED_80MHZ;
  1006. }
  1007. ssb_device_enable(dev->dev, flags);
  1008. msleep(2); /* Wait for the PLL to turn on. */
  1009. /* Now take the PHY out of Reset again */
  1010. tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
  1011. tmslow |= SSB_TMSLOW_FGC;
  1012. tmslow &= ~B43_TMSLOW_PHYRESET;
  1013. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  1014. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  1015. msleep(1);
  1016. tmslow &= ~SSB_TMSLOW_FGC;
  1017. ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
  1018. ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
  1019. msleep(1);
  1020. /* Turn Analog ON, but only if we already know the PHY-type.
  1021. * This protects against very early setup where we don't know the
  1022. * PHY-type, yet. wireless_core_reset will be called once again later,
  1023. * when we know the PHY-type. */
  1024. if (dev->phy.ops)
  1025. dev->phy.ops->switch_analog(dev, 1);
  1026. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  1027. macctl &= ~B43_MACCTL_GMODE;
  1028. if (flags & B43_TMSLOW_GMODE)
  1029. macctl |= B43_MACCTL_GMODE;
  1030. macctl |= B43_MACCTL_IHR_ENABLED;
  1031. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  1032. }
  1033. static void handle_irq_transmit_status(struct b43_wldev *dev)
  1034. {
  1035. u32 v0, v1;
  1036. u16 tmp;
  1037. struct b43_txstatus stat;
  1038. while (1) {
  1039. v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
  1040. if (!(v0 & 0x00000001))
  1041. break;
  1042. v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
  1043. stat.cookie = (v0 >> 16);
  1044. stat.seq = (v1 & 0x0000FFFF);
  1045. stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
  1046. tmp = (v0 & 0x0000FFFF);
  1047. stat.frame_count = ((tmp & 0xF000) >> 12);
  1048. stat.rts_count = ((tmp & 0x0F00) >> 8);
  1049. stat.supp_reason = ((tmp & 0x001C) >> 2);
  1050. stat.pm_indicated = !!(tmp & 0x0080);
  1051. stat.intermediate = !!(tmp & 0x0040);
  1052. stat.for_ampdu = !!(tmp & 0x0020);
  1053. stat.acked = !!(tmp & 0x0002);
  1054. b43_handle_txstatus(dev, &stat);
  1055. }
  1056. }
  1057. static void drain_txstatus_queue(struct b43_wldev *dev)
  1058. {
  1059. u32 dummy;
  1060. if (dev->dev->id.revision < 5)
  1061. return;
  1062. /* Read all entries from the microcode TXstatus FIFO
  1063. * and throw them away.
  1064. */
  1065. while (1) {
  1066. dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
  1067. if (!(dummy & 0x00000001))
  1068. break;
  1069. dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
  1070. }
  1071. }
  1072. static u32 b43_jssi_read(struct b43_wldev *dev)
  1073. {
  1074. u32 val = 0;
  1075. val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
  1076. val <<= 16;
  1077. val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
  1078. return val;
  1079. }
  1080. static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
  1081. {
  1082. b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
  1083. b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
  1084. }
  1085. static void b43_generate_noise_sample(struct b43_wldev *dev)
  1086. {
  1087. b43_jssi_write(dev, 0x7F7F7F7F);
  1088. b43_write32(dev, B43_MMIO_MACCMD,
  1089. b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
  1090. }
  1091. static void b43_calculate_link_quality(struct b43_wldev *dev)
  1092. {
  1093. /* Top half of Link Quality calculation. */
  1094. if (dev->phy.type != B43_PHYTYPE_G)
  1095. return;
  1096. if (dev->noisecalc.calculation_running)
  1097. return;
  1098. dev->noisecalc.calculation_running = 1;
  1099. dev->noisecalc.nr_samples = 0;
  1100. b43_generate_noise_sample(dev);
  1101. }
  1102. static void handle_irq_noise(struct b43_wldev *dev)
  1103. {
  1104. struct b43_phy_g *phy = dev->phy.g;
  1105. u16 tmp;
  1106. u8 noise[4];
  1107. u8 i, j;
  1108. s32 average;
  1109. /* Bottom half of Link Quality calculation. */
  1110. if (dev->phy.type != B43_PHYTYPE_G)
  1111. return;
  1112. /* Possible race condition: It might be possible that the user
  1113. * changed to a different channel in the meantime since we
  1114. * started the calculation. We ignore that fact, since it's
  1115. * not really that much of a problem. The background noise is
  1116. * an estimation only anyway. Slightly wrong results will get damped
  1117. * by the averaging of the 8 sample rounds. Additionally the
  1118. * value is shortlived. So it will be replaced by the next noise
  1119. * calculation round soon. */
  1120. B43_WARN_ON(!dev->noisecalc.calculation_running);
  1121. *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
  1122. if (noise[0] == 0x7F || noise[1] == 0x7F ||
  1123. noise[2] == 0x7F || noise[3] == 0x7F)
  1124. goto generate_new;
  1125. /* Get the noise samples. */
  1126. B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
  1127. i = dev->noisecalc.nr_samples;
  1128. noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  1129. noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  1130. noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  1131. noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
  1132. dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
  1133. dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
  1134. dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
  1135. dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
  1136. dev->noisecalc.nr_samples++;
  1137. if (dev->noisecalc.nr_samples == 8) {
  1138. /* Calculate the Link Quality by the noise samples. */
  1139. average = 0;
  1140. for (i = 0; i < 8; i++) {
  1141. for (j = 0; j < 4; j++)
  1142. average += dev->noisecalc.samples[i][j];
  1143. }
  1144. average /= (8 * 4);
  1145. average *= 125;
  1146. average += 64;
  1147. average /= 128;
  1148. tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
  1149. tmp = (tmp / 128) & 0x1F;
  1150. if (tmp >= 8)
  1151. average += 2;
  1152. else
  1153. average -= 25;
  1154. if (tmp == 8)
  1155. average -= 72;
  1156. else
  1157. average -= 48;
  1158. dev->stats.link_noise = average;
  1159. dev->noisecalc.calculation_running = 0;
  1160. return;
  1161. }
  1162. generate_new:
  1163. b43_generate_noise_sample(dev);
  1164. }
  1165. static void handle_irq_tbtt_indication(struct b43_wldev *dev)
  1166. {
  1167. if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
  1168. ///TODO: PS TBTT
  1169. } else {
  1170. if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
  1171. b43_power_saving_ctl_bits(dev, 0);
  1172. }
  1173. if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
  1174. dev->dfq_valid = 1;
  1175. }
  1176. static void handle_irq_atim_end(struct b43_wldev *dev)
  1177. {
  1178. if (dev->dfq_valid) {
  1179. b43_write32(dev, B43_MMIO_MACCMD,
  1180. b43_read32(dev, B43_MMIO_MACCMD)
  1181. | B43_MACCMD_DFQ_VALID);
  1182. dev->dfq_valid = 0;
  1183. }
  1184. }
  1185. static void handle_irq_pmq(struct b43_wldev *dev)
  1186. {
  1187. u32 tmp;
  1188. //TODO: AP mode.
  1189. while (1) {
  1190. tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
  1191. if (!(tmp & 0x00000008))
  1192. break;
  1193. }
  1194. /* 16bit write is odd, but correct. */
  1195. b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
  1196. }
  1197. static void b43_write_template_common(struct b43_wldev *dev,
  1198. const u8 *data, u16 size,
  1199. u16 ram_offset,
  1200. u16 shm_size_offset, u8 rate)
  1201. {
  1202. u32 i, tmp;
  1203. struct b43_plcp_hdr4 plcp;
  1204. plcp.data = 0;
  1205. b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
  1206. b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
  1207. ram_offset += sizeof(u32);
  1208. /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
  1209. * So leave the first two bytes of the next write blank.
  1210. */
  1211. tmp = (u32) (data[0]) << 16;
  1212. tmp |= (u32) (data[1]) << 24;
  1213. b43_ram_write(dev, ram_offset, tmp);
  1214. ram_offset += sizeof(u32);
  1215. for (i = 2; i < size; i += sizeof(u32)) {
  1216. tmp = (u32) (data[i + 0]);
  1217. if (i + 1 < size)
  1218. tmp |= (u32) (data[i + 1]) << 8;
  1219. if (i + 2 < size)
  1220. tmp |= (u32) (data[i + 2]) << 16;
  1221. if (i + 3 < size)
  1222. tmp |= (u32) (data[i + 3]) << 24;
  1223. b43_ram_write(dev, ram_offset + i - 2, tmp);
  1224. }
  1225. b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
  1226. size + sizeof(struct b43_plcp_hdr6));
  1227. }
  1228. /* Check if the use of the antenna that ieee80211 told us to
  1229. * use is possible. This will fall back to DEFAULT.
  1230. * "antenna_nr" is the antenna identifier we got from ieee80211. */
  1231. u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
  1232. u8 antenna_nr)
  1233. {
  1234. u8 antenna_mask;
  1235. if (antenna_nr == 0) {
  1236. /* Zero means "use default antenna". That's always OK. */
  1237. return 0;
  1238. }
  1239. /* Get the mask of available antennas. */
  1240. if (dev->phy.gmode)
  1241. antenna_mask = dev->dev->bus->sprom.ant_available_bg;
  1242. else
  1243. antenna_mask = dev->dev->bus->sprom.ant_available_a;
  1244. if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
  1245. /* This antenna is not available. Fall back to default. */
  1246. return 0;
  1247. }
  1248. return antenna_nr;
  1249. }
  1250. /* Convert a b43 antenna number value to the PHY TX control value. */
  1251. static u16 b43_antenna_to_phyctl(int antenna)
  1252. {
  1253. switch (antenna) {
  1254. case B43_ANTENNA0:
  1255. return B43_TXH_PHY_ANT0;
  1256. case B43_ANTENNA1:
  1257. return B43_TXH_PHY_ANT1;
  1258. case B43_ANTENNA2:
  1259. return B43_TXH_PHY_ANT2;
  1260. case B43_ANTENNA3:
  1261. return B43_TXH_PHY_ANT3;
  1262. case B43_ANTENNA_AUTO0:
  1263. case B43_ANTENNA_AUTO1:
  1264. return B43_TXH_PHY_ANT01AUTO;
  1265. }
  1266. B43_WARN_ON(1);
  1267. return 0;
  1268. }
  1269. static void b43_write_beacon_template(struct b43_wldev *dev,
  1270. u16 ram_offset,
  1271. u16 shm_size_offset)
  1272. {
  1273. unsigned int i, len, variable_len;
  1274. const struct ieee80211_mgmt *bcn;
  1275. const u8 *ie;
  1276. bool tim_found = 0;
  1277. unsigned int rate;
  1278. u16 ctl;
  1279. int antenna;
  1280. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
  1281. bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
  1282. len = min((size_t) dev->wl->current_beacon->len,
  1283. 0x200 - sizeof(struct b43_plcp_hdr6));
  1284. rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
  1285. b43_write_template_common(dev, (const u8 *)bcn,
  1286. len, ram_offset, shm_size_offset, rate);
  1287. /* Write the PHY TX control parameters. */
  1288. antenna = B43_ANTENNA_DEFAULT;
  1289. antenna = b43_antenna_to_phyctl(antenna);
  1290. ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
  1291. /* We can't send beacons with short preamble. Would get PHY errors. */
  1292. ctl &= ~B43_TXH_PHY_SHORTPRMBL;
  1293. ctl &= ~B43_TXH_PHY_ANT;
  1294. ctl &= ~B43_TXH_PHY_ENC;
  1295. ctl |= antenna;
  1296. if (b43_is_cck_rate(rate))
  1297. ctl |= B43_TXH_PHY_ENC_CCK;
  1298. else
  1299. ctl |= B43_TXH_PHY_ENC_OFDM;
  1300. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
  1301. /* Find the position of the TIM and the DTIM_period value
  1302. * and write them to SHM. */
  1303. ie = bcn->u.beacon.variable;
  1304. variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
  1305. for (i = 0; i < variable_len - 2; ) {
  1306. uint8_t ie_id, ie_len;
  1307. ie_id = ie[i];
  1308. ie_len = ie[i + 1];
  1309. if (ie_id == 5) {
  1310. u16 tim_position;
  1311. u16 dtim_period;
  1312. /* This is the TIM Information Element */
  1313. /* Check whether the ie_len is in the beacon data range. */
  1314. if (variable_len < ie_len + 2 + i)
  1315. break;
  1316. /* A valid TIM is at least 4 bytes long. */
  1317. if (ie_len < 4)
  1318. break;
  1319. tim_found = 1;
  1320. tim_position = sizeof(struct b43_plcp_hdr6);
  1321. tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
  1322. tim_position += i;
  1323. dtim_period = ie[i + 3];
  1324. b43_shm_write16(dev, B43_SHM_SHARED,
  1325. B43_SHM_SH_TIMBPOS, tim_position);
  1326. b43_shm_write16(dev, B43_SHM_SHARED,
  1327. B43_SHM_SH_DTIMPER, dtim_period);
  1328. break;
  1329. }
  1330. i += ie_len + 2;
  1331. }
  1332. if (!tim_found) {
  1333. /*
  1334. * If ucode wants to modify TIM do it behind the beacon, this
  1335. * will happen, for example, when doing mesh networking.
  1336. */
  1337. b43_shm_write16(dev, B43_SHM_SHARED,
  1338. B43_SHM_SH_TIMBPOS,
  1339. len + sizeof(struct b43_plcp_hdr6));
  1340. b43_shm_write16(dev, B43_SHM_SHARED,
  1341. B43_SHM_SH_DTIMPER, 0);
  1342. }
  1343. b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
  1344. }
  1345. static void b43_upload_beacon0(struct b43_wldev *dev)
  1346. {
  1347. struct b43_wl *wl = dev->wl;
  1348. if (wl->beacon0_uploaded)
  1349. return;
  1350. b43_write_beacon_template(dev, 0x68, 0x18);
  1351. wl->beacon0_uploaded = 1;
  1352. }
  1353. static void b43_upload_beacon1(struct b43_wldev *dev)
  1354. {
  1355. struct b43_wl *wl = dev->wl;
  1356. if (wl->beacon1_uploaded)
  1357. return;
  1358. b43_write_beacon_template(dev, 0x468, 0x1A);
  1359. wl->beacon1_uploaded = 1;
  1360. }
  1361. static void handle_irq_beacon(struct b43_wldev *dev)
  1362. {
  1363. struct b43_wl *wl = dev->wl;
  1364. u32 cmd, beacon0_valid, beacon1_valid;
  1365. if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
  1366. !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
  1367. return;
  1368. /* This is the bottom half of the asynchronous beacon update. */
  1369. /* Ignore interrupt in the future. */
  1370. dev->irq_mask &= ~B43_IRQ_BEACON;
  1371. cmd = b43_read32(dev, B43_MMIO_MACCMD);
  1372. beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
  1373. beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
  1374. /* Schedule interrupt manually, if busy. */
  1375. if (beacon0_valid && beacon1_valid) {
  1376. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
  1377. dev->irq_mask |= B43_IRQ_BEACON;
  1378. return;
  1379. }
  1380. if (unlikely(wl->beacon_templates_virgin)) {
  1381. /* We never uploaded a beacon before.
  1382. * Upload both templates now, but only mark one valid. */
  1383. wl->beacon_templates_virgin = 0;
  1384. b43_upload_beacon0(dev);
  1385. b43_upload_beacon1(dev);
  1386. cmd = b43_read32(dev, B43_MMIO_MACCMD);
  1387. cmd |= B43_MACCMD_BEACON0_VALID;
  1388. b43_write32(dev, B43_MMIO_MACCMD, cmd);
  1389. } else {
  1390. if (!beacon0_valid) {
  1391. b43_upload_beacon0(dev);
  1392. cmd = b43_read32(dev, B43_MMIO_MACCMD);
  1393. cmd |= B43_MACCMD_BEACON0_VALID;
  1394. b43_write32(dev, B43_MMIO_MACCMD, cmd);
  1395. } else if (!beacon1_valid) {
  1396. b43_upload_beacon1(dev);
  1397. cmd = b43_read32(dev, B43_MMIO_MACCMD);
  1398. cmd |= B43_MACCMD_BEACON1_VALID;
  1399. b43_write32(dev, B43_MMIO_MACCMD, cmd);
  1400. }
  1401. }
  1402. }
  1403. static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
  1404. {
  1405. u32 old_irq_mask = dev->irq_mask;
  1406. /* update beacon right away or defer to irq */
  1407. handle_irq_beacon(dev);
  1408. if (old_irq_mask != dev->irq_mask) {
  1409. /* The handler updated the IRQ mask. */
  1410. B43_WARN_ON(!dev->irq_mask);
  1411. if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
  1412. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
  1413. } else {
  1414. /* Device interrupts are currently disabled. That means
  1415. * we just ran the hardirq handler and scheduled the
  1416. * IRQ thread. The thread will write the IRQ mask when
  1417. * it finished, so there's nothing to do here. Writing
  1418. * the mask _here_ would incorrectly re-enable IRQs. */
  1419. }
  1420. }
  1421. }
  1422. static void b43_beacon_update_trigger_work(struct work_struct *work)
  1423. {
  1424. struct b43_wl *wl = container_of(work, struct b43_wl,
  1425. beacon_update_trigger);
  1426. struct b43_wldev *dev;
  1427. mutex_lock(&wl->mutex);
  1428. dev = wl->current_dev;
  1429. if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
  1430. if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
  1431. /* wl->mutex is enough. */
  1432. b43_do_beacon_update_trigger_work(dev);
  1433. mmiowb();
  1434. } else {
  1435. spin_lock_irq(&wl->hardirq_lock);
  1436. b43_do_beacon_update_trigger_work(dev);
  1437. mmiowb();
  1438. spin_unlock_irq(&wl->hardirq_lock);
  1439. }
  1440. }
  1441. mutex_unlock(&wl->mutex);
  1442. }
  1443. /* Asynchronously update the packet templates in template RAM.
  1444. * Locking: Requires wl->mutex to be locked. */
  1445. static void b43_update_templates(struct b43_wl *wl)
  1446. {
  1447. struct sk_buff *beacon;
  1448. /* This is the top half of the ansynchronous beacon update.
  1449. * The bottom half is the beacon IRQ.
  1450. * Beacon update must be asynchronous to avoid sending an
  1451. * invalid beacon. This can happen for example, if the firmware
  1452. * transmits a beacon while we are updating it. */
  1453. /* We could modify the existing beacon and set the aid bit in
  1454. * the TIM field, but that would probably require resizing and
  1455. * moving of data within the beacon template.
  1456. * Simply request a new beacon and let mac80211 do the hard work. */
  1457. beacon = ieee80211_beacon_get(wl->hw, wl->vif);
  1458. if (unlikely(!beacon))
  1459. return;
  1460. if (wl->current_beacon)
  1461. dev_kfree_skb_any(wl->current_beacon);
  1462. wl->current_beacon = beacon;
  1463. wl->beacon0_uploaded = 0;
  1464. wl->beacon1_uploaded = 0;
  1465. ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
  1466. }
  1467. static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
  1468. {
  1469. b43_time_lock(dev);
  1470. if (dev->dev->id.revision >= 3) {
  1471. b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
  1472. b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
  1473. } else {
  1474. b43_write16(dev, 0x606, (beacon_int >> 6));
  1475. b43_write16(dev, 0x610, beacon_int);
  1476. }
  1477. b43_time_unlock(dev);
  1478. b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
  1479. }
  1480. static void b43_handle_firmware_panic(struct b43_wldev *dev)
  1481. {
  1482. u16 reason;
  1483. /* Read the register that contains the reason code for the panic. */
  1484. reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
  1485. b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
  1486. switch (reason) {
  1487. default:
  1488. b43dbg(dev->wl, "The panic reason is unknown.\n");
  1489. /* fallthrough */
  1490. case B43_FWPANIC_DIE:
  1491. /* Do not restart the controller or firmware.
  1492. * The device is nonfunctional from now on.
  1493. * Restarting would result in this panic to trigger again,
  1494. * so we avoid that recursion. */
  1495. break;
  1496. case B43_FWPANIC_RESTART:
  1497. b43_controller_restart(dev, "Microcode panic");
  1498. break;
  1499. }
  1500. }
  1501. static void handle_irq_ucode_debug(struct b43_wldev *dev)
  1502. {
  1503. unsigned int i, cnt;
  1504. u16 reason, marker_id, marker_line;
  1505. __le16 *buf;
  1506. /* The proprietary firmware doesn't have this IRQ. */
  1507. if (!dev->fw.opensource)
  1508. return;
  1509. /* Read the register that contains the reason code for this IRQ. */
  1510. reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
  1511. switch (reason) {
  1512. case B43_DEBUGIRQ_PANIC:
  1513. b43_handle_firmware_panic(dev);
  1514. break;
  1515. case B43_DEBUGIRQ_DUMP_SHM:
  1516. if (!B43_DEBUG)
  1517. break; /* Only with driver debugging enabled. */
  1518. buf = kmalloc(4096, GFP_ATOMIC);
  1519. if (!buf) {
  1520. b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
  1521. goto out;
  1522. }
  1523. for (i = 0; i < 4096; i += 2) {
  1524. u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
  1525. buf[i / 2] = cpu_to_le16(tmp);
  1526. }
  1527. b43info(dev->wl, "Shared memory dump:\n");
  1528. print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
  1529. 16, 2, buf, 4096, 1);
  1530. kfree(buf);
  1531. break;
  1532. case B43_DEBUGIRQ_DUMP_REGS:
  1533. if (!B43_DEBUG)
  1534. break; /* Only with driver debugging enabled. */
  1535. b43info(dev->wl, "Microcode register dump:\n");
  1536. for (i = 0, cnt = 0; i < 64; i++) {
  1537. u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
  1538. if (cnt == 0)
  1539. printk(KERN_INFO);
  1540. printk("r%02u: 0x%04X ", i, tmp);
  1541. cnt++;
  1542. if (cnt == 6) {
  1543. printk("\n");
  1544. cnt = 0;
  1545. }
  1546. }
  1547. printk("\n");
  1548. break;
  1549. case B43_DEBUGIRQ_MARKER:
  1550. if (!B43_DEBUG)
  1551. break; /* Only with driver debugging enabled. */
  1552. marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
  1553. B43_MARKER_ID_REG);
  1554. marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
  1555. B43_MARKER_LINE_REG);
  1556. b43info(dev->wl, "The firmware just executed the MARKER(%u) "
  1557. "at line number %u\n",
  1558. marker_id, marker_line);
  1559. break;
  1560. default:
  1561. b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
  1562. reason);
  1563. }
  1564. out:
  1565. /* Acknowledge the debug-IRQ, so the firmware can continue. */
  1566. b43_shm_write16(dev, B43_SHM_SCRATCH,
  1567. B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
  1568. }
  1569. static void b43_do_interrupt_thread(struct b43_wldev *dev)
  1570. {
  1571. u32 reason;
  1572. u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
  1573. u32 merged_dma_reason = 0;
  1574. int i;
  1575. if (unlikely(b43_status(dev) != B43_STAT_STARTED))
  1576. return;
  1577. reason = dev->irq_reason;
  1578. for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
  1579. dma_reason[i] = dev->dma_reason[i];
  1580. merged_dma_reason |= dma_reason[i];
  1581. }
  1582. if (unlikely(reason & B43_IRQ_MAC_TXERR))
  1583. b43err(dev->wl, "MAC transmission error\n");
  1584. if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
  1585. b43err(dev->wl, "PHY transmission error\n");
  1586. rmb();
  1587. if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
  1588. atomic_set(&dev->phy.txerr_cnt,
  1589. B43_PHY_TX_BADNESS_LIMIT);
  1590. b43err(dev->wl, "Too many PHY TX errors, "
  1591. "restarting the controller\n");
  1592. b43_controller_restart(dev, "PHY TX errors");
  1593. }
  1594. }
  1595. if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
  1596. B43_DMAIRQ_NONFATALMASK))) {
  1597. if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
  1598. b43err(dev->wl, "Fatal DMA error: "
  1599. "0x%08X, 0x%08X, 0x%08X, "
  1600. "0x%08X, 0x%08X, 0x%08X\n",
  1601. dma_reason[0], dma_reason[1],
  1602. dma_reason[2], dma_reason[3],
  1603. dma_reason[4], dma_reason[5]);
  1604. b43err(dev->wl, "This device does not support DMA "
  1605. "on your system. It will now be switched to PIO.\n");
  1606. /* Fall back to PIO transfers if we get fatal DMA errors! */
  1607. dev->use_pio = 1;
  1608. b43_controller_restart(dev, "DMA error");
  1609. return;
  1610. }
  1611. if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
  1612. b43err(dev->wl, "DMA error: "
  1613. "0x%08X, 0x%08X, 0x%08X, "
  1614. "0x%08X, 0x%08X, 0x%08X\n",
  1615. dma_reason[0], dma_reason[1],
  1616. dma_reason[2], dma_reason[3],
  1617. dma_reason[4], dma_reason[5]);
  1618. }
  1619. }
  1620. if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
  1621. handle_irq_ucode_debug(dev);
  1622. if (reason & B43_IRQ_TBTT_INDI)
  1623. handle_irq_tbtt_indication(dev);
  1624. if (reason & B43_IRQ_ATIM_END)
  1625. handle_irq_atim_end(dev);
  1626. if (reason & B43_IRQ_BEACON)
  1627. handle_irq_beacon(dev);
  1628. if (reason & B43_IRQ_PMQ)
  1629. handle_irq_pmq(dev);
  1630. if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
  1631. ;/* TODO */
  1632. if (reason & B43_IRQ_NOISESAMPLE_OK)
  1633. handle_irq_noise(dev);
  1634. /* Check the DMA reason registers for received data. */
  1635. if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
  1636. if (b43_using_pio_transfers(dev))
  1637. b43_pio_rx(dev->pio.rx_queue);
  1638. else
  1639. b43_dma_rx(dev->dma.rx_ring);
  1640. }
  1641. B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
  1642. B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
  1643. B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
  1644. B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
  1645. B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
  1646. if (reason & B43_IRQ_TX_OK)
  1647. handle_irq_transmit_status(dev);
  1648. /* Re-enable interrupts on the device by restoring the current interrupt mask. */
  1649. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
  1650. #if B43_DEBUG
  1651. if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
  1652. dev->irq_count++;
  1653. for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
  1654. if (reason & (1 << i))
  1655. dev->irq_bit_count[i]++;
  1656. }
  1657. }
  1658. #endif
  1659. }
  1660. /* Interrupt thread handler. Handles device interrupts in thread context. */
  1661. static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
  1662. {
  1663. struct b43_wldev *dev = dev_id;
  1664. mutex_lock(&dev->wl->mutex);
  1665. b43_do_interrupt_thread(dev);
  1666. mmiowb();
  1667. mutex_unlock(&dev->wl->mutex);
  1668. return IRQ_HANDLED;
  1669. }
  1670. static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
  1671. {
  1672. u32 reason;
  1673. /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
  1674. * On SDIO, this runs under wl->mutex. */
  1675. reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  1676. if (reason == 0xffffffff) /* shared IRQ */
  1677. return IRQ_NONE;
  1678. reason &= dev->irq_mask;
  1679. if (!reason)
  1680. return IRQ_HANDLED;
  1681. dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
  1682. & 0x0001DC00;
  1683. dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
  1684. & 0x0000DC00;
  1685. dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
  1686. & 0x0000DC00;
  1687. dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
  1688. & 0x0001DC00;
  1689. dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
  1690. & 0x0000DC00;
  1691. /* Unused ring
  1692. dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
  1693. & 0x0000DC00;
  1694. */
  1695. /* ACK the interrupt. */
  1696. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
  1697. b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
  1698. b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
  1699. b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
  1700. b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
  1701. b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
  1702. /* Unused ring
  1703. b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
  1704. */
  1705. /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
  1706. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
  1707. /* Save the reason bitmasks for the IRQ thread handler. */
  1708. dev->irq_reason = reason;
  1709. return IRQ_WAKE_THREAD;
  1710. }
  1711. /* Interrupt handler top-half. This runs with interrupts disabled. */
  1712. static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
  1713. {
  1714. struct b43_wldev *dev = dev_id;
  1715. irqreturn_t ret;
  1716. if (unlikely(b43_status(dev) < B43_STAT_STARTED))
  1717. return IRQ_NONE;
  1718. spin_lock(&dev->wl->hardirq_lock);
  1719. ret = b43_do_interrupt(dev);
  1720. mmiowb();
  1721. spin_unlock(&dev->wl->hardirq_lock);
  1722. return ret;
  1723. }
  1724. /* SDIO interrupt handler. This runs in process context. */
  1725. static void b43_sdio_interrupt_handler(struct b43_wldev *dev)
  1726. {
  1727. struct b43_wl *wl = dev->wl;
  1728. irqreturn_t ret;
  1729. mutex_lock(&wl->mutex);
  1730. ret = b43_do_interrupt(dev);
  1731. if (ret == IRQ_WAKE_THREAD)
  1732. b43_do_interrupt_thread(dev);
  1733. mutex_unlock(&wl->mutex);
  1734. }
  1735. void b43_do_release_fw(struct b43_firmware_file *fw)
  1736. {
  1737. release_firmware(fw->data);
  1738. fw->data = NULL;
  1739. fw->filename = NULL;
  1740. }
  1741. static void b43_release_firmware(struct b43_wldev *dev)
  1742. {
  1743. b43_do_release_fw(&dev->fw.ucode);
  1744. b43_do_release_fw(&dev->fw.pcm);
  1745. b43_do_release_fw(&dev->fw.initvals);
  1746. b43_do_release_fw(&dev->fw.initvals_band);
  1747. }
  1748. static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
  1749. {
  1750. const char text[] =
  1751. "You must go to " \
  1752. "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
  1753. "and download the correct firmware for this driver version. " \
  1754. "Please carefully read all instructions on this website.\n";
  1755. if (error)
  1756. b43err(wl, text);
  1757. else
  1758. b43warn(wl, text);
  1759. }
  1760. int b43_do_request_fw(struct b43_request_fw_context *ctx,
  1761. const char *name,
  1762. struct b43_firmware_file *fw)
  1763. {
  1764. const struct firmware *blob;
  1765. struct b43_fw_header *hdr;
  1766. u32 size;
  1767. int err;
  1768. if (!name) {
  1769. /* Don't fetch anything. Free possibly cached firmware. */
  1770. /* FIXME: We should probably keep it anyway, to save some headache
  1771. * on suspend/resume with multiband devices. */
  1772. b43_do_release_fw(fw);
  1773. return 0;
  1774. }
  1775. if (fw->filename) {
  1776. if ((fw->type == ctx->req_type) &&
  1777. (strcmp(fw->filename, name) == 0))
  1778. return 0; /* Already have this fw. */
  1779. /* Free the cached firmware first. */
  1780. /* FIXME: We should probably do this later after we successfully
  1781. * got the new fw. This could reduce headache with multiband devices.
  1782. * We could also redesign this to cache the firmware for all possible
  1783. * bands all the time. */
  1784. b43_do_release_fw(fw);
  1785. }
  1786. switch (ctx->req_type) {
  1787. case B43_FWTYPE_PROPRIETARY:
  1788. snprintf(ctx->fwname, sizeof(ctx->fwname),
  1789. "b43%s/%s.fw",
  1790. modparam_fwpostfix, name);
  1791. break;
  1792. case B43_FWTYPE_OPENSOURCE:
  1793. snprintf(ctx->fwname, sizeof(ctx->fwname),
  1794. "b43-open%s/%s.fw",
  1795. modparam_fwpostfix, name);
  1796. break;
  1797. default:
  1798. B43_WARN_ON(1);
  1799. return -ENOSYS;
  1800. }
  1801. err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
  1802. if (err == -ENOENT) {
  1803. snprintf(ctx->errors[ctx->req_type],
  1804. sizeof(ctx->errors[ctx->req_type]),
  1805. "Firmware file \"%s\" not found\n", ctx->fwname);
  1806. return err;
  1807. } else if (err) {
  1808. snprintf(ctx->errors[ctx->req_type],
  1809. sizeof(ctx->errors[ctx->req_type]),
  1810. "Firmware file \"%s\" request failed (err=%d)\n",
  1811. ctx->fwname, err);
  1812. return err;
  1813. }
  1814. if (blob->size < sizeof(struct b43_fw_header))
  1815. goto err_format;
  1816. hdr = (struct b43_fw_header *)(blob->data);
  1817. switch (hdr->type) {
  1818. case B43_FW_TYPE_UCODE:
  1819. case B43_FW_TYPE_PCM:
  1820. size = be32_to_cpu(hdr->size);
  1821. if (size != blob->size - sizeof(struct b43_fw_header))
  1822. goto err_format;
  1823. /* fallthrough */
  1824. case B43_FW_TYPE_IV:
  1825. if (hdr->ver != 1)
  1826. goto err_format;
  1827. break;
  1828. default:
  1829. goto err_format;
  1830. }
  1831. fw->data = blob;
  1832. fw->filename = name;
  1833. fw->type = ctx->req_type;
  1834. return 0;
  1835. err_format:
  1836. snprintf(ctx->errors[ctx->req_type],
  1837. sizeof(ctx->errors[ctx->req_type]),
  1838. "Firmware file \"%s\" format error.\n", ctx->fwname);
  1839. release_firmware(blob);
  1840. return -EPROTO;
  1841. }
  1842. static int b43_try_request_fw(struct b43_request_fw_context *ctx)
  1843. {
  1844. struct b43_wldev *dev = ctx->dev;
  1845. struct b43_firmware *fw = &ctx->dev->fw;
  1846. const u8 rev = ctx->dev->dev->id.revision;
  1847. const char *filename;
  1848. u32 tmshigh;
  1849. int err;
  1850. /* Get microcode */
  1851. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  1852. if ((rev >= 5) && (rev <= 10))
  1853. filename = "ucode5";
  1854. else if ((rev >= 11) && (rev <= 12))
  1855. filename = "ucode11";
  1856. else if (rev == 13)
  1857. filename = "ucode13";
  1858. else if (rev == 14)
  1859. filename = "ucode14";
  1860. else if (rev >= 15)
  1861. filename = "ucode15";
  1862. else
  1863. goto err_no_ucode;
  1864. err = b43_do_request_fw(ctx, filename, &fw->ucode);
  1865. if (err)
  1866. goto err_load;
  1867. /* Get PCM code */
  1868. if ((rev >= 5) && (rev <= 10))
  1869. filename = "pcm5";
  1870. else if (rev >= 11)
  1871. filename = NULL;
  1872. else
  1873. goto err_no_pcm;
  1874. fw->pcm_request_failed = 0;
  1875. err = b43_do_request_fw(ctx, filename, &fw->pcm);
  1876. if (err == -ENOENT) {
  1877. /* We did not find a PCM file? Not fatal, but
  1878. * core rev <= 10 must do without hwcrypto then. */
  1879. fw->pcm_request_failed = 1;
  1880. } else if (err)
  1881. goto err_load;
  1882. /* Get initvals */
  1883. switch (dev->phy.type) {
  1884. case B43_PHYTYPE_A:
  1885. if ((rev >= 5) && (rev <= 10)) {
  1886. if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
  1887. filename = "a0g1initvals5";
  1888. else
  1889. filename = "a0g0initvals5";
  1890. } else
  1891. goto err_no_initvals;
  1892. break;
  1893. case B43_PHYTYPE_G:
  1894. if ((rev >= 5) && (rev <= 10))
  1895. filename = "b0g0initvals5";
  1896. else if (rev >= 13)
  1897. filename = "b0g0initvals13";
  1898. else
  1899. goto err_no_initvals;
  1900. break;
  1901. case B43_PHYTYPE_N:
  1902. if ((rev >= 11) && (rev <= 12))
  1903. filename = "n0initvals11";
  1904. else
  1905. goto err_no_initvals;
  1906. break;
  1907. case B43_PHYTYPE_LP:
  1908. if (rev == 13)
  1909. filename = "lp0initvals13";
  1910. else if (rev == 14)
  1911. filename = "lp0initvals14";
  1912. else if (rev >= 15)
  1913. filename = "lp0initvals15";
  1914. else
  1915. goto err_no_initvals;
  1916. break;
  1917. default:
  1918. goto err_no_initvals;
  1919. }
  1920. err = b43_do_request_fw(ctx, filename, &fw->initvals);
  1921. if (err)
  1922. goto err_load;
  1923. /* Get bandswitch initvals */
  1924. switch (dev->phy.type) {
  1925. case B43_PHYTYPE_A:
  1926. if ((rev >= 5) && (rev <= 10)) {
  1927. if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
  1928. filename = "a0g1bsinitvals5";
  1929. else
  1930. filename = "a0g0bsinitvals5";
  1931. } else if (rev >= 11)
  1932. filename = NULL;
  1933. else
  1934. goto err_no_initvals;
  1935. break;
  1936. case B43_PHYTYPE_G:
  1937. if ((rev >= 5) && (rev <= 10))
  1938. filename = "b0g0bsinitvals5";
  1939. else if (rev >= 11)
  1940. filename = NULL;
  1941. else
  1942. goto err_no_initvals;
  1943. break;
  1944. case B43_PHYTYPE_N:
  1945. if ((rev >= 11) && (rev <= 12))
  1946. filename = "n0bsinitvals11";
  1947. else
  1948. goto err_no_initvals;
  1949. break;
  1950. case B43_PHYTYPE_LP:
  1951. if (rev == 13)
  1952. filename = "lp0bsinitvals13";
  1953. else if (rev == 14)
  1954. filename = "lp0bsinitvals14";
  1955. else if (rev >= 15)
  1956. filename = "lp0bsinitvals15";
  1957. else
  1958. goto err_no_initvals;
  1959. break;
  1960. default:
  1961. goto err_no_initvals;
  1962. }
  1963. err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
  1964. if (err)
  1965. goto err_load;
  1966. return 0;
  1967. err_no_ucode:
  1968. err = ctx->fatal_failure = -EOPNOTSUPP;
  1969. b43err(dev->wl, "The driver does not know which firmware (ucode) "
  1970. "is required for your device (wl-core rev %u)\n", rev);
  1971. goto error;
  1972. err_no_pcm:
  1973. err = ctx->fatal_failure = -EOPNOTSUPP;
  1974. b43err(dev->wl, "The driver does not know which firmware (PCM) "
  1975. "is required for your device (wl-core rev %u)\n", rev);
  1976. goto error;
  1977. err_no_initvals:
  1978. err = ctx->fatal_failure = -EOPNOTSUPP;
  1979. b43err(dev->wl, "The driver does not know which firmware (initvals) "
  1980. "is required for your device (wl-core rev %u)\n", rev);
  1981. goto error;
  1982. err_load:
  1983. /* We failed to load this firmware image. The error message
  1984. * already is in ctx->errors. Return and let our caller decide
  1985. * what to do. */
  1986. goto error;
  1987. error:
  1988. b43_release_firmware(dev);
  1989. return err;
  1990. }
  1991. static int b43_request_firmware(struct b43_wldev *dev)
  1992. {
  1993. struct b43_request_fw_context *ctx;
  1994. unsigned int i;
  1995. int err;
  1996. const char *errmsg;
  1997. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  1998. if (!ctx)
  1999. return -ENOMEM;
  2000. ctx->dev = dev;
  2001. ctx->req_type = B43_FWTYPE_PROPRIETARY;
  2002. err = b43_try_request_fw(ctx);
  2003. if (!err)
  2004. goto out; /* Successfully loaded it. */
  2005. err = ctx->fatal_failure;
  2006. if (err)
  2007. goto out;
  2008. ctx->req_type = B43_FWTYPE_OPENSOURCE;
  2009. err = b43_try_request_fw(ctx);
  2010. if (!err)
  2011. goto out; /* Successfully loaded it. */
  2012. err = ctx->fatal_failure;
  2013. if (err)
  2014. goto out;
  2015. /* Could not find a usable firmware. Print the errors. */
  2016. for (i = 0; i < B43_NR_FWTYPES; i++) {
  2017. errmsg = ctx->errors[i];
  2018. if (strlen(errmsg))
  2019. b43err(dev->wl, errmsg);
  2020. }
  2021. b43_print_fw_helptext(dev->wl, 1);
  2022. err = -ENOENT;
  2023. out:
  2024. kfree(ctx);
  2025. return err;
  2026. }
  2027. static int b43_upload_microcode(struct b43_wldev *dev)
  2028. {
  2029. struct wiphy *wiphy = dev->wl->hw->wiphy;
  2030. const size_t hdr_len = sizeof(struct b43_fw_header);
  2031. const __be32 *data;
  2032. unsigned int i, len;
  2033. u16 fwrev, fwpatch, fwdate, fwtime;
  2034. u32 tmp, macctl;
  2035. int err = 0;
  2036. /* Jump the microcode PSM to offset 0 */
  2037. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  2038. B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
  2039. macctl |= B43_MACCTL_PSM_JMP0;
  2040. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  2041. /* Zero out all microcode PSM registers and shared memory. */
  2042. for (i = 0; i < 64; i++)
  2043. b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
  2044. for (i = 0; i < 4096; i += 2)
  2045. b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
  2046. /* Upload Microcode. */
  2047. data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
  2048. len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
  2049. b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
  2050. for (i = 0; i < len; i++) {
  2051. b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
  2052. udelay(10);
  2053. }
  2054. if (dev->fw.pcm.data) {
  2055. /* Upload PCM data. */
  2056. data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
  2057. len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
  2058. b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
  2059. b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
  2060. /* No need for autoinc bit in SHM_HW */
  2061. b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
  2062. for (i = 0; i < len; i++) {
  2063. b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
  2064. udelay(10);
  2065. }
  2066. }
  2067. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
  2068. /* Start the microcode PSM */
  2069. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  2070. macctl &= ~B43_MACCTL_PSM_JMP0;
  2071. macctl |= B43_MACCTL_PSM_RUN;
  2072. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  2073. /* Wait for the microcode to load and respond */
  2074. i = 0;
  2075. while (1) {
  2076. tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  2077. if (tmp == B43_IRQ_MAC_SUSPENDED)
  2078. break;
  2079. i++;
  2080. if (i >= 20) {
  2081. b43err(dev->wl, "Microcode not responding\n");
  2082. b43_print_fw_helptext(dev->wl, 1);
  2083. err = -ENODEV;
  2084. goto error;
  2085. }
  2086. msleep(50);
  2087. }
  2088. b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
  2089. /* Get and check the revisions. */
  2090. fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
  2091. fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
  2092. fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
  2093. fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
  2094. if (fwrev <= 0x128) {
  2095. b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
  2096. "binary drivers older than version 4.x is unsupported. "
  2097. "You must upgrade your firmware files.\n");
  2098. b43_print_fw_helptext(dev->wl, 1);
  2099. err = -EOPNOTSUPP;
  2100. goto error;
  2101. }
  2102. dev->fw.rev = fwrev;
  2103. dev->fw.patch = fwpatch;
  2104. dev->fw.opensource = (fwdate == 0xFFFF);
  2105. /* Default to use-all-queues. */
  2106. dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
  2107. dev->qos_enabled = !!modparam_qos;
  2108. /* Default to firmware/hardware crypto acceleration. */
  2109. dev->hwcrypto_enabled = 1;
  2110. if (dev->fw.opensource) {
  2111. u16 fwcapa;
  2112. /* Patchlevel info is encoded in the "time" field. */
  2113. dev->fw.patch = fwtime;
  2114. b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
  2115. dev->fw.rev, dev->fw.patch);
  2116. fwcapa = b43_fwcapa_read(dev);
  2117. if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
  2118. b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
  2119. /* Disable hardware crypto and fall back to software crypto. */
  2120. dev->hwcrypto_enabled = 0;
  2121. }
  2122. if (!(fwcapa & B43_FWCAPA_QOS)) {
  2123. b43info(dev->wl, "QoS not supported by firmware\n");
  2124. /* Disable QoS. Tweak hw->queues to 1. It will be restored before
  2125. * ieee80211_unregister to make sure the networking core can
  2126. * properly free possible resources. */
  2127. dev->wl->hw->queues = 1;
  2128. dev->qos_enabled = 0;
  2129. }
  2130. } else {
  2131. b43info(dev->wl, "Loading firmware version %u.%u "
  2132. "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
  2133. fwrev, fwpatch,
  2134. (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
  2135. (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
  2136. if (dev->fw.pcm_request_failed) {
  2137. b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
  2138. "Hardware accelerated cryptography is disabled.\n");
  2139. b43_print_fw_helptext(dev->wl, 0);
  2140. }
  2141. }
  2142. snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
  2143. dev->fw.rev, dev->fw.patch);
  2144. wiphy->hw_version = dev->dev->id.coreid;
  2145. if (b43_is_old_txhdr_format(dev)) {
  2146. /* We're over the deadline, but we keep support for old fw
  2147. * until it turns out to be in major conflict with something new. */
  2148. b43warn(dev->wl, "You are using an old firmware image. "
  2149. "Support for old firmware will be removed soon "
  2150. "(official deadline was July 2008).\n");
  2151. b43_print_fw_helptext(dev->wl, 0);
  2152. }
  2153. return 0;
  2154. error:
  2155. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  2156. macctl &= ~B43_MACCTL_PSM_RUN;
  2157. macctl |= B43_MACCTL_PSM_JMP0;
  2158. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  2159. return err;
  2160. }
  2161. static int b43_write_initvals(struct b43_wldev *dev,
  2162. const struct b43_iv *ivals,
  2163. size_t count,
  2164. size_t array_size)
  2165. {
  2166. const struct b43_iv *iv;
  2167. u16 offset;
  2168. size_t i;
  2169. bool bit32;
  2170. BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
  2171. iv = ivals;
  2172. for (i = 0; i < count; i++) {
  2173. if (array_size < sizeof(iv->offset_size))
  2174. goto err_format;
  2175. array_size -= sizeof(iv->offset_size);
  2176. offset = be16_to_cpu(iv->offset_size);
  2177. bit32 = !!(offset & B43_IV_32BIT);
  2178. offset &= B43_IV_OFFSET_MASK;
  2179. if (offset >= 0x1000)
  2180. goto err_format;
  2181. if (bit32) {
  2182. u32 value;
  2183. if (array_size < sizeof(iv->data.d32))
  2184. goto err_format;
  2185. array_size -= sizeof(iv->data.d32);
  2186. value = get_unaligned_be32(&iv->data.d32);
  2187. b43_write32(dev, offset, value);
  2188. iv = (const struct b43_iv *)((const uint8_t *)iv +
  2189. sizeof(__be16) +
  2190. sizeof(__be32));
  2191. } else {
  2192. u16 value;
  2193. if (array_size < sizeof(iv->data.d16))
  2194. goto err_format;
  2195. array_size -= sizeof(iv->data.d16);
  2196. value = be16_to_cpu(iv->data.d16);
  2197. b43_write16(dev, offset, value);
  2198. iv = (const struct b43_iv *)((const uint8_t *)iv +
  2199. sizeof(__be16) +
  2200. sizeof(__be16));
  2201. }
  2202. }
  2203. if (array_size)
  2204. goto err_format;
  2205. return 0;
  2206. err_format:
  2207. b43err(dev->wl, "Initial Values Firmware file-format error.\n");
  2208. b43_print_fw_helptext(dev->wl, 1);
  2209. return -EPROTO;
  2210. }
  2211. static int b43_upload_initvals(struct b43_wldev *dev)
  2212. {
  2213. const size_t hdr_len = sizeof(struct b43_fw_header);
  2214. const struct b43_fw_header *hdr;
  2215. struct b43_firmware *fw = &dev->fw;
  2216. const struct b43_iv *ivals;
  2217. size_t count;
  2218. int err;
  2219. hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
  2220. ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
  2221. count = be32_to_cpu(hdr->size);
  2222. err = b43_write_initvals(dev, ivals, count,
  2223. fw->initvals.data->size - hdr_len);
  2224. if (err)
  2225. goto out;
  2226. if (fw->initvals_band.data) {
  2227. hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
  2228. ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
  2229. count = be32_to_cpu(hdr->size);
  2230. err = b43_write_initvals(dev, ivals, count,
  2231. fw->initvals_band.data->size - hdr_len);
  2232. if (err)
  2233. goto out;
  2234. }
  2235. out:
  2236. return err;
  2237. }
  2238. /* Initialize the GPIOs
  2239. * http://bcm-specs.sipsolutions.net/GPIO
  2240. */
  2241. static int b43_gpio_init(struct b43_wldev *dev)
  2242. {
  2243. struct ssb_bus *bus = dev->dev->bus;
  2244. struct ssb_device *gpiodev, *pcidev = NULL;
  2245. u32 mask, set;
  2246. b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
  2247. & ~B43_MACCTL_GPOUTSMSK);
  2248. b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
  2249. | 0x000F);
  2250. mask = 0x0000001F;
  2251. set = 0x0000000F;
  2252. if (dev->dev->bus->chip_id == 0x4301) {
  2253. mask |= 0x0060;
  2254. set |= 0x0060;
  2255. }
  2256. if (0 /* FIXME: conditional unknown */ ) {
  2257. b43_write16(dev, B43_MMIO_GPIO_MASK,
  2258. b43_read16(dev, B43_MMIO_GPIO_MASK)
  2259. | 0x0100);
  2260. mask |= 0x0180;
  2261. set |= 0x0180;
  2262. }
  2263. if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
  2264. b43_write16(dev, B43_MMIO_GPIO_MASK,
  2265. b43_read16(dev, B43_MMIO_GPIO_MASK)
  2266. | 0x0200);
  2267. mask |= 0x0200;
  2268. set |= 0x0200;
  2269. }
  2270. if (dev->dev->id.revision >= 2)
  2271. mask |= 0x0010; /* FIXME: This is redundant. */
  2272. #ifdef CONFIG_SSB_DRIVER_PCICORE
  2273. pcidev = bus->pcicore.dev;
  2274. #endif
  2275. gpiodev = bus->chipco.dev ? : pcidev;
  2276. if (!gpiodev)
  2277. return 0;
  2278. ssb_write32(gpiodev, B43_GPIO_CONTROL,
  2279. (ssb_read32(gpiodev, B43_GPIO_CONTROL)
  2280. & mask) | set);
  2281. return 0;
  2282. }
  2283. /* Turn off all GPIO stuff. Call this on module unload, for example. */
  2284. static void b43_gpio_cleanup(struct b43_wldev *dev)
  2285. {
  2286. struct ssb_bus *bus = dev->dev->bus;
  2287. struct ssb_device *gpiodev, *pcidev = NULL;
  2288. #ifdef CONFIG_SSB_DRIVER_PCICORE
  2289. pcidev = bus->pcicore.dev;
  2290. #endif
  2291. gpiodev = bus->chipco.dev ? : pcidev;
  2292. if (!gpiodev)
  2293. return;
  2294. ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
  2295. }
  2296. /* http://bcm-specs.sipsolutions.net/EnableMac */
  2297. void b43_mac_enable(struct b43_wldev *dev)
  2298. {
  2299. if (b43_debug(dev, B43_DBG_FIRMWARE)) {
  2300. u16 fwstate;
  2301. fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
  2302. B43_SHM_SH_UCODESTAT);
  2303. if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
  2304. (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
  2305. b43err(dev->wl, "b43_mac_enable(): The firmware "
  2306. "should be suspended, but current state is %u\n",
  2307. fwstate);
  2308. }
  2309. }
  2310. dev->mac_suspended--;
  2311. B43_WARN_ON(dev->mac_suspended < 0);
  2312. if (dev->mac_suspended == 0) {
  2313. b43_write32(dev, B43_MMIO_MACCTL,
  2314. b43_read32(dev, B43_MMIO_MACCTL)
  2315. | B43_MACCTL_ENABLED);
  2316. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
  2317. B43_IRQ_MAC_SUSPENDED);
  2318. /* Commit writes */
  2319. b43_read32(dev, B43_MMIO_MACCTL);
  2320. b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  2321. b43_power_saving_ctl_bits(dev, 0);
  2322. }
  2323. }
  2324. /* http://bcm-specs.sipsolutions.net/SuspendMAC */
  2325. void b43_mac_suspend(struct b43_wldev *dev)
  2326. {
  2327. int i;
  2328. u32 tmp;
  2329. might_sleep();
  2330. B43_WARN_ON(dev->mac_suspended < 0);
  2331. if (dev->mac_suspended == 0) {
  2332. b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
  2333. b43_write32(dev, B43_MMIO_MACCTL,
  2334. b43_read32(dev, B43_MMIO_MACCTL)
  2335. & ~B43_MACCTL_ENABLED);
  2336. /* force pci to flush the write */
  2337. b43_read32(dev, B43_MMIO_MACCTL);
  2338. for (i = 35; i; i--) {
  2339. tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  2340. if (tmp & B43_IRQ_MAC_SUSPENDED)
  2341. goto out;
  2342. udelay(10);
  2343. }
  2344. /* Hm, it seems this will take some time. Use msleep(). */
  2345. for (i = 40; i; i--) {
  2346. tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
  2347. if (tmp & B43_IRQ_MAC_SUSPENDED)
  2348. goto out;
  2349. msleep(1);
  2350. }
  2351. b43err(dev->wl, "MAC suspend failed\n");
  2352. }
  2353. out:
  2354. dev->mac_suspended++;
  2355. }
  2356. static void b43_adjust_opmode(struct b43_wldev *dev)
  2357. {
  2358. struct b43_wl *wl = dev->wl;
  2359. u32 ctl;
  2360. u16 cfp_pretbtt;
  2361. ctl = b43_read32(dev, B43_MMIO_MACCTL);
  2362. /* Reset status to STA infrastructure mode. */
  2363. ctl &= ~B43_MACCTL_AP;
  2364. ctl &= ~B43_MACCTL_KEEP_CTL;
  2365. ctl &= ~B43_MACCTL_KEEP_BADPLCP;
  2366. ctl &= ~B43_MACCTL_KEEP_BAD;
  2367. ctl &= ~B43_MACCTL_PROMISC;
  2368. ctl &= ~B43_MACCTL_BEACPROMISC;
  2369. ctl |= B43_MACCTL_INFRA;
  2370. if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
  2371. b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
  2372. ctl |= B43_MACCTL_AP;
  2373. else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
  2374. ctl &= ~B43_MACCTL_INFRA;
  2375. if (wl->filter_flags & FIF_CONTROL)
  2376. ctl |= B43_MACCTL_KEEP_CTL;
  2377. if (wl->filter_flags & FIF_FCSFAIL)
  2378. ctl |= B43_MACCTL_KEEP_BAD;
  2379. if (wl->filter_flags & FIF_PLCPFAIL)
  2380. ctl |= B43_MACCTL_KEEP_BADPLCP;
  2381. if (wl->filter_flags & FIF_PROMISC_IN_BSS)
  2382. ctl |= B43_MACCTL_PROMISC;
  2383. if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
  2384. ctl |= B43_MACCTL_BEACPROMISC;
  2385. /* Workaround: On old hardware the HW-MAC-address-filter
  2386. * doesn't work properly, so always run promisc in filter
  2387. * it in software. */
  2388. if (dev->dev->id.revision <= 4)
  2389. ctl |= B43_MACCTL_PROMISC;
  2390. b43_write32(dev, B43_MMIO_MACCTL, ctl);
  2391. cfp_pretbtt = 2;
  2392. if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
  2393. if (dev->dev->bus->chip_id == 0x4306 &&
  2394. dev->dev->bus->chip_rev == 3)
  2395. cfp_pretbtt = 100;
  2396. else
  2397. cfp_pretbtt = 50;
  2398. }
  2399. b43_write16(dev, 0x612, cfp_pretbtt);
  2400. /* FIXME: We don't currently implement the PMQ mechanism,
  2401. * so always disable it. If we want to implement PMQ,
  2402. * we need to enable it here (clear DISCPMQ) in AP mode.
  2403. */
  2404. if (0 /* ctl & B43_MACCTL_AP */) {
  2405. b43_write32(dev, B43_MMIO_MACCTL,
  2406. b43_read32(dev, B43_MMIO_MACCTL)
  2407. & ~B43_MACCTL_DISCPMQ);
  2408. } else {
  2409. b43_write32(dev, B43_MMIO_MACCTL,
  2410. b43_read32(dev, B43_MMIO_MACCTL)
  2411. | B43_MACCTL_DISCPMQ);
  2412. }
  2413. }
  2414. static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
  2415. {
  2416. u16 offset;
  2417. if (is_ofdm) {
  2418. offset = 0x480;
  2419. offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
  2420. } else {
  2421. offset = 0x4C0;
  2422. offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
  2423. }
  2424. b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
  2425. b43_shm_read16(dev, B43_SHM_SHARED, offset));
  2426. }
  2427. static void b43_rate_memory_init(struct b43_wldev *dev)
  2428. {
  2429. switch (dev->phy.type) {
  2430. case B43_PHYTYPE_A:
  2431. case B43_PHYTYPE_G:
  2432. case B43_PHYTYPE_N:
  2433. case B43_PHYTYPE_LP:
  2434. b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
  2435. b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
  2436. b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
  2437. b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
  2438. b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
  2439. b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
  2440. b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
  2441. if (dev->phy.type == B43_PHYTYPE_A)
  2442. break;
  2443. /* fallthrough */
  2444. case B43_PHYTYPE_B:
  2445. b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
  2446. b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
  2447. b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
  2448. b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
  2449. break;
  2450. default:
  2451. B43_WARN_ON(1);
  2452. }
  2453. }
  2454. /* Set the default values for the PHY TX Control Words. */
  2455. static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
  2456. {
  2457. u16 ctl = 0;
  2458. ctl |= B43_TXH_PHY_ENC_CCK;
  2459. ctl |= B43_TXH_PHY_ANT01AUTO;
  2460. ctl |= B43_TXH_PHY_TXPWR;
  2461. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
  2462. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
  2463. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
  2464. }
  2465. /* Set the TX-Antenna for management frames sent by firmware. */
  2466. static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
  2467. {
  2468. u16 ant;
  2469. u16 tmp;
  2470. ant = b43_antenna_to_phyctl(antenna);
  2471. /* For ACK/CTS */
  2472. tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
  2473. tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
  2474. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
  2475. /* For Probe Resposes */
  2476. tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
  2477. tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
  2478. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
  2479. }
  2480. /* This is the opposite of b43_chip_init() */
  2481. static void b43_chip_exit(struct b43_wldev *dev)
  2482. {
  2483. b43_phy_exit(dev);
  2484. b43_gpio_cleanup(dev);
  2485. /* firmware is released later */
  2486. }
  2487. /* Initialize the chip
  2488. * http://bcm-specs.sipsolutions.net/ChipInit
  2489. */
  2490. static int b43_chip_init(struct b43_wldev *dev)
  2491. {
  2492. struct b43_phy *phy = &dev->phy;
  2493. int err;
  2494. u32 value32, macctl;
  2495. u16 value16;
  2496. /* Initialize the MAC control */
  2497. macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
  2498. if (dev->phy.gmode)
  2499. macctl |= B43_MACCTL_GMODE;
  2500. macctl |= B43_MACCTL_INFRA;
  2501. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  2502. err = b43_request_firmware(dev);
  2503. if (err)
  2504. goto out;
  2505. err = b43_upload_microcode(dev);
  2506. if (err)
  2507. goto out; /* firmware is released later */
  2508. err = b43_gpio_init(dev);
  2509. if (err)
  2510. goto out; /* firmware is released later */
  2511. err = b43_upload_initvals(dev);
  2512. if (err)
  2513. goto err_gpio_clean;
  2514. /* Turn the Analog on and initialize the PHY. */
  2515. phy->ops->switch_analog(dev, 1);
  2516. err = b43_phy_init(dev);
  2517. if (err)
  2518. goto err_gpio_clean;
  2519. /* Disable Interference Mitigation. */
  2520. if (phy->ops->interf_mitigation)
  2521. phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
  2522. /* Select the antennae */
  2523. if (phy->ops->set_rx_antenna)
  2524. phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
  2525. b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
  2526. if (phy->type == B43_PHYTYPE_B) {
  2527. value16 = b43_read16(dev, 0x005E);
  2528. value16 |= 0x0004;
  2529. b43_write16(dev, 0x005E, value16);
  2530. }
  2531. b43_write32(dev, 0x0100, 0x01000000);
  2532. if (dev->dev->id.revision < 5)
  2533. b43_write32(dev, 0x010C, 0x01000000);
  2534. b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
  2535. & ~B43_MACCTL_INFRA);
  2536. b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
  2537. | B43_MACCTL_INFRA);
  2538. /* Probe Response Timeout value */
  2539. /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
  2540. b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
  2541. /* Initially set the wireless operation mode. */
  2542. b43_adjust_opmode(dev);
  2543. if (dev->dev->id.revision < 3) {
  2544. b43_write16(dev, 0x060E, 0x0000);
  2545. b43_write16(dev, 0x0610, 0x8000);
  2546. b43_write16(dev, 0x0604, 0x0000);
  2547. b43_write16(dev, 0x0606, 0x0200);
  2548. } else {
  2549. b43_write32(dev, 0x0188, 0x80000000);
  2550. b43_write32(dev, 0x018C, 0x02000000);
  2551. }
  2552. b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
  2553. b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
  2554. b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
  2555. b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
  2556. b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
  2557. b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
  2558. b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
  2559. value32 = ssb_read32(dev->dev, SSB_TMSLOW);
  2560. value32 |= 0x00100000;
  2561. ssb_write32(dev->dev, SSB_TMSLOW, value32);
  2562. b43_write16(dev, B43_MMIO_POWERUP_DELAY,
  2563. dev->dev->bus->chipco.fast_pwrup_delay);
  2564. err = 0;
  2565. b43dbg(dev->wl, "Chip initialized\n");
  2566. out:
  2567. return err;
  2568. err_gpio_clean:
  2569. b43_gpio_cleanup(dev);
  2570. return err;
  2571. }
  2572. static void b43_periodic_every60sec(struct b43_wldev *dev)
  2573. {
  2574. const struct b43_phy_operations *ops = dev->phy.ops;
  2575. if (ops->pwork_60sec)
  2576. ops->pwork_60sec(dev);
  2577. /* Force check the TX power emission now. */
  2578. b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
  2579. }
  2580. static void b43_periodic_every30sec(struct b43_wldev *dev)
  2581. {
  2582. /* Update device statistics. */
  2583. b43_calculate_link_quality(dev);
  2584. }
  2585. static void b43_periodic_every15sec(struct b43_wldev *dev)
  2586. {
  2587. struct b43_phy *phy = &dev->phy;
  2588. u16 wdr;
  2589. if (dev->fw.opensource) {
  2590. /* Check if the firmware is still alive.
  2591. * It will reset the watchdog counter to 0 in its idle loop. */
  2592. wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
  2593. if (unlikely(wdr)) {
  2594. b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
  2595. b43_controller_restart(dev, "Firmware watchdog");
  2596. return;
  2597. } else {
  2598. b43_shm_write16(dev, B43_SHM_SCRATCH,
  2599. B43_WATCHDOG_REG, 1);
  2600. }
  2601. }
  2602. if (phy->ops->pwork_15sec)
  2603. phy->ops->pwork_15sec(dev);
  2604. atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
  2605. wmb();
  2606. #if B43_DEBUG
  2607. if (b43_debug(dev, B43_DBG_VERBOSESTATS)) {
  2608. unsigned int i;
  2609. b43dbg(dev->wl, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
  2610. dev->irq_count / 15,
  2611. dev->tx_count / 15,
  2612. dev->rx_count / 15);
  2613. dev->irq_count = 0;
  2614. dev->tx_count = 0;
  2615. dev->rx_count = 0;
  2616. for (i = 0; i < ARRAY_SIZE(dev->irq_bit_count); i++) {
  2617. if (dev->irq_bit_count[i]) {
  2618. b43dbg(dev->wl, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
  2619. dev->irq_bit_count[i] / 15, i, (1 << i));
  2620. dev->irq_bit_count[i] = 0;
  2621. }
  2622. }
  2623. }
  2624. #endif
  2625. }
  2626. static void do_periodic_work(struct b43_wldev *dev)
  2627. {
  2628. unsigned int state;
  2629. state = dev->periodic_state;
  2630. if (state % 4 == 0)
  2631. b43_periodic_every60sec(dev);
  2632. if (state % 2 == 0)
  2633. b43_periodic_every30sec(dev);
  2634. b43_periodic_every15sec(dev);
  2635. }
  2636. /* Periodic work locking policy:
  2637. * The whole periodic work handler is protected by
  2638. * wl->mutex. If another lock is needed somewhere in the
  2639. * pwork callchain, it's acquired in-place, where it's needed.
  2640. */
  2641. static void b43_periodic_work_handler(struct work_struct *work)
  2642. {
  2643. struct b43_wldev *dev = container_of(work, struct b43_wldev,
  2644. periodic_work.work);
  2645. struct b43_wl *wl = dev->wl;
  2646. unsigned long delay;
  2647. mutex_lock(&wl->mutex);
  2648. if (unlikely(b43_status(dev) != B43_STAT_STARTED))
  2649. goto out;
  2650. if (b43_debug(dev, B43_DBG_PWORK_STOP))
  2651. goto out_requeue;
  2652. do_periodic_work(dev);
  2653. dev->periodic_state++;
  2654. out_requeue:
  2655. if (b43_debug(dev, B43_DBG_PWORK_FAST))
  2656. delay = msecs_to_jiffies(50);
  2657. else
  2658. delay = round_jiffies_relative(HZ * 15);
  2659. ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
  2660. out:
  2661. mutex_unlock(&wl->mutex);
  2662. }
  2663. static void b43_periodic_tasks_setup(struct b43_wldev *dev)
  2664. {
  2665. struct delayed_work *work = &dev->periodic_work;
  2666. dev->periodic_state = 0;
  2667. INIT_DELAYED_WORK(work, b43_periodic_work_handler);
  2668. ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
  2669. }
  2670. /* Check if communication with the device works correctly. */
  2671. static int b43_validate_chipaccess(struct b43_wldev *dev)
  2672. {
  2673. u32 v, backup0, backup4;
  2674. backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
  2675. backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
  2676. /* Check for read/write and endianness problems. */
  2677. b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
  2678. if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
  2679. goto error;
  2680. b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
  2681. if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
  2682. goto error;
  2683. /* Check if unaligned 32bit SHM_SHARED access works properly.
  2684. * However, don't bail out on failure, because it's noncritical. */
  2685. b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
  2686. b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
  2687. b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
  2688. b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
  2689. if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
  2690. b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
  2691. b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
  2692. if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
  2693. b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
  2694. b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
  2695. b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
  2696. b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
  2697. b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
  2698. b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
  2699. if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
  2700. /* The 32bit register shadows the two 16bit registers
  2701. * with update sideeffects. Validate this. */
  2702. b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
  2703. b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
  2704. if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
  2705. goto error;
  2706. if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
  2707. goto error;
  2708. }
  2709. b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
  2710. v = b43_read32(dev, B43_MMIO_MACCTL);
  2711. v |= B43_MACCTL_GMODE;
  2712. if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
  2713. goto error;
  2714. return 0;
  2715. error:
  2716. b43err(dev->wl, "Failed to validate the chipaccess\n");
  2717. return -ENODEV;
  2718. }
  2719. static void b43_security_init(struct b43_wldev *dev)
  2720. {
  2721. dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
  2722. /* KTP is a word address, but we address SHM bytewise.
  2723. * So multiply by two.
  2724. */
  2725. dev->ktp *= 2;
  2726. /* Number of RCMTA address slots */
  2727. b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
  2728. /* Clear the key memory. */
  2729. b43_clear_keys(dev);
  2730. }
  2731. #ifdef CONFIG_B43_HWRNG
  2732. static int b43_rng_read(struct hwrng *rng, u32 *data)
  2733. {
  2734. struct b43_wl *wl = (struct b43_wl *)rng->priv;
  2735. struct b43_wldev *dev;
  2736. int count = -ENODEV;
  2737. mutex_lock(&wl->mutex);
  2738. dev = wl->current_dev;
  2739. if (likely(dev && b43_status(dev) >= B43_STAT_INITIALIZED)) {
  2740. *data = b43_read16(dev, B43_MMIO_RNG);
  2741. count = sizeof(u16);
  2742. }
  2743. mutex_unlock(&wl->mutex);
  2744. return count;
  2745. }
  2746. #endif /* CONFIG_B43_HWRNG */
  2747. static void b43_rng_exit(struct b43_wl *wl)
  2748. {
  2749. #ifdef CONFIG_B43_HWRNG
  2750. if (wl->rng_initialized)
  2751. hwrng_unregister(&wl->rng);
  2752. #endif /* CONFIG_B43_HWRNG */
  2753. }
  2754. static int b43_rng_init(struct b43_wl *wl)
  2755. {
  2756. int err = 0;
  2757. #ifdef CONFIG_B43_HWRNG
  2758. snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
  2759. "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
  2760. wl->rng.name = wl->rng_name;
  2761. wl->rng.data_read = b43_rng_read;
  2762. wl->rng.priv = (unsigned long)wl;
  2763. wl->rng_initialized = 1;
  2764. err = hwrng_register(&wl->rng);
  2765. if (err) {
  2766. wl->rng_initialized = 0;
  2767. b43err(wl, "Failed to register the random "
  2768. "number generator (%d)\n", err);
  2769. }
  2770. #endif /* CONFIG_B43_HWRNG */
  2771. return err;
  2772. }
  2773. static void b43_tx_work(struct work_struct *work)
  2774. {
  2775. struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
  2776. struct b43_wldev *dev;
  2777. struct sk_buff *skb;
  2778. int err = 0;
  2779. mutex_lock(&wl->mutex);
  2780. dev = wl->current_dev;
  2781. if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
  2782. mutex_unlock(&wl->mutex);
  2783. return;
  2784. }
  2785. while (skb_queue_len(&wl->tx_queue)) {
  2786. skb = skb_dequeue(&wl->tx_queue);
  2787. if (b43_using_pio_transfers(dev))
  2788. err = b43_pio_tx(dev, skb);
  2789. else
  2790. err = b43_dma_tx(dev, skb);
  2791. if (unlikely(err))
  2792. dev_kfree_skb(skb); /* Drop it */
  2793. }
  2794. #if B43_DEBUG
  2795. dev->tx_count++;
  2796. #endif
  2797. mutex_unlock(&wl->mutex);
  2798. }
  2799. static int b43_op_tx(struct ieee80211_hw *hw,
  2800. struct sk_buff *skb)
  2801. {
  2802. struct b43_wl *wl = hw_to_b43_wl(hw);
  2803. if (unlikely(skb->len < 2 + 2 + 6)) {
  2804. /* Too short, this can't be a valid frame. */
  2805. dev_kfree_skb_any(skb);
  2806. return NETDEV_TX_OK;
  2807. }
  2808. B43_WARN_ON(skb_shinfo(skb)->nr_frags);
  2809. skb_queue_tail(&wl->tx_queue, skb);
  2810. ieee80211_queue_work(wl->hw, &wl->tx_work);
  2811. return NETDEV_TX_OK;
  2812. }
  2813. static void b43_qos_params_upload(struct b43_wldev *dev,
  2814. const struct ieee80211_tx_queue_params *p,
  2815. u16 shm_offset)
  2816. {
  2817. u16 params[B43_NR_QOSPARAMS];
  2818. int bslots, tmp;
  2819. unsigned int i;
  2820. if (!dev->qos_enabled)
  2821. return;
  2822. bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
  2823. memset(&params, 0, sizeof(params));
  2824. params[B43_QOSPARAM_TXOP] = p->txop * 32;
  2825. params[B43_QOSPARAM_CWMIN] = p->cw_min;
  2826. params[B43_QOSPARAM_CWMAX] = p->cw_max;
  2827. params[B43_QOSPARAM_CWCUR] = p->cw_min;
  2828. params[B43_QOSPARAM_AIFS] = p->aifs;
  2829. params[B43_QOSPARAM_BSLOTS] = bslots;
  2830. params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
  2831. for (i = 0; i < ARRAY_SIZE(params); i++) {
  2832. if (i == B43_QOSPARAM_STATUS) {
  2833. tmp = b43_shm_read16(dev, B43_SHM_SHARED,
  2834. shm_offset + (i * 2));
  2835. /* Mark the parameters as updated. */
  2836. tmp |= 0x100;
  2837. b43_shm_write16(dev, B43_SHM_SHARED,
  2838. shm_offset + (i * 2),
  2839. tmp);
  2840. } else {
  2841. b43_shm_write16(dev, B43_SHM_SHARED,
  2842. shm_offset + (i * 2),
  2843. params[i]);
  2844. }
  2845. }
  2846. }
  2847. /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
  2848. static const u16 b43_qos_shm_offsets[] = {
  2849. /* [mac80211-queue-nr] = SHM_OFFSET, */
  2850. [0] = B43_QOS_VOICE,
  2851. [1] = B43_QOS_VIDEO,
  2852. [2] = B43_QOS_BESTEFFORT,
  2853. [3] = B43_QOS_BACKGROUND,
  2854. };
  2855. /* Update all QOS parameters in hardware. */
  2856. static void b43_qos_upload_all(struct b43_wldev *dev)
  2857. {
  2858. struct b43_wl *wl = dev->wl;
  2859. struct b43_qos_params *params;
  2860. unsigned int i;
  2861. if (!dev->qos_enabled)
  2862. return;
  2863. BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
  2864. ARRAY_SIZE(wl->qos_params));
  2865. b43_mac_suspend(dev);
  2866. for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
  2867. params = &(wl->qos_params[i]);
  2868. b43_qos_params_upload(dev, &(params->p),
  2869. b43_qos_shm_offsets[i]);
  2870. }
  2871. b43_mac_enable(dev);
  2872. }
  2873. static void b43_qos_clear(struct b43_wl *wl)
  2874. {
  2875. struct b43_qos_params *params;
  2876. unsigned int i;
  2877. /* Initialize QoS parameters to sane defaults. */
  2878. BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
  2879. ARRAY_SIZE(wl->qos_params));
  2880. for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
  2881. params = &(wl->qos_params[i]);
  2882. switch (b43_qos_shm_offsets[i]) {
  2883. case B43_QOS_VOICE:
  2884. params->p.txop = 0;
  2885. params->p.aifs = 2;
  2886. params->p.cw_min = 0x0001;
  2887. params->p.cw_max = 0x0001;
  2888. break;
  2889. case B43_QOS_VIDEO:
  2890. params->p.txop = 0;
  2891. params->p.aifs = 2;
  2892. params->p.cw_min = 0x0001;
  2893. params->p.cw_max = 0x0001;
  2894. break;
  2895. case B43_QOS_BESTEFFORT:
  2896. params->p.txop = 0;
  2897. params->p.aifs = 3;
  2898. params->p.cw_min = 0x0001;
  2899. params->p.cw_max = 0x03FF;
  2900. break;
  2901. case B43_QOS_BACKGROUND:
  2902. params->p.txop = 0;
  2903. params->p.aifs = 7;
  2904. params->p.cw_min = 0x0001;
  2905. params->p.cw_max = 0x03FF;
  2906. break;
  2907. default:
  2908. B43_WARN_ON(1);
  2909. }
  2910. }
  2911. }
  2912. /* Initialize the core's QOS capabilities */
  2913. static void b43_qos_init(struct b43_wldev *dev)
  2914. {
  2915. if (!dev->qos_enabled) {
  2916. /* Disable QOS support. */
  2917. b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_EDCF);
  2918. b43_write16(dev, B43_MMIO_IFSCTL,
  2919. b43_read16(dev, B43_MMIO_IFSCTL)
  2920. & ~B43_MMIO_IFSCTL_USE_EDCF);
  2921. b43dbg(dev->wl, "QoS disabled\n");
  2922. return;
  2923. }
  2924. /* Upload the current QOS parameters. */
  2925. b43_qos_upload_all(dev);
  2926. /* Enable QOS support. */
  2927. b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
  2928. b43_write16(dev, B43_MMIO_IFSCTL,
  2929. b43_read16(dev, B43_MMIO_IFSCTL)
  2930. | B43_MMIO_IFSCTL_USE_EDCF);
  2931. b43dbg(dev->wl, "QoS enabled\n");
  2932. }
  2933. static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
  2934. const struct ieee80211_tx_queue_params *params)
  2935. {
  2936. struct b43_wl *wl = hw_to_b43_wl(hw);
  2937. struct b43_wldev *dev;
  2938. unsigned int queue = (unsigned int)_queue;
  2939. int err = -ENODEV;
  2940. if (queue >= ARRAY_SIZE(wl->qos_params)) {
  2941. /* Queue not available or don't support setting
  2942. * params on this queue. Return success to not
  2943. * confuse mac80211. */
  2944. return 0;
  2945. }
  2946. BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
  2947. ARRAY_SIZE(wl->qos_params));
  2948. mutex_lock(&wl->mutex);
  2949. dev = wl->current_dev;
  2950. if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
  2951. goto out_unlock;
  2952. memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
  2953. b43_mac_suspend(dev);
  2954. b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
  2955. b43_qos_shm_offsets[queue]);
  2956. b43_mac_enable(dev);
  2957. err = 0;
  2958. out_unlock:
  2959. mutex_unlock(&wl->mutex);
  2960. return err;
  2961. }
  2962. static int b43_op_get_stats(struct ieee80211_hw *hw,
  2963. struct ieee80211_low_level_stats *stats)
  2964. {
  2965. struct b43_wl *wl = hw_to_b43_wl(hw);
  2966. mutex_lock(&wl->mutex);
  2967. memcpy(stats, &wl->ieee_stats, sizeof(*stats));
  2968. mutex_unlock(&wl->mutex);
  2969. return 0;
  2970. }
  2971. static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
  2972. {
  2973. struct b43_wl *wl = hw_to_b43_wl(hw);
  2974. struct b43_wldev *dev;
  2975. u64 tsf;
  2976. mutex_lock(&wl->mutex);
  2977. dev = wl->current_dev;
  2978. if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
  2979. b43_tsf_read(dev, &tsf);
  2980. else
  2981. tsf = 0;
  2982. mutex_unlock(&wl->mutex);
  2983. return tsf;
  2984. }
  2985. static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  2986. {
  2987. struct b43_wl *wl = hw_to_b43_wl(hw);
  2988. struct b43_wldev *dev;
  2989. mutex_lock(&wl->mutex);
  2990. dev = wl->current_dev;
  2991. if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
  2992. b43_tsf_write(dev, tsf);
  2993. mutex_unlock(&wl->mutex);
  2994. }
  2995. static void b43_put_phy_into_reset(struct b43_wldev *dev)
  2996. {
  2997. struct ssb_device *sdev = dev->dev;
  2998. u32 tmslow;
  2999. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  3000. tmslow &= ~B43_TMSLOW_GMODE;
  3001. tmslow |= B43_TMSLOW_PHYRESET;
  3002. tmslow |= SSB_TMSLOW_FGC;
  3003. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  3004. msleep(1);
  3005. tmslow = ssb_read32(sdev, SSB_TMSLOW);
  3006. tmslow &= ~SSB_TMSLOW_FGC;
  3007. tmslow |= B43_TMSLOW_PHYRESET;
  3008. ssb_write32(sdev, SSB_TMSLOW, tmslow);
  3009. msleep(1);
  3010. }
  3011. static const char *band_to_string(enum ieee80211_band band)
  3012. {
  3013. switch (band) {
  3014. case IEEE80211_BAND_5GHZ:
  3015. return "5";
  3016. case IEEE80211_BAND_2GHZ:
  3017. return "2.4";
  3018. default:
  3019. break;
  3020. }
  3021. B43_WARN_ON(1);
  3022. return "";
  3023. }
  3024. /* Expects wl->mutex locked */
  3025. static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
  3026. {
  3027. struct b43_wldev *up_dev = NULL;
  3028. struct b43_wldev *down_dev;
  3029. struct b43_wldev *d;
  3030. int err;
  3031. bool uninitialized_var(gmode);
  3032. int prev_status;
  3033. /* Find a device and PHY which supports the band. */
  3034. list_for_each_entry(d, &wl->devlist, list) {
  3035. switch (chan->band) {
  3036. case IEEE80211_BAND_5GHZ:
  3037. if (d->phy.supports_5ghz) {
  3038. up_dev = d;
  3039. gmode = 0;
  3040. }
  3041. break;
  3042. case IEEE80211_BAND_2GHZ:
  3043. if (d->phy.supports_2ghz) {
  3044. up_dev = d;
  3045. gmode = 1;
  3046. }
  3047. break;
  3048. default:
  3049. B43_WARN_ON(1);
  3050. return -EINVAL;
  3051. }
  3052. if (up_dev)
  3053. break;
  3054. }
  3055. if (!up_dev) {
  3056. b43err(wl, "Could not find a device for %s-GHz band operation\n",
  3057. band_to_string(chan->band));
  3058. return -ENODEV;
  3059. }
  3060. if ((up_dev == wl->current_dev) &&
  3061. (!!wl->current_dev->phy.gmode == !!gmode)) {
  3062. /* This device is already running. */
  3063. return 0;
  3064. }
  3065. b43dbg(wl, "Switching to %s-GHz band\n",
  3066. band_to_string(chan->band));
  3067. down_dev = wl->current_dev;
  3068. prev_status = b43_status(down_dev);
  3069. /* Shutdown the currently running core. */
  3070. if (prev_status >= B43_STAT_STARTED)
  3071. down_dev = b43_wireless_core_stop(down_dev);
  3072. if (prev_status >= B43_STAT_INITIALIZED)
  3073. b43_wireless_core_exit(down_dev);
  3074. if (down_dev != up_dev) {
  3075. /* We switch to a different core, so we put PHY into
  3076. * RESET on the old core. */
  3077. b43_put_phy_into_reset(down_dev);
  3078. }
  3079. /* Now start the new core. */
  3080. up_dev->phy.gmode = gmode;
  3081. if (prev_status >= B43_STAT_INITIALIZED) {
  3082. err = b43_wireless_core_init(up_dev);
  3083. if (err) {
  3084. b43err(wl, "Fatal: Could not initialize device for "
  3085. "selected %s-GHz band\n",
  3086. band_to_string(chan->band));
  3087. goto init_failure;
  3088. }
  3089. }
  3090. if (prev_status >= B43_STAT_STARTED) {
  3091. err = b43_wireless_core_start(up_dev);
  3092. if (err) {
  3093. b43err(wl, "Fatal: Coult not start device for "
  3094. "selected %s-GHz band\n",
  3095. band_to_string(chan->band));
  3096. b43_wireless_core_exit(up_dev);
  3097. goto init_failure;
  3098. }
  3099. }
  3100. B43_WARN_ON(b43_status(up_dev) != prev_status);
  3101. wl->current_dev = up_dev;
  3102. return 0;
  3103. init_failure:
  3104. /* Whoops, failed to init the new core. No core is operating now. */
  3105. wl->current_dev = NULL;
  3106. return err;
  3107. }
  3108. /* Write the short and long frame retry limit values. */
  3109. static void b43_set_retry_limits(struct b43_wldev *dev,
  3110. unsigned int short_retry,
  3111. unsigned int long_retry)
  3112. {
  3113. /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
  3114. * the chip-internal counter. */
  3115. short_retry = min(short_retry, (unsigned int)0xF);
  3116. long_retry = min(long_retry, (unsigned int)0xF);
  3117. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
  3118. short_retry);
  3119. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
  3120. long_retry);
  3121. }
  3122. static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
  3123. {
  3124. struct b43_wl *wl = hw_to_b43_wl(hw);
  3125. struct b43_wldev *dev;
  3126. struct b43_phy *phy;
  3127. struct ieee80211_conf *conf = &hw->conf;
  3128. int antenna;
  3129. int err = 0;
  3130. mutex_lock(&wl->mutex);
  3131. /* Switch the band (if necessary). This might change the active core. */
  3132. err = b43_switch_band(wl, conf->channel);
  3133. if (err)
  3134. goto out_unlock_mutex;
  3135. dev = wl->current_dev;
  3136. phy = &dev->phy;
  3137. if (conf_is_ht(conf))
  3138. phy->is_40mhz =
  3139. (conf_is_ht40_minus(conf) || conf_is_ht40_plus(conf));
  3140. else
  3141. phy->is_40mhz = false;
  3142. b43_mac_suspend(dev);
  3143. if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
  3144. b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
  3145. conf->long_frame_max_tx_count);
  3146. changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
  3147. if (!changed)
  3148. goto out_mac_enable;
  3149. /* Switch to the requested channel.
  3150. * The firmware takes care of races with the TX handler. */
  3151. if (conf->channel->hw_value != phy->channel)
  3152. b43_switch_channel(dev, conf->channel->hw_value);
  3153. dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
  3154. /* Adjust the desired TX power level. */
  3155. if (conf->power_level != 0) {
  3156. if (conf->power_level != phy->desired_txpower) {
  3157. phy->desired_txpower = conf->power_level;
  3158. b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
  3159. B43_TXPWR_IGNORE_TSSI);
  3160. }
  3161. }
  3162. /* Antennas for RX and management frame TX. */
  3163. antenna = B43_ANTENNA_DEFAULT;
  3164. b43_mgmtframe_txantenna(dev, antenna);
  3165. antenna = B43_ANTENNA_DEFAULT;
  3166. if (phy->ops->set_rx_antenna)
  3167. phy->ops->set_rx_antenna(dev, antenna);
  3168. if (wl->radio_enabled != phy->radio_on) {
  3169. if (wl->radio_enabled) {
  3170. b43_software_rfkill(dev, false);
  3171. b43info(dev->wl, "Radio turned on by software\n");
  3172. if (!dev->radio_hw_enable) {
  3173. b43info(dev->wl, "The hardware RF-kill button "
  3174. "still turns the radio physically off. "
  3175. "Press the button to turn it on.\n");
  3176. }
  3177. } else {
  3178. b43_software_rfkill(dev, true);
  3179. b43info(dev->wl, "Radio turned off by software\n");
  3180. }
  3181. }
  3182. out_mac_enable:
  3183. b43_mac_enable(dev);
  3184. out_unlock_mutex:
  3185. mutex_unlock(&wl->mutex);
  3186. return err;
  3187. }
  3188. static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
  3189. {
  3190. struct ieee80211_supported_band *sband =
  3191. dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
  3192. struct ieee80211_rate *rate;
  3193. int i;
  3194. u16 basic, direct, offset, basic_offset, rateptr;
  3195. for (i = 0; i < sband->n_bitrates; i++) {
  3196. rate = &sband->bitrates[i];
  3197. if (b43_is_cck_rate(rate->hw_value)) {
  3198. direct = B43_SHM_SH_CCKDIRECT;
  3199. basic = B43_SHM_SH_CCKBASIC;
  3200. offset = b43_plcp_get_ratecode_cck(rate->hw_value);
  3201. offset &= 0xF;
  3202. } else {
  3203. direct = B43_SHM_SH_OFDMDIRECT;
  3204. basic = B43_SHM_SH_OFDMBASIC;
  3205. offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
  3206. offset &= 0xF;
  3207. }
  3208. rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
  3209. if (b43_is_cck_rate(rate->hw_value)) {
  3210. basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
  3211. basic_offset &= 0xF;
  3212. } else {
  3213. basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
  3214. basic_offset &= 0xF;
  3215. }
  3216. /*
  3217. * Get the pointer that we need to point to
  3218. * from the direct map
  3219. */
  3220. rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
  3221. direct + 2 * basic_offset);
  3222. /* and write it to the basic map */
  3223. b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
  3224. rateptr);
  3225. }
  3226. }
  3227. static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
  3228. struct ieee80211_vif *vif,
  3229. struct ieee80211_bss_conf *conf,
  3230. u32 changed)
  3231. {
  3232. struct b43_wl *wl = hw_to_b43_wl(hw);
  3233. struct b43_wldev *dev;
  3234. mutex_lock(&wl->mutex);
  3235. dev = wl->current_dev;
  3236. if (!dev || b43_status(dev) < B43_STAT_STARTED)
  3237. goto out_unlock_mutex;
  3238. B43_WARN_ON(wl->vif != vif);
  3239. if (changed & BSS_CHANGED_BSSID) {
  3240. if (conf->bssid)
  3241. memcpy(wl->bssid, conf->bssid, ETH_ALEN);
  3242. else
  3243. memset(wl->bssid, 0, ETH_ALEN);
  3244. }
  3245. if (b43_status(dev) >= B43_STAT_INITIALIZED) {
  3246. if (changed & BSS_CHANGED_BEACON &&
  3247. (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
  3248. b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
  3249. b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
  3250. b43_update_templates(wl);
  3251. if (changed & BSS_CHANGED_BSSID)
  3252. b43_write_mac_bssid_templates(dev);
  3253. }
  3254. b43_mac_suspend(dev);
  3255. /* Update templates for AP/mesh mode. */
  3256. if (changed & BSS_CHANGED_BEACON_INT &&
  3257. (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
  3258. b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
  3259. b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
  3260. b43_set_beacon_int(dev, conf->beacon_int);
  3261. if (changed & BSS_CHANGED_BASIC_RATES)
  3262. b43_update_basic_rates(dev, conf->basic_rates);
  3263. if (changed & BSS_CHANGED_ERP_SLOT) {
  3264. if (conf->use_short_slot)
  3265. b43_short_slot_timing_enable(dev);
  3266. else
  3267. b43_short_slot_timing_disable(dev);
  3268. }
  3269. b43_mac_enable(dev);
  3270. out_unlock_mutex:
  3271. mutex_unlock(&wl->mutex);
  3272. }
  3273. static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  3274. struct ieee80211_vif *vif, struct ieee80211_sta *sta,
  3275. struct ieee80211_key_conf *key)
  3276. {
  3277. struct b43_wl *wl = hw_to_b43_wl(hw);
  3278. struct b43_wldev *dev;
  3279. u8 algorithm;
  3280. u8 index;
  3281. int err;
  3282. static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
  3283. if (modparam_nohwcrypt)
  3284. return -ENOSPC; /* User disabled HW-crypto */
  3285. mutex_lock(&wl->mutex);
  3286. dev = wl->current_dev;
  3287. err = -ENODEV;
  3288. if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
  3289. goto out_unlock;
  3290. if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
  3291. /* We don't have firmware for the crypto engine.
  3292. * Must use software-crypto. */
  3293. err = -EOPNOTSUPP;
  3294. goto out_unlock;
  3295. }
  3296. err = -EINVAL;
  3297. switch (key->cipher) {
  3298. case WLAN_CIPHER_SUITE_WEP40:
  3299. algorithm = B43_SEC_ALGO_WEP40;
  3300. break;
  3301. case WLAN_CIPHER_SUITE_WEP104:
  3302. algorithm = B43_SEC_ALGO_WEP104;
  3303. break;
  3304. case WLAN_CIPHER_SUITE_TKIP:
  3305. algorithm = B43_SEC_ALGO_TKIP;
  3306. break;
  3307. case WLAN_CIPHER_SUITE_CCMP:
  3308. algorithm = B43_SEC_ALGO_AES;
  3309. break;
  3310. default:
  3311. B43_WARN_ON(1);
  3312. goto out_unlock;
  3313. }
  3314. index = (u8) (key->keyidx);
  3315. if (index > 3)
  3316. goto out_unlock;
  3317. switch (cmd) {
  3318. case SET_KEY:
  3319. if (algorithm == B43_SEC_ALGO_TKIP &&
  3320. (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
  3321. !modparam_hwtkip)) {
  3322. /* We support only pairwise key */
  3323. err = -EOPNOTSUPP;
  3324. goto out_unlock;
  3325. }
  3326. if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
  3327. if (WARN_ON(!sta)) {
  3328. err = -EOPNOTSUPP;
  3329. goto out_unlock;
  3330. }
  3331. /* Pairwise key with an assigned MAC address. */
  3332. err = b43_key_write(dev, -1, algorithm,
  3333. key->key, key->keylen,
  3334. sta->addr, key);
  3335. } else {
  3336. /* Group key */
  3337. err = b43_key_write(dev, index, algorithm,
  3338. key->key, key->keylen, NULL, key);
  3339. }
  3340. if (err)
  3341. goto out_unlock;
  3342. if (algorithm == B43_SEC_ALGO_WEP40 ||
  3343. algorithm == B43_SEC_ALGO_WEP104) {
  3344. b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
  3345. } else {
  3346. b43_hf_write(dev,
  3347. b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
  3348. }
  3349. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  3350. if (algorithm == B43_SEC_ALGO_TKIP)
  3351. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  3352. break;
  3353. case DISABLE_KEY: {
  3354. err = b43_key_clear(dev, key->hw_key_idx);
  3355. if (err)
  3356. goto out_unlock;
  3357. break;
  3358. }
  3359. default:
  3360. B43_WARN_ON(1);
  3361. }
  3362. out_unlock:
  3363. if (!err) {
  3364. b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
  3365. "mac: %pM\n",
  3366. cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
  3367. sta ? sta->addr : bcast_addr);
  3368. b43_dump_keymemory(dev);
  3369. }
  3370. mutex_unlock(&wl->mutex);
  3371. return err;
  3372. }
  3373. static void b43_op_configure_filter(struct ieee80211_hw *hw,
  3374. unsigned int changed, unsigned int *fflags,
  3375. u64 multicast)
  3376. {
  3377. struct b43_wl *wl = hw_to_b43_wl(hw);
  3378. struct b43_wldev *dev;
  3379. mutex_lock(&wl->mutex);
  3380. dev = wl->current_dev;
  3381. if (!dev) {
  3382. *fflags = 0;
  3383. goto out_unlock;
  3384. }
  3385. *fflags &= FIF_PROMISC_IN_BSS |
  3386. FIF_ALLMULTI |
  3387. FIF_FCSFAIL |
  3388. FIF_PLCPFAIL |
  3389. FIF_CONTROL |
  3390. FIF_OTHER_BSS |
  3391. FIF_BCN_PRBRESP_PROMISC;
  3392. changed &= FIF_PROMISC_IN_BSS |
  3393. FIF_ALLMULTI |
  3394. FIF_FCSFAIL |
  3395. FIF_PLCPFAIL |
  3396. FIF_CONTROL |
  3397. FIF_OTHER_BSS |
  3398. FIF_BCN_PRBRESP_PROMISC;
  3399. wl->filter_flags = *fflags;
  3400. if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
  3401. b43_adjust_opmode(dev);
  3402. out_unlock:
  3403. mutex_unlock(&wl->mutex);
  3404. }
  3405. /* Locking: wl->mutex
  3406. * Returns the current dev. This might be different from the passed in dev,
  3407. * because the core might be gone away while we unlocked the mutex. */
  3408. static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
  3409. {
  3410. struct b43_wl *wl = dev->wl;
  3411. struct b43_wldev *orig_dev;
  3412. u32 mask;
  3413. redo:
  3414. if (!dev || b43_status(dev) < B43_STAT_STARTED)
  3415. return dev;
  3416. /* Cancel work. Unlock to avoid deadlocks. */
  3417. mutex_unlock(&wl->mutex);
  3418. cancel_delayed_work_sync(&dev->periodic_work);
  3419. cancel_work_sync(&wl->tx_work);
  3420. mutex_lock(&wl->mutex);
  3421. dev = wl->current_dev;
  3422. if (!dev || b43_status(dev) < B43_STAT_STARTED) {
  3423. /* Whoops, aliens ate up the device while we were unlocked. */
  3424. return dev;
  3425. }
  3426. /* Disable interrupts on the device. */
  3427. b43_set_status(dev, B43_STAT_INITIALIZED);
  3428. if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
  3429. /* wl->mutex is locked. That is enough. */
  3430. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
  3431. b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
  3432. } else {
  3433. spin_lock_irq(&wl->hardirq_lock);
  3434. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
  3435. b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
  3436. spin_unlock_irq(&wl->hardirq_lock);
  3437. }
  3438. /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
  3439. orig_dev = dev;
  3440. mutex_unlock(&wl->mutex);
  3441. if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
  3442. b43_sdio_free_irq(dev);
  3443. } else {
  3444. synchronize_irq(dev->dev->irq);
  3445. free_irq(dev->dev->irq, dev);
  3446. }
  3447. mutex_lock(&wl->mutex);
  3448. dev = wl->current_dev;
  3449. if (!dev)
  3450. return dev;
  3451. if (dev != orig_dev) {
  3452. if (b43_status(dev) >= B43_STAT_STARTED)
  3453. goto redo;
  3454. return dev;
  3455. }
  3456. mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
  3457. B43_WARN_ON(mask != 0xFFFFFFFF && mask);
  3458. /* Drain the TX queue */
  3459. while (skb_queue_len(&wl->tx_queue))
  3460. dev_kfree_skb(skb_dequeue(&wl->tx_queue));
  3461. b43_mac_suspend(dev);
  3462. b43_leds_exit(dev);
  3463. b43dbg(wl, "Wireless interface stopped\n");
  3464. return dev;
  3465. }
  3466. /* Locking: wl->mutex */
  3467. static int b43_wireless_core_start(struct b43_wldev *dev)
  3468. {
  3469. int err;
  3470. B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
  3471. drain_txstatus_queue(dev);
  3472. if (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) {
  3473. err = b43_sdio_request_irq(dev, b43_sdio_interrupt_handler);
  3474. if (err) {
  3475. b43err(dev->wl, "Cannot request SDIO IRQ\n");
  3476. goto out;
  3477. }
  3478. } else {
  3479. err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
  3480. b43_interrupt_thread_handler,
  3481. IRQF_SHARED, KBUILD_MODNAME, dev);
  3482. if (err) {
  3483. b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
  3484. goto out;
  3485. }
  3486. }
  3487. /* We are ready to run. */
  3488. ieee80211_wake_queues(dev->wl->hw);
  3489. b43_set_status(dev, B43_STAT_STARTED);
  3490. /* Start data flow (TX/RX). */
  3491. b43_mac_enable(dev);
  3492. b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
  3493. /* Start maintainance work */
  3494. b43_periodic_tasks_setup(dev);
  3495. b43_leds_init(dev);
  3496. b43dbg(dev->wl, "Wireless interface started\n");
  3497. out:
  3498. return err;
  3499. }
  3500. /* Get PHY and RADIO versioning numbers */
  3501. static int b43_phy_versioning(struct b43_wldev *dev)
  3502. {
  3503. struct b43_phy *phy = &dev->phy;
  3504. u32 tmp;
  3505. u8 analog_type;
  3506. u8 phy_type;
  3507. u8 phy_rev;
  3508. u16 radio_manuf;
  3509. u16 radio_ver;
  3510. u16 radio_rev;
  3511. int unsupported = 0;
  3512. /* Get PHY versioning */
  3513. tmp = b43_read16(dev, B43_MMIO_PHY_VER);
  3514. analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
  3515. phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
  3516. phy_rev = (tmp & B43_PHYVER_VERSION);
  3517. switch (phy_type) {
  3518. case B43_PHYTYPE_A:
  3519. if (phy_rev >= 4)
  3520. unsupported = 1;
  3521. break;
  3522. case B43_PHYTYPE_B:
  3523. if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
  3524. && phy_rev != 7)
  3525. unsupported = 1;
  3526. break;
  3527. case B43_PHYTYPE_G:
  3528. if (phy_rev > 9)
  3529. unsupported = 1;
  3530. break;
  3531. #ifdef CONFIG_B43_PHY_N
  3532. case B43_PHYTYPE_N:
  3533. if (phy_rev > 2)
  3534. unsupported = 1;
  3535. break;
  3536. #endif
  3537. #ifdef CONFIG_B43_PHY_LP
  3538. case B43_PHYTYPE_LP:
  3539. if (phy_rev > 2)
  3540. unsupported = 1;
  3541. break;
  3542. #endif
  3543. default:
  3544. unsupported = 1;
  3545. };
  3546. if (unsupported) {
  3547. b43err(dev->wl, "FOUND UNSUPPORTED PHY "
  3548. "(Analog %u, Type %u, Revision %u)\n",
  3549. analog_type, phy_type, phy_rev);
  3550. return -EOPNOTSUPP;
  3551. }
  3552. b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
  3553. analog_type, phy_type, phy_rev);
  3554. /* Get RADIO versioning */
  3555. if (dev->dev->bus->chip_id == 0x4317) {
  3556. if (dev->dev->bus->chip_rev == 0)
  3557. tmp = 0x3205017F;
  3558. else if (dev->dev->bus->chip_rev == 1)
  3559. tmp = 0x4205017F;
  3560. else
  3561. tmp = 0x5205017F;
  3562. } else {
  3563. b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
  3564. tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
  3565. b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
  3566. tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
  3567. }
  3568. radio_manuf = (tmp & 0x00000FFF);
  3569. radio_ver = (tmp & 0x0FFFF000) >> 12;
  3570. radio_rev = (tmp & 0xF0000000) >> 28;
  3571. if (radio_manuf != 0x17F /* Broadcom */)
  3572. unsupported = 1;
  3573. switch (phy_type) {
  3574. case B43_PHYTYPE_A:
  3575. if (radio_ver != 0x2060)
  3576. unsupported = 1;
  3577. if (radio_rev != 1)
  3578. unsupported = 1;
  3579. if (radio_manuf != 0x17F)
  3580. unsupported = 1;
  3581. break;
  3582. case B43_PHYTYPE_B:
  3583. if ((radio_ver & 0xFFF0) != 0x2050)
  3584. unsupported = 1;
  3585. break;
  3586. case B43_PHYTYPE_G:
  3587. if (radio_ver != 0x2050)
  3588. unsupported = 1;
  3589. break;
  3590. case B43_PHYTYPE_N:
  3591. if (radio_ver != 0x2055 && radio_ver != 0x2056)
  3592. unsupported = 1;
  3593. break;
  3594. case B43_PHYTYPE_LP:
  3595. if (radio_ver != 0x2062 && radio_ver != 0x2063)
  3596. unsupported = 1;
  3597. break;
  3598. default:
  3599. B43_WARN_ON(1);
  3600. }
  3601. if (unsupported) {
  3602. b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
  3603. "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
  3604. radio_manuf, radio_ver, radio_rev);
  3605. return -EOPNOTSUPP;
  3606. }
  3607. b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
  3608. radio_manuf, radio_ver, radio_rev);
  3609. phy->radio_manuf = radio_manuf;
  3610. phy->radio_ver = radio_ver;
  3611. phy->radio_rev = radio_rev;
  3612. phy->analog = analog_type;
  3613. phy->type = phy_type;
  3614. phy->rev = phy_rev;
  3615. return 0;
  3616. }
  3617. static void setup_struct_phy_for_init(struct b43_wldev *dev,
  3618. struct b43_phy *phy)
  3619. {
  3620. phy->hardware_power_control = !!modparam_hwpctl;
  3621. phy->next_txpwr_check_time = jiffies;
  3622. /* PHY TX errors counter. */
  3623. atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
  3624. #if B43_DEBUG
  3625. phy->phy_locked = 0;
  3626. phy->radio_locked = 0;
  3627. #endif
  3628. }
  3629. static void setup_struct_wldev_for_init(struct b43_wldev *dev)
  3630. {
  3631. dev->dfq_valid = 0;
  3632. /* Assume the radio is enabled. If it's not enabled, the state will
  3633. * immediately get fixed on the first periodic work run. */
  3634. dev->radio_hw_enable = 1;
  3635. /* Stats */
  3636. memset(&dev->stats, 0, sizeof(dev->stats));
  3637. setup_struct_phy_for_init(dev, &dev->phy);
  3638. /* IRQ related flags */
  3639. dev->irq_reason = 0;
  3640. memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
  3641. dev->irq_mask = B43_IRQ_MASKTEMPLATE;
  3642. if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
  3643. dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
  3644. dev->mac_suspended = 1;
  3645. /* Noise calculation context */
  3646. memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
  3647. }
  3648. static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
  3649. {
  3650. struct ssb_sprom *sprom = &dev->dev->bus->sprom;
  3651. u64 hf;
  3652. if (!modparam_btcoex)
  3653. return;
  3654. if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
  3655. return;
  3656. if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
  3657. return;
  3658. hf = b43_hf_read(dev);
  3659. if (sprom->boardflags_lo & B43_BFL_BTCMOD)
  3660. hf |= B43_HF_BTCOEXALT;
  3661. else
  3662. hf |= B43_HF_BTCOEX;
  3663. b43_hf_write(dev, hf);
  3664. }
  3665. static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
  3666. {
  3667. if (!modparam_btcoex)
  3668. return;
  3669. //TODO
  3670. }
  3671. static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
  3672. {
  3673. #ifdef CONFIG_SSB_DRIVER_PCICORE
  3674. struct ssb_bus *bus = dev->dev->bus;
  3675. u32 tmp;
  3676. if (bus->pcicore.dev &&
  3677. bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
  3678. bus->pcicore.dev->id.revision <= 5) {
  3679. /* IMCFGLO timeouts workaround. */
  3680. tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
  3681. switch (bus->bustype) {
  3682. case SSB_BUSTYPE_PCI:
  3683. case SSB_BUSTYPE_PCMCIA:
  3684. tmp &= ~SSB_IMCFGLO_REQTO;
  3685. tmp &= ~SSB_IMCFGLO_SERTO;
  3686. tmp |= 0x32;
  3687. break;
  3688. case SSB_BUSTYPE_SSB:
  3689. tmp &= ~SSB_IMCFGLO_REQTO;
  3690. tmp &= ~SSB_IMCFGLO_SERTO;
  3691. tmp |= 0x53;
  3692. break;
  3693. default:
  3694. break;
  3695. }
  3696. ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
  3697. }
  3698. #endif /* CONFIG_SSB_DRIVER_PCICORE */
  3699. }
  3700. static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
  3701. {
  3702. u16 pu_delay;
  3703. /* The time value is in microseconds. */
  3704. if (dev->phy.type == B43_PHYTYPE_A)
  3705. pu_delay = 3700;
  3706. else
  3707. pu_delay = 1050;
  3708. if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
  3709. pu_delay = 500;
  3710. if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
  3711. pu_delay = max(pu_delay, (u16)2400);
  3712. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
  3713. }
  3714. /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
  3715. static void b43_set_pretbtt(struct b43_wldev *dev)
  3716. {
  3717. u16 pretbtt;
  3718. /* The time value is in microseconds. */
  3719. if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
  3720. pretbtt = 2;
  3721. } else {
  3722. if (dev->phy.type == B43_PHYTYPE_A)
  3723. pretbtt = 120;
  3724. else
  3725. pretbtt = 250;
  3726. }
  3727. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
  3728. b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
  3729. }
  3730. /* Shutdown a wireless core */
  3731. /* Locking: wl->mutex */
  3732. static void b43_wireless_core_exit(struct b43_wldev *dev)
  3733. {
  3734. u32 macctl;
  3735. B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
  3736. if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
  3737. return;
  3738. /* Unregister HW RNG driver */
  3739. b43_rng_exit(dev->wl);
  3740. b43_set_status(dev, B43_STAT_UNINIT);
  3741. /* Stop the microcode PSM. */
  3742. macctl = b43_read32(dev, B43_MMIO_MACCTL);
  3743. macctl &= ~B43_MACCTL_PSM_RUN;
  3744. macctl |= B43_MACCTL_PSM_JMP0;
  3745. b43_write32(dev, B43_MMIO_MACCTL, macctl);
  3746. b43_dma_free(dev);
  3747. b43_pio_free(dev);
  3748. b43_chip_exit(dev);
  3749. dev->phy.ops->switch_analog(dev, 0);
  3750. if (dev->wl->current_beacon) {
  3751. dev_kfree_skb_any(dev->wl->current_beacon);
  3752. dev->wl->current_beacon = NULL;
  3753. }
  3754. ssb_device_disable(dev->dev, 0);
  3755. ssb_bus_may_powerdown(dev->dev->bus);
  3756. }
  3757. /* Initialize a wireless core */
  3758. static int b43_wireless_core_init(struct b43_wldev *dev)
  3759. {
  3760. struct ssb_bus *bus = dev->dev->bus;
  3761. struct ssb_sprom *sprom = &bus->sprom;
  3762. struct b43_phy *phy = &dev->phy;
  3763. int err;
  3764. u64 hf;
  3765. u32 tmp;
  3766. B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
  3767. err = ssb_bus_powerup(bus, 0);
  3768. if (err)
  3769. goto out;
  3770. if (!ssb_device_is_enabled(dev->dev)) {
  3771. tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
  3772. b43_wireless_core_reset(dev, tmp);
  3773. }
  3774. /* Reset all data structures. */
  3775. setup_struct_wldev_for_init(dev);
  3776. phy->ops->prepare_structs(dev);
  3777. /* Enable IRQ routing to this device. */
  3778. ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
  3779. b43_imcfglo_timeouts_workaround(dev);
  3780. b43_bluetooth_coext_disable(dev);
  3781. if (phy->ops->prepare_hardware) {
  3782. err = phy->ops->prepare_hardware(dev);
  3783. if (err)
  3784. goto err_busdown;
  3785. }
  3786. err = b43_chip_init(dev);
  3787. if (err)
  3788. goto err_busdown;
  3789. b43_shm_write16(dev, B43_SHM_SHARED,
  3790. B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
  3791. hf = b43_hf_read(dev);
  3792. if (phy->type == B43_PHYTYPE_G) {
  3793. hf |= B43_HF_SYMW;
  3794. if (phy->rev == 1)
  3795. hf |= B43_HF_GDCW;
  3796. if (sprom->boardflags_lo & B43_BFL_PACTRL)
  3797. hf |= B43_HF_OFDMPABOOST;
  3798. }
  3799. if (phy->radio_ver == 0x2050) {
  3800. if (phy->radio_rev == 6)
  3801. hf |= B43_HF_4318TSSI;
  3802. if (phy->radio_rev < 6)
  3803. hf |= B43_HF_VCORECALC;
  3804. }
  3805. if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
  3806. hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
  3807. #ifdef CONFIG_SSB_DRIVER_PCICORE
  3808. if ((bus->bustype == SSB_BUSTYPE_PCI) &&
  3809. (bus->pcicore.dev->id.revision <= 10))
  3810. hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
  3811. #endif
  3812. hf &= ~B43_HF_SKCFPUP;
  3813. b43_hf_write(dev, hf);
  3814. b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
  3815. B43_DEFAULT_LONG_RETRY_LIMIT);
  3816. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
  3817. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
  3818. /* Disable sending probe responses from firmware.
  3819. * Setting the MaxTime to one usec will always trigger
  3820. * a timeout, so we never send any probe resp.
  3821. * A timeout of zero is infinite. */
  3822. b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
  3823. b43_rate_memory_init(dev);
  3824. b43_set_phytxctl_defaults(dev);
  3825. /* Minimum Contention Window */
  3826. if (phy->type == B43_PHYTYPE_B)
  3827. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
  3828. else
  3829. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
  3830. /* Maximum Contention Window */
  3831. b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
  3832. if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) ||
  3833. (dev->dev->bus->bustype == SSB_BUSTYPE_SDIO) ||
  3834. dev->use_pio) {
  3835. dev->__using_pio_transfers = 1;
  3836. err = b43_pio_init(dev);
  3837. } else {
  3838. dev->__using_pio_transfers = 0;
  3839. err = b43_dma_init(dev);
  3840. }
  3841. if (err)
  3842. goto err_chip_exit;
  3843. b43_qos_init(dev);
  3844. b43_set_synth_pu_delay(dev, 1);
  3845. b43_bluetooth_coext_enable(dev);
  3846. ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
  3847. b43_upload_card_macaddress(dev);
  3848. b43_security_init(dev);
  3849. ieee80211_wake_queues(dev->wl->hw);
  3850. b43_set_status(dev, B43_STAT_INITIALIZED);
  3851. /* Register HW RNG driver */
  3852. b43_rng_init(dev->wl);
  3853. out:
  3854. return err;
  3855. err_chip_exit:
  3856. b43_chip_exit(dev);
  3857. err_busdown:
  3858. ssb_bus_may_powerdown(bus);
  3859. B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
  3860. return err;
  3861. }
  3862. static int b43_op_add_interface(struct ieee80211_hw *hw,
  3863. struct ieee80211_vif *vif)
  3864. {
  3865. struct b43_wl *wl = hw_to_b43_wl(hw);
  3866. struct b43_wldev *dev;
  3867. int err = -EOPNOTSUPP;
  3868. /* TODO: allow WDS/AP devices to coexist */
  3869. if (vif->type != NL80211_IFTYPE_AP &&
  3870. vif->type != NL80211_IFTYPE_MESH_POINT &&
  3871. vif->type != NL80211_IFTYPE_STATION &&
  3872. vif->type != NL80211_IFTYPE_WDS &&
  3873. vif->type != NL80211_IFTYPE_ADHOC)
  3874. return -EOPNOTSUPP;
  3875. mutex_lock(&wl->mutex);
  3876. if (wl->operating)
  3877. goto out_mutex_unlock;
  3878. b43dbg(wl, "Adding Interface type %d\n", vif->type);
  3879. dev = wl->current_dev;
  3880. wl->operating = 1;
  3881. wl->vif = vif;
  3882. wl->if_type = vif->type;
  3883. memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
  3884. b43_adjust_opmode(dev);
  3885. b43_set_pretbtt(dev);
  3886. b43_set_synth_pu_delay(dev, 0);
  3887. b43_upload_card_macaddress(dev);
  3888. err = 0;
  3889. out_mutex_unlock:
  3890. mutex_unlock(&wl->mutex);
  3891. return err;
  3892. }
  3893. static void b43_op_remove_interface(struct ieee80211_hw *hw,
  3894. struct ieee80211_vif *vif)
  3895. {
  3896. struct b43_wl *wl = hw_to_b43_wl(hw);
  3897. struct b43_wldev *dev = wl->current_dev;
  3898. b43dbg(wl, "Removing Interface type %d\n", vif->type);
  3899. mutex_lock(&wl->mutex);
  3900. B43_WARN_ON(!wl->operating);
  3901. B43_WARN_ON(wl->vif != vif);
  3902. wl->vif = NULL;
  3903. wl->operating = 0;
  3904. b43_adjust_opmode(dev);
  3905. memset(wl->mac_addr, 0, ETH_ALEN);
  3906. b43_upload_card_macaddress(dev);
  3907. mutex_unlock(&wl->mutex);
  3908. }
  3909. static int b43_op_start(struct ieee80211_hw *hw)
  3910. {
  3911. struct b43_wl *wl = hw_to_b43_wl(hw);
  3912. struct b43_wldev *dev = wl->current_dev;
  3913. int did_init = 0;
  3914. int err = 0;
  3915. /* Kill all old instance specific information to make sure
  3916. * the card won't use it in the short timeframe between start
  3917. * and mac80211 reconfiguring it. */
  3918. memset(wl->bssid, 0, ETH_ALEN);
  3919. memset(wl->mac_addr, 0, ETH_ALEN);
  3920. wl->filter_flags = 0;
  3921. wl->radiotap_enabled = 0;
  3922. b43_qos_clear(wl);
  3923. wl->beacon0_uploaded = 0;
  3924. wl->beacon1_uploaded = 0;
  3925. wl->beacon_templates_virgin = 1;
  3926. wl->radio_enabled = 1;
  3927. mutex_lock(&wl->mutex);
  3928. if (b43_status(dev) < B43_STAT_INITIALIZED) {
  3929. err = b43_wireless_core_init(dev);
  3930. if (err)
  3931. goto out_mutex_unlock;
  3932. did_init = 1;
  3933. }
  3934. if (b43_status(dev) < B43_STAT_STARTED) {
  3935. err = b43_wireless_core_start(dev);
  3936. if (err) {
  3937. if (did_init)
  3938. b43_wireless_core_exit(dev);
  3939. goto out_mutex_unlock;
  3940. }
  3941. }
  3942. /* XXX: only do if device doesn't support rfkill irq */
  3943. wiphy_rfkill_start_polling(hw->wiphy);
  3944. out_mutex_unlock:
  3945. mutex_unlock(&wl->mutex);
  3946. return err;
  3947. }
  3948. static void b43_op_stop(struct ieee80211_hw *hw)
  3949. {
  3950. struct b43_wl *wl = hw_to_b43_wl(hw);
  3951. struct b43_wldev *dev = wl->current_dev;
  3952. cancel_work_sync(&(wl->beacon_update_trigger));
  3953. mutex_lock(&wl->mutex);
  3954. if (b43_status(dev) >= B43_STAT_STARTED) {
  3955. dev = b43_wireless_core_stop(dev);
  3956. if (!dev)
  3957. goto out_unlock;
  3958. }
  3959. b43_wireless_core_exit(dev);
  3960. wl->radio_enabled = 0;
  3961. out_unlock:
  3962. mutex_unlock(&wl->mutex);
  3963. cancel_work_sync(&(wl->txpower_adjust_work));
  3964. }
  3965. static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
  3966. struct ieee80211_sta *sta, bool set)
  3967. {
  3968. struct b43_wl *wl = hw_to_b43_wl(hw);
  3969. /* FIXME: add locking */
  3970. b43_update_templates(wl);
  3971. return 0;
  3972. }
  3973. static void b43_op_sta_notify(struct ieee80211_hw *hw,
  3974. struct ieee80211_vif *vif,
  3975. enum sta_notify_cmd notify_cmd,
  3976. struct ieee80211_sta *sta)
  3977. {
  3978. struct b43_wl *wl = hw_to_b43_wl(hw);
  3979. B43_WARN_ON(!vif || wl->vif != vif);
  3980. }
  3981. static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
  3982. {
  3983. struct b43_wl *wl = hw_to_b43_wl(hw);
  3984. struct b43_wldev *dev;
  3985. mutex_lock(&wl->mutex);
  3986. dev = wl->current_dev;
  3987. if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
  3988. /* Disable CFP update during scan on other channels. */
  3989. b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
  3990. }
  3991. mutex_unlock(&wl->mutex);
  3992. }
  3993. static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
  3994. {
  3995. struct b43_wl *wl = hw_to_b43_wl(hw);
  3996. struct b43_wldev *dev;
  3997. mutex_lock(&wl->mutex);
  3998. dev = wl->current_dev;
  3999. if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
  4000. /* Re-enable CFP update. */
  4001. b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
  4002. }
  4003. mutex_unlock(&wl->mutex);
  4004. }
  4005. static int b43_op_get_survey(struct ieee80211_hw *hw, int idx,
  4006. struct survey_info *survey)
  4007. {
  4008. struct b43_wl *wl = hw_to_b43_wl(hw);
  4009. struct b43_wldev *dev = wl->current_dev;
  4010. struct ieee80211_conf *conf = &hw->conf;
  4011. if (idx != 0)
  4012. return -ENOENT;
  4013. survey->channel = conf->channel;
  4014. survey->filled = SURVEY_INFO_NOISE_DBM;
  4015. survey->noise = dev->stats.link_noise;
  4016. return 0;
  4017. }
  4018. static const struct ieee80211_ops b43_hw_ops = {
  4019. .tx = b43_op_tx,
  4020. .conf_tx = b43_op_conf_tx,
  4021. .add_interface = b43_op_add_interface,
  4022. .remove_interface = b43_op_remove_interface,
  4023. .config = b43_op_config,
  4024. .bss_info_changed = b43_op_bss_info_changed,
  4025. .configure_filter = b43_op_configure_filter,
  4026. .set_key = b43_op_set_key,
  4027. .update_tkip_key = b43_op_update_tkip_key,
  4028. .get_stats = b43_op_get_stats,
  4029. .get_tsf = b43_op_get_tsf,
  4030. .set_tsf = b43_op_set_tsf,
  4031. .start = b43_op_start,
  4032. .stop = b43_op_stop,
  4033. .set_tim = b43_op_beacon_set_tim,
  4034. .sta_notify = b43_op_sta_notify,
  4035. .sw_scan_start = b43_op_sw_scan_start_notifier,
  4036. .sw_scan_complete = b43_op_sw_scan_complete_notifier,
  4037. .get_survey = b43_op_get_survey,
  4038. .rfkill_poll = b43_rfkill_poll,
  4039. };
  4040. /* Hard-reset the chip. Do not call this directly.
  4041. * Use b43_controller_restart()
  4042. */
  4043. static void b43_chip_reset(struct work_struct *work)
  4044. {
  4045. struct b43_wldev *dev =
  4046. container_of(work, struct b43_wldev, restart_work);
  4047. struct b43_wl *wl = dev->wl;
  4048. int err = 0;
  4049. int prev_status;
  4050. mutex_lock(&wl->mutex);
  4051. prev_status = b43_status(dev);
  4052. /* Bring the device down... */
  4053. if (prev_status >= B43_STAT_STARTED) {
  4054. dev = b43_wireless_core_stop(dev);
  4055. if (!dev) {
  4056. err = -ENODEV;
  4057. goto out;
  4058. }
  4059. }
  4060. if (prev_status >= B43_STAT_INITIALIZED)
  4061. b43_wireless_core_exit(dev);
  4062. /* ...and up again. */
  4063. if (prev_status >= B43_STAT_INITIALIZED) {
  4064. err = b43_wireless_core_init(dev);
  4065. if (err)
  4066. goto out;
  4067. }
  4068. if (prev_status >= B43_STAT_STARTED) {
  4069. err = b43_wireless_core_start(dev);
  4070. if (err) {
  4071. b43_wireless_core_exit(dev);
  4072. goto out;
  4073. }
  4074. }
  4075. out:
  4076. if (err)
  4077. wl->current_dev = NULL; /* Failed to init the dev. */
  4078. mutex_unlock(&wl->mutex);
  4079. if (err)
  4080. b43err(wl, "Controller restart FAILED\n");
  4081. else
  4082. b43info(wl, "Controller restarted\n");
  4083. }
  4084. static int b43_setup_bands(struct b43_wldev *dev,
  4085. bool have_2ghz_phy, bool have_5ghz_phy)
  4086. {
  4087. struct ieee80211_hw *hw = dev->wl->hw;
  4088. if (have_2ghz_phy)
  4089. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
  4090. if (dev->phy.type == B43_PHYTYPE_N) {
  4091. if (have_5ghz_phy)
  4092. hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
  4093. } else {
  4094. if (have_5ghz_phy)
  4095. hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
  4096. }
  4097. dev->phy.supports_2ghz = have_2ghz_phy;
  4098. dev->phy.supports_5ghz = have_5ghz_phy;
  4099. return 0;
  4100. }
  4101. static void b43_wireless_core_detach(struct b43_wldev *dev)
  4102. {
  4103. /* We release firmware that late to not be required to re-request
  4104. * is all the time when we reinit the core. */
  4105. b43_release_firmware(dev);
  4106. b43_phy_free(dev);
  4107. }
  4108. static int b43_wireless_core_attach(struct b43_wldev *dev)
  4109. {
  4110. struct b43_wl *wl = dev->wl;
  4111. struct ssb_bus *bus = dev->dev->bus;
  4112. struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
  4113. int err;
  4114. bool have_2ghz_phy = 0, have_5ghz_phy = 0;
  4115. u32 tmp;
  4116. /* Do NOT do any device initialization here.
  4117. * Do it in wireless_core_init() instead.
  4118. * This function is for gathering basic information about the HW, only.
  4119. * Also some structs may be set up here. But most likely you want to have
  4120. * that in core_init(), too.
  4121. */
  4122. err = ssb_bus_powerup(bus, 0);
  4123. if (err) {
  4124. b43err(wl, "Bus powerup failed\n");
  4125. goto out;
  4126. }
  4127. /* Get the PHY type. */
  4128. if (dev->dev->id.revision >= 5) {
  4129. u32 tmshigh;
  4130. tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
  4131. have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
  4132. have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
  4133. } else
  4134. B43_WARN_ON(1);
  4135. dev->phy.gmode = have_2ghz_phy;
  4136. dev->phy.radio_on = 1;
  4137. tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
  4138. b43_wireless_core_reset(dev, tmp);
  4139. err = b43_phy_versioning(dev);
  4140. if (err)
  4141. goto err_powerdown;
  4142. /* Check if this device supports multiband. */
  4143. if (!pdev ||
  4144. (pdev->device != 0x4312 &&
  4145. pdev->device != 0x4319 && pdev->device != 0x4324)) {
  4146. /* No multiband support. */
  4147. have_2ghz_phy = 0;
  4148. have_5ghz_phy = 0;
  4149. switch (dev->phy.type) {
  4150. case B43_PHYTYPE_A:
  4151. have_5ghz_phy = 1;
  4152. break;
  4153. case B43_PHYTYPE_LP: //FIXME not always!
  4154. #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
  4155. have_5ghz_phy = 1;
  4156. #endif
  4157. case B43_PHYTYPE_G:
  4158. case B43_PHYTYPE_N:
  4159. have_2ghz_phy = 1;
  4160. break;
  4161. default:
  4162. B43_WARN_ON(1);
  4163. }
  4164. }
  4165. if (dev->phy.type == B43_PHYTYPE_A) {
  4166. /* FIXME */
  4167. b43err(wl, "IEEE 802.11a devices are unsupported\n");
  4168. err = -EOPNOTSUPP;
  4169. goto err_powerdown;
  4170. }
  4171. if (1 /* disable A-PHY */) {
  4172. /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
  4173. if (dev->phy.type != B43_PHYTYPE_N &&
  4174. dev->phy.type != B43_PHYTYPE_LP) {
  4175. have_2ghz_phy = 1;
  4176. have_5ghz_phy = 0;
  4177. }
  4178. }
  4179. err = b43_phy_allocate(dev);
  4180. if (err)
  4181. goto err_powerdown;
  4182. dev->phy.gmode = have_2ghz_phy;
  4183. tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
  4184. b43_wireless_core_reset(dev, tmp);
  4185. err = b43_validate_chipaccess(dev);
  4186. if (err)
  4187. goto err_phy_free;
  4188. err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
  4189. if (err)
  4190. goto err_phy_free;
  4191. /* Now set some default "current_dev" */
  4192. if (!wl->current_dev)
  4193. wl->current_dev = dev;
  4194. INIT_WORK(&dev->restart_work, b43_chip_reset);
  4195. dev->phy.ops->switch_analog(dev, 0);
  4196. ssb_device_disable(dev->dev, 0);
  4197. ssb_bus_may_powerdown(bus);
  4198. out:
  4199. return err;
  4200. err_phy_free:
  4201. b43_phy_free(dev);
  4202. err_powerdown:
  4203. ssb_bus_may_powerdown(bus);
  4204. return err;
  4205. }
  4206. static void b43_one_core_detach(struct ssb_device *dev)
  4207. {
  4208. struct b43_wldev *wldev;
  4209. struct b43_wl *wl;
  4210. /* Do not cancel ieee80211-workqueue based work here.
  4211. * See comment in b43_remove(). */
  4212. wldev = ssb_get_drvdata(dev);
  4213. wl = wldev->wl;
  4214. b43_debugfs_remove_device(wldev);
  4215. b43_wireless_core_detach(wldev);
  4216. list_del(&wldev->list);
  4217. wl->nr_devs--;
  4218. ssb_set_drvdata(dev, NULL);
  4219. kfree(wldev);
  4220. }
  4221. static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
  4222. {
  4223. struct b43_wldev *wldev;
  4224. struct pci_dev *pdev;
  4225. int err = -ENOMEM;
  4226. if (!list_empty(&wl->devlist)) {
  4227. /* We are not the first core on this chip. */
  4228. pdev = (dev->bus->bustype == SSB_BUSTYPE_PCI) ? dev->bus->host_pci : NULL;
  4229. /* Only special chips support more than one wireless
  4230. * core, although some of the other chips have more than
  4231. * one wireless core as well. Check for this and
  4232. * bail out early.
  4233. */
  4234. if (!pdev ||
  4235. ((pdev->device != 0x4321) &&
  4236. (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
  4237. b43dbg(wl, "Ignoring unconnected 802.11 core\n");
  4238. return -ENODEV;
  4239. }
  4240. }
  4241. wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
  4242. if (!wldev)
  4243. goto out;
  4244. wldev->use_pio = b43_modparam_pio;
  4245. wldev->dev = dev;
  4246. wldev->wl = wl;
  4247. b43_set_status(wldev, B43_STAT_UNINIT);
  4248. wldev->bad_frames_preempt = modparam_bad_frames_preempt;
  4249. INIT_LIST_HEAD(&wldev->list);
  4250. err = b43_wireless_core_attach(wldev);
  4251. if (err)
  4252. goto err_kfree_wldev;
  4253. list_add(&wldev->list, &wl->devlist);
  4254. wl->nr_devs++;
  4255. ssb_set_drvdata(dev, wldev);
  4256. b43_debugfs_add_device(wldev);
  4257. out:
  4258. return err;
  4259. err_kfree_wldev:
  4260. kfree(wldev);
  4261. return err;
  4262. }
  4263. #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
  4264. (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
  4265. (pdev->device == _device) && \
  4266. (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
  4267. (pdev->subsystem_device == _subdevice) )
  4268. static void b43_sprom_fixup(struct ssb_bus *bus)
  4269. {
  4270. struct pci_dev *pdev;
  4271. /* boardflags workarounds */
  4272. if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
  4273. bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
  4274. bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
  4275. if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
  4276. bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
  4277. bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
  4278. if (bus->bustype == SSB_BUSTYPE_PCI) {
  4279. pdev = bus->host_pci;
  4280. if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
  4281. IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
  4282. IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
  4283. IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
  4284. IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
  4285. IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
  4286. IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
  4287. bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
  4288. }
  4289. }
  4290. static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
  4291. {
  4292. struct ieee80211_hw *hw = wl->hw;
  4293. ssb_set_devtypedata(dev, NULL);
  4294. ieee80211_free_hw(hw);
  4295. }
  4296. static int b43_wireless_init(struct ssb_device *dev)
  4297. {
  4298. struct ssb_sprom *sprom = &dev->bus->sprom;
  4299. struct ieee80211_hw *hw;
  4300. struct b43_wl *wl;
  4301. int err = -ENOMEM;
  4302. b43_sprom_fixup(dev->bus);
  4303. hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
  4304. if (!hw) {
  4305. b43err(NULL, "Could not allocate ieee80211 device\n");
  4306. goto out;
  4307. }
  4308. wl = hw_to_b43_wl(hw);
  4309. /* fill hw info */
  4310. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  4311. IEEE80211_HW_SIGNAL_DBM;
  4312. hw->wiphy->interface_modes =
  4313. BIT(NL80211_IFTYPE_AP) |
  4314. BIT(NL80211_IFTYPE_MESH_POINT) |
  4315. BIT(NL80211_IFTYPE_STATION) |
  4316. BIT(NL80211_IFTYPE_WDS) |
  4317. BIT(NL80211_IFTYPE_ADHOC);
  4318. hw->queues = modparam_qos ? 4 : 1;
  4319. wl->mac80211_initially_registered_queues = hw->queues;
  4320. hw->max_rates = 2;
  4321. SET_IEEE80211_DEV(hw, dev->dev);
  4322. if (is_valid_ether_addr(sprom->et1mac))
  4323. SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
  4324. else
  4325. SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
  4326. /* Initialize struct b43_wl */
  4327. wl->hw = hw;
  4328. mutex_init(&wl->mutex);
  4329. spin_lock_init(&wl->hardirq_lock);
  4330. INIT_LIST_HEAD(&wl->devlist);
  4331. INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
  4332. INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
  4333. INIT_WORK(&wl->tx_work, b43_tx_work);
  4334. skb_queue_head_init(&wl->tx_queue);
  4335. ssb_set_devtypedata(dev, wl);
  4336. b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
  4337. dev->bus->chip_id, dev->id.revision);
  4338. err = 0;
  4339. out:
  4340. return err;
  4341. }
  4342. static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
  4343. {
  4344. struct b43_wl *wl;
  4345. int err;
  4346. int first = 0;
  4347. wl = ssb_get_devtypedata(dev);
  4348. if (!wl) {
  4349. /* Probing the first core. Must setup common struct b43_wl */
  4350. first = 1;
  4351. err = b43_wireless_init(dev);
  4352. if (err)
  4353. goto out;
  4354. wl = ssb_get_devtypedata(dev);
  4355. B43_WARN_ON(!wl);
  4356. }
  4357. err = b43_one_core_attach(dev, wl);
  4358. if (err)
  4359. goto err_wireless_exit;
  4360. if (first) {
  4361. err = ieee80211_register_hw(wl->hw);
  4362. if (err)
  4363. goto err_one_core_detach;
  4364. b43_leds_register(wl->current_dev);
  4365. }
  4366. out:
  4367. return err;
  4368. err_one_core_detach:
  4369. b43_one_core_detach(dev);
  4370. err_wireless_exit:
  4371. if (first)
  4372. b43_wireless_exit(dev, wl);
  4373. return err;
  4374. }
  4375. static void b43_remove(struct ssb_device *dev)
  4376. {
  4377. struct b43_wl *wl = ssb_get_devtypedata(dev);
  4378. struct b43_wldev *wldev = ssb_get_drvdata(dev);
  4379. /* We must cancel any work here before unregistering from ieee80211,
  4380. * as the ieee80211 unreg will destroy the workqueue. */
  4381. cancel_work_sync(&wldev->restart_work);
  4382. B43_WARN_ON(!wl);
  4383. if (wl->current_dev == wldev) {
  4384. /* Restore the queues count before unregistering, because firmware detect
  4385. * might have modified it. Restoring is important, so the networking
  4386. * stack can properly free resources. */
  4387. wl->hw->queues = wl->mac80211_initially_registered_queues;
  4388. b43_leds_stop(wldev);
  4389. ieee80211_unregister_hw(wl->hw);
  4390. }
  4391. b43_one_core_detach(dev);
  4392. if (list_empty(&wl->devlist)) {
  4393. b43_leds_unregister(wl);
  4394. /* Last core on the chip unregistered.
  4395. * We can destroy common struct b43_wl.
  4396. */
  4397. b43_wireless_exit(dev, wl);
  4398. }
  4399. }
  4400. /* Perform a hardware reset. This can be called from any context. */
  4401. void b43_controller_restart(struct b43_wldev *dev, const char *reason)
  4402. {
  4403. /* Must avoid requeueing, if we are in shutdown. */
  4404. if (b43_status(dev) < B43_STAT_INITIALIZED)
  4405. return;
  4406. b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
  4407. ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
  4408. }
  4409. static struct ssb_driver b43_ssb_driver = {
  4410. .name = KBUILD_MODNAME,
  4411. .id_table = b43_ssb_tbl,
  4412. .probe = b43_probe,
  4413. .remove = b43_remove,
  4414. };
  4415. static void b43_print_driverinfo(void)
  4416. {
  4417. const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
  4418. *feat_leds = "", *feat_sdio = "";
  4419. #ifdef CONFIG_B43_PCI_AUTOSELECT
  4420. feat_pci = "P";
  4421. #endif
  4422. #ifdef CONFIG_B43_PCMCIA
  4423. feat_pcmcia = "M";
  4424. #endif
  4425. #ifdef CONFIG_B43_PHY_N
  4426. feat_nphy = "N";
  4427. #endif
  4428. #ifdef CONFIG_B43_LEDS
  4429. feat_leds = "L";
  4430. #endif
  4431. #ifdef CONFIG_B43_SDIO
  4432. feat_sdio = "S";
  4433. #endif
  4434. printk(KERN_INFO "Broadcom 43xx driver loaded "
  4435. "[ Features: %s%s%s%s%s, Firmware-ID: "
  4436. B43_SUPPORTED_FIRMWARE_ID " ]\n",
  4437. feat_pci, feat_pcmcia, feat_nphy,
  4438. feat_leds, feat_sdio);
  4439. }
  4440. static int __init b43_init(void)
  4441. {
  4442. int err;
  4443. b43_debugfs_init();
  4444. err = b43_pcmcia_init();
  4445. if (err)
  4446. goto err_dfs_exit;
  4447. err = b43_sdio_init();
  4448. if (err)
  4449. goto err_pcmcia_exit;
  4450. err = ssb_driver_register(&b43_ssb_driver);
  4451. if (err)
  4452. goto err_sdio_exit;
  4453. b43_print_driverinfo();
  4454. return err;
  4455. err_sdio_exit:
  4456. b43_sdio_exit();
  4457. err_pcmcia_exit:
  4458. b43_pcmcia_exit();
  4459. err_dfs_exit:
  4460. b43_debugfs_exit();
  4461. return err;
  4462. }
  4463. static void __exit b43_exit(void)
  4464. {
  4465. ssb_driver_unregister(&b43_ssb_driver);
  4466. b43_sdio_exit();
  4467. b43_pcmcia_exit();
  4468. b43_debugfs_exit();
  4469. }
  4470. module_init(b43_init)
  4471. module_exit(b43_exit)