hw.c 65 KB

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  1. /*
  2. * Copyright (c) 2008-2010 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/io.h>
  17. #include <linux/slab.h>
  18. #include <asm/unaligned.h>
  19. #include "hw.h"
  20. #include "hw-ops.h"
  21. #include "rc.h"
  22. #include "ar9003_mac.h"
  23. static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  24. MODULE_AUTHOR("Atheros Communications");
  25. MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26. MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27. MODULE_LICENSE("Dual BSD/GPL");
  28. static int __init ath9k_init(void)
  29. {
  30. return 0;
  31. }
  32. module_init(ath9k_init);
  33. static void __exit ath9k_exit(void)
  34. {
  35. return;
  36. }
  37. module_exit(ath9k_exit);
  38. /* Private hardware callbacks */
  39. static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  40. {
  41. ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  42. }
  43. static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  44. {
  45. ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  46. }
  47. static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  48. {
  49. struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  50. return priv_ops->macversion_supported(ah->hw_version.macVersion);
  51. }
  52. static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  53. struct ath9k_channel *chan)
  54. {
  55. return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  56. }
  57. static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
  58. {
  59. if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
  60. return;
  61. ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
  62. }
  63. static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
  64. {
  65. /* You will not have this callback if using the old ANI */
  66. if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
  67. return;
  68. ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
  69. }
  70. /********************/
  71. /* Helper Functions */
  72. /********************/
  73. static void ath9k_hw_set_clockrate(struct ath_hw *ah)
  74. {
  75. struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  76. struct ath_common *common = ath9k_hw_common(ah);
  77. unsigned int clockrate;
  78. if (!ah->curchan) /* should really check for CCK instead */
  79. clockrate = ATH9K_CLOCK_RATE_CCK;
  80. else if (conf->channel->band == IEEE80211_BAND_2GHZ)
  81. clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
  82. else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
  83. clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
  84. else
  85. clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
  86. if (conf_is_ht40(conf))
  87. clockrate *= 2;
  88. common->clockrate = clockrate;
  89. }
  90. static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  91. {
  92. struct ath_common *common = ath9k_hw_common(ah);
  93. return usecs * common->clockrate;
  94. }
  95. bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  96. {
  97. int i;
  98. BUG_ON(timeout < AH_TIME_QUANTUM);
  99. for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  100. if ((REG_READ(ah, reg) & mask) == val)
  101. return true;
  102. udelay(AH_TIME_QUANTUM);
  103. }
  104. ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
  105. "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  106. timeout, reg, REG_READ(ah, reg), mask, val);
  107. return false;
  108. }
  109. EXPORT_SYMBOL(ath9k_hw_wait);
  110. u32 ath9k_hw_reverse_bits(u32 val, u32 n)
  111. {
  112. u32 retval;
  113. int i;
  114. for (i = 0, retval = 0; i < n; i++) {
  115. retval = (retval << 1) | (val & 1);
  116. val >>= 1;
  117. }
  118. return retval;
  119. }
  120. bool ath9k_get_channel_edges(struct ath_hw *ah,
  121. u16 flags, u16 *low,
  122. u16 *high)
  123. {
  124. struct ath9k_hw_capabilities *pCap = &ah->caps;
  125. if (flags & CHANNEL_5GHZ) {
  126. *low = pCap->low_5ghz_chan;
  127. *high = pCap->high_5ghz_chan;
  128. return true;
  129. }
  130. if ((flags & CHANNEL_2GHZ)) {
  131. *low = pCap->low_2ghz_chan;
  132. *high = pCap->high_2ghz_chan;
  133. return true;
  134. }
  135. return false;
  136. }
  137. u16 ath9k_hw_computetxtime(struct ath_hw *ah,
  138. u8 phy, int kbps,
  139. u32 frameLen, u16 rateix,
  140. bool shortPreamble)
  141. {
  142. u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
  143. if (kbps == 0)
  144. return 0;
  145. switch (phy) {
  146. case WLAN_RC_PHY_CCK:
  147. phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
  148. if (shortPreamble)
  149. phyTime >>= 1;
  150. numBits = frameLen << 3;
  151. txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
  152. break;
  153. case WLAN_RC_PHY_OFDM:
  154. if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
  155. bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
  156. numBits = OFDM_PLCP_BITS + (frameLen << 3);
  157. numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
  158. txTime = OFDM_SIFS_TIME_QUARTER
  159. + OFDM_PREAMBLE_TIME_QUARTER
  160. + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
  161. } else if (ah->curchan &&
  162. IS_CHAN_HALF_RATE(ah->curchan)) {
  163. bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
  164. numBits = OFDM_PLCP_BITS + (frameLen << 3);
  165. numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
  166. txTime = OFDM_SIFS_TIME_HALF +
  167. OFDM_PREAMBLE_TIME_HALF
  168. + (numSymbols * OFDM_SYMBOL_TIME_HALF);
  169. } else {
  170. bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
  171. numBits = OFDM_PLCP_BITS + (frameLen << 3);
  172. numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
  173. txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
  174. + (numSymbols * OFDM_SYMBOL_TIME);
  175. }
  176. break;
  177. default:
  178. ath_err(ath9k_hw_common(ah),
  179. "Unknown phy %u (rate ix %u)\n", phy, rateix);
  180. txTime = 0;
  181. break;
  182. }
  183. return txTime;
  184. }
  185. EXPORT_SYMBOL(ath9k_hw_computetxtime);
  186. void ath9k_hw_get_channel_centers(struct ath_hw *ah,
  187. struct ath9k_channel *chan,
  188. struct chan_centers *centers)
  189. {
  190. int8_t extoff;
  191. if (!IS_CHAN_HT40(chan)) {
  192. centers->ctl_center = centers->ext_center =
  193. centers->synth_center = chan->channel;
  194. return;
  195. }
  196. if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
  197. (chan->chanmode == CHANNEL_G_HT40PLUS)) {
  198. centers->synth_center =
  199. chan->channel + HT40_CHANNEL_CENTER_SHIFT;
  200. extoff = 1;
  201. } else {
  202. centers->synth_center =
  203. chan->channel - HT40_CHANNEL_CENTER_SHIFT;
  204. extoff = -1;
  205. }
  206. centers->ctl_center =
  207. centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
  208. /* 25 MHz spacing is supported by hw but not on upper layers */
  209. centers->ext_center =
  210. centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
  211. }
  212. /******************/
  213. /* Chip Revisions */
  214. /******************/
  215. static void ath9k_hw_read_revisions(struct ath_hw *ah)
  216. {
  217. u32 val;
  218. val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
  219. if (val == 0xFF) {
  220. val = REG_READ(ah, AR_SREV);
  221. ah->hw_version.macVersion =
  222. (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
  223. ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
  224. ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
  225. } else {
  226. if (!AR_SREV_9100(ah))
  227. ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
  228. ah->hw_version.macRev = val & AR_SREV_REVISION;
  229. if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
  230. ah->is_pciexpress = true;
  231. }
  232. }
  233. /************************************/
  234. /* HW Attach, Detach, Init Routines */
  235. /************************************/
  236. static void ath9k_hw_disablepcie(struct ath_hw *ah)
  237. {
  238. if (AR_SREV_9100(ah))
  239. return;
  240. ENABLE_REGWRITE_BUFFER(ah);
  241. REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
  242. REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
  243. REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
  244. REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
  245. REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
  246. REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
  247. REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
  248. REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
  249. REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
  250. REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
  251. REGWRITE_BUFFER_FLUSH(ah);
  252. }
  253. /* This should work for all families including legacy */
  254. static bool ath9k_hw_chip_test(struct ath_hw *ah)
  255. {
  256. struct ath_common *common = ath9k_hw_common(ah);
  257. u32 regAddr[2] = { AR_STA_ID0 };
  258. u32 regHold[2];
  259. static const u32 patternData[4] = {
  260. 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
  261. };
  262. int i, j, loop_max;
  263. if (!AR_SREV_9300_20_OR_LATER(ah)) {
  264. loop_max = 2;
  265. regAddr[1] = AR_PHY_BASE + (8 << 2);
  266. } else
  267. loop_max = 1;
  268. for (i = 0; i < loop_max; i++) {
  269. u32 addr = regAddr[i];
  270. u32 wrData, rdData;
  271. regHold[i] = REG_READ(ah, addr);
  272. for (j = 0; j < 0x100; j++) {
  273. wrData = (j << 16) | j;
  274. REG_WRITE(ah, addr, wrData);
  275. rdData = REG_READ(ah, addr);
  276. if (rdData != wrData) {
  277. ath_err(common,
  278. "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
  279. addr, wrData, rdData);
  280. return false;
  281. }
  282. }
  283. for (j = 0; j < 4; j++) {
  284. wrData = patternData[j];
  285. REG_WRITE(ah, addr, wrData);
  286. rdData = REG_READ(ah, addr);
  287. if (wrData != rdData) {
  288. ath_err(common,
  289. "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
  290. addr, wrData, rdData);
  291. return false;
  292. }
  293. }
  294. REG_WRITE(ah, regAddr[i], regHold[i]);
  295. }
  296. udelay(100);
  297. return true;
  298. }
  299. static void ath9k_hw_init_config(struct ath_hw *ah)
  300. {
  301. int i;
  302. ah->config.dma_beacon_response_time = 2;
  303. ah->config.sw_beacon_response_time = 10;
  304. ah->config.additional_swba_backoff = 0;
  305. ah->config.ack_6mb = 0x0;
  306. ah->config.cwm_ignore_extcca = 0;
  307. ah->config.pcie_powersave_enable = 0;
  308. ah->config.pcie_clock_req = 0;
  309. ah->config.pcie_waen = 0;
  310. ah->config.analog_shiftreg = 1;
  311. ah->config.enable_ani = true;
  312. for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
  313. ah->config.spurchans[i][0] = AR_NO_SPUR;
  314. ah->config.spurchans[i][1] = AR_NO_SPUR;
  315. }
  316. if (ah->hw_version.devid != AR2427_DEVID_PCIE)
  317. ah->config.ht_enable = 1;
  318. else
  319. ah->config.ht_enable = 0;
  320. ah->config.rx_intr_mitigation = true;
  321. ah->config.pcieSerDesWrite = true;
  322. /*
  323. * We need this for PCI devices only (Cardbus, PCI, miniPCI)
  324. * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
  325. * This means we use it for all AR5416 devices, and the few
  326. * minor PCI AR9280 devices out there.
  327. *
  328. * Serialization is required because these devices do not handle
  329. * well the case of two concurrent reads/writes due to the latency
  330. * involved. During one read/write another read/write can be issued
  331. * on another CPU while the previous read/write may still be working
  332. * on our hardware, if we hit this case the hardware poops in a loop.
  333. * We prevent this by serializing reads and writes.
  334. *
  335. * This issue is not present on PCI-Express devices or pre-AR5416
  336. * devices (legacy, 802.11abg).
  337. */
  338. if (num_possible_cpus() > 1)
  339. ah->config.serialize_regmode = SER_REG_MODE_AUTO;
  340. }
  341. static void ath9k_hw_init_defaults(struct ath_hw *ah)
  342. {
  343. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  344. regulatory->country_code = CTRY_DEFAULT;
  345. regulatory->power_limit = MAX_RATE_POWER;
  346. regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
  347. ah->hw_version.magic = AR5416_MAGIC;
  348. ah->hw_version.subvendorid = 0;
  349. ah->atim_window = 0;
  350. ah->sta_id1_defaults =
  351. AR_STA_ID1_CRPT_MIC_ENABLE |
  352. AR_STA_ID1_MCAST_KSRCH;
  353. ah->beacon_interval = 100;
  354. ah->enable_32kHz_clock = DONT_USE_32KHZ;
  355. ah->slottime = (u32) -1;
  356. ah->globaltxtimeout = (u32) -1;
  357. ah->power_mode = ATH9K_PM_UNDEFINED;
  358. }
  359. static int ath9k_hw_init_macaddr(struct ath_hw *ah)
  360. {
  361. struct ath_common *common = ath9k_hw_common(ah);
  362. u32 sum;
  363. int i;
  364. u16 eeval;
  365. static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
  366. sum = 0;
  367. for (i = 0; i < 3; i++) {
  368. eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
  369. sum += eeval;
  370. common->macaddr[2 * i] = eeval >> 8;
  371. common->macaddr[2 * i + 1] = eeval & 0xff;
  372. }
  373. if (sum == 0 || sum == 0xffff * 3)
  374. return -EADDRNOTAVAIL;
  375. return 0;
  376. }
  377. static int ath9k_hw_post_init(struct ath_hw *ah)
  378. {
  379. int ecode;
  380. if (!AR_SREV_9271(ah)) {
  381. if (!ath9k_hw_chip_test(ah))
  382. return -ENODEV;
  383. }
  384. if (!AR_SREV_9300_20_OR_LATER(ah)) {
  385. ecode = ar9002_hw_rf_claim(ah);
  386. if (ecode != 0)
  387. return ecode;
  388. }
  389. ecode = ath9k_hw_eeprom_init(ah);
  390. if (ecode != 0)
  391. return ecode;
  392. ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
  393. "Eeprom VER: %d, REV: %d\n",
  394. ah->eep_ops->get_eeprom_ver(ah),
  395. ah->eep_ops->get_eeprom_rev(ah));
  396. ecode = ath9k_hw_rf_alloc_ext_banks(ah);
  397. if (ecode) {
  398. ath_err(ath9k_hw_common(ah),
  399. "Failed allocating banks for external radio\n");
  400. ath9k_hw_rf_free_ext_banks(ah);
  401. return ecode;
  402. }
  403. if (!AR_SREV_9100(ah)) {
  404. ath9k_hw_ani_setup(ah);
  405. ath9k_hw_ani_init(ah);
  406. }
  407. return 0;
  408. }
  409. static void ath9k_hw_attach_ops(struct ath_hw *ah)
  410. {
  411. if (AR_SREV_9300_20_OR_LATER(ah))
  412. ar9003_hw_attach_ops(ah);
  413. else
  414. ar9002_hw_attach_ops(ah);
  415. }
  416. /* Called for all hardware families */
  417. static int __ath9k_hw_init(struct ath_hw *ah)
  418. {
  419. struct ath_common *common = ath9k_hw_common(ah);
  420. int r = 0;
  421. if (ah->hw_version.devid == AR5416_AR9100_DEVID)
  422. ah->hw_version.macVersion = AR_SREV_VERSION_9100;
  423. if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
  424. ath_err(common, "Couldn't reset chip\n");
  425. return -EIO;
  426. }
  427. ath9k_hw_init_defaults(ah);
  428. ath9k_hw_init_config(ah);
  429. ath9k_hw_attach_ops(ah);
  430. if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
  431. ath_err(common, "Couldn't wakeup chip\n");
  432. return -EIO;
  433. }
  434. if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
  435. if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
  436. ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
  437. !ah->is_pciexpress)) {
  438. ah->config.serialize_regmode =
  439. SER_REG_MODE_ON;
  440. } else {
  441. ah->config.serialize_regmode =
  442. SER_REG_MODE_OFF;
  443. }
  444. }
  445. ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
  446. ah->config.serialize_regmode);
  447. if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
  448. ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
  449. else
  450. ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
  451. if (!ath9k_hw_macversion_supported(ah)) {
  452. ath_err(common,
  453. "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
  454. ah->hw_version.macVersion, ah->hw_version.macRev);
  455. return -EOPNOTSUPP;
  456. }
  457. if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
  458. ah->is_pciexpress = false;
  459. ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
  460. ath9k_hw_init_cal_settings(ah);
  461. ah->ani_function = ATH9K_ANI_ALL;
  462. if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
  463. ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
  464. if (!AR_SREV_9300_20_OR_LATER(ah))
  465. ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
  466. ath9k_hw_init_mode_regs(ah);
  467. /*
  468. * Read back AR_WA into a permanent copy and set bits 14 and 17.
  469. * We need to do this to avoid RMW of this register. We cannot
  470. * read the reg when chip is asleep.
  471. */
  472. ah->WARegVal = REG_READ(ah, AR_WA);
  473. ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
  474. AR_WA_ASPM_TIMER_BASED_DISABLE);
  475. if (ah->is_pciexpress)
  476. ath9k_hw_configpcipowersave(ah, 0, 0);
  477. else
  478. ath9k_hw_disablepcie(ah);
  479. if (!AR_SREV_9300_20_OR_LATER(ah))
  480. ar9002_hw_cck_chan14_spread(ah);
  481. r = ath9k_hw_post_init(ah);
  482. if (r)
  483. return r;
  484. ath9k_hw_init_mode_gain_regs(ah);
  485. r = ath9k_hw_fill_cap_info(ah);
  486. if (r)
  487. return r;
  488. r = ath9k_hw_init_macaddr(ah);
  489. if (r) {
  490. ath_err(common, "Failed to initialize MAC address\n");
  491. return r;
  492. }
  493. if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
  494. ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
  495. else
  496. ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
  497. ah->bb_watchdog_timeout_ms = 25;
  498. common->state = ATH_HW_INITIALIZED;
  499. return 0;
  500. }
  501. int ath9k_hw_init(struct ath_hw *ah)
  502. {
  503. int ret;
  504. struct ath_common *common = ath9k_hw_common(ah);
  505. /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
  506. switch (ah->hw_version.devid) {
  507. case AR5416_DEVID_PCI:
  508. case AR5416_DEVID_PCIE:
  509. case AR5416_AR9100_DEVID:
  510. case AR9160_DEVID_PCI:
  511. case AR9280_DEVID_PCI:
  512. case AR9280_DEVID_PCIE:
  513. case AR9285_DEVID_PCIE:
  514. case AR9287_DEVID_PCI:
  515. case AR9287_DEVID_PCIE:
  516. case AR2427_DEVID_PCIE:
  517. case AR9300_DEVID_PCIE:
  518. case AR9300_DEVID_AR9485_PCIE:
  519. break;
  520. default:
  521. if (common->bus_ops->ath_bus_type == ATH_USB)
  522. break;
  523. ath_err(common, "Hardware device ID 0x%04x not supported\n",
  524. ah->hw_version.devid);
  525. return -EOPNOTSUPP;
  526. }
  527. ret = __ath9k_hw_init(ah);
  528. if (ret) {
  529. ath_err(common,
  530. "Unable to initialize hardware; initialization status: %d\n",
  531. ret);
  532. return ret;
  533. }
  534. return 0;
  535. }
  536. EXPORT_SYMBOL(ath9k_hw_init);
  537. static void ath9k_hw_init_qos(struct ath_hw *ah)
  538. {
  539. ENABLE_REGWRITE_BUFFER(ah);
  540. REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
  541. REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
  542. REG_WRITE(ah, AR_QOS_NO_ACK,
  543. SM(2, AR_QOS_NO_ACK_TWO_BIT) |
  544. SM(5, AR_QOS_NO_ACK_BIT_OFF) |
  545. SM(0, AR_QOS_NO_ACK_BYTE_OFF));
  546. REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
  547. REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
  548. REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
  549. REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
  550. REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
  551. REGWRITE_BUFFER_FLUSH(ah);
  552. }
  553. static void ath9k_hw_init_pll(struct ath_hw *ah,
  554. struct ath9k_channel *chan)
  555. {
  556. u32 pll;
  557. if (AR_SREV_9485(ah))
  558. REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
  559. pll = ath9k_hw_compute_pll_control(ah, chan);
  560. REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
  561. /* Switch the core clock for ar9271 to 117Mhz */
  562. if (AR_SREV_9271(ah)) {
  563. udelay(500);
  564. REG_WRITE(ah, 0x50040, 0x304);
  565. }
  566. udelay(RTC_PLL_SETTLE_DELAY);
  567. REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
  568. }
  569. static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
  570. enum nl80211_iftype opmode)
  571. {
  572. u32 imr_reg = AR_IMR_TXERR |
  573. AR_IMR_TXURN |
  574. AR_IMR_RXERR |
  575. AR_IMR_RXORN |
  576. AR_IMR_BCNMISC;
  577. if (AR_SREV_9300_20_OR_LATER(ah)) {
  578. imr_reg |= AR_IMR_RXOK_HP;
  579. if (ah->config.rx_intr_mitigation)
  580. imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
  581. else
  582. imr_reg |= AR_IMR_RXOK_LP;
  583. } else {
  584. if (ah->config.rx_intr_mitigation)
  585. imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
  586. else
  587. imr_reg |= AR_IMR_RXOK;
  588. }
  589. if (ah->config.tx_intr_mitigation)
  590. imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
  591. else
  592. imr_reg |= AR_IMR_TXOK;
  593. if (opmode == NL80211_IFTYPE_AP)
  594. imr_reg |= AR_IMR_MIB;
  595. ENABLE_REGWRITE_BUFFER(ah);
  596. REG_WRITE(ah, AR_IMR, imr_reg);
  597. ah->imrs2_reg |= AR_IMR_S2_GTT;
  598. REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
  599. if (!AR_SREV_9100(ah)) {
  600. REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
  601. REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
  602. REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
  603. }
  604. REGWRITE_BUFFER_FLUSH(ah);
  605. if (AR_SREV_9300_20_OR_LATER(ah)) {
  606. REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
  607. REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
  608. REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
  609. REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
  610. }
  611. }
  612. static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
  613. {
  614. u32 val = ath9k_hw_mac_to_clks(ah, us);
  615. val = min(val, (u32) 0xFFFF);
  616. REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
  617. }
  618. static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
  619. {
  620. u32 val = ath9k_hw_mac_to_clks(ah, us);
  621. val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
  622. REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
  623. }
  624. static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
  625. {
  626. u32 val = ath9k_hw_mac_to_clks(ah, us);
  627. val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
  628. REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
  629. }
  630. static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
  631. {
  632. if (tu > 0xFFFF) {
  633. ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
  634. "bad global tx timeout %u\n", tu);
  635. ah->globaltxtimeout = (u32) -1;
  636. return false;
  637. } else {
  638. REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
  639. ah->globaltxtimeout = tu;
  640. return true;
  641. }
  642. }
  643. void ath9k_hw_init_global_settings(struct ath_hw *ah)
  644. {
  645. struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  646. int acktimeout;
  647. int slottime;
  648. int sifstime;
  649. ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
  650. ah->misc_mode);
  651. if (ah->misc_mode != 0)
  652. REG_WRITE(ah, AR_PCU_MISC,
  653. REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
  654. if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
  655. sifstime = 16;
  656. else
  657. sifstime = 10;
  658. /* As defined by IEEE 802.11-2007 17.3.8.6 */
  659. slottime = ah->slottime + 3 * ah->coverage_class;
  660. acktimeout = slottime + sifstime;
  661. /*
  662. * Workaround for early ACK timeouts, add an offset to match the
  663. * initval's 64us ack timeout value.
  664. * This was initially only meant to work around an issue with delayed
  665. * BA frames in some implementations, but it has been found to fix ACK
  666. * timeout issues in other cases as well.
  667. */
  668. if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
  669. acktimeout += 64 - sifstime - ah->slottime;
  670. ath9k_hw_setslottime(ah, slottime);
  671. ath9k_hw_set_ack_timeout(ah, acktimeout);
  672. ath9k_hw_set_cts_timeout(ah, acktimeout);
  673. if (ah->globaltxtimeout != (u32) -1)
  674. ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
  675. }
  676. EXPORT_SYMBOL(ath9k_hw_init_global_settings);
  677. void ath9k_hw_deinit(struct ath_hw *ah)
  678. {
  679. struct ath_common *common = ath9k_hw_common(ah);
  680. if (common->state < ATH_HW_INITIALIZED)
  681. goto free_hw;
  682. ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
  683. free_hw:
  684. ath9k_hw_rf_free_ext_banks(ah);
  685. }
  686. EXPORT_SYMBOL(ath9k_hw_deinit);
  687. /*******/
  688. /* INI */
  689. /*******/
  690. u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
  691. {
  692. u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
  693. if (IS_CHAN_B(chan))
  694. ctl |= CTL_11B;
  695. else if (IS_CHAN_G(chan))
  696. ctl |= CTL_11G;
  697. else
  698. ctl |= CTL_11A;
  699. return ctl;
  700. }
  701. /****************************************/
  702. /* Reset and Channel Switching Routines */
  703. /****************************************/
  704. static inline void ath9k_hw_set_dma(struct ath_hw *ah)
  705. {
  706. struct ath_common *common = ath9k_hw_common(ah);
  707. u32 regval;
  708. ENABLE_REGWRITE_BUFFER(ah);
  709. /*
  710. * set AHB_MODE not to do cacheline prefetches
  711. */
  712. if (!AR_SREV_9300_20_OR_LATER(ah)) {
  713. regval = REG_READ(ah, AR_AHB_MODE);
  714. REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
  715. }
  716. /*
  717. * let mac dma reads be in 128 byte chunks
  718. */
  719. regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
  720. REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
  721. REGWRITE_BUFFER_FLUSH(ah);
  722. /*
  723. * Restore TX Trigger Level to its pre-reset value.
  724. * The initial value depends on whether aggregation is enabled, and is
  725. * adjusted whenever underruns are detected.
  726. */
  727. if (!AR_SREV_9300_20_OR_LATER(ah))
  728. REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
  729. ENABLE_REGWRITE_BUFFER(ah);
  730. /*
  731. * let mac dma writes be in 128 byte chunks
  732. */
  733. regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
  734. REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
  735. /*
  736. * Setup receive FIFO threshold to hold off TX activities
  737. */
  738. REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
  739. if (AR_SREV_9300_20_OR_LATER(ah)) {
  740. REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
  741. REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
  742. ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
  743. ah->caps.rx_status_len);
  744. }
  745. /*
  746. * reduce the number of usable entries in PCU TXBUF to avoid
  747. * wrap around issues.
  748. */
  749. if (AR_SREV_9285(ah)) {
  750. /* For AR9285 the number of Fifos are reduced to half.
  751. * So set the usable tx buf size also to half to
  752. * avoid data/delimiter underruns
  753. */
  754. REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
  755. AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
  756. } else if (!AR_SREV_9271(ah)) {
  757. REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
  758. AR_PCU_TXBUF_CTRL_USABLE_SIZE);
  759. }
  760. REGWRITE_BUFFER_FLUSH(ah);
  761. if (AR_SREV_9300_20_OR_LATER(ah))
  762. ath9k_hw_reset_txstatus_ring(ah);
  763. }
  764. static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
  765. {
  766. u32 val;
  767. val = REG_READ(ah, AR_STA_ID1);
  768. val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
  769. switch (opmode) {
  770. case NL80211_IFTYPE_AP:
  771. REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
  772. | AR_STA_ID1_KSRCH_MODE);
  773. REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
  774. break;
  775. case NL80211_IFTYPE_ADHOC:
  776. case NL80211_IFTYPE_MESH_POINT:
  777. REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
  778. | AR_STA_ID1_KSRCH_MODE);
  779. REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
  780. break;
  781. case NL80211_IFTYPE_STATION:
  782. REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
  783. break;
  784. default:
  785. if (ah->is_monitoring)
  786. REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
  787. break;
  788. }
  789. }
  790. void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
  791. u32 *coef_mantissa, u32 *coef_exponent)
  792. {
  793. u32 coef_exp, coef_man;
  794. for (coef_exp = 31; coef_exp > 0; coef_exp--)
  795. if ((coef_scaled >> coef_exp) & 0x1)
  796. break;
  797. coef_exp = 14 - (coef_exp - COEF_SCALE_S);
  798. coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
  799. *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
  800. *coef_exponent = coef_exp - 16;
  801. }
  802. static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
  803. {
  804. u32 rst_flags;
  805. u32 tmpReg;
  806. if (AR_SREV_9100(ah)) {
  807. u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
  808. val &= ~AR_RTC_DERIVED_CLK_PERIOD;
  809. val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
  810. REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
  811. (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
  812. }
  813. ENABLE_REGWRITE_BUFFER(ah);
  814. if (AR_SREV_9300_20_OR_LATER(ah)) {
  815. REG_WRITE(ah, AR_WA, ah->WARegVal);
  816. udelay(10);
  817. }
  818. REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
  819. AR_RTC_FORCE_WAKE_ON_INT);
  820. if (AR_SREV_9100(ah)) {
  821. rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
  822. AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
  823. } else {
  824. tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
  825. if (tmpReg &
  826. (AR_INTR_SYNC_LOCAL_TIMEOUT |
  827. AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
  828. u32 val;
  829. REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
  830. val = AR_RC_HOSTIF;
  831. if (!AR_SREV_9300_20_OR_LATER(ah))
  832. val |= AR_RC_AHB;
  833. REG_WRITE(ah, AR_RC, val);
  834. } else if (!AR_SREV_9300_20_OR_LATER(ah))
  835. REG_WRITE(ah, AR_RC, AR_RC_AHB);
  836. rst_flags = AR_RTC_RC_MAC_WARM;
  837. if (type == ATH9K_RESET_COLD)
  838. rst_flags |= AR_RTC_RC_MAC_COLD;
  839. }
  840. REG_WRITE(ah, AR_RTC_RC, rst_flags);
  841. REGWRITE_BUFFER_FLUSH(ah);
  842. udelay(50);
  843. REG_WRITE(ah, AR_RTC_RC, 0);
  844. if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
  845. ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
  846. "RTC stuck in MAC reset\n");
  847. return false;
  848. }
  849. if (!AR_SREV_9100(ah))
  850. REG_WRITE(ah, AR_RC, 0);
  851. if (AR_SREV_9100(ah))
  852. udelay(50);
  853. return true;
  854. }
  855. static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
  856. {
  857. ENABLE_REGWRITE_BUFFER(ah);
  858. if (AR_SREV_9300_20_OR_LATER(ah)) {
  859. REG_WRITE(ah, AR_WA, ah->WARegVal);
  860. udelay(10);
  861. }
  862. REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
  863. AR_RTC_FORCE_WAKE_ON_INT);
  864. if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
  865. REG_WRITE(ah, AR_RC, AR_RC_AHB);
  866. REG_WRITE(ah, AR_RTC_RESET, 0);
  867. udelay(2);
  868. REGWRITE_BUFFER_FLUSH(ah);
  869. if (!AR_SREV_9300_20_OR_LATER(ah))
  870. udelay(2);
  871. if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
  872. REG_WRITE(ah, AR_RC, 0);
  873. REG_WRITE(ah, AR_RTC_RESET, 1);
  874. if (!ath9k_hw_wait(ah,
  875. AR_RTC_STATUS,
  876. AR_RTC_STATUS_M,
  877. AR_RTC_STATUS_ON,
  878. AH_WAIT_TIMEOUT)) {
  879. ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
  880. "RTC not waking up\n");
  881. return false;
  882. }
  883. ath9k_hw_read_revisions(ah);
  884. return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
  885. }
  886. static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
  887. {
  888. if (AR_SREV_9300_20_OR_LATER(ah)) {
  889. REG_WRITE(ah, AR_WA, ah->WARegVal);
  890. udelay(10);
  891. }
  892. REG_WRITE(ah, AR_RTC_FORCE_WAKE,
  893. AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
  894. switch (type) {
  895. case ATH9K_RESET_POWER_ON:
  896. return ath9k_hw_set_reset_power_on(ah);
  897. case ATH9K_RESET_WARM:
  898. case ATH9K_RESET_COLD:
  899. return ath9k_hw_set_reset(ah, type);
  900. default:
  901. return false;
  902. }
  903. }
  904. static bool ath9k_hw_chip_reset(struct ath_hw *ah,
  905. struct ath9k_channel *chan)
  906. {
  907. if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
  908. if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
  909. return false;
  910. } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
  911. return false;
  912. if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
  913. return false;
  914. ah->chip_fullsleep = false;
  915. ath9k_hw_init_pll(ah, chan);
  916. ath9k_hw_set_rfmode(ah, chan);
  917. return true;
  918. }
  919. static bool ath9k_hw_channel_change(struct ath_hw *ah,
  920. struct ath9k_channel *chan)
  921. {
  922. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  923. struct ath_common *common = ath9k_hw_common(ah);
  924. struct ieee80211_channel *channel = chan->chan;
  925. u32 qnum;
  926. int r;
  927. for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
  928. if (ath9k_hw_numtxpending(ah, qnum)) {
  929. ath_dbg(common, ATH_DBG_QUEUE,
  930. "Transmit frames pending on queue %d\n", qnum);
  931. return false;
  932. }
  933. }
  934. if (!ath9k_hw_rfbus_req(ah)) {
  935. ath_err(common, "Could not kill baseband RX\n");
  936. return false;
  937. }
  938. ath9k_hw_set_channel_regs(ah, chan);
  939. r = ath9k_hw_rf_set_freq(ah, chan);
  940. if (r) {
  941. ath_err(common, "Failed to set channel\n");
  942. return false;
  943. }
  944. ath9k_hw_set_clockrate(ah);
  945. ah->eep_ops->set_txpower(ah, chan,
  946. ath9k_regd_get_ctl(regulatory, chan),
  947. channel->max_antenna_gain * 2,
  948. channel->max_power * 2,
  949. min((u32) MAX_RATE_POWER,
  950. (u32) regulatory->power_limit), false);
  951. ath9k_hw_rfbus_done(ah);
  952. if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
  953. ath9k_hw_set_delta_slope(ah, chan);
  954. ath9k_hw_spur_mitigate_freq(ah, chan);
  955. return true;
  956. }
  957. bool ath9k_hw_check_alive(struct ath_hw *ah)
  958. {
  959. int count = 50;
  960. u32 reg;
  961. if (AR_SREV_9285_12_OR_LATER(ah))
  962. return true;
  963. do {
  964. reg = REG_READ(ah, AR_OBS_BUS_1);
  965. if ((reg & 0x7E7FFFEF) == 0x00702400)
  966. continue;
  967. switch (reg & 0x7E000B00) {
  968. case 0x1E000000:
  969. case 0x52000B00:
  970. case 0x18000B00:
  971. continue;
  972. default:
  973. return true;
  974. }
  975. } while (count-- > 0);
  976. return false;
  977. }
  978. EXPORT_SYMBOL(ath9k_hw_check_alive);
  979. int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
  980. struct ath9k_hw_cal_data *caldata, bool bChannelChange)
  981. {
  982. struct ath_common *common = ath9k_hw_common(ah);
  983. u32 saveLedState;
  984. struct ath9k_channel *curchan = ah->curchan;
  985. u32 saveDefAntenna;
  986. u32 macStaId1;
  987. u64 tsf = 0;
  988. int i, r;
  989. ah->txchainmask = common->tx_chainmask;
  990. ah->rxchainmask = common->rx_chainmask;
  991. if (!ah->chip_fullsleep) {
  992. ath9k_hw_abortpcurecv(ah);
  993. if (!ath9k_hw_stopdmarecv(ah)) {
  994. ath_dbg(common, ATH_DBG_XMIT,
  995. "Failed to stop receive dma\n");
  996. bChannelChange = false;
  997. }
  998. }
  999. if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
  1000. return -EIO;
  1001. if (curchan && !ah->chip_fullsleep)
  1002. ath9k_hw_getnf(ah, curchan);
  1003. ah->caldata = caldata;
  1004. if (caldata &&
  1005. (chan->channel != caldata->channel ||
  1006. (chan->channelFlags & ~CHANNEL_CW_INT) !=
  1007. (caldata->channelFlags & ~CHANNEL_CW_INT))) {
  1008. /* Operating channel changed, reset channel calibration data */
  1009. memset(caldata, 0, sizeof(*caldata));
  1010. ath9k_init_nfcal_hist_buffer(ah, chan);
  1011. }
  1012. if (bChannelChange &&
  1013. (ah->chip_fullsleep != true) &&
  1014. (ah->curchan != NULL) &&
  1015. (chan->channel != ah->curchan->channel) &&
  1016. ((chan->channelFlags & CHANNEL_ALL) ==
  1017. (ah->curchan->channelFlags & CHANNEL_ALL)) &&
  1018. (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
  1019. if (ath9k_hw_channel_change(ah, chan)) {
  1020. ath9k_hw_loadnf(ah, ah->curchan);
  1021. ath9k_hw_start_nfcal(ah, true);
  1022. if (AR_SREV_9271(ah))
  1023. ar9002_hw_load_ani_reg(ah, chan);
  1024. return 0;
  1025. }
  1026. }
  1027. saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
  1028. if (saveDefAntenna == 0)
  1029. saveDefAntenna = 1;
  1030. macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
  1031. /* For chips on which RTC reset is done, save TSF before it gets cleared */
  1032. if (AR_SREV_9100(ah) ||
  1033. (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
  1034. tsf = ath9k_hw_gettsf64(ah);
  1035. saveLedState = REG_READ(ah, AR_CFG_LED) &
  1036. (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
  1037. AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
  1038. ath9k_hw_mark_phy_inactive(ah);
  1039. /* Only required on the first reset */
  1040. if (AR_SREV_9271(ah) && ah->htc_reset_init) {
  1041. REG_WRITE(ah,
  1042. AR9271_RESET_POWER_DOWN_CONTROL,
  1043. AR9271_RADIO_RF_RST);
  1044. udelay(50);
  1045. }
  1046. if (!ath9k_hw_chip_reset(ah, chan)) {
  1047. ath_err(common, "Chip reset failed\n");
  1048. return -EINVAL;
  1049. }
  1050. /* Only required on the first reset */
  1051. if (AR_SREV_9271(ah) && ah->htc_reset_init) {
  1052. ah->htc_reset_init = false;
  1053. REG_WRITE(ah,
  1054. AR9271_RESET_POWER_DOWN_CONTROL,
  1055. AR9271_GATE_MAC_CTL);
  1056. udelay(50);
  1057. }
  1058. /* Restore TSF */
  1059. if (tsf)
  1060. ath9k_hw_settsf64(ah, tsf);
  1061. if (AR_SREV_9280_20_OR_LATER(ah))
  1062. REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
  1063. if (!AR_SREV_9300_20_OR_LATER(ah))
  1064. ar9002_hw_enable_async_fifo(ah);
  1065. r = ath9k_hw_process_ini(ah, chan);
  1066. if (r)
  1067. return r;
  1068. /*
  1069. * Some AR91xx SoC devices frequently fail to accept TSF writes
  1070. * right after the chip reset. When that happens, write a new
  1071. * value after the initvals have been applied, with an offset
  1072. * based on measured time difference
  1073. */
  1074. if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
  1075. tsf += 1500;
  1076. ath9k_hw_settsf64(ah, tsf);
  1077. }
  1078. /* Setup MFP options for CCMP */
  1079. if (AR_SREV_9280_20_OR_LATER(ah)) {
  1080. /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
  1081. * frames when constructing CCMP AAD. */
  1082. REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
  1083. 0xc7ff);
  1084. ah->sw_mgmt_crypto = false;
  1085. } else if (AR_SREV_9160_10_OR_LATER(ah)) {
  1086. /* Disable hardware crypto for management frames */
  1087. REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
  1088. AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
  1089. REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
  1090. AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
  1091. ah->sw_mgmt_crypto = true;
  1092. } else
  1093. ah->sw_mgmt_crypto = true;
  1094. if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
  1095. ath9k_hw_set_delta_slope(ah, chan);
  1096. ath9k_hw_spur_mitigate_freq(ah, chan);
  1097. ah->eep_ops->set_board_values(ah, chan);
  1098. ath9k_hw_set_operating_mode(ah, ah->opmode);
  1099. ENABLE_REGWRITE_BUFFER(ah);
  1100. REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
  1101. REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
  1102. | macStaId1
  1103. | AR_STA_ID1_RTS_USE_DEF
  1104. | (ah->config.
  1105. ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
  1106. | ah->sta_id1_defaults);
  1107. ath_hw_setbssidmask(common);
  1108. REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
  1109. ath9k_hw_write_associd(ah);
  1110. REG_WRITE(ah, AR_ISR, ~0);
  1111. REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
  1112. REGWRITE_BUFFER_FLUSH(ah);
  1113. r = ath9k_hw_rf_set_freq(ah, chan);
  1114. if (r)
  1115. return r;
  1116. ath9k_hw_set_clockrate(ah);
  1117. ENABLE_REGWRITE_BUFFER(ah);
  1118. for (i = 0; i < AR_NUM_DCU; i++)
  1119. REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
  1120. REGWRITE_BUFFER_FLUSH(ah);
  1121. ah->intr_txqs = 0;
  1122. for (i = 0; i < ah->caps.total_queues; i++)
  1123. ath9k_hw_resettxqueue(ah, i);
  1124. ath9k_hw_init_interrupt_masks(ah, ah->opmode);
  1125. ath9k_hw_ani_cache_ini_regs(ah);
  1126. ath9k_hw_init_qos(ah);
  1127. if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
  1128. ath9k_enable_rfkill(ah);
  1129. ath9k_hw_init_global_settings(ah);
  1130. if (!AR_SREV_9300_20_OR_LATER(ah)) {
  1131. ar9002_hw_update_async_fifo(ah);
  1132. ar9002_hw_enable_wep_aggregation(ah);
  1133. }
  1134. REG_WRITE(ah, AR_STA_ID1,
  1135. REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
  1136. ath9k_hw_set_dma(ah);
  1137. REG_WRITE(ah, AR_OBS, 8);
  1138. if (ah->config.rx_intr_mitigation) {
  1139. REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
  1140. REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
  1141. }
  1142. if (ah->config.tx_intr_mitigation) {
  1143. REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
  1144. REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
  1145. }
  1146. ath9k_hw_init_bb(ah, chan);
  1147. if (!ath9k_hw_init_cal(ah, chan))
  1148. return -EIO;
  1149. ENABLE_REGWRITE_BUFFER(ah);
  1150. ath9k_hw_restore_chainmask(ah);
  1151. REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
  1152. REGWRITE_BUFFER_FLUSH(ah);
  1153. /*
  1154. * For big endian systems turn on swapping for descriptors
  1155. */
  1156. if (AR_SREV_9100(ah)) {
  1157. u32 mask;
  1158. mask = REG_READ(ah, AR_CFG);
  1159. if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
  1160. ath_dbg(common, ATH_DBG_RESET,
  1161. "CFG Byte Swap Set 0x%x\n", mask);
  1162. } else {
  1163. mask =
  1164. INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
  1165. REG_WRITE(ah, AR_CFG, mask);
  1166. ath_dbg(common, ATH_DBG_RESET,
  1167. "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
  1168. }
  1169. } else {
  1170. if (common->bus_ops->ath_bus_type == ATH_USB) {
  1171. /* Configure AR9271 target WLAN */
  1172. if (AR_SREV_9271(ah))
  1173. REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
  1174. else
  1175. REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
  1176. }
  1177. #ifdef __BIG_ENDIAN
  1178. else
  1179. REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
  1180. #endif
  1181. }
  1182. if (ah->btcoex_hw.enabled)
  1183. ath9k_hw_btcoex_enable(ah);
  1184. if (AR_SREV_9300_20_OR_LATER(ah))
  1185. ar9003_hw_bb_watchdog_config(ah);
  1186. return 0;
  1187. }
  1188. EXPORT_SYMBOL(ath9k_hw_reset);
  1189. /******************************/
  1190. /* Power Management (Chipset) */
  1191. /******************************/
  1192. /*
  1193. * Notify Power Mgt is disabled in self-generated frames.
  1194. * If requested, force chip to sleep.
  1195. */
  1196. static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
  1197. {
  1198. REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
  1199. if (setChip) {
  1200. /*
  1201. * Clear the RTC force wake bit to allow the
  1202. * mac to go to sleep.
  1203. */
  1204. REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
  1205. AR_RTC_FORCE_WAKE_EN);
  1206. if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
  1207. REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
  1208. /* Shutdown chip. Active low */
  1209. if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
  1210. REG_CLR_BIT(ah, (AR_RTC_RESET),
  1211. AR_RTC_RESET_EN);
  1212. }
  1213. /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
  1214. if (AR_SREV_9300_20_OR_LATER(ah))
  1215. REG_WRITE(ah, AR_WA,
  1216. ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
  1217. }
  1218. /*
  1219. * Notify Power Management is enabled in self-generating
  1220. * frames. If request, set power mode of chip to
  1221. * auto/normal. Duration in units of 128us (1/8 TU).
  1222. */
  1223. static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
  1224. {
  1225. REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
  1226. if (setChip) {
  1227. struct ath9k_hw_capabilities *pCap = &ah->caps;
  1228. if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1229. /* Set WakeOnInterrupt bit; clear ForceWake bit */
  1230. REG_WRITE(ah, AR_RTC_FORCE_WAKE,
  1231. AR_RTC_FORCE_WAKE_ON_INT);
  1232. } else {
  1233. /*
  1234. * Clear the RTC force wake bit to allow the
  1235. * mac to go to sleep.
  1236. */
  1237. REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
  1238. AR_RTC_FORCE_WAKE_EN);
  1239. }
  1240. }
  1241. /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
  1242. if (AR_SREV_9300_20_OR_LATER(ah))
  1243. REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
  1244. }
  1245. static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
  1246. {
  1247. u32 val;
  1248. int i;
  1249. /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
  1250. if (AR_SREV_9300_20_OR_LATER(ah)) {
  1251. REG_WRITE(ah, AR_WA, ah->WARegVal);
  1252. udelay(10);
  1253. }
  1254. if (setChip) {
  1255. if ((REG_READ(ah, AR_RTC_STATUS) &
  1256. AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
  1257. if (ath9k_hw_set_reset_reg(ah,
  1258. ATH9K_RESET_POWER_ON) != true) {
  1259. return false;
  1260. }
  1261. if (!AR_SREV_9300_20_OR_LATER(ah))
  1262. ath9k_hw_init_pll(ah, NULL);
  1263. }
  1264. if (AR_SREV_9100(ah))
  1265. REG_SET_BIT(ah, AR_RTC_RESET,
  1266. AR_RTC_RESET_EN);
  1267. REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
  1268. AR_RTC_FORCE_WAKE_EN);
  1269. udelay(50);
  1270. for (i = POWER_UP_TIME / 50; i > 0; i--) {
  1271. val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
  1272. if (val == AR_RTC_STATUS_ON)
  1273. break;
  1274. udelay(50);
  1275. REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
  1276. AR_RTC_FORCE_WAKE_EN);
  1277. }
  1278. if (i == 0) {
  1279. ath_err(ath9k_hw_common(ah),
  1280. "Failed to wakeup in %uus\n",
  1281. POWER_UP_TIME / 20);
  1282. return false;
  1283. }
  1284. }
  1285. REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
  1286. return true;
  1287. }
  1288. bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
  1289. {
  1290. struct ath_common *common = ath9k_hw_common(ah);
  1291. int status = true, setChip = true;
  1292. static const char *modes[] = {
  1293. "AWAKE",
  1294. "FULL-SLEEP",
  1295. "NETWORK SLEEP",
  1296. "UNDEFINED"
  1297. };
  1298. if (ah->power_mode == mode)
  1299. return status;
  1300. ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
  1301. modes[ah->power_mode], modes[mode]);
  1302. switch (mode) {
  1303. case ATH9K_PM_AWAKE:
  1304. status = ath9k_hw_set_power_awake(ah, setChip);
  1305. break;
  1306. case ATH9K_PM_FULL_SLEEP:
  1307. ath9k_set_power_sleep(ah, setChip);
  1308. ah->chip_fullsleep = true;
  1309. break;
  1310. case ATH9K_PM_NETWORK_SLEEP:
  1311. ath9k_set_power_network_sleep(ah, setChip);
  1312. break;
  1313. default:
  1314. ath_err(common, "Unknown power mode %u\n", mode);
  1315. return false;
  1316. }
  1317. ah->power_mode = mode;
  1318. /*
  1319. * XXX: If this warning never comes up after a while then
  1320. * simply keep the ATH_DBG_WARN_ON_ONCE() but make
  1321. * ath9k_hw_setpower() return type void.
  1322. */
  1323. ATH_DBG_WARN_ON_ONCE(!status);
  1324. return status;
  1325. }
  1326. EXPORT_SYMBOL(ath9k_hw_setpower);
  1327. /*******************/
  1328. /* Beacon Handling */
  1329. /*******************/
  1330. void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
  1331. {
  1332. int flags = 0;
  1333. ah->beacon_interval = beacon_period;
  1334. ENABLE_REGWRITE_BUFFER(ah);
  1335. switch (ah->opmode) {
  1336. case NL80211_IFTYPE_ADHOC:
  1337. case NL80211_IFTYPE_MESH_POINT:
  1338. REG_SET_BIT(ah, AR_TXCFG,
  1339. AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
  1340. REG_WRITE(ah, AR_NEXT_NDP_TIMER,
  1341. TU_TO_USEC(next_beacon +
  1342. (ah->atim_window ? ah->
  1343. atim_window : 1)));
  1344. flags |= AR_NDP_TIMER_EN;
  1345. case NL80211_IFTYPE_AP:
  1346. REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
  1347. REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
  1348. TU_TO_USEC(next_beacon -
  1349. ah->config.
  1350. dma_beacon_response_time));
  1351. REG_WRITE(ah, AR_NEXT_SWBA,
  1352. TU_TO_USEC(next_beacon -
  1353. ah->config.
  1354. sw_beacon_response_time));
  1355. flags |=
  1356. AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
  1357. break;
  1358. default:
  1359. ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
  1360. "%s: unsupported opmode: %d\n",
  1361. __func__, ah->opmode);
  1362. return;
  1363. break;
  1364. }
  1365. REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
  1366. REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
  1367. REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
  1368. REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
  1369. REGWRITE_BUFFER_FLUSH(ah);
  1370. beacon_period &= ~ATH9K_BEACON_ENA;
  1371. if (beacon_period & ATH9K_BEACON_RESET_TSF) {
  1372. ath9k_hw_reset_tsf(ah);
  1373. }
  1374. REG_SET_BIT(ah, AR_TIMER_MODE, flags);
  1375. }
  1376. EXPORT_SYMBOL(ath9k_hw_beaconinit);
  1377. void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
  1378. const struct ath9k_beacon_state *bs)
  1379. {
  1380. u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
  1381. struct ath9k_hw_capabilities *pCap = &ah->caps;
  1382. struct ath_common *common = ath9k_hw_common(ah);
  1383. ENABLE_REGWRITE_BUFFER(ah);
  1384. REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
  1385. REG_WRITE(ah, AR_BEACON_PERIOD,
  1386. TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
  1387. REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
  1388. TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
  1389. REGWRITE_BUFFER_FLUSH(ah);
  1390. REG_RMW_FIELD(ah, AR_RSSI_THR,
  1391. AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
  1392. beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
  1393. if (bs->bs_sleepduration > beaconintval)
  1394. beaconintval = bs->bs_sleepduration;
  1395. dtimperiod = bs->bs_dtimperiod;
  1396. if (bs->bs_sleepduration > dtimperiod)
  1397. dtimperiod = bs->bs_sleepduration;
  1398. if (beaconintval == dtimperiod)
  1399. nextTbtt = bs->bs_nextdtim;
  1400. else
  1401. nextTbtt = bs->bs_nexttbtt;
  1402. ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
  1403. ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
  1404. ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
  1405. ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
  1406. ENABLE_REGWRITE_BUFFER(ah);
  1407. REG_WRITE(ah, AR_NEXT_DTIM,
  1408. TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
  1409. REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
  1410. REG_WRITE(ah, AR_SLEEP1,
  1411. SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
  1412. | AR_SLEEP1_ASSUME_DTIM);
  1413. if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
  1414. beacontimeout = (BEACON_TIMEOUT_VAL << 3);
  1415. else
  1416. beacontimeout = MIN_BEACON_TIMEOUT_VAL;
  1417. REG_WRITE(ah, AR_SLEEP2,
  1418. SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
  1419. REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
  1420. REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
  1421. REGWRITE_BUFFER_FLUSH(ah);
  1422. REG_SET_BIT(ah, AR_TIMER_MODE,
  1423. AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
  1424. AR_DTIM_TIMER_EN);
  1425. /* TSF Out of Range Threshold */
  1426. REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
  1427. }
  1428. EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
  1429. /*******************/
  1430. /* HW Capabilities */
  1431. /*******************/
  1432. int ath9k_hw_fill_cap_info(struct ath_hw *ah)
  1433. {
  1434. struct ath9k_hw_capabilities *pCap = &ah->caps;
  1435. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  1436. struct ath_common *common = ath9k_hw_common(ah);
  1437. struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
  1438. u16 capField = 0, eeval;
  1439. u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
  1440. eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
  1441. regulatory->current_rd = eeval;
  1442. eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
  1443. if (AR_SREV_9285_12_OR_LATER(ah))
  1444. eeval |= AR9285_RDEXT_DEFAULT;
  1445. regulatory->current_rd_ext = eeval;
  1446. capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
  1447. if (ah->opmode != NL80211_IFTYPE_AP &&
  1448. ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
  1449. if (regulatory->current_rd == 0x64 ||
  1450. regulatory->current_rd == 0x65)
  1451. regulatory->current_rd += 5;
  1452. else if (regulatory->current_rd == 0x41)
  1453. regulatory->current_rd = 0x43;
  1454. ath_dbg(common, ATH_DBG_REGULATORY,
  1455. "regdomain mapped to 0x%x\n", regulatory->current_rd);
  1456. }
  1457. eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
  1458. if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
  1459. ath_err(common,
  1460. "no band has been marked as supported in EEPROM\n");
  1461. return -EINVAL;
  1462. }
  1463. if (eeval & AR5416_OPFLAGS_11A)
  1464. pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
  1465. if (eeval & AR5416_OPFLAGS_11G)
  1466. pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
  1467. pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
  1468. /*
  1469. * For AR9271 we will temporarilly uses the rx chainmax as read from
  1470. * the EEPROM.
  1471. */
  1472. if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
  1473. !(eeval & AR5416_OPFLAGS_11A) &&
  1474. !(AR_SREV_9271(ah)))
  1475. /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
  1476. pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
  1477. else
  1478. /* Use rx_chainmask from EEPROM. */
  1479. pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
  1480. ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
  1481. /* enable key search for every frame in an aggregate */
  1482. if (AR_SREV_9300_20_OR_LATER(ah))
  1483. ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
  1484. pCap->low_2ghz_chan = 2312;
  1485. pCap->high_2ghz_chan = 2732;
  1486. pCap->low_5ghz_chan = 4920;
  1487. pCap->high_5ghz_chan = 6100;
  1488. common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
  1489. if (ah->config.ht_enable)
  1490. pCap->hw_caps |= ATH9K_HW_CAP_HT;
  1491. else
  1492. pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
  1493. if (capField & AR_EEPROM_EEPCAP_MAXQCU)
  1494. pCap->total_queues =
  1495. MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
  1496. else
  1497. pCap->total_queues = ATH9K_NUM_TX_QUEUES;
  1498. if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
  1499. pCap->keycache_size =
  1500. 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
  1501. else
  1502. pCap->keycache_size = AR_KEYTABLE_SIZE;
  1503. if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
  1504. pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
  1505. else
  1506. pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
  1507. if (AR_SREV_9271(ah))
  1508. pCap->num_gpio_pins = AR9271_NUM_GPIO;
  1509. else if (AR_DEVID_7010(ah))
  1510. pCap->num_gpio_pins = AR7010_NUM_GPIO;
  1511. else if (AR_SREV_9285_12_OR_LATER(ah))
  1512. pCap->num_gpio_pins = AR9285_NUM_GPIO;
  1513. else if (AR_SREV_9280_20_OR_LATER(ah))
  1514. pCap->num_gpio_pins = AR928X_NUM_GPIO;
  1515. else
  1516. pCap->num_gpio_pins = AR_NUM_GPIO;
  1517. if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
  1518. pCap->hw_caps |= ATH9K_HW_CAP_CST;
  1519. pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
  1520. } else {
  1521. pCap->rts_aggr_limit = (8 * 1024);
  1522. }
  1523. pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
  1524. #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
  1525. ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
  1526. if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
  1527. ah->rfkill_gpio =
  1528. MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
  1529. ah->rfkill_polarity =
  1530. MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
  1531. pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
  1532. }
  1533. #endif
  1534. if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
  1535. pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
  1536. else
  1537. pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
  1538. if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
  1539. pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
  1540. else
  1541. pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
  1542. if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
  1543. pCap->reg_cap =
  1544. AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
  1545. AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
  1546. AR_EEPROM_EEREGCAP_EN_KK_U2 |
  1547. AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
  1548. } else {
  1549. pCap->reg_cap =
  1550. AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
  1551. AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
  1552. }
  1553. /* Advertise midband for AR5416 with FCC midband set in eeprom */
  1554. if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
  1555. AR_SREV_5416(ah))
  1556. pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
  1557. pCap->num_antcfg_5ghz =
  1558. ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
  1559. pCap->num_antcfg_2ghz =
  1560. ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
  1561. if (AR_SREV_9280_20_OR_LATER(ah) && common->btcoex_enabled) {
  1562. btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
  1563. btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
  1564. if (AR_SREV_9285(ah)) {
  1565. btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
  1566. btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
  1567. } else {
  1568. btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
  1569. }
  1570. } else {
  1571. btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
  1572. }
  1573. if (AR_SREV_9300_20_OR_LATER(ah)) {
  1574. pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
  1575. if (!AR_SREV_9485(ah))
  1576. pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
  1577. pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
  1578. pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
  1579. pCap->rx_status_len = sizeof(struct ar9003_rxs);
  1580. pCap->tx_desc_len = sizeof(struct ar9003_txc);
  1581. pCap->txs_len = sizeof(struct ar9003_txs);
  1582. if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
  1583. pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
  1584. } else {
  1585. pCap->tx_desc_len = sizeof(struct ath_desc);
  1586. if (AR_SREV_9280_20(ah) &&
  1587. ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
  1588. AR5416_EEP_MINOR_VER_16) ||
  1589. ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
  1590. pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
  1591. }
  1592. if (AR_SREV_9300_20_OR_LATER(ah))
  1593. pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
  1594. if (AR_SREV_9300_20_OR_LATER(ah))
  1595. ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
  1596. if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
  1597. pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
  1598. if (AR_SREV_9285(ah))
  1599. if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
  1600. ant_div_ctl1 =
  1601. ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
  1602. if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
  1603. pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
  1604. }
  1605. if (AR_SREV_9300_20_OR_LATER(ah)) {
  1606. if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
  1607. pCap->hw_caps |= ATH9K_HW_CAP_APM;
  1608. }
  1609. if (AR_SREV_9485_10(ah)) {
  1610. pCap->pcie_lcr_extsync_en = true;
  1611. pCap->pcie_lcr_offset = 0x80;
  1612. }
  1613. tx_chainmask = pCap->tx_chainmask;
  1614. rx_chainmask = pCap->rx_chainmask;
  1615. while (tx_chainmask || rx_chainmask) {
  1616. if (tx_chainmask & BIT(0))
  1617. pCap->max_txchains++;
  1618. if (rx_chainmask & BIT(0))
  1619. pCap->max_rxchains++;
  1620. tx_chainmask >>= 1;
  1621. rx_chainmask >>= 1;
  1622. }
  1623. return 0;
  1624. }
  1625. /****************************/
  1626. /* GPIO / RFKILL / Antennae */
  1627. /****************************/
  1628. static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
  1629. u32 gpio, u32 type)
  1630. {
  1631. int addr;
  1632. u32 gpio_shift, tmp;
  1633. if (gpio > 11)
  1634. addr = AR_GPIO_OUTPUT_MUX3;
  1635. else if (gpio > 5)
  1636. addr = AR_GPIO_OUTPUT_MUX2;
  1637. else
  1638. addr = AR_GPIO_OUTPUT_MUX1;
  1639. gpio_shift = (gpio % 6) * 5;
  1640. if (AR_SREV_9280_20_OR_LATER(ah)
  1641. || (addr != AR_GPIO_OUTPUT_MUX1)) {
  1642. REG_RMW(ah, addr, (type << gpio_shift),
  1643. (0x1f << gpio_shift));
  1644. } else {
  1645. tmp = REG_READ(ah, addr);
  1646. tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
  1647. tmp &= ~(0x1f << gpio_shift);
  1648. tmp |= (type << gpio_shift);
  1649. REG_WRITE(ah, addr, tmp);
  1650. }
  1651. }
  1652. void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
  1653. {
  1654. u32 gpio_shift;
  1655. BUG_ON(gpio >= ah->caps.num_gpio_pins);
  1656. if (AR_DEVID_7010(ah)) {
  1657. gpio_shift = gpio;
  1658. REG_RMW(ah, AR7010_GPIO_OE,
  1659. (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
  1660. (AR7010_GPIO_OE_MASK << gpio_shift));
  1661. return;
  1662. }
  1663. gpio_shift = gpio << 1;
  1664. REG_RMW(ah,
  1665. AR_GPIO_OE_OUT,
  1666. (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
  1667. (AR_GPIO_OE_OUT_DRV << gpio_shift));
  1668. }
  1669. EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
  1670. u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
  1671. {
  1672. #define MS_REG_READ(x, y) \
  1673. (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
  1674. if (gpio >= ah->caps.num_gpio_pins)
  1675. return 0xffffffff;
  1676. if (AR_DEVID_7010(ah)) {
  1677. u32 val;
  1678. val = REG_READ(ah, AR7010_GPIO_IN);
  1679. return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
  1680. } else if (AR_SREV_9300_20_OR_LATER(ah))
  1681. return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
  1682. AR_GPIO_BIT(gpio)) != 0;
  1683. else if (AR_SREV_9271(ah))
  1684. return MS_REG_READ(AR9271, gpio) != 0;
  1685. else if (AR_SREV_9287_11_OR_LATER(ah))
  1686. return MS_REG_READ(AR9287, gpio) != 0;
  1687. else if (AR_SREV_9285_12_OR_LATER(ah))
  1688. return MS_REG_READ(AR9285, gpio) != 0;
  1689. else if (AR_SREV_9280_20_OR_LATER(ah))
  1690. return MS_REG_READ(AR928X, gpio) != 0;
  1691. else
  1692. return MS_REG_READ(AR, gpio) != 0;
  1693. }
  1694. EXPORT_SYMBOL(ath9k_hw_gpio_get);
  1695. void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
  1696. u32 ah_signal_type)
  1697. {
  1698. u32 gpio_shift;
  1699. if (AR_DEVID_7010(ah)) {
  1700. gpio_shift = gpio;
  1701. REG_RMW(ah, AR7010_GPIO_OE,
  1702. (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
  1703. (AR7010_GPIO_OE_MASK << gpio_shift));
  1704. return;
  1705. }
  1706. ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
  1707. gpio_shift = 2 * gpio;
  1708. REG_RMW(ah,
  1709. AR_GPIO_OE_OUT,
  1710. (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
  1711. (AR_GPIO_OE_OUT_DRV << gpio_shift));
  1712. }
  1713. EXPORT_SYMBOL(ath9k_hw_cfg_output);
  1714. void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
  1715. {
  1716. if (AR_DEVID_7010(ah)) {
  1717. val = val ? 0 : 1;
  1718. REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
  1719. AR_GPIO_BIT(gpio));
  1720. return;
  1721. }
  1722. if (AR_SREV_9271(ah))
  1723. val = ~val;
  1724. REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
  1725. AR_GPIO_BIT(gpio));
  1726. }
  1727. EXPORT_SYMBOL(ath9k_hw_set_gpio);
  1728. u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
  1729. {
  1730. return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
  1731. }
  1732. EXPORT_SYMBOL(ath9k_hw_getdefantenna);
  1733. void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
  1734. {
  1735. REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
  1736. }
  1737. EXPORT_SYMBOL(ath9k_hw_setantenna);
  1738. /*********************/
  1739. /* General Operation */
  1740. /*********************/
  1741. u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
  1742. {
  1743. u32 bits = REG_READ(ah, AR_RX_FILTER);
  1744. u32 phybits = REG_READ(ah, AR_PHY_ERR);
  1745. if (phybits & AR_PHY_ERR_RADAR)
  1746. bits |= ATH9K_RX_FILTER_PHYRADAR;
  1747. if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
  1748. bits |= ATH9K_RX_FILTER_PHYERR;
  1749. return bits;
  1750. }
  1751. EXPORT_SYMBOL(ath9k_hw_getrxfilter);
  1752. void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
  1753. {
  1754. u32 phybits;
  1755. ENABLE_REGWRITE_BUFFER(ah);
  1756. REG_WRITE(ah, AR_RX_FILTER, bits);
  1757. phybits = 0;
  1758. if (bits & ATH9K_RX_FILTER_PHYRADAR)
  1759. phybits |= AR_PHY_ERR_RADAR;
  1760. if (bits & ATH9K_RX_FILTER_PHYERR)
  1761. phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
  1762. REG_WRITE(ah, AR_PHY_ERR, phybits);
  1763. if (phybits)
  1764. REG_WRITE(ah, AR_RXCFG,
  1765. REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
  1766. else
  1767. REG_WRITE(ah, AR_RXCFG,
  1768. REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
  1769. REGWRITE_BUFFER_FLUSH(ah);
  1770. }
  1771. EXPORT_SYMBOL(ath9k_hw_setrxfilter);
  1772. bool ath9k_hw_phy_disable(struct ath_hw *ah)
  1773. {
  1774. if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
  1775. return false;
  1776. ath9k_hw_init_pll(ah, NULL);
  1777. return true;
  1778. }
  1779. EXPORT_SYMBOL(ath9k_hw_phy_disable);
  1780. bool ath9k_hw_disable(struct ath_hw *ah)
  1781. {
  1782. if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
  1783. return false;
  1784. if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
  1785. return false;
  1786. ath9k_hw_init_pll(ah, NULL);
  1787. return true;
  1788. }
  1789. EXPORT_SYMBOL(ath9k_hw_disable);
  1790. void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
  1791. {
  1792. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  1793. struct ath9k_channel *chan = ah->curchan;
  1794. struct ieee80211_channel *channel = chan->chan;
  1795. regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
  1796. ah->eep_ops->set_txpower(ah, chan,
  1797. ath9k_regd_get_ctl(regulatory, chan),
  1798. channel->max_antenna_gain * 2,
  1799. channel->max_power * 2,
  1800. min((u32) MAX_RATE_POWER,
  1801. (u32) regulatory->power_limit), test);
  1802. }
  1803. EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
  1804. void ath9k_hw_setopmode(struct ath_hw *ah)
  1805. {
  1806. ath9k_hw_set_operating_mode(ah, ah->opmode);
  1807. }
  1808. EXPORT_SYMBOL(ath9k_hw_setopmode);
  1809. void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
  1810. {
  1811. REG_WRITE(ah, AR_MCAST_FIL0, filter0);
  1812. REG_WRITE(ah, AR_MCAST_FIL1, filter1);
  1813. }
  1814. EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
  1815. void ath9k_hw_write_associd(struct ath_hw *ah)
  1816. {
  1817. struct ath_common *common = ath9k_hw_common(ah);
  1818. REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
  1819. REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
  1820. ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
  1821. }
  1822. EXPORT_SYMBOL(ath9k_hw_write_associd);
  1823. #define ATH9K_MAX_TSF_READ 10
  1824. u64 ath9k_hw_gettsf64(struct ath_hw *ah)
  1825. {
  1826. u32 tsf_lower, tsf_upper1, tsf_upper2;
  1827. int i;
  1828. tsf_upper1 = REG_READ(ah, AR_TSF_U32);
  1829. for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
  1830. tsf_lower = REG_READ(ah, AR_TSF_L32);
  1831. tsf_upper2 = REG_READ(ah, AR_TSF_U32);
  1832. if (tsf_upper2 == tsf_upper1)
  1833. break;
  1834. tsf_upper1 = tsf_upper2;
  1835. }
  1836. WARN_ON( i == ATH9K_MAX_TSF_READ );
  1837. return (((u64)tsf_upper1 << 32) | tsf_lower);
  1838. }
  1839. EXPORT_SYMBOL(ath9k_hw_gettsf64);
  1840. void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
  1841. {
  1842. REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
  1843. REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
  1844. }
  1845. EXPORT_SYMBOL(ath9k_hw_settsf64);
  1846. void ath9k_hw_reset_tsf(struct ath_hw *ah)
  1847. {
  1848. if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
  1849. AH_TSF_WRITE_TIMEOUT))
  1850. ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
  1851. "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
  1852. REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
  1853. }
  1854. EXPORT_SYMBOL(ath9k_hw_reset_tsf);
  1855. void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
  1856. {
  1857. if (setting)
  1858. ah->misc_mode |= AR_PCU_TX_ADD_TSF;
  1859. else
  1860. ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
  1861. }
  1862. EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
  1863. void ath9k_hw_set11nmac2040(struct ath_hw *ah)
  1864. {
  1865. struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  1866. u32 macmode;
  1867. if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
  1868. macmode = AR_2040_JOINED_RX_CLEAR;
  1869. else
  1870. macmode = 0;
  1871. REG_WRITE(ah, AR_2040_MODE, macmode);
  1872. }
  1873. /* HW Generic timers configuration */
  1874. static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
  1875. {
  1876. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  1877. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  1878. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  1879. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  1880. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  1881. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  1882. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  1883. {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
  1884. {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
  1885. {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
  1886. AR_NDP2_TIMER_MODE, 0x0002},
  1887. {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
  1888. AR_NDP2_TIMER_MODE, 0x0004},
  1889. {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
  1890. AR_NDP2_TIMER_MODE, 0x0008},
  1891. {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
  1892. AR_NDP2_TIMER_MODE, 0x0010},
  1893. {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
  1894. AR_NDP2_TIMER_MODE, 0x0020},
  1895. {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
  1896. AR_NDP2_TIMER_MODE, 0x0040},
  1897. {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
  1898. AR_NDP2_TIMER_MODE, 0x0080}
  1899. };
  1900. /* HW generic timer primitives */
  1901. /* compute and clear index of rightmost 1 */
  1902. static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
  1903. {
  1904. u32 b;
  1905. b = *mask;
  1906. b &= (0-b);
  1907. *mask &= ~b;
  1908. b *= debruijn32;
  1909. b >>= 27;
  1910. return timer_table->gen_timer_index[b];
  1911. }
  1912. static u32 ath9k_hw_gettsf32(struct ath_hw *ah)
  1913. {
  1914. return REG_READ(ah, AR_TSF_L32);
  1915. }
  1916. struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
  1917. void (*trigger)(void *),
  1918. void (*overflow)(void *),
  1919. void *arg,
  1920. u8 timer_index)
  1921. {
  1922. struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
  1923. struct ath_gen_timer *timer;
  1924. timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
  1925. if (timer == NULL) {
  1926. ath_err(ath9k_hw_common(ah),
  1927. "Failed to allocate memory for hw timer[%d]\n",
  1928. timer_index);
  1929. return NULL;
  1930. }
  1931. /* allocate a hardware generic timer slot */
  1932. timer_table->timers[timer_index] = timer;
  1933. timer->index = timer_index;
  1934. timer->trigger = trigger;
  1935. timer->overflow = overflow;
  1936. timer->arg = arg;
  1937. return timer;
  1938. }
  1939. EXPORT_SYMBOL(ath_gen_timer_alloc);
  1940. void ath9k_hw_gen_timer_start(struct ath_hw *ah,
  1941. struct ath_gen_timer *timer,
  1942. u32 timer_next,
  1943. u32 timer_period)
  1944. {
  1945. struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
  1946. u32 tsf;
  1947. BUG_ON(!timer_period);
  1948. set_bit(timer->index, &timer_table->timer_mask.timer_bits);
  1949. tsf = ath9k_hw_gettsf32(ah);
  1950. ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
  1951. "current tsf %x period %x timer_next %x\n",
  1952. tsf, timer_period, timer_next);
  1953. /*
  1954. * Pull timer_next forward if the current TSF already passed it
  1955. * because of software latency
  1956. */
  1957. if (timer_next < tsf)
  1958. timer_next = tsf + timer_period;
  1959. /*
  1960. * Program generic timer registers
  1961. */
  1962. REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
  1963. timer_next);
  1964. REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
  1965. timer_period);
  1966. REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
  1967. gen_tmr_configuration[timer->index].mode_mask);
  1968. /* Enable both trigger and thresh interrupt masks */
  1969. REG_SET_BIT(ah, AR_IMR_S5,
  1970. (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
  1971. SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
  1972. }
  1973. EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
  1974. void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
  1975. {
  1976. struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
  1977. if ((timer->index < AR_FIRST_NDP_TIMER) ||
  1978. (timer->index >= ATH_MAX_GEN_TIMER)) {
  1979. return;
  1980. }
  1981. /* Clear generic timer enable bits. */
  1982. REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
  1983. gen_tmr_configuration[timer->index].mode_mask);
  1984. /* Disable both trigger and thresh interrupt masks */
  1985. REG_CLR_BIT(ah, AR_IMR_S5,
  1986. (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
  1987. SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
  1988. clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
  1989. }
  1990. EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
  1991. void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
  1992. {
  1993. struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
  1994. /* free the hardware generic timer slot */
  1995. timer_table->timers[timer->index] = NULL;
  1996. kfree(timer);
  1997. }
  1998. EXPORT_SYMBOL(ath_gen_timer_free);
  1999. /*
  2000. * Generic Timer Interrupts handling
  2001. */
  2002. void ath_gen_timer_isr(struct ath_hw *ah)
  2003. {
  2004. struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
  2005. struct ath_gen_timer *timer;
  2006. struct ath_common *common = ath9k_hw_common(ah);
  2007. u32 trigger_mask, thresh_mask, index;
  2008. /* get hardware generic timer interrupt status */
  2009. trigger_mask = ah->intr_gen_timer_trigger;
  2010. thresh_mask = ah->intr_gen_timer_thresh;
  2011. trigger_mask &= timer_table->timer_mask.val;
  2012. thresh_mask &= timer_table->timer_mask.val;
  2013. trigger_mask &= ~thresh_mask;
  2014. while (thresh_mask) {
  2015. index = rightmost_index(timer_table, &thresh_mask);
  2016. timer = timer_table->timers[index];
  2017. BUG_ON(!timer);
  2018. ath_dbg(common, ATH_DBG_HWTIMER,
  2019. "TSF overflow for Gen timer %d\n", index);
  2020. timer->overflow(timer->arg);
  2021. }
  2022. while (trigger_mask) {
  2023. index = rightmost_index(timer_table, &trigger_mask);
  2024. timer = timer_table->timers[index];
  2025. BUG_ON(!timer);
  2026. ath_dbg(common, ATH_DBG_HWTIMER,
  2027. "Gen timer[%d] trigger\n", index);
  2028. timer->trigger(timer->arg);
  2029. }
  2030. }
  2031. EXPORT_SYMBOL(ath_gen_timer_isr);
  2032. /********/
  2033. /* HTC */
  2034. /********/
  2035. void ath9k_hw_htc_resetinit(struct ath_hw *ah)
  2036. {
  2037. ah->htc_reset_init = true;
  2038. }
  2039. EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
  2040. static struct {
  2041. u32 version;
  2042. const char * name;
  2043. } ath_mac_bb_names[] = {
  2044. /* Devices with external radios */
  2045. { AR_SREV_VERSION_5416_PCI, "5416" },
  2046. { AR_SREV_VERSION_5416_PCIE, "5418" },
  2047. { AR_SREV_VERSION_9100, "9100" },
  2048. { AR_SREV_VERSION_9160, "9160" },
  2049. /* Single-chip solutions */
  2050. { AR_SREV_VERSION_9280, "9280" },
  2051. { AR_SREV_VERSION_9285, "9285" },
  2052. { AR_SREV_VERSION_9287, "9287" },
  2053. { AR_SREV_VERSION_9271, "9271" },
  2054. { AR_SREV_VERSION_9300, "9300" },
  2055. };
  2056. /* For devices with external radios */
  2057. static struct {
  2058. u16 version;
  2059. const char * name;
  2060. } ath_rf_names[] = {
  2061. { 0, "5133" },
  2062. { AR_RAD5133_SREV_MAJOR, "5133" },
  2063. { AR_RAD5122_SREV_MAJOR, "5122" },
  2064. { AR_RAD2133_SREV_MAJOR, "2133" },
  2065. { AR_RAD2122_SREV_MAJOR, "2122" }
  2066. };
  2067. /*
  2068. * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
  2069. */
  2070. static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
  2071. {
  2072. int i;
  2073. for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
  2074. if (ath_mac_bb_names[i].version == mac_bb_version) {
  2075. return ath_mac_bb_names[i].name;
  2076. }
  2077. }
  2078. return "????";
  2079. }
  2080. /*
  2081. * Return the RF name. "????" is returned if the RF is unknown.
  2082. * Used for devices with external radios.
  2083. */
  2084. static const char *ath9k_hw_rf_name(u16 rf_version)
  2085. {
  2086. int i;
  2087. for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
  2088. if (ath_rf_names[i].version == rf_version) {
  2089. return ath_rf_names[i].name;
  2090. }
  2091. }
  2092. return "????";
  2093. }
  2094. void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
  2095. {
  2096. int used;
  2097. /* chipsets >= AR9280 are single-chip */
  2098. if (AR_SREV_9280_20_OR_LATER(ah)) {
  2099. used = snprintf(hw_name, len,
  2100. "Atheros AR%s Rev:%x",
  2101. ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
  2102. ah->hw_version.macRev);
  2103. }
  2104. else {
  2105. used = snprintf(hw_name, len,
  2106. "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
  2107. ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
  2108. ah->hw_version.macRev,
  2109. ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
  2110. AR_RADIO_SREV_MAJOR)),
  2111. ah->hw_version.phyRev);
  2112. }
  2113. hw_name[used] = '\0';
  2114. }
  2115. EXPORT_SYMBOL(ath9k_hw_name);