eeprom_4k.c 34 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "hw.h"
  17. #include "ar9002_phy.h"
  18. static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
  19. {
  20. return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
  21. }
  22. static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
  23. {
  24. return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
  25. }
  26. static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  27. {
  28. #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  29. struct ath_common *common = ath9k_hw_common(ah);
  30. u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  31. int addr, eep_start_loc = 0;
  32. eep_start_loc = 64;
  33. if (!ath9k_hw_use_flash(ah)) {
  34. ath_dbg(common, ATH_DBG_EEPROM,
  35. "Reading from EEPROM, not flash\n");
  36. }
  37. for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
  38. if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
  39. ath_dbg(common, ATH_DBG_EEPROM,
  40. "Unable to read eeprom region\n");
  41. return false;
  42. }
  43. eep_data++;
  44. }
  45. return true;
  46. #undef SIZE_EEPROM_4K
  47. }
  48. static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
  49. {
  50. #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  51. struct ath_common *common = ath9k_hw_common(ah);
  52. struct ar5416_eeprom_4k *eep =
  53. (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
  54. u16 *eepdata, temp, magic, magic2;
  55. u32 sum = 0, el;
  56. bool need_swap = false;
  57. int i, addr;
  58. if (!ath9k_hw_use_flash(ah)) {
  59. if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
  60. &magic)) {
  61. ath_err(common, "Reading Magic # failed\n");
  62. return false;
  63. }
  64. ath_dbg(common, ATH_DBG_EEPROM,
  65. "Read Magic = 0x%04X\n", magic);
  66. if (magic != AR5416_EEPROM_MAGIC) {
  67. magic2 = swab16(magic);
  68. if (magic2 == AR5416_EEPROM_MAGIC) {
  69. need_swap = true;
  70. eepdata = (u16 *) (&ah->eeprom);
  71. for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
  72. temp = swab16(*eepdata);
  73. *eepdata = temp;
  74. eepdata++;
  75. }
  76. } else {
  77. ath_err(common,
  78. "Invalid EEPROM Magic. Endianness mismatch.\n");
  79. return -EINVAL;
  80. }
  81. }
  82. }
  83. ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
  84. need_swap ? "True" : "False");
  85. if (need_swap)
  86. el = swab16(ah->eeprom.map4k.baseEepHeader.length);
  87. else
  88. el = ah->eeprom.map4k.baseEepHeader.length;
  89. if (el > sizeof(struct ar5416_eeprom_4k))
  90. el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
  91. else
  92. el = el / sizeof(u16);
  93. eepdata = (u16 *)(&ah->eeprom);
  94. for (i = 0; i < el; i++)
  95. sum ^= *eepdata++;
  96. if (need_swap) {
  97. u32 integer;
  98. u16 word;
  99. ath_dbg(common, ATH_DBG_EEPROM,
  100. "EEPROM Endianness is not native.. Changing\n");
  101. word = swab16(eep->baseEepHeader.length);
  102. eep->baseEepHeader.length = word;
  103. word = swab16(eep->baseEepHeader.checksum);
  104. eep->baseEepHeader.checksum = word;
  105. word = swab16(eep->baseEepHeader.version);
  106. eep->baseEepHeader.version = word;
  107. word = swab16(eep->baseEepHeader.regDmn[0]);
  108. eep->baseEepHeader.regDmn[0] = word;
  109. word = swab16(eep->baseEepHeader.regDmn[1]);
  110. eep->baseEepHeader.regDmn[1] = word;
  111. word = swab16(eep->baseEepHeader.rfSilent);
  112. eep->baseEepHeader.rfSilent = word;
  113. word = swab16(eep->baseEepHeader.blueToothOptions);
  114. eep->baseEepHeader.blueToothOptions = word;
  115. word = swab16(eep->baseEepHeader.deviceCap);
  116. eep->baseEepHeader.deviceCap = word;
  117. integer = swab32(eep->modalHeader.antCtrlCommon);
  118. eep->modalHeader.antCtrlCommon = integer;
  119. for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
  120. integer = swab32(eep->modalHeader.antCtrlChain[i]);
  121. eep->modalHeader.antCtrlChain[i] = integer;
  122. }
  123. for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
  124. word = swab16(eep->modalHeader.spurChans[i].spurChan);
  125. eep->modalHeader.spurChans[i].spurChan = word;
  126. }
  127. }
  128. if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
  129. ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
  130. ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
  131. sum, ah->eep_ops->get_eeprom_ver(ah));
  132. return -EINVAL;
  133. }
  134. return 0;
  135. #undef EEPROM_4K_SIZE
  136. }
  137. static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
  138. enum eeprom_param param)
  139. {
  140. struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
  141. struct modal_eep_4k_header *pModal = &eep->modalHeader;
  142. struct base_eep_header_4k *pBase = &eep->baseEepHeader;
  143. u16 ver_minor;
  144. ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
  145. switch (param) {
  146. case EEP_NFTHRESH_2:
  147. return pModal->noiseFloorThreshCh[0];
  148. case EEP_MAC_LSW:
  149. return pBase->macAddr[0] << 8 | pBase->macAddr[1];
  150. case EEP_MAC_MID:
  151. return pBase->macAddr[2] << 8 | pBase->macAddr[3];
  152. case EEP_MAC_MSW:
  153. return pBase->macAddr[4] << 8 | pBase->macAddr[5];
  154. case EEP_REG_0:
  155. return pBase->regDmn[0];
  156. case EEP_REG_1:
  157. return pBase->regDmn[1];
  158. case EEP_OP_CAP:
  159. return pBase->deviceCap;
  160. case EEP_OP_MODE:
  161. return pBase->opCapFlags;
  162. case EEP_RF_SILENT:
  163. return pBase->rfSilent;
  164. case EEP_OB_2:
  165. return pModal->ob_0;
  166. case EEP_DB_2:
  167. return pModal->db1_1;
  168. case EEP_MINOR_REV:
  169. return ver_minor;
  170. case EEP_TX_MASK:
  171. return pBase->txMask;
  172. case EEP_RX_MASK:
  173. return pBase->rxMask;
  174. case EEP_FRAC_N_5G:
  175. return 0;
  176. case EEP_PWR_TABLE_OFFSET:
  177. return AR5416_PWR_TABLE_OFFSET_DB;
  178. case EEP_MODAL_VER:
  179. return pModal->version;
  180. case EEP_ANT_DIV_CTL1:
  181. return pModal->antdiv_ctl1;
  182. case EEP_TXGAIN_TYPE:
  183. if (ver_minor >= AR5416_EEP_MINOR_VER_19)
  184. return pBase->txGainType;
  185. else
  186. return AR5416_EEP_TXGAIN_ORIGINAL;
  187. default:
  188. return 0;
  189. }
  190. }
  191. static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
  192. struct ath9k_channel *chan,
  193. struct cal_data_per_freq_4k *pRawDataSet,
  194. u8 *bChans, u16 availPiers,
  195. u16 tPdGainOverlap,
  196. u16 *pPdGainBoundaries, u8 *pPDADCValues,
  197. u16 numXpdGains)
  198. {
  199. #define TMP_VAL_VPD_TABLE \
  200. ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
  201. int i, j, k;
  202. int16_t ss;
  203. u16 idxL = 0, idxR = 0, numPiers;
  204. static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
  205. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  206. static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
  207. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  208. static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
  209. [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
  210. u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
  211. u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
  212. u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
  213. int16_t vpdStep;
  214. int16_t tmpVal;
  215. u16 sizeCurrVpdTable, maxIndex, tgtIndex;
  216. bool match;
  217. int16_t minDelta = 0;
  218. struct chan_centers centers;
  219. #define PD_GAIN_BOUNDARY_DEFAULT 58;
  220. memset(&minPwrT4, 0, AR9287_NUM_PD_GAINS);
  221. ath9k_hw_get_channel_centers(ah, chan, &centers);
  222. for (numPiers = 0; numPiers < availPiers; numPiers++) {
  223. if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
  224. break;
  225. }
  226. match = ath9k_hw_get_lower_upper_index(
  227. (u8)FREQ2FBIN(centers.synth_center,
  228. IS_CHAN_2GHZ(chan)), bChans, numPiers,
  229. &idxL, &idxR);
  230. if (match) {
  231. for (i = 0; i < numXpdGains; i++) {
  232. minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
  233. maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
  234. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  235. pRawDataSet[idxL].pwrPdg[i],
  236. pRawDataSet[idxL].vpdPdg[i],
  237. AR5416_EEP4K_PD_GAIN_ICEPTS,
  238. vpdTableI[i]);
  239. }
  240. } else {
  241. for (i = 0; i < numXpdGains; i++) {
  242. pVpdL = pRawDataSet[idxL].vpdPdg[i];
  243. pPwrL = pRawDataSet[idxL].pwrPdg[i];
  244. pVpdR = pRawDataSet[idxR].vpdPdg[i];
  245. pPwrR = pRawDataSet[idxR].pwrPdg[i];
  246. minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
  247. maxPwrT4[i] =
  248. min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
  249. pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
  250. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  251. pPwrL, pVpdL,
  252. AR5416_EEP4K_PD_GAIN_ICEPTS,
  253. vpdTableL[i]);
  254. ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
  255. pPwrR, pVpdR,
  256. AR5416_EEP4K_PD_GAIN_ICEPTS,
  257. vpdTableR[i]);
  258. for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
  259. vpdTableI[i][j] =
  260. (u8)(ath9k_hw_interpolate((u16)
  261. FREQ2FBIN(centers.
  262. synth_center,
  263. IS_CHAN_2GHZ
  264. (chan)),
  265. bChans[idxL], bChans[idxR],
  266. vpdTableL[i][j], vpdTableR[i][j]));
  267. }
  268. }
  269. }
  270. k = 0;
  271. for (i = 0; i < numXpdGains; i++) {
  272. if (i == (numXpdGains - 1))
  273. pPdGainBoundaries[i] =
  274. (u16)(maxPwrT4[i] / 2);
  275. else
  276. pPdGainBoundaries[i] =
  277. (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
  278. pPdGainBoundaries[i] =
  279. min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
  280. if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
  281. minDelta = pPdGainBoundaries[0] - 23;
  282. pPdGainBoundaries[0] = 23;
  283. } else {
  284. minDelta = 0;
  285. }
  286. if (i == 0) {
  287. if (AR_SREV_9280_20_OR_LATER(ah))
  288. ss = (int16_t)(0 - (minPwrT4[i] / 2));
  289. else
  290. ss = 0;
  291. } else {
  292. ss = (int16_t)((pPdGainBoundaries[i - 1] -
  293. (minPwrT4[i] / 2)) -
  294. tPdGainOverlap + 1 + minDelta);
  295. }
  296. vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
  297. vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
  298. while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  299. tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
  300. pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
  301. ss++;
  302. }
  303. sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
  304. tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
  305. (minPwrT4[i] / 2));
  306. maxIndex = (tgtIndex < sizeCurrVpdTable) ?
  307. tgtIndex : sizeCurrVpdTable;
  308. while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
  309. pPDADCValues[k++] = vpdTableI[i][ss++];
  310. vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
  311. vpdTableI[i][sizeCurrVpdTable - 2]);
  312. vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
  313. if (tgtIndex >= maxIndex) {
  314. while ((ss <= tgtIndex) &&
  315. (k < (AR5416_NUM_PDADC_VALUES - 1))) {
  316. tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
  317. pPDADCValues[k++] = (u8)((tmpVal > 255) ?
  318. 255 : tmpVal);
  319. ss++;
  320. }
  321. }
  322. }
  323. while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
  324. pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
  325. i++;
  326. }
  327. while (k < AR5416_NUM_PDADC_VALUES) {
  328. pPDADCValues[k] = pPDADCValues[k - 1];
  329. k++;
  330. }
  331. return;
  332. #undef TMP_VAL_VPD_TABLE
  333. }
  334. static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
  335. struct ath9k_channel *chan,
  336. int16_t *pTxPowerIndexOffset)
  337. {
  338. struct ath_common *common = ath9k_hw_common(ah);
  339. struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
  340. struct cal_data_per_freq_4k *pRawDataset;
  341. u8 *pCalBChans = NULL;
  342. u16 pdGainOverlap_t2;
  343. static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
  344. u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
  345. u16 numPiers, i, j;
  346. u16 numXpdGain, xpdMask;
  347. u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
  348. u32 reg32, regOffset, regChainOffset;
  349. xpdMask = pEepData->modalHeader.xpdGain;
  350. if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
  351. AR5416_EEP_MINOR_VER_2) {
  352. pdGainOverlap_t2 =
  353. pEepData->modalHeader.pdGainOverlap;
  354. } else {
  355. pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
  356. AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
  357. }
  358. pCalBChans = pEepData->calFreqPier2G;
  359. numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
  360. numXpdGain = 0;
  361. for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
  362. if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
  363. if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
  364. break;
  365. xpdGainValues[numXpdGain] =
  366. (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
  367. numXpdGain++;
  368. }
  369. }
  370. REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
  371. (numXpdGain - 1) & 0x3);
  372. REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
  373. xpdGainValues[0]);
  374. REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
  375. xpdGainValues[1]);
  376. REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
  377. for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
  378. if (AR_SREV_5416_20_OR_LATER(ah) &&
  379. (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
  380. (i != 0)) {
  381. regChainOffset = (i == 1) ? 0x2000 : 0x1000;
  382. } else
  383. regChainOffset = i * 0x1000;
  384. if (pEepData->baseEepHeader.txMask & (1 << i)) {
  385. pRawDataset = pEepData->calPierData2G[i];
  386. ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
  387. pRawDataset, pCalBChans,
  388. numPiers, pdGainOverlap_t2,
  389. gainBoundaries,
  390. pdadcValues, numXpdGain);
  391. ENABLE_REGWRITE_BUFFER(ah);
  392. if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
  393. REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
  394. SM(pdGainOverlap_t2,
  395. AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
  396. | SM(gainBoundaries[0],
  397. AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
  398. | SM(gainBoundaries[1],
  399. AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
  400. | SM(gainBoundaries[2],
  401. AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
  402. | SM(gainBoundaries[3],
  403. AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
  404. }
  405. regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
  406. for (j = 0; j < 32; j++) {
  407. reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
  408. ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
  409. ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
  410. ((pdadcValues[4 * j + 3] & 0xFF) << 24);
  411. REG_WRITE(ah, regOffset, reg32);
  412. ath_dbg(common, ATH_DBG_EEPROM,
  413. "PDADC (%d,%4x): %4.4x %8.8x\n",
  414. i, regChainOffset, regOffset,
  415. reg32);
  416. ath_dbg(common, ATH_DBG_EEPROM,
  417. "PDADC: Chain %d | "
  418. "PDADC %3d Value %3d | "
  419. "PDADC %3d Value %3d | "
  420. "PDADC %3d Value %3d | "
  421. "PDADC %3d Value %3d |\n",
  422. i, 4 * j, pdadcValues[4 * j],
  423. 4 * j + 1, pdadcValues[4 * j + 1],
  424. 4 * j + 2, pdadcValues[4 * j + 2],
  425. 4 * j + 3, pdadcValues[4 * j + 3]);
  426. regOffset += 4;
  427. }
  428. REGWRITE_BUFFER_FLUSH(ah);
  429. }
  430. }
  431. *pTxPowerIndexOffset = 0;
  432. }
  433. static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
  434. struct ath9k_channel *chan,
  435. int16_t *ratesArray,
  436. u16 cfgCtl,
  437. u16 AntennaReduction,
  438. u16 twiceMaxRegulatoryPower,
  439. u16 powerLimit)
  440. {
  441. #define CMP_TEST_GRP \
  442. (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) == \
  443. pEepData->ctlIndex[i]) \
  444. || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
  445. ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
  446. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  447. int i;
  448. int16_t twiceLargestAntenna;
  449. u16 twiceMinEdgePower;
  450. u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
  451. u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
  452. u16 numCtlModes;
  453. const u16 *pCtlMode;
  454. u16 ctlMode, freq;
  455. struct chan_centers centers;
  456. struct cal_ctl_data_4k *rep;
  457. struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
  458. static const u16 tpScaleReductionTable[5] =
  459. { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
  460. struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
  461. 0, { 0, 0, 0, 0}
  462. };
  463. struct cal_target_power_leg targetPowerOfdmExt = {
  464. 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
  465. 0, { 0, 0, 0, 0 }
  466. };
  467. struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
  468. 0, {0, 0, 0, 0}
  469. };
  470. static const u16 ctlModesFor11g[] = {
  471. CTL_11B, CTL_11G, CTL_2GHT20,
  472. CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
  473. };
  474. ath9k_hw_get_channel_centers(ah, chan, &centers);
  475. twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
  476. twiceLargestAntenna = (int16_t)min(AntennaReduction -
  477. twiceLargestAntenna, 0);
  478. maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
  479. if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
  480. maxRegAllowedPower -=
  481. (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
  482. }
  483. scaledPower = min(powerLimit, maxRegAllowedPower);
  484. scaledPower = max((u16)0, scaledPower);
  485. numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
  486. pCtlMode = ctlModesFor11g;
  487. ath9k_hw_get_legacy_target_powers(ah, chan,
  488. pEepData->calTargetPowerCck,
  489. AR5416_NUM_2G_CCK_TARGET_POWERS,
  490. &targetPowerCck, 4, false);
  491. ath9k_hw_get_legacy_target_powers(ah, chan,
  492. pEepData->calTargetPower2G,
  493. AR5416_NUM_2G_20_TARGET_POWERS,
  494. &targetPowerOfdm, 4, false);
  495. ath9k_hw_get_target_powers(ah, chan,
  496. pEepData->calTargetPower2GHT20,
  497. AR5416_NUM_2G_20_TARGET_POWERS,
  498. &targetPowerHt20, 8, false);
  499. if (IS_CHAN_HT40(chan)) {
  500. numCtlModes = ARRAY_SIZE(ctlModesFor11g);
  501. ath9k_hw_get_target_powers(ah, chan,
  502. pEepData->calTargetPower2GHT40,
  503. AR5416_NUM_2G_40_TARGET_POWERS,
  504. &targetPowerHt40, 8, true);
  505. ath9k_hw_get_legacy_target_powers(ah, chan,
  506. pEepData->calTargetPowerCck,
  507. AR5416_NUM_2G_CCK_TARGET_POWERS,
  508. &targetPowerCckExt, 4, true);
  509. ath9k_hw_get_legacy_target_powers(ah, chan,
  510. pEepData->calTargetPower2G,
  511. AR5416_NUM_2G_20_TARGET_POWERS,
  512. &targetPowerOfdmExt, 4, true);
  513. }
  514. for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
  515. bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
  516. (pCtlMode[ctlMode] == CTL_2GHT40);
  517. if (isHt40CtlMode)
  518. freq = centers.synth_center;
  519. else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
  520. freq = centers.ext_center;
  521. else
  522. freq = centers.ctl_center;
  523. if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
  524. ah->eep_ops->get_eeprom_rev(ah) <= 2)
  525. twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
  526. for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
  527. pEepData->ctlIndex[i]; i++) {
  528. if (CMP_TEST_GRP) {
  529. rep = &(pEepData->ctlData[i]);
  530. twiceMinEdgePower = ath9k_hw_get_max_edge_power(
  531. freq,
  532. rep->ctlEdges[
  533. ar5416_get_ntxchains(ah->txchainmask) - 1],
  534. IS_CHAN_2GHZ(chan),
  535. AR5416_EEP4K_NUM_BAND_EDGES);
  536. if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
  537. twiceMaxEdgePower =
  538. min(twiceMaxEdgePower,
  539. twiceMinEdgePower);
  540. } else {
  541. twiceMaxEdgePower = twiceMinEdgePower;
  542. break;
  543. }
  544. }
  545. }
  546. minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
  547. switch (pCtlMode[ctlMode]) {
  548. case CTL_11B:
  549. for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
  550. targetPowerCck.tPow2x[i] =
  551. min((u16)targetPowerCck.tPow2x[i],
  552. minCtlPower);
  553. }
  554. break;
  555. case CTL_11G:
  556. for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
  557. targetPowerOfdm.tPow2x[i] =
  558. min((u16)targetPowerOfdm.tPow2x[i],
  559. minCtlPower);
  560. }
  561. break;
  562. case CTL_2GHT20:
  563. for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
  564. targetPowerHt20.tPow2x[i] =
  565. min((u16)targetPowerHt20.tPow2x[i],
  566. minCtlPower);
  567. }
  568. break;
  569. case CTL_11B_EXT:
  570. targetPowerCckExt.tPow2x[0] =
  571. min((u16)targetPowerCckExt.tPow2x[0],
  572. minCtlPower);
  573. break;
  574. case CTL_11G_EXT:
  575. targetPowerOfdmExt.tPow2x[0] =
  576. min((u16)targetPowerOfdmExt.tPow2x[0],
  577. minCtlPower);
  578. break;
  579. case CTL_2GHT40:
  580. for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
  581. targetPowerHt40.tPow2x[i] =
  582. min((u16)targetPowerHt40.tPow2x[i],
  583. minCtlPower);
  584. }
  585. break;
  586. default:
  587. break;
  588. }
  589. }
  590. ratesArray[rate6mb] =
  591. ratesArray[rate9mb] =
  592. ratesArray[rate12mb] =
  593. ratesArray[rate18mb] =
  594. ratesArray[rate24mb] =
  595. targetPowerOfdm.tPow2x[0];
  596. ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
  597. ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
  598. ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
  599. ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
  600. for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
  601. ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
  602. ratesArray[rate1l] = targetPowerCck.tPow2x[0];
  603. ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
  604. ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
  605. ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
  606. if (IS_CHAN_HT40(chan)) {
  607. for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
  608. ratesArray[rateHt40_0 + i] =
  609. targetPowerHt40.tPow2x[i];
  610. }
  611. ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
  612. ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
  613. ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
  614. ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
  615. }
  616. #undef CMP_TEST_GRP
  617. }
  618. static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
  619. struct ath9k_channel *chan,
  620. u16 cfgCtl,
  621. u8 twiceAntennaReduction,
  622. u8 twiceMaxRegulatoryPower,
  623. u8 powerLimit, bool test)
  624. {
  625. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  626. struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
  627. struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
  628. int16_t ratesArray[Ar5416RateSize];
  629. int16_t txPowerIndexOffset = 0;
  630. u8 ht40PowerIncForPdadc = 2;
  631. int i;
  632. memset(ratesArray, 0, sizeof(ratesArray));
  633. if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
  634. AR5416_EEP_MINOR_VER_2) {
  635. ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
  636. }
  637. ath9k_hw_set_4k_power_per_rate_table(ah, chan,
  638. &ratesArray[0], cfgCtl,
  639. twiceAntennaReduction,
  640. twiceMaxRegulatoryPower,
  641. powerLimit);
  642. ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset);
  643. regulatory->max_power_level = 0;
  644. for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
  645. ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
  646. if (ratesArray[i] > AR5416_MAX_RATE_POWER)
  647. ratesArray[i] = AR5416_MAX_RATE_POWER;
  648. if (ratesArray[i] > regulatory->max_power_level)
  649. regulatory->max_power_level = ratesArray[i];
  650. }
  651. if (test)
  652. return;
  653. /* Update regulatory */
  654. i = rate6mb;
  655. if (IS_CHAN_HT40(chan))
  656. i = rateHt40_0;
  657. else if (IS_CHAN_HT20(chan))
  658. i = rateHt20_0;
  659. regulatory->max_power_level = ratesArray[i];
  660. if (AR_SREV_9280_20_OR_LATER(ah)) {
  661. for (i = 0; i < Ar5416RateSize; i++)
  662. ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
  663. }
  664. ENABLE_REGWRITE_BUFFER(ah);
  665. /* OFDM power per rate */
  666. REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
  667. ATH9K_POW_SM(ratesArray[rate18mb], 24)
  668. | ATH9K_POW_SM(ratesArray[rate12mb], 16)
  669. | ATH9K_POW_SM(ratesArray[rate9mb], 8)
  670. | ATH9K_POW_SM(ratesArray[rate6mb], 0));
  671. REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
  672. ATH9K_POW_SM(ratesArray[rate54mb], 24)
  673. | ATH9K_POW_SM(ratesArray[rate48mb], 16)
  674. | ATH9K_POW_SM(ratesArray[rate36mb], 8)
  675. | ATH9K_POW_SM(ratesArray[rate24mb], 0));
  676. /* CCK power per rate */
  677. REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
  678. ATH9K_POW_SM(ratesArray[rate2s], 24)
  679. | ATH9K_POW_SM(ratesArray[rate2l], 16)
  680. | ATH9K_POW_SM(ratesArray[rateXr], 8)
  681. | ATH9K_POW_SM(ratesArray[rate1l], 0));
  682. REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
  683. ATH9K_POW_SM(ratesArray[rate11s], 24)
  684. | ATH9K_POW_SM(ratesArray[rate11l], 16)
  685. | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
  686. | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
  687. /* HT20 power per rate */
  688. REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
  689. ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
  690. | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
  691. | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
  692. | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
  693. REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
  694. ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
  695. | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
  696. | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
  697. | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
  698. /* HT40 power per rate */
  699. if (IS_CHAN_HT40(chan)) {
  700. REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
  701. ATH9K_POW_SM(ratesArray[rateHt40_3] +
  702. ht40PowerIncForPdadc, 24)
  703. | ATH9K_POW_SM(ratesArray[rateHt40_2] +
  704. ht40PowerIncForPdadc, 16)
  705. | ATH9K_POW_SM(ratesArray[rateHt40_1] +
  706. ht40PowerIncForPdadc, 8)
  707. | ATH9K_POW_SM(ratesArray[rateHt40_0] +
  708. ht40PowerIncForPdadc, 0));
  709. REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
  710. ATH9K_POW_SM(ratesArray[rateHt40_7] +
  711. ht40PowerIncForPdadc, 24)
  712. | ATH9K_POW_SM(ratesArray[rateHt40_6] +
  713. ht40PowerIncForPdadc, 16)
  714. | ATH9K_POW_SM(ratesArray[rateHt40_5] +
  715. ht40PowerIncForPdadc, 8)
  716. | ATH9K_POW_SM(ratesArray[rateHt40_4] +
  717. ht40PowerIncForPdadc, 0));
  718. REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
  719. ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
  720. | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
  721. | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
  722. | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
  723. }
  724. REGWRITE_BUFFER_FLUSH(ah);
  725. }
  726. static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
  727. struct ath9k_channel *chan)
  728. {
  729. struct modal_eep_4k_header *pModal;
  730. struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
  731. u8 biaslevel;
  732. if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
  733. return;
  734. if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
  735. return;
  736. pModal = &eep->modalHeader;
  737. if (pModal->xpaBiasLvl != 0xff) {
  738. biaslevel = pModal->xpaBiasLvl;
  739. INI_RA(&ah->iniAddac, 7, 1) =
  740. (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
  741. }
  742. }
  743. static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
  744. struct modal_eep_4k_header *pModal,
  745. struct ar5416_eeprom_4k *eep,
  746. u8 txRxAttenLocal)
  747. {
  748. REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
  749. pModal->antCtrlChain[0]);
  750. REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
  751. (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
  752. ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
  753. AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
  754. SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
  755. SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
  756. if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
  757. AR5416_EEP_MINOR_VER_3) {
  758. txRxAttenLocal = pModal->txRxAttenCh[0];
  759. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
  760. AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
  761. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
  762. AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
  763. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
  764. AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
  765. pModal->xatten2Margin[0]);
  766. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
  767. AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
  768. /* Set the block 1 value to block 0 value */
  769. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
  770. AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
  771. pModal->bswMargin[0]);
  772. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
  773. AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
  774. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
  775. AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
  776. pModal->xatten2Margin[0]);
  777. REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
  778. AR_PHY_GAIN_2GHZ_XATTEN2_DB,
  779. pModal->xatten2Db[0]);
  780. }
  781. REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
  782. AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
  783. REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
  784. AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
  785. REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
  786. AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
  787. REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
  788. AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
  789. }
  790. /*
  791. * Read EEPROM header info and program the device for correct operation
  792. * given the channel value.
  793. */
  794. static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
  795. struct ath9k_channel *chan)
  796. {
  797. struct modal_eep_4k_header *pModal;
  798. struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
  799. u8 txRxAttenLocal;
  800. u8 ob[5], db1[5], db2[5];
  801. u8 ant_div_control1, ant_div_control2;
  802. u32 regVal;
  803. pModal = &eep->modalHeader;
  804. txRxAttenLocal = 23;
  805. REG_WRITE(ah, AR_PHY_SWITCH_COM,
  806. ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
  807. /* Single chain for 4K EEPROM*/
  808. ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
  809. /* Initialize Ant Diversity settings from EEPROM */
  810. if (pModal->version >= 3) {
  811. ant_div_control1 = pModal->antdiv_ctl1;
  812. ant_div_control2 = pModal->antdiv_ctl2;
  813. regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
  814. regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
  815. regVal |= SM(ant_div_control1,
  816. AR_PHY_9285_ANT_DIV_CTL);
  817. regVal |= SM(ant_div_control2,
  818. AR_PHY_9285_ANT_DIV_ALT_LNACONF);
  819. regVal |= SM((ant_div_control2 >> 2),
  820. AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
  821. regVal |= SM((ant_div_control1 >> 1),
  822. AR_PHY_9285_ANT_DIV_ALT_GAINTB);
  823. regVal |= SM((ant_div_control1 >> 2),
  824. AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
  825. REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
  826. regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
  827. regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
  828. regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
  829. regVal |= SM((ant_div_control1 >> 3),
  830. AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
  831. REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
  832. regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
  833. }
  834. if (pModal->version >= 2) {
  835. ob[0] = pModal->ob_0;
  836. ob[1] = pModal->ob_1;
  837. ob[2] = pModal->ob_2;
  838. ob[3] = pModal->ob_3;
  839. ob[4] = pModal->ob_4;
  840. db1[0] = pModal->db1_0;
  841. db1[1] = pModal->db1_1;
  842. db1[2] = pModal->db1_2;
  843. db1[3] = pModal->db1_3;
  844. db1[4] = pModal->db1_4;
  845. db2[0] = pModal->db2_0;
  846. db2[1] = pModal->db2_1;
  847. db2[2] = pModal->db2_2;
  848. db2[3] = pModal->db2_3;
  849. db2[4] = pModal->db2_4;
  850. } else if (pModal->version == 1) {
  851. ob[0] = pModal->ob_0;
  852. ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
  853. db1[0] = pModal->db1_0;
  854. db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
  855. db2[0] = pModal->db2_0;
  856. db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
  857. } else {
  858. int i;
  859. for (i = 0; i < 5; i++) {
  860. ob[i] = pModal->ob_0;
  861. db1[i] = pModal->db1_0;
  862. db2[i] = pModal->db1_0;
  863. }
  864. }
  865. if (AR_SREV_9271(ah)) {
  866. ath9k_hw_analog_shift_rmw(ah,
  867. AR9285_AN_RF2G3,
  868. AR9271_AN_RF2G3_OB_cck,
  869. AR9271_AN_RF2G3_OB_cck_S,
  870. ob[0]);
  871. ath9k_hw_analog_shift_rmw(ah,
  872. AR9285_AN_RF2G3,
  873. AR9271_AN_RF2G3_OB_psk,
  874. AR9271_AN_RF2G3_OB_psk_S,
  875. ob[1]);
  876. ath9k_hw_analog_shift_rmw(ah,
  877. AR9285_AN_RF2G3,
  878. AR9271_AN_RF2G3_OB_qam,
  879. AR9271_AN_RF2G3_OB_qam_S,
  880. ob[2]);
  881. ath9k_hw_analog_shift_rmw(ah,
  882. AR9285_AN_RF2G3,
  883. AR9271_AN_RF2G3_DB_1,
  884. AR9271_AN_RF2G3_DB_1_S,
  885. db1[0]);
  886. ath9k_hw_analog_shift_rmw(ah,
  887. AR9285_AN_RF2G4,
  888. AR9271_AN_RF2G4_DB_2,
  889. AR9271_AN_RF2G4_DB_2_S,
  890. db2[0]);
  891. } else {
  892. ath9k_hw_analog_shift_rmw(ah,
  893. AR9285_AN_RF2G3,
  894. AR9285_AN_RF2G3_OB_0,
  895. AR9285_AN_RF2G3_OB_0_S,
  896. ob[0]);
  897. ath9k_hw_analog_shift_rmw(ah,
  898. AR9285_AN_RF2G3,
  899. AR9285_AN_RF2G3_OB_1,
  900. AR9285_AN_RF2G3_OB_1_S,
  901. ob[1]);
  902. ath9k_hw_analog_shift_rmw(ah,
  903. AR9285_AN_RF2G3,
  904. AR9285_AN_RF2G3_OB_2,
  905. AR9285_AN_RF2G3_OB_2_S,
  906. ob[2]);
  907. ath9k_hw_analog_shift_rmw(ah,
  908. AR9285_AN_RF2G3,
  909. AR9285_AN_RF2G3_OB_3,
  910. AR9285_AN_RF2G3_OB_3_S,
  911. ob[3]);
  912. ath9k_hw_analog_shift_rmw(ah,
  913. AR9285_AN_RF2G3,
  914. AR9285_AN_RF2G3_OB_4,
  915. AR9285_AN_RF2G3_OB_4_S,
  916. ob[4]);
  917. ath9k_hw_analog_shift_rmw(ah,
  918. AR9285_AN_RF2G3,
  919. AR9285_AN_RF2G3_DB1_0,
  920. AR9285_AN_RF2G3_DB1_0_S,
  921. db1[0]);
  922. ath9k_hw_analog_shift_rmw(ah,
  923. AR9285_AN_RF2G3,
  924. AR9285_AN_RF2G3_DB1_1,
  925. AR9285_AN_RF2G3_DB1_1_S,
  926. db1[1]);
  927. ath9k_hw_analog_shift_rmw(ah,
  928. AR9285_AN_RF2G3,
  929. AR9285_AN_RF2G3_DB1_2,
  930. AR9285_AN_RF2G3_DB1_2_S,
  931. db1[2]);
  932. ath9k_hw_analog_shift_rmw(ah,
  933. AR9285_AN_RF2G4,
  934. AR9285_AN_RF2G4_DB1_3,
  935. AR9285_AN_RF2G4_DB1_3_S,
  936. db1[3]);
  937. ath9k_hw_analog_shift_rmw(ah,
  938. AR9285_AN_RF2G4,
  939. AR9285_AN_RF2G4_DB1_4,
  940. AR9285_AN_RF2G4_DB1_4_S, db1[4]);
  941. ath9k_hw_analog_shift_rmw(ah,
  942. AR9285_AN_RF2G4,
  943. AR9285_AN_RF2G4_DB2_0,
  944. AR9285_AN_RF2G4_DB2_0_S,
  945. db2[0]);
  946. ath9k_hw_analog_shift_rmw(ah,
  947. AR9285_AN_RF2G4,
  948. AR9285_AN_RF2G4_DB2_1,
  949. AR9285_AN_RF2G4_DB2_1_S,
  950. db2[1]);
  951. ath9k_hw_analog_shift_rmw(ah,
  952. AR9285_AN_RF2G4,
  953. AR9285_AN_RF2G4_DB2_2,
  954. AR9285_AN_RF2G4_DB2_2_S,
  955. db2[2]);
  956. ath9k_hw_analog_shift_rmw(ah,
  957. AR9285_AN_RF2G4,
  958. AR9285_AN_RF2G4_DB2_3,
  959. AR9285_AN_RF2G4_DB2_3_S,
  960. db2[3]);
  961. ath9k_hw_analog_shift_rmw(ah,
  962. AR9285_AN_RF2G4,
  963. AR9285_AN_RF2G4_DB2_4,
  964. AR9285_AN_RF2G4_DB2_4_S,
  965. db2[4]);
  966. }
  967. REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
  968. pModal->switchSettling);
  969. REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
  970. pModal->adcDesiredSize);
  971. REG_WRITE(ah, AR_PHY_RF_CTL4,
  972. SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
  973. SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
  974. SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
  975. SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
  976. REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
  977. pModal->txEndToRxOn);
  978. if (AR_SREV_9271_10(ah))
  979. REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
  980. pModal->txEndToRxOn);
  981. REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
  982. pModal->thresh62);
  983. REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
  984. pModal->thresh62);
  985. if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
  986. AR5416_EEP_MINOR_VER_2) {
  987. REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
  988. pModal->txFrameToDataStart);
  989. REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
  990. pModal->txFrameToPaOn);
  991. }
  992. if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
  993. AR5416_EEP_MINOR_VER_3) {
  994. if (IS_CHAN_HT40(chan))
  995. REG_RMW_FIELD(ah, AR_PHY_SETTLING,
  996. AR_PHY_SETTLING_SWITCH,
  997. pModal->swSettleHt40);
  998. }
  999. }
  1000. static u32 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
  1001. struct ath9k_channel *chan)
  1002. {
  1003. struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
  1004. struct modal_eep_4k_header *pModal = &eep->modalHeader;
  1005. return pModal->antCtrlCommon;
  1006. }
  1007. static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
  1008. enum ath9k_hal_freq_band freq_band)
  1009. {
  1010. return 1;
  1011. }
  1012. static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
  1013. {
  1014. #define EEP_MAP4K_SPURCHAN \
  1015. (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
  1016. struct ath_common *common = ath9k_hw_common(ah);
  1017. u16 spur_val = AR_NO_SPUR;
  1018. ath_dbg(common, ATH_DBG_ANI,
  1019. "Getting spur idx:%d is2Ghz:%d val:%x\n",
  1020. i, is2GHz, ah->config.spurchans[i][is2GHz]);
  1021. switch (ah->config.spurmode) {
  1022. case SPUR_DISABLE:
  1023. break;
  1024. case SPUR_ENABLE_IOCTL:
  1025. spur_val = ah->config.spurchans[i][is2GHz];
  1026. ath_dbg(common, ATH_DBG_ANI,
  1027. "Getting spur val from new loc. %d\n", spur_val);
  1028. break;
  1029. case SPUR_ENABLE_EEPROM:
  1030. spur_val = EEP_MAP4K_SPURCHAN;
  1031. break;
  1032. }
  1033. return spur_val;
  1034. #undef EEP_MAP4K_SPURCHAN
  1035. }
  1036. const struct eeprom_ops eep_4k_ops = {
  1037. .check_eeprom = ath9k_hw_4k_check_eeprom,
  1038. .get_eeprom = ath9k_hw_4k_get_eeprom,
  1039. .fill_eeprom = ath9k_hw_4k_fill_eeprom,
  1040. .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
  1041. .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
  1042. .get_num_ant_config = ath9k_hw_4k_get_num_ant_config,
  1043. .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
  1044. .set_board_values = ath9k_hw_4k_set_board_values,
  1045. .set_addac = ath9k_hw_4k_set_addac,
  1046. .set_txpower = ath9k_hw_4k_set_txpower,
  1047. .get_spur_channel = ath9k_hw_4k_get_spur_channel
  1048. };