ar9003_eeprom.c 137 KB

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  1. /*
  2. * Copyright (c) 2010 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include "hw.h"
  17. #include "ar9003_phy.h"
  18. #include "ar9003_eeprom.h"
  19. #define COMP_HDR_LEN 4
  20. #define COMP_CKSUM_LEN 2
  21. #define AR_CH0_TOP (0x00016288)
  22. #define AR_CH0_TOP_XPABIASLVL (0x300)
  23. #define AR_CH0_TOP_XPABIASLVL_S (8)
  24. #define AR_CH0_THERM (0x00016290)
  25. #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
  26. #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
  27. #define AR_CH0_THERM_XPASHORT2GND 0x4
  28. #define AR_CH0_THERM_XPASHORT2GND_S 2
  29. #define AR_SWITCH_TABLE_COM_ALL (0xffff)
  30. #define AR_SWITCH_TABLE_COM_ALL_S (0)
  31. #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
  32. #define AR_SWITCH_TABLE_COM2_ALL_S (0)
  33. #define AR_SWITCH_TABLE_ALL (0xfff)
  34. #define AR_SWITCH_TABLE_ALL_S (0)
  35. #define LE16(x) __constant_cpu_to_le16(x)
  36. #define LE32(x) __constant_cpu_to_le32(x)
  37. /* Local defines to distinguish between extension and control CTL's */
  38. #define EXT_ADDITIVE (0x8000)
  39. #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  40. #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  41. #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  42. #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
  43. #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
  44. #define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
  45. #define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
  46. #define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
  47. #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
  48. #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
  49. #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
  50. static int ar9003_hw_power_interpolate(int32_t x,
  51. int32_t *px, int32_t *py, u_int16_t np);
  52. static const struct ar9300_eeprom ar9300_default = {
  53. .eepromVersion = 2,
  54. .templateVersion = 2,
  55. .macAddr = {1, 2, 3, 4, 5, 6},
  56. .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  57. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
  58. .baseEepHeader = {
  59. .regDmn = { LE16(0), LE16(0x1f) },
  60. .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
  61. .opCapFlags = {
  62. .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
  63. .eepMisc = 0,
  64. },
  65. .rfSilent = 0,
  66. .blueToothOptions = 0,
  67. .deviceCap = 0,
  68. .deviceType = 5, /* takes lower byte in eeprom location */
  69. .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  70. .params_for_tuning_caps = {0, 0},
  71. .featureEnable = 0x0c,
  72. /*
  73. * bit0 - enable tx temp comp - disabled
  74. * bit1 - enable tx volt comp - disabled
  75. * bit2 - enable fastClock - enabled
  76. * bit3 - enable doubling - enabled
  77. * bit4 - enable internal regulator - disabled
  78. * bit5 - enable pa predistortion - disabled
  79. */
  80. .miscConfiguration = 0, /* bit0 - turn down drivestrength */
  81. .eepromWriteEnableGpio = 3,
  82. .wlanDisableGpio = 0,
  83. .wlanLedGpio = 8,
  84. .rxBandSelectGpio = 0xff,
  85. .txrxgain = 0,
  86. .swreg = 0,
  87. },
  88. .modalHeader2G = {
  89. /* ar9300_modal_eep_header 2g */
  90. /* 4 idle,t1,t2,b(4 bits per setting) */
  91. .antCtrlCommon = LE32(0x110),
  92. /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
  93. .antCtrlCommon2 = LE32(0x22222),
  94. /*
  95. * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
  96. * rx1, rx12, b (2 bits each)
  97. */
  98. .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
  99. /*
  100. * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
  101. * for ar9280 (0xa20c/b20c 5:0)
  102. */
  103. .xatten1DB = {0, 0, 0},
  104. /*
  105. * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
  106. * for ar9280 (0xa20c/b20c 16:12
  107. */
  108. .xatten1Margin = {0, 0, 0},
  109. .tempSlope = 36,
  110. .voltSlope = 0,
  111. /*
  112. * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
  113. * channels in usual fbin coding format
  114. */
  115. .spurChans = {0, 0, 0, 0, 0},
  116. /*
  117. * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
  118. * if the register is per chain
  119. */
  120. .noiseFloorThreshCh = {-1, 0, 0},
  121. .ob = {1, 1, 1},/* 3 chain */
  122. .db_stage2 = {1, 1, 1}, /* 3 chain */
  123. .db_stage3 = {0, 0, 0},
  124. .db_stage4 = {0, 0, 0},
  125. .xpaBiasLvl = 0,
  126. .txFrameToDataStart = 0x0e,
  127. .txFrameToPaOn = 0x0e,
  128. .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
  129. .antennaGain = 0,
  130. .switchSettling = 0x2c,
  131. .adcDesiredSize = -30,
  132. .txEndToXpaOff = 0,
  133. .txEndToRxOn = 0x2,
  134. .txFrameToXpaOn = 0xe,
  135. .thresh62 = 28,
  136. .papdRateMaskHt20 = LE32(0x0cf0e0e0),
  137. .papdRateMaskHt40 = LE32(0x6cf0e0e0),
  138. .futureModal = {
  139. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  140. },
  141. },
  142. .base_ext1 = {
  143. .ant_div_control = 0,
  144. .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  145. },
  146. .calFreqPier2G = {
  147. FREQ2FBIN(2412, 1),
  148. FREQ2FBIN(2437, 1),
  149. FREQ2FBIN(2472, 1),
  150. },
  151. /* ar9300_cal_data_per_freq_op_loop 2g */
  152. .calPierData2G = {
  153. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  154. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  155. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  156. },
  157. .calTarget_freqbin_Cck = {
  158. FREQ2FBIN(2412, 1),
  159. FREQ2FBIN(2484, 1),
  160. },
  161. .calTarget_freqbin_2G = {
  162. FREQ2FBIN(2412, 1),
  163. FREQ2FBIN(2437, 1),
  164. FREQ2FBIN(2472, 1)
  165. },
  166. .calTarget_freqbin_2GHT20 = {
  167. FREQ2FBIN(2412, 1),
  168. FREQ2FBIN(2437, 1),
  169. FREQ2FBIN(2472, 1)
  170. },
  171. .calTarget_freqbin_2GHT40 = {
  172. FREQ2FBIN(2412, 1),
  173. FREQ2FBIN(2437, 1),
  174. FREQ2FBIN(2472, 1)
  175. },
  176. .calTargetPowerCck = {
  177. /* 1L-5L,5S,11L,11S */
  178. { {36, 36, 36, 36} },
  179. { {36, 36, 36, 36} },
  180. },
  181. .calTargetPower2G = {
  182. /* 6-24,36,48,54 */
  183. { {32, 32, 28, 24} },
  184. { {32, 32, 28, 24} },
  185. { {32, 32, 28, 24} },
  186. },
  187. .calTargetPower2GHT20 = {
  188. { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
  189. { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
  190. { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
  191. },
  192. .calTargetPower2GHT40 = {
  193. { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
  194. { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
  195. { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
  196. },
  197. .ctlIndex_2G = {
  198. 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
  199. 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
  200. },
  201. .ctl_freqbin_2G = {
  202. {
  203. FREQ2FBIN(2412, 1),
  204. FREQ2FBIN(2417, 1),
  205. FREQ2FBIN(2457, 1),
  206. FREQ2FBIN(2462, 1)
  207. },
  208. {
  209. FREQ2FBIN(2412, 1),
  210. FREQ2FBIN(2417, 1),
  211. FREQ2FBIN(2462, 1),
  212. 0xFF,
  213. },
  214. {
  215. FREQ2FBIN(2412, 1),
  216. FREQ2FBIN(2417, 1),
  217. FREQ2FBIN(2462, 1),
  218. 0xFF,
  219. },
  220. {
  221. FREQ2FBIN(2422, 1),
  222. FREQ2FBIN(2427, 1),
  223. FREQ2FBIN(2447, 1),
  224. FREQ2FBIN(2452, 1)
  225. },
  226. {
  227. /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  228. /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  229. /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  230. /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
  231. },
  232. {
  233. /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  234. /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  235. /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  236. 0,
  237. },
  238. {
  239. /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  240. /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  241. FREQ2FBIN(2472, 1),
  242. 0,
  243. },
  244. {
  245. /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
  246. /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
  247. /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
  248. /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
  249. },
  250. {
  251. /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  252. /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  253. /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  254. },
  255. {
  256. /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  257. /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  258. /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  259. 0
  260. },
  261. {
  262. /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  263. /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  264. /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  265. 0
  266. },
  267. {
  268. /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
  269. /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
  270. /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
  271. /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
  272. }
  273. },
  274. .ctlPowerData_2G = {
  275. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  276. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  277. { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
  278. { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
  279. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  280. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  281. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
  282. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  283. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  284. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  285. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
  286. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
  287. },
  288. .modalHeader5G = {
  289. /* 4 idle,t1,t2,b (4 bits per setting) */
  290. .antCtrlCommon = LE32(0x110),
  291. /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
  292. .antCtrlCommon2 = LE32(0x22222),
  293. /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
  294. .antCtrlChain = {
  295. LE16(0x000), LE16(0x000), LE16(0x000),
  296. },
  297. /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
  298. .xatten1DB = {0, 0, 0},
  299. /*
  300. * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
  301. * for merlin (0xa20c/b20c 16:12
  302. */
  303. .xatten1Margin = {0, 0, 0},
  304. .tempSlope = 68,
  305. .voltSlope = 0,
  306. /* spurChans spur channels in usual fbin coding format */
  307. .spurChans = {0, 0, 0, 0, 0},
  308. /* noiseFloorThreshCh Check if the register is per chain */
  309. .noiseFloorThreshCh = {-1, 0, 0},
  310. .ob = {3, 3, 3}, /* 3 chain */
  311. .db_stage2 = {3, 3, 3}, /* 3 chain */
  312. .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
  313. .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
  314. .xpaBiasLvl = 0,
  315. .txFrameToDataStart = 0x0e,
  316. .txFrameToPaOn = 0x0e,
  317. .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
  318. .antennaGain = 0,
  319. .switchSettling = 0x2d,
  320. .adcDesiredSize = -30,
  321. .txEndToXpaOff = 0,
  322. .txEndToRxOn = 0x2,
  323. .txFrameToXpaOn = 0xe,
  324. .thresh62 = 28,
  325. .papdRateMaskHt20 = LE32(0x0c80c080),
  326. .papdRateMaskHt40 = LE32(0x0080c080),
  327. .futureModal = {
  328. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  329. },
  330. },
  331. .base_ext2 = {
  332. .tempSlopeLow = 0,
  333. .tempSlopeHigh = 0,
  334. .xatten1DBLow = {0, 0, 0},
  335. .xatten1MarginLow = {0, 0, 0},
  336. .xatten1DBHigh = {0, 0, 0},
  337. .xatten1MarginHigh = {0, 0, 0}
  338. },
  339. .calFreqPier5G = {
  340. FREQ2FBIN(5180, 0),
  341. FREQ2FBIN(5220, 0),
  342. FREQ2FBIN(5320, 0),
  343. FREQ2FBIN(5400, 0),
  344. FREQ2FBIN(5500, 0),
  345. FREQ2FBIN(5600, 0),
  346. FREQ2FBIN(5725, 0),
  347. FREQ2FBIN(5825, 0)
  348. },
  349. .calPierData5G = {
  350. {
  351. {0, 0, 0, 0, 0},
  352. {0, 0, 0, 0, 0},
  353. {0, 0, 0, 0, 0},
  354. {0, 0, 0, 0, 0},
  355. {0, 0, 0, 0, 0},
  356. {0, 0, 0, 0, 0},
  357. {0, 0, 0, 0, 0},
  358. {0, 0, 0, 0, 0},
  359. },
  360. {
  361. {0, 0, 0, 0, 0},
  362. {0, 0, 0, 0, 0},
  363. {0, 0, 0, 0, 0},
  364. {0, 0, 0, 0, 0},
  365. {0, 0, 0, 0, 0},
  366. {0, 0, 0, 0, 0},
  367. {0, 0, 0, 0, 0},
  368. {0, 0, 0, 0, 0},
  369. },
  370. {
  371. {0, 0, 0, 0, 0},
  372. {0, 0, 0, 0, 0},
  373. {0, 0, 0, 0, 0},
  374. {0, 0, 0, 0, 0},
  375. {0, 0, 0, 0, 0},
  376. {0, 0, 0, 0, 0},
  377. {0, 0, 0, 0, 0},
  378. {0, 0, 0, 0, 0},
  379. },
  380. },
  381. .calTarget_freqbin_5G = {
  382. FREQ2FBIN(5180, 0),
  383. FREQ2FBIN(5220, 0),
  384. FREQ2FBIN(5320, 0),
  385. FREQ2FBIN(5400, 0),
  386. FREQ2FBIN(5500, 0),
  387. FREQ2FBIN(5600, 0),
  388. FREQ2FBIN(5725, 0),
  389. FREQ2FBIN(5825, 0)
  390. },
  391. .calTarget_freqbin_5GHT20 = {
  392. FREQ2FBIN(5180, 0),
  393. FREQ2FBIN(5240, 0),
  394. FREQ2FBIN(5320, 0),
  395. FREQ2FBIN(5500, 0),
  396. FREQ2FBIN(5700, 0),
  397. FREQ2FBIN(5745, 0),
  398. FREQ2FBIN(5725, 0),
  399. FREQ2FBIN(5825, 0)
  400. },
  401. .calTarget_freqbin_5GHT40 = {
  402. FREQ2FBIN(5180, 0),
  403. FREQ2FBIN(5240, 0),
  404. FREQ2FBIN(5320, 0),
  405. FREQ2FBIN(5500, 0),
  406. FREQ2FBIN(5700, 0),
  407. FREQ2FBIN(5745, 0),
  408. FREQ2FBIN(5725, 0),
  409. FREQ2FBIN(5825, 0)
  410. },
  411. .calTargetPower5G = {
  412. /* 6-24,36,48,54 */
  413. { {20, 20, 20, 10} },
  414. { {20, 20, 20, 10} },
  415. { {20, 20, 20, 10} },
  416. { {20, 20, 20, 10} },
  417. { {20, 20, 20, 10} },
  418. { {20, 20, 20, 10} },
  419. { {20, 20, 20, 10} },
  420. { {20, 20, 20, 10} },
  421. },
  422. .calTargetPower5GHT20 = {
  423. /*
  424. * 0_8_16,1-3_9-11_17-19,
  425. * 4,5,6,7,12,13,14,15,20,21,22,23
  426. */
  427. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  428. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  429. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  430. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  431. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  432. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  433. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  434. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  435. },
  436. .calTargetPower5GHT40 = {
  437. /*
  438. * 0_8_16,1-3_9-11_17-19,
  439. * 4,5,6,7,12,13,14,15,20,21,22,23
  440. */
  441. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  442. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  443. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  444. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  445. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  446. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  447. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  448. { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
  449. },
  450. .ctlIndex_5G = {
  451. 0x10, 0x16, 0x18, 0x40, 0x46,
  452. 0x48, 0x30, 0x36, 0x38
  453. },
  454. .ctl_freqbin_5G = {
  455. {
  456. /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  457. /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  458. /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
  459. /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
  460. /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
  461. /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  462. /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
  463. /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
  464. },
  465. {
  466. /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  467. /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  468. /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
  469. /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
  470. /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
  471. /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  472. /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
  473. /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
  474. },
  475. {
  476. /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
  477. /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
  478. /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
  479. /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
  480. /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
  481. /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
  482. /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
  483. /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
  484. },
  485. {
  486. /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  487. /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
  488. /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
  489. /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
  490. /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
  491. /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  492. /* Data[3].ctlEdges[6].bChannel */ 0xFF,
  493. /* Data[3].ctlEdges[7].bChannel */ 0xFF,
  494. },
  495. {
  496. /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  497. /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  498. /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
  499. /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
  500. /* Data[4].ctlEdges[4].bChannel */ 0xFF,
  501. /* Data[4].ctlEdges[5].bChannel */ 0xFF,
  502. /* Data[4].ctlEdges[6].bChannel */ 0xFF,
  503. /* Data[4].ctlEdges[7].bChannel */ 0xFF,
  504. },
  505. {
  506. /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
  507. /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
  508. /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
  509. /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
  510. /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
  511. /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
  512. /* Data[5].ctlEdges[6].bChannel */ 0xFF,
  513. /* Data[5].ctlEdges[7].bChannel */ 0xFF
  514. },
  515. {
  516. /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  517. /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
  518. /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
  519. /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
  520. /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
  521. /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
  522. /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
  523. /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
  524. },
  525. {
  526. /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  527. /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  528. /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
  529. /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
  530. /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
  531. /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  532. /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
  533. /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
  534. },
  535. {
  536. /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
  537. /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
  538. /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
  539. /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
  540. /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
  541. /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
  542. /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
  543. /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
  544. }
  545. },
  546. .ctlPowerData_5G = {
  547. {
  548. {
  549. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  550. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  551. }
  552. },
  553. {
  554. {
  555. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  556. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  557. }
  558. },
  559. {
  560. {
  561. CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  562. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  563. }
  564. },
  565. {
  566. {
  567. CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  568. CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  569. }
  570. },
  571. {
  572. {
  573. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  574. CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  575. }
  576. },
  577. {
  578. {
  579. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  580. CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  581. }
  582. },
  583. {
  584. {
  585. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  586. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  587. }
  588. },
  589. {
  590. {
  591. CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  592. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  593. }
  594. },
  595. {
  596. {
  597. CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
  598. CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  599. }
  600. },
  601. }
  602. };
  603. static const struct ar9300_eeprom ar9300_x113 = {
  604. .eepromVersion = 2,
  605. .templateVersion = 6,
  606. .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
  607. .custData = {"x113-023-f0000"},
  608. .baseEepHeader = {
  609. .regDmn = { LE16(0), LE16(0x1f) },
  610. .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
  611. .opCapFlags = {
  612. .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
  613. .eepMisc = 0,
  614. },
  615. .rfSilent = 0,
  616. .blueToothOptions = 0,
  617. .deviceCap = 0,
  618. .deviceType = 5, /* takes lower byte in eeprom location */
  619. .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  620. .params_for_tuning_caps = {0, 0},
  621. .featureEnable = 0x0d,
  622. /*
  623. * bit0 - enable tx temp comp - disabled
  624. * bit1 - enable tx volt comp - disabled
  625. * bit2 - enable fastClock - enabled
  626. * bit3 - enable doubling - enabled
  627. * bit4 - enable internal regulator - disabled
  628. * bit5 - enable pa predistortion - disabled
  629. */
  630. .miscConfiguration = 0, /* bit0 - turn down drivestrength */
  631. .eepromWriteEnableGpio = 6,
  632. .wlanDisableGpio = 0,
  633. .wlanLedGpio = 8,
  634. .rxBandSelectGpio = 0xff,
  635. .txrxgain = 0x21,
  636. .swreg = 0,
  637. },
  638. .modalHeader2G = {
  639. /* ar9300_modal_eep_header 2g */
  640. /* 4 idle,t1,t2,b(4 bits per setting) */
  641. .antCtrlCommon = LE32(0x110),
  642. /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
  643. .antCtrlCommon2 = LE32(0x44444),
  644. /*
  645. * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
  646. * rx1, rx12, b (2 bits each)
  647. */
  648. .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
  649. /*
  650. * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
  651. * for ar9280 (0xa20c/b20c 5:0)
  652. */
  653. .xatten1DB = {0, 0, 0},
  654. /*
  655. * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
  656. * for ar9280 (0xa20c/b20c 16:12
  657. */
  658. .xatten1Margin = {0, 0, 0},
  659. .tempSlope = 25,
  660. .voltSlope = 0,
  661. /*
  662. * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
  663. * channels in usual fbin coding format
  664. */
  665. .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
  666. /*
  667. * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
  668. * if the register is per chain
  669. */
  670. .noiseFloorThreshCh = {-1, 0, 0},
  671. .ob = {1, 1, 1},/* 3 chain */
  672. .db_stage2 = {1, 1, 1}, /* 3 chain */
  673. .db_stage3 = {0, 0, 0},
  674. .db_stage4 = {0, 0, 0},
  675. .xpaBiasLvl = 0,
  676. .txFrameToDataStart = 0x0e,
  677. .txFrameToPaOn = 0x0e,
  678. .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
  679. .antennaGain = 0,
  680. .switchSettling = 0x2c,
  681. .adcDesiredSize = -30,
  682. .txEndToXpaOff = 0,
  683. .txEndToRxOn = 0x2,
  684. .txFrameToXpaOn = 0xe,
  685. .thresh62 = 28,
  686. .papdRateMaskHt20 = LE32(0x0c80c080),
  687. .papdRateMaskHt40 = LE32(0x0080c080),
  688. .futureModal = {
  689. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  690. },
  691. },
  692. .base_ext1 = {
  693. .ant_div_control = 0,
  694. .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  695. },
  696. .calFreqPier2G = {
  697. FREQ2FBIN(2412, 1),
  698. FREQ2FBIN(2437, 1),
  699. FREQ2FBIN(2472, 1),
  700. },
  701. /* ar9300_cal_data_per_freq_op_loop 2g */
  702. .calPierData2G = {
  703. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  704. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  705. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  706. },
  707. .calTarget_freqbin_Cck = {
  708. FREQ2FBIN(2412, 1),
  709. FREQ2FBIN(2472, 1),
  710. },
  711. .calTarget_freqbin_2G = {
  712. FREQ2FBIN(2412, 1),
  713. FREQ2FBIN(2437, 1),
  714. FREQ2FBIN(2472, 1)
  715. },
  716. .calTarget_freqbin_2GHT20 = {
  717. FREQ2FBIN(2412, 1),
  718. FREQ2FBIN(2437, 1),
  719. FREQ2FBIN(2472, 1)
  720. },
  721. .calTarget_freqbin_2GHT40 = {
  722. FREQ2FBIN(2412, 1),
  723. FREQ2FBIN(2437, 1),
  724. FREQ2FBIN(2472, 1)
  725. },
  726. .calTargetPowerCck = {
  727. /* 1L-5L,5S,11L,11S */
  728. { {34, 34, 34, 34} },
  729. { {34, 34, 34, 34} },
  730. },
  731. .calTargetPower2G = {
  732. /* 6-24,36,48,54 */
  733. { {34, 34, 32, 32} },
  734. { {34, 34, 32, 32} },
  735. { {34, 34, 32, 32} },
  736. },
  737. .calTargetPower2GHT20 = {
  738. { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
  739. { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
  740. { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
  741. },
  742. .calTargetPower2GHT40 = {
  743. { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
  744. { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
  745. { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
  746. },
  747. .ctlIndex_2G = {
  748. 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
  749. 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
  750. },
  751. .ctl_freqbin_2G = {
  752. {
  753. FREQ2FBIN(2412, 1),
  754. FREQ2FBIN(2417, 1),
  755. FREQ2FBIN(2457, 1),
  756. FREQ2FBIN(2462, 1)
  757. },
  758. {
  759. FREQ2FBIN(2412, 1),
  760. FREQ2FBIN(2417, 1),
  761. FREQ2FBIN(2462, 1),
  762. 0xFF,
  763. },
  764. {
  765. FREQ2FBIN(2412, 1),
  766. FREQ2FBIN(2417, 1),
  767. FREQ2FBIN(2462, 1),
  768. 0xFF,
  769. },
  770. {
  771. FREQ2FBIN(2422, 1),
  772. FREQ2FBIN(2427, 1),
  773. FREQ2FBIN(2447, 1),
  774. FREQ2FBIN(2452, 1)
  775. },
  776. {
  777. /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  778. /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  779. /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  780. /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
  781. },
  782. {
  783. /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  784. /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  785. /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  786. 0,
  787. },
  788. {
  789. /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  790. /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  791. FREQ2FBIN(2472, 1),
  792. 0,
  793. },
  794. {
  795. /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
  796. /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
  797. /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
  798. /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
  799. },
  800. {
  801. /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  802. /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  803. /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  804. },
  805. {
  806. /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  807. /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  808. /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  809. 0
  810. },
  811. {
  812. /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  813. /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  814. /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  815. 0
  816. },
  817. {
  818. /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
  819. /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
  820. /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
  821. /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
  822. }
  823. },
  824. .ctlPowerData_2G = {
  825. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  826. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  827. { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
  828. { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
  829. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  830. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  831. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
  832. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  833. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  834. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  835. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
  836. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
  837. },
  838. .modalHeader5G = {
  839. /* 4 idle,t1,t2,b (4 bits per setting) */
  840. .antCtrlCommon = LE32(0x220),
  841. /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
  842. .antCtrlCommon2 = LE32(0x11111),
  843. /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
  844. .antCtrlChain = {
  845. LE16(0x150), LE16(0x150), LE16(0x150),
  846. },
  847. /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
  848. .xatten1DB = {0, 0, 0},
  849. /*
  850. * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
  851. * for merlin (0xa20c/b20c 16:12
  852. */
  853. .xatten1Margin = {0, 0, 0},
  854. .tempSlope = 68,
  855. .voltSlope = 0,
  856. /* spurChans spur channels in usual fbin coding format */
  857. .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
  858. /* noiseFloorThreshCh Check if the register is per chain */
  859. .noiseFloorThreshCh = {-1, 0, 0},
  860. .ob = {3, 3, 3}, /* 3 chain */
  861. .db_stage2 = {3, 3, 3}, /* 3 chain */
  862. .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
  863. .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
  864. .xpaBiasLvl = 0,
  865. .txFrameToDataStart = 0x0e,
  866. .txFrameToPaOn = 0x0e,
  867. .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
  868. .antennaGain = 0,
  869. .switchSettling = 0x2d,
  870. .adcDesiredSize = -30,
  871. .txEndToXpaOff = 0,
  872. .txEndToRxOn = 0x2,
  873. .txFrameToXpaOn = 0xe,
  874. .thresh62 = 28,
  875. .papdRateMaskHt20 = LE32(0x0cf0e0e0),
  876. .papdRateMaskHt40 = LE32(0x6cf0e0e0),
  877. .futureModal = {
  878. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  879. },
  880. },
  881. .base_ext2 = {
  882. .tempSlopeLow = 72,
  883. .tempSlopeHigh = 105,
  884. .xatten1DBLow = {0, 0, 0},
  885. .xatten1MarginLow = {0, 0, 0},
  886. .xatten1DBHigh = {0, 0, 0},
  887. .xatten1MarginHigh = {0, 0, 0}
  888. },
  889. .calFreqPier5G = {
  890. FREQ2FBIN(5180, 0),
  891. FREQ2FBIN(5240, 0),
  892. FREQ2FBIN(5320, 0),
  893. FREQ2FBIN(5400, 0),
  894. FREQ2FBIN(5500, 0),
  895. FREQ2FBIN(5600, 0),
  896. FREQ2FBIN(5745, 0),
  897. FREQ2FBIN(5785, 0)
  898. },
  899. .calPierData5G = {
  900. {
  901. {0, 0, 0, 0, 0},
  902. {0, 0, 0, 0, 0},
  903. {0, 0, 0, 0, 0},
  904. {0, 0, 0, 0, 0},
  905. {0, 0, 0, 0, 0},
  906. {0, 0, 0, 0, 0},
  907. {0, 0, 0, 0, 0},
  908. {0, 0, 0, 0, 0},
  909. },
  910. {
  911. {0, 0, 0, 0, 0},
  912. {0, 0, 0, 0, 0},
  913. {0, 0, 0, 0, 0},
  914. {0, 0, 0, 0, 0},
  915. {0, 0, 0, 0, 0},
  916. {0, 0, 0, 0, 0},
  917. {0, 0, 0, 0, 0},
  918. {0, 0, 0, 0, 0},
  919. },
  920. {
  921. {0, 0, 0, 0, 0},
  922. {0, 0, 0, 0, 0},
  923. {0, 0, 0, 0, 0},
  924. {0, 0, 0, 0, 0},
  925. {0, 0, 0, 0, 0},
  926. {0, 0, 0, 0, 0},
  927. {0, 0, 0, 0, 0},
  928. {0, 0, 0, 0, 0},
  929. },
  930. },
  931. .calTarget_freqbin_5G = {
  932. FREQ2FBIN(5180, 0),
  933. FREQ2FBIN(5220, 0),
  934. FREQ2FBIN(5320, 0),
  935. FREQ2FBIN(5400, 0),
  936. FREQ2FBIN(5500, 0),
  937. FREQ2FBIN(5600, 0),
  938. FREQ2FBIN(5745, 0),
  939. FREQ2FBIN(5785, 0)
  940. },
  941. .calTarget_freqbin_5GHT20 = {
  942. FREQ2FBIN(5180, 0),
  943. FREQ2FBIN(5240, 0),
  944. FREQ2FBIN(5320, 0),
  945. FREQ2FBIN(5400, 0),
  946. FREQ2FBIN(5500, 0),
  947. FREQ2FBIN(5700, 0),
  948. FREQ2FBIN(5745, 0),
  949. FREQ2FBIN(5825, 0)
  950. },
  951. .calTarget_freqbin_5GHT40 = {
  952. FREQ2FBIN(5190, 0),
  953. FREQ2FBIN(5230, 0),
  954. FREQ2FBIN(5320, 0),
  955. FREQ2FBIN(5410, 0),
  956. FREQ2FBIN(5510, 0),
  957. FREQ2FBIN(5670, 0),
  958. FREQ2FBIN(5755, 0),
  959. FREQ2FBIN(5825, 0)
  960. },
  961. .calTargetPower5G = {
  962. /* 6-24,36,48,54 */
  963. { {42, 40, 40, 34} },
  964. { {42, 40, 40, 34} },
  965. { {42, 40, 40, 34} },
  966. { {42, 40, 40, 34} },
  967. { {42, 40, 40, 34} },
  968. { {42, 40, 40, 34} },
  969. { {42, 40, 40, 34} },
  970. { {42, 40, 40, 34} },
  971. },
  972. .calTargetPower5GHT20 = {
  973. /*
  974. * 0_8_16,1-3_9-11_17-19,
  975. * 4,5,6,7,12,13,14,15,20,21,22,23
  976. */
  977. { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
  978. { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
  979. { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
  980. { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
  981. { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
  982. { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
  983. { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
  984. { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
  985. },
  986. .calTargetPower5GHT40 = {
  987. /*
  988. * 0_8_16,1-3_9-11_17-19,
  989. * 4,5,6,7,12,13,14,15,20,21,22,23
  990. */
  991. { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
  992. { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
  993. { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
  994. { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
  995. { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
  996. { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
  997. { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
  998. { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
  999. },
  1000. .ctlIndex_5G = {
  1001. 0x10, 0x16, 0x18, 0x40, 0x46,
  1002. 0x48, 0x30, 0x36, 0x38
  1003. },
  1004. .ctl_freqbin_5G = {
  1005. {
  1006. /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  1007. /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  1008. /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
  1009. /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
  1010. /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
  1011. /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  1012. /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
  1013. /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
  1014. },
  1015. {
  1016. /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  1017. /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  1018. /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
  1019. /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
  1020. /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
  1021. /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  1022. /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
  1023. /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
  1024. },
  1025. {
  1026. /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
  1027. /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
  1028. /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
  1029. /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
  1030. /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
  1031. /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
  1032. /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
  1033. /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
  1034. },
  1035. {
  1036. /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  1037. /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
  1038. /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
  1039. /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
  1040. /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
  1041. /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  1042. /* Data[3].ctlEdges[6].bChannel */ 0xFF,
  1043. /* Data[3].ctlEdges[7].bChannel */ 0xFF,
  1044. },
  1045. {
  1046. /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  1047. /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  1048. /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
  1049. /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
  1050. /* Data[4].ctlEdges[4].bChannel */ 0xFF,
  1051. /* Data[4].ctlEdges[5].bChannel */ 0xFF,
  1052. /* Data[4].ctlEdges[6].bChannel */ 0xFF,
  1053. /* Data[4].ctlEdges[7].bChannel */ 0xFF,
  1054. },
  1055. {
  1056. /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
  1057. /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
  1058. /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
  1059. /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
  1060. /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
  1061. /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
  1062. /* Data[5].ctlEdges[6].bChannel */ 0xFF,
  1063. /* Data[5].ctlEdges[7].bChannel */ 0xFF
  1064. },
  1065. {
  1066. /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  1067. /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
  1068. /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
  1069. /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
  1070. /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
  1071. /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
  1072. /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
  1073. /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
  1074. },
  1075. {
  1076. /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  1077. /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  1078. /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
  1079. /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
  1080. /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
  1081. /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  1082. /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
  1083. /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
  1084. },
  1085. {
  1086. /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
  1087. /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
  1088. /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
  1089. /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
  1090. /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
  1091. /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
  1092. /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
  1093. /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
  1094. }
  1095. },
  1096. .ctlPowerData_5G = {
  1097. {
  1098. {
  1099. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  1100. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  1101. }
  1102. },
  1103. {
  1104. {
  1105. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  1106. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  1107. }
  1108. },
  1109. {
  1110. {
  1111. CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  1112. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  1113. }
  1114. },
  1115. {
  1116. {
  1117. CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  1118. CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  1119. }
  1120. },
  1121. {
  1122. {
  1123. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  1124. CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  1125. }
  1126. },
  1127. {
  1128. {
  1129. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  1130. CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  1131. }
  1132. },
  1133. {
  1134. {
  1135. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  1136. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  1137. }
  1138. },
  1139. {
  1140. {
  1141. CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  1142. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  1143. }
  1144. },
  1145. {
  1146. {
  1147. CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
  1148. CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  1149. }
  1150. },
  1151. }
  1152. };
  1153. static const struct ar9300_eeprom ar9300_h112 = {
  1154. .eepromVersion = 2,
  1155. .templateVersion = 3,
  1156. .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
  1157. .custData = {"h112-241-f0000"},
  1158. .baseEepHeader = {
  1159. .regDmn = { LE16(0), LE16(0x1f) },
  1160. .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
  1161. .opCapFlags = {
  1162. .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
  1163. .eepMisc = 0,
  1164. },
  1165. .rfSilent = 0,
  1166. .blueToothOptions = 0,
  1167. .deviceCap = 0,
  1168. .deviceType = 5, /* takes lower byte in eeprom location */
  1169. .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  1170. .params_for_tuning_caps = {0, 0},
  1171. .featureEnable = 0x0d,
  1172. /*
  1173. * bit0 - enable tx temp comp - disabled
  1174. * bit1 - enable tx volt comp - disabled
  1175. * bit2 - enable fastClock - enabled
  1176. * bit3 - enable doubling - enabled
  1177. * bit4 - enable internal regulator - disabled
  1178. * bit5 - enable pa predistortion - disabled
  1179. */
  1180. .miscConfiguration = 0, /* bit0 - turn down drivestrength */
  1181. .eepromWriteEnableGpio = 6,
  1182. .wlanDisableGpio = 0,
  1183. .wlanLedGpio = 8,
  1184. .rxBandSelectGpio = 0xff,
  1185. .txrxgain = 0x10,
  1186. .swreg = 0,
  1187. },
  1188. .modalHeader2G = {
  1189. /* ar9300_modal_eep_header 2g */
  1190. /* 4 idle,t1,t2,b(4 bits per setting) */
  1191. .antCtrlCommon = LE32(0x110),
  1192. /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
  1193. .antCtrlCommon2 = LE32(0x44444),
  1194. /*
  1195. * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
  1196. * rx1, rx12, b (2 bits each)
  1197. */
  1198. .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
  1199. /*
  1200. * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
  1201. * for ar9280 (0xa20c/b20c 5:0)
  1202. */
  1203. .xatten1DB = {0, 0, 0},
  1204. /*
  1205. * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
  1206. * for ar9280 (0xa20c/b20c 16:12
  1207. */
  1208. .xatten1Margin = {0, 0, 0},
  1209. .tempSlope = 25,
  1210. .voltSlope = 0,
  1211. /*
  1212. * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
  1213. * channels in usual fbin coding format
  1214. */
  1215. .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
  1216. /*
  1217. * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
  1218. * if the register is per chain
  1219. */
  1220. .noiseFloorThreshCh = {-1, 0, 0},
  1221. .ob = {1, 1, 1},/* 3 chain */
  1222. .db_stage2 = {1, 1, 1}, /* 3 chain */
  1223. .db_stage3 = {0, 0, 0},
  1224. .db_stage4 = {0, 0, 0},
  1225. .xpaBiasLvl = 0,
  1226. .txFrameToDataStart = 0x0e,
  1227. .txFrameToPaOn = 0x0e,
  1228. .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
  1229. .antennaGain = 0,
  1230. .switchSettling = 0x2c,
  1231. .adcDesiredSize = -30,
  1232. .txEndToXpaOff = 0,
  1233. .txEndToRxOn = 0x2,
  1234. .txFrameToXpaOn = 0xe,
  1235. .thresh62 = 28,
  1236. .papdRateMaskHt20 = LE32(0x80c080),
  1237. .papdRateMaskHt40 = LE32(0x80c080),
  1238. .futureModal = {
  1239. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1240. },
  1241. },
  1242. .base_ext1 = {
  1243. .ant_div_control = 0,
  1244. .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  1245. },
  1246. .calFreqPier2G = {
  1247. FREQ2FBIN(2412, 1),
  1248. FREQ2FBIN(2437, 1),
  1249. FREQ2FBIN(2472, 1),
  1250. },
  1251. /* ar9300_cal_data_per_freq_op_loop 2g */
  1252. .calPierData2G = {
  1253. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  1254. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  1255. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  1256. },
  1257. .calTarget_freqbin_Cck = {
  1258. FREQ2FBIN(2412, 1),
  1259. FREQ2FBIN(2484, 1),
  1260. },
  1261. .calTarget_freqbin_2G = {
  1262. FREQ2FBIN(2412, 1),
  1263. FREQ2FBIN(2437, 1),
  1264. FREQ2FBIN(2472, 1)
  1265. },
  1266. .calTarget_freqbin_2GHT20 = {
  1267. FREQ2FBIN(2412, 1),
  1268. FREQ2FBIN(2437, 1),
  1269. FREQ2FBIN(2472, 1)
  1270. },
  1271. .calTarget_freqbin_2GHT40 = {
  1272. FREQ2FBIN(2412, 1),
  1273. FREQ2FBIN(2437, 1),
  1274. FREQ2FBIN(2472, 1)
  1275. },
  1276. .calTargetPowerCck = {
  1277. /* 1L-5L,5S,11L,11S */
  1278. { {34, 34, 34, 34} },
  1279. { {34, 34, 34, 34} },
  1280. },
  1281. .calTargetPower2G = {
  1282. /* 6-24,36,48,54 */
  1283. { {34, 34, 32, 32} },
  1284. { {34, 34, 32, 32} },
  1285. { {34, 34, 32, 32} },
  1286. },
  1287. .calTargetPower2GHT20 = {
  1288. { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
  1289. { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
  1290. { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
  1291. },
  1292. .calTargetPower2GHT40 = {
  1293. { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
  1294. { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
  1295. { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
  1296. },
  1297. .ctlIndex_2G = {
  1298. 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
  1299. 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
  1300. },
  1301. .ctl_freqbin_2G = {
  1302. {
  1303. FREQ2FBIN(2412, 1),
  1304. FREQ2FBIN(2417, 1),
  1305. FREQ2FBIN(2457, 1),
  1306. FREQ2FBIN(2462, 1)
  1307. },
  1308. {
  1309. FREQ2FBIN(2412, 1),
  1310. FREQ2FBIN(2417, 1),
  1311. FREQ2FBIN(2462, 1),
  1312. 0xFF,
  1313. },
  1314. {
  1315. FREQ2FBIN(2412, 1),
  1316. FREQ2FBIN(2417, 1),
  1317. FREQ2FBIN(2462, 1),
  1318. 0xFF,
  1319. },
  1320. {
  1321. FREQ2FBIN(2422, 1),
  1322. FREQ2FBIN(2427, 1),
  1323. FREQ2FBIN(2447, 1),
  1324. FREQ2FBIN(2452, 1)
  1325. },
  1326. {
  1327. /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  1328. /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  1329. /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  1330. /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
  1331. },
  1332. {
  1333. /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  1334. /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  1335. /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  1336. 0,
  1337. },
  1338. {
  1339. /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  1340. /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  1341. FREQ2FBIN(2472, 1),
  1342. 0,
  1343. },
  1344. {
  1345. /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
  1346. /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
  1347. /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
  1348. /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
  1349. },
  1350. {
  1351. /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  1352. /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  1353. /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  1354. },
  1355. {
  1356. /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  1357. /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  1358. /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  1359. 0
  1360. },
  1361. {
  1362. /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  1363. /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  1364. /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  1365. 0
  1366. },
  1367. {
  1368. /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
  1369. /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
  1370. /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
  1371. /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
  1372. }
  1373. },
  1374. .ctlPowerData_2G = {
  1375. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1376. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1377. { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
  1378. { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
  1379. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1380. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1381. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
  1382. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1383. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1384. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1385. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
  1386. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
  1387. },
  1388. .modalHeader5G = {
  1389. /* 4 idle,t1,t2,b (4 bits per setting) */
  1390. .antCtrlCommon = LE32(0x220),
  1391. /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
  1392. .antCtrlCommon2 = LE32(0x44444),
  1393. /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
  1394. .antCtrlChain = {
  1395. LE16(0x150), LE16(0x150), LE16(0x150),
  1396. },
  1397. /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
  1398. .xatten1DB = {0, 0, 0},
  1399. /*
  1400. * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
  1401. * for merlin (0xa20c/b20c 16:12
  1402. */
  1403. .xatten1Margin = {0, 0, 0},
  1404. .tempSlope = 45,
  1405. .voltSlope = 0,
  1406. /* spurChans spur channels in usual fbin coding format */
  1407. .spurChans = {0, 0, 0, 0, 0},
  1408. /* noiseFloorThreshCh Check if the register is per chain */
  1409. .noiseFloorThreshCh = {-1, 0, 0},
  1410. .ob = {3, 3, 3}, /* 3 chain */
  1411. .db_stage2 = {3, 3, 3}, /* 3 chain */
  1412. .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
  1413. .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
  1414. .xpaBiasLvl = 0,
  1415. .txFrameToDataStart = 0x0e,
  1416. .txFrameToPaOn = 0x0e,
  1417. .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
  1418. .antennaGain = 0,
  1419. .switchSettling = 0x2d,
  1420. .adcDesiredSize = -30,
  1421. .txEndToXpaOff = 0,
  1422. .txEndToRxOn = 0x2,
  1423. .txFrameToXpaOn = 0xe,
  1424. .thresh62 = 28,
  1425. .papdRateMaskHt20 = LE32(0x0cf0e0e0),
  1426. .papdRateMaskHt40 = LE32(0x6cf0e0e0),
  1427. .futureModal = {
  1428. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1429. },
  1430. },
  1431. .base_ext2 = {
  1432. .tempSlopeLow = 40,
  1433. .tempSlopeHigh = 50,
  1434. .xatten1DBLow = {0, 0, 0},
  1435. .xatten1MarginLow = {0, 0, 0},
  1436. .xatten1DBHigh = {0, 0, 0},
  1437. .xatten1MarginHigh = {0, 0, 0}
  1438. },
  1439. .calFreqPier5G = {
  1440. FREQ2FBIN(5180, 0),
  1441. FREQ2FBIN(5220, 0),
  1442. FREQ2FBIN(5320, 0),
  1443. FREQ2FBIN(5400, 0),
  1444. FREQ2FBIN(5500, 0),
  1445. FREQ2FBIN(5600, 0),
  1446. FREQ2FBIN(5700, 0),
  1447. FREQ2FBIN(5825, 0)
  1448. },
  1449. .calPierData5G = {
  1450. {
  1451. {0, 0, 0, 0, 0},
  1452. {0, 0, 0, 0, 0},
  1453. {0, 0, 0, 0, 0},
  1454. {0, 0, 0, 0, 0},
  1455. {0, 0, 0, 0, 0},
  1456. {0, 0, 0, 0, 0},
  1457. {0, 0, 0, 0, 0},
  1458. {0, 0, 0, 0, 0},
  1459. },
  1460. {
  1461. {0, 0, 0, 0, 0},
  1462. {0, 0, 0, 0, 0},
  1463. {0, 0, 0, 0, 0},
  1464. {0, 0, 0, 0, 0},
  1465. {0, 0, 0, 0, 0},
  1466. {0, 0, 0, 0, 0},
  1467. {0, 0, 0, 0, 0},
  1468. {0, 0, 0, 0, 0},
  1469. },
  1470. {
  1471. {0, 0, 0, 0, 0},
  1472. {0, 0, 0, 0, 0},
  1473. {0, 0, 0, 0, 0},
  1474. {0, 0, 0, 0, 0},
  1475. {0, 0, 0, 0, 0},
  1476. {0, 0, 0, 0, 0},
  1477. {0, 0, 0, 0, 0},
  1478. {0, 0, 0, 0, 0},
  1479. },
  1480. },
  1481. .calTarget_freqbin_5G = {
  1482. FREQ2FBIN(5180, 0),
  1483. FREQ2FBIN(5240, 0),
  1484. FREQ2FBIN(5320, 0),
  1485. FREQ2FBIN(5400, 0),
  1486. FREQ2FBIN(5500, 0),
  1487. FREQ2FBIN(5600, 0),
  1488. FREQ2FBIN(5700, 0),
  1489. FREQ2FBIN(5825, 0)
  1490. },
  1491. .calTarget_freqbin_5GHT20 = {
  1492. FREQ2FBIN(5180, 0),
  1493. FREQ2FBIN(5240, 0),
  1494. FREQ2FBIN(5320, 0),
  1495. FREQ2FBIN(5400, 0),
  1496. FREQ2FBIN(5500, 0),
  1497. FREQ2FBIN(5700, 0),
  1498. FREQ2FBIN(5745, 0),
  1499. FREQ2FBIN(5825, 0)
  1500. },
  1501. .calTarget_freqbin_5GHT40 = {
  1502. FREQ2FBIN(5180, 0),
  1503. FREQ2FBIN(5240, 0),
  1504. FREQ2FBIN(5320, 0),
  1505. FREQ2FBIN(5400, 0),
  1506. FREQ2FBIN(5500, 0),
  1507. FREQ2FBIN(5700, 0),
  1508. FREQ2FBIN(5745, 0),
  1509. FREQ2FBIN(5825, 0)
  1510. },
  1511. .calTargetPower5G = {
  1512. /* 6-24,36,48,54 */
  1513. { {30, 30, 28, 24} },
  1514. { {30, 30, 28, 24} },
  1515. { {30, 30, 28, 24} },
  1516. { {30, 30, 28, 24} },
  1517. { {30, 30, 28, 24} },
  1518. { {30, 30, 28, 24} },
  1519. { {30, 30, 28, 24} },
  1520. { {30, 30, 28, 24} },
  1521. },
  1522. .calTargetPower5GHT20 = {
  1523. /*
  1524. * 0_8_16,1-3_9-11_17-19,
  1525. * 4,5,6,7,12,13,14,15,20,21,22,23
  1526. */
  1527. { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
  1528. { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
  1529. { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
  1530. { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
  1531. { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
  1532. { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
  1533. { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
  1534. { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
  1535. },
  1536. .calTargetPower5GHT40 = {
  1537. /*
  1538. * 0_8_16,1-3_9-11_17-19,
  1539. * 4,5,6,7,12,13,14,15,20,21,22,23
  1540. */
  1541. { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
  1542. { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
  1543. { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
  1544. { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
  1545. { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
  1546. { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
  1547. { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
  1548. { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
  1549. },
  1550. .ctlIndex_5G = {
  1551. 0x10, 0x16, 0x18, 0x40, 0x46,
  1552. 0x48, 0x30, 0x36, 0x38
  1553. },
  1554. .ctl_freqbin_5G = {
  1555. {
  1556. /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  1557. /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  1558. /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
  1559. /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
  1560. /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
  1561. /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  1562. /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
  1563. /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
  1564. },
  1565. {
  1566. /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  1567. /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  1568. /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
  1569. /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
  1570. /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
  1571. /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  1572. /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
  1573. /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
  1574. },
  1575. {
  1576. /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
  1577. /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
  1578. /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
  1579. /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
  1580. /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
  1581. /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
  1582. /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
  1583. /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
  1584. },
  1585. {
  1586. /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  1587. /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
  1588. /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
  1589. /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
  1590. /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
  1591. /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  1592. /* Data[3].ctlEdges[6].bChannel */ 0xFF,
  1593. /* Data[3].ctlEdges[7].bChannel */ 0xFF,
  1594. },
  1595. {
  1596. /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  1597. /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  1598. /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
  1599. /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
  1600. /* Data[4].ctlEdges[4].bChannel */ 0xFF,
  1601. /* Data[4].ctlEdges[5].bChannel */ 0xFF,
  1602. /* Data[4].ctlEdges[6].bChannel */ 0xFF,
  1603. /* Data[4].ctlEdges[7].bChannel */ 0xFF,
  1604. },
  1605. {
  1606. /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
  1607. /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
  1608. /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
  1609. /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
  1610. /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
  1611. /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
  1612. /* Data[5].ctlEdges[6].bChannel */ 0xFF,
  1613. /* Data[5].ctlEdges[7].bChannel */ 0xFF
  1614. },
  1615. {
  1616. /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  1617. /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
  1618. /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
  1619. /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
  1620. /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
  1621. /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
  1622. /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
  1623. /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
  1624. },
  1625. {
  1626. /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  1627. /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  1628. /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
  1629. /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
  1630. /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
  1631. /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  1632. /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
  1633. /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
  1634. },
  1635. {
  1636. /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
  1637. /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
  1638. /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
  1639. /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
  1640. /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
  1641. /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
  1642. /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
  1643. /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
  1644. }
  1645. },
  1646. .ctlPowerData_5G = {
  1647. {
  1648. {
  1649. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  1650. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  1651. }
  1652. },
  1653. {
  1654. {
  1655. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  1656. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  1657. }
  1658. },
  1659. {
  1660. {
  1661. CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  1662. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  1663. }
  1664. },
  1665. {
  1666. {
  1667. CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  1668. CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  1669. }
  1670. },
  1671. {
  1672. {
  1673. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  1674. CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  1675. }
  1676. },
  1677. {
  1678. {
  1679. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  1680. CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  1681. }
  1682. },
  1683. {
  1684. {
  1685. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  1686. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  1687. }
  1688. },
  1689. {
  1690. {
  1691. CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  1692. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  1693. }
  1694. },
  1695. {
  1696. {
  1697. CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
  1698. CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  1699. }
  1700. },
  1701. }
  1702. };
  1703. static const struct ar9300_eeprom ar9300_x112 = {
  1704. .eepromVersion = 2,
  1705. .templateVersion = 5,
  1706. .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
  1707. .custData = {"x112-041-f0000"},
  1708. .baseEepHeader = {
  1709. .regDmn = { LE16(0), LE16(0x1f) },
  1710. .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
  1711. .opCapFlags = {
  1712. .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
  1713. .eepMisc = 0,
  1714. },
  1715. .rfSilent = 0,
  1716. .blueToothOptions = 0,
  1717. .deviceCap = 0,
  1718. .deviceType = 5, /* takes lower byte in eeprom location */
  1719. .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  1720. .params_for_tuning_caps = {0, 0},
  1721. .featureEnable = 0x0d,
  1722. /*
  1723. * bit0 - enable tx temp comp - disabled
  1724. * bit1 - enable tx volt comp - disabled
  1725. * bit2 - enable fastclock - enabled
  1726. * bit3 - enable doubling - enabled
  1727. * bit4 - enable internal regulator - disabled
  1728. * bit5 - enable pa predistortion - disabled
  1729. */
  1730. .miscConfiguration = 0, /* bit0 - turn down drivestrength */
  1731. .eepromWriteEnableGpio = 6,
  1732. .wlanDisableGpio = 0,
  1733. .wlanLedGpio = 8,
  1734. .rxBandSelectGpio = 0xff,
  1735. .txrxgain = 0x0,
  1736. .swreg = 0,
  1737. },
  1738. .modalHeader2G = {
  1739. /* ar9300_modal_eep_header 2g */
  1740. /* 4 idle,t1,t2,b(4 bits per setting) */
  1741. .antCtrlCommon = LE32(0x110),
  1742. /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
  1743. .antCtrlCommon2 = LE32(0x22222),
  1744. /*
  1745. * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
  1746. * rx1, rx12, b (2 bits each)
  1747. */
  1748. .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
  1749. /*
  1750. * xatten1DB[AR9300_max_chains]; 3 xatten1_db
  1751. * for ar9280 (0xa20c/b20c 5:0)
  1752. */
  1753. .xatten1DB = {0x1b, 0x1b, 0x1b},
  1754. /*
  1755. * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
  1756. * for ar9280 (0xa20c/b20c 16:12
  1757. */
  1758. .xatten1Margin = {0x15, 0x15, 0x15},
  1759. .tempSlope = 50,
  1760. .voltSlope = 0,
  1761. /*
  1762. * spurChans[OSPrey_eeprom_modal_sPURS]; spur
  1763. * channels in usual fbin coding format
  1764. */
  1765. .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
  1766. /*
  1767. * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
  1768. * if the register is per chain
  1769. */
  1770. .noiseFloorThreshCh = {-1, 0, 0},
  1771. .ob = {1, 1, 1},/* 3 chain */
  1772. .db_stage2 = {1, 1, 1}, /* 3 chain */
  1773. .db_stage3 = {0, 0, 0},
  1774. .db_stage4 = {0, 0, 0},
  1775. .xpaBiasLvl = 0,
  1776. .txFrameToDataStart = 0x0e,
  1777. .txFrameToPaOn = 0x0e,
  1778. .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
  1779. .antennaGain = 0,
  1780. .switchSettling = 0x2c,
  1781. .adcDesiredSize = -30,
  1782. .txEndToXpaOff = 0,
  1783. .txEndToRxOn = 0x2,
  1784. .txFrameToXpaOn = 0xe,
  1785. .thresh62 = 28,
  1786. .papdRateMaskHt20 = LE32(0x0c80c080),
  1787. .papdRateMaskHt40 = LE32(0x0080c080),
  1788. .futureModal = {
  1789. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1790. },
  1791. },
  1792. .base_ext1 = {
  1793. .ant_div_control = 0,
  1794. .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  1795. },
  1796. .calFreqPier2G = {
  1797. FREQ2FBIN(2412, 1),
  1798. FREQ2FBIN(2437, 1),
  1799. FREQ2FBIN(2472, 1),
  1800. },
  1801. /* ar9300_cal_data_per_freq_op_loop 2g */
  1802. .calPierData2G = {
  1803. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  1804. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  1805. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  1806. },
  1807. .calTarget_freqbin_Cck = {
  1808. FREQ2FBIN(2412, 1),
  1809. FREQ2FBIN(2472, 1),
  1810. },
  1811. .calTarget_freqbin_2G = {
  1812. FREQ2FBIN(2412, 1),
  1813. FREQ2FBIN(2437, 1),
  1814. FREQ2FBIN(2472, 1)
  1815. },
  1816. .calTarget_freqbin_2GHT20 = {
  1817. FREQ2FBIN(2412, 1),
  1818. FREQ2FBIN(2437, 1),
  1819. FREQ2FBIN(2472, 1)
  1820. },
  1821. .calTarget_freqbin_2GHT40 = {
  1822. FREQ2FBIN(2412, 1),
  1823. FREQ2FBIN(2437, 1),
  1824. FREQ2FBIN(2472, 1)
  1825. },
  1826. .calTargetPowerCck = {
  1827. /* 1L-5L,5S,11L,11s */
  1828. { {38, 38, 38, 38} },
  1829. { {38, 38, 38, 38} },
  1830. },
  1831. .calTargetPower2G = {
  1832. /* 6-24,36,48,54 */
  1833. { {38, 38, 36, 34} },
  1834. { {38, 38, 36, 34} },
  1835. { {38, 38, 34, 32} },
  1836. },
  1837. .calTargetPower2GHT20 = {
  1838. { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
  1839. { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
  1840. { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
  1841. },
  1842. .calTargetPower2GHT40 = {
  1843. { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
  1844. { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
  1845. { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
  1846. },
  1847. .ctlIndex_2G = {
  1848. 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
  1849. 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
  1850. },
  1851. .ctl_freqbin_2G = {
  1852. {
  1853. FREQ2FBIN(2412, 1),
  1854. FREQ2FBIN(2417, 1),
  1855. FREQ2FBIN(2457, 1),
  1856. FREQ2FBIN(2462, 1)
  1857. },
  1858. {
  1859. FREQ2FBIN(2412, 1),
  1860. FREQ2FBIN(2417, 1),
  1861. FREQ2FBIN(2462, 1),
  1862. 0xFF,
  1863. },
  1864. {
  1865. FREQ2FBIN(2412, 1),
  1866. FREQ2FBIN(2417, 1),
  1867. FREQ2FBIN(2462, 1),
  1868. 0xFF,
  1869. },
  1870. {
  1871. FREQ2FBIN(2422, 1),
  1872. FREQ2FBIN(2427, 1),
  1873. FREQ2FBIN(2447, 1),
  1874. FREQ2FBIN(2452, 1)
  1875. },
  1876. {
  1877. /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
  1878. /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
  1879. /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
  1880. /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
  1881. },
  1882. {
  1883. /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
  1884. /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
  1885. /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
  1886. 0,
  1887. },
  1888. {
  1889. /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
  1890. /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
  1891. FREQ2FBIN(2472, 1),
  1892. 0,
  1893. },
  1894. {
  1895. /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
  1896. /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
  1897. /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
  1898. /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
  1899. },
  1900. {
  1901. /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
  1902. /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
  1903. /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
  1904. },
  1905. {
  1906. /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
  1907. /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
  1908. /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
  1909. 0
  1910. },
  1911. {
  1912. /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
  1913. /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
  1914. /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
  1915. 0
  1916. },
  1917. {
  1918. /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
  1919. /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
  1920. /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
  1921. /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
  1922. }
  1923. },
  1924. .ctlPowerData_2G = {
  1925. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1926. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1927. { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
  1928. { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
  1929. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1930. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1931. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
  1932. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1933. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1934. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  1935. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
  1936. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
  1937. },
  1938. .modalHeader5G = {
  1939. /* 4 idle,t1,t2,b (4 bits per setting) */
  1940. .antCtrlCommon = LE32(0x110),
  1941. /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
  1942. .antCtrlCommon2 = LE32(0x22222),
  1943. /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
  1944. .antCtrlChain = {
  1945. LE16(0x0), LE16(0x0), LE16(0x0),
  1946. },
  1947. /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
  1948. .xatten1DB = {0x13, 0x19, 0x17},
  1949. /*
  1950. * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
  1951. * for merlin (0xa20c/b20c 16:12
  1952. */
  1953. .xatten1Margin = {0x19, 0x19, 0x19},
  1954. .tempSlope = 70,
  1955. .voltSlope = 15,
  1956. /* spurChans spur channels in usual fbin coding format */
  1957. .spurChans = {0, 0, 0, 0, 0},
  1958. /* noiseFloorThreshch check if the register is per chain */
  1959. .noiseFloorThreshCh = {-1, 0, 0},
  1960. .ob = {3, 3, 3}, /* 3 chain */
  1961. .db_stage2 = {3, 3, 3}, /* 3 chain */
  1962. .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
  1963. .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
  1964. .xpaBiasLvl = 0,
  1965. .txFrameToDataStart = 0x0e,
  1966. .txFrameToPaOn = 0x0e,
  1967. .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
  1968. .antennaGain = 0,
  1969. .switchSettling = 0x2d,
  1970. .adcDesiredSize = -30,
  1971. .txEndToXpaOff = 0,
  1972. .txEndToRxOn = 0x2,
  1973. .txFrameToXpaOn = 0xe,
  1974. .thresh62 = 28,
  1975. .papdRateMaskHt20 = LE32(0x0cf0e0e0),
  1976. .papdRateMaskHt40 = LE32(0x6cf0e0e0),
  1977. .futureModal = {
  1978. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1979. },
  1980. },
  1981. .base_ext2 = {
  1982. .tempSlopeLow = 72,
  1983. .tempSlopeHigh = 105,
  1984. .xatten1DBLow = {0x10, 0x14, 0x10},
  1985. .xatten1MarginLow = {0x19, 0x19 , 0x19},
  1986. .xatten1DBHigh = {0x1d, 0x20, 0x24},
  1987. .xatten1MarginHigh = {0x10, 0x10, 0x10}
  1988. },
  1989. .calFreqPier5G = {
  1990. FREQ2FBIN(5180, 0),
  1991. FREQ2FBIN(5220, 0),
  1992. FREQ2FBIN(5320, 0),
  1993. FREQ2FBIN(5400, 0),
  1994. FREQ2FBIN(5500, 0),
  1995. FREQ2FBIN(5600, 0),
  1996. FREQ2FBIN(5700, 0),
  1997. FREQ2FBIN(5785, 0)
  1998. },
  1999. .calPierData5G = {
  2000. {
  2001. {0, 0, 0, 0, 0},
  2002. {0, 0, 0, 0, 0},
  2003. {0, 0, 0, 0, 0},
  2004. {0, 0, 0, 0, 0},
  2005. {0, 0, 0, 0, 0},
  2006. {0, 0, 0, 0, 0},
  2007. {0, 0, 0, 0, 0},
  2008. {0, 0, 0, 0, 0},
  2009. },
  2010. {
  2011. {0, 0, 0, 0, 0},
  2012. {0, 0, 0, 0, 0},
  2013. {0, 0, 0, 0, 0},
  2014. {0, 0, 0, 0, 0},
  2015. {0, 0, 0, 0, 0},
  2016. {0, 0, 0, 0, 0},
  2017. {0, 0, 0, 0, 0},
  2018. {0, 0, 0, 0, 0},
  2019. },
  2020. {
  2021. {0, 0, 0, 0, 0},
  2022. {0, 0, 0, 0, 0},
  2023. {0, 0, 0, 0, 0},
  2024. {0, 0, 0, 0, 0},
  2025. {0, 0, 0, 0, 0},
  2026. {0, 0, 0, 0, 0},
  2027. {0, 0, 0, 0, 0},
  2028. {0, 0, 0, 0, 0},
  2029. },
  2030. },
  2031. .calTarget_freqbin_5G = {
  2032. FREQ2FBIN(5180, 0),
  2033. FREQ2FBIN(5220, 0),
  2034. FREQ2FBIN(5320, 0),
  2035. FREQ2FBIN(5400, 0),
  2036. FREQ2FBIN(5500, 0),
  2037. FREQ2FBIN(5600, 0),
  2038. FREQ2FBIN(5725, 0),
  2039. FREQ2FBIN(5825, 0)
  2040. },
  2041. .calTarget_freqbin_5GHT20 = {
  2042. FREQ2FBIN(5180, 0),
  2043. FREQ2FBIN(5220, 0),
  2044. FREQ2FBIN(5320, 0),
  2045. FREQ2FBIN(5400, 0),
  2046. FREQ2FBIN(5500, 0),
  2047. FREQ2FBIN(5600, 0),
  2048. FREQ2FBIN(5725, 0),
  2049. FREQ2FBIN(5825, 0)
  2050. },
  2051. .calTarget_freqbin_5GHT40 = {
  2052. FREQ2FBIN(5180, 0),
  2053. FREQ2FBIN(5220, 0),
  2054. FREQ2FBIN(5320, 0),
  2055. FREQ2FBIN(5400, 0),
  2056. FREQ2FBIN(5500, 0),
  2057. FREQ2FBIN(5600, 0),
  2058. FREQ2FBIN(5725, 0),
  2059. FREQ2FBIN(5825, 0)
  2060. },
  2061. .calTargetPower5G = {
  2062. /* 6-24,36,48,54 */
  2063. { {32, 32, 28, 26} },
  2064. { {32, 32, 28, 26} },
  2065. { {32, 32, 28, 26} },
  2066. { {32, 32, 26, 24} },
  2067. { {32, 32, 26, 24} },
  2068. { {32, 32, 24, 22} },
  2069. { {30, 30, 24, 22} },
  2070. { {30, 30, 24, 22} },
  2071. },
  2072. .calTargetPower5GHT20 = {
  2073. /*
  2074. * 0_8_16,1-3_9-11_17-19,
  2075. * 4,5,6,7,12,13,14,15,20,21,22,23
  2076. */
  2077. { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
  2078. { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
  2079. { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
  2080. { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
  2081. { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
  2082. { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
  2083. { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
  2084. { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
  2085. },
  2086. .calTargetPower5GHT40 = {
  2087. /*
  2088. * 0_8_16,1-3_9-11_17-19,
  2089. * 4,5,6,7,12,13,14,15,20,21,22,23
  2090. */
  2091. { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
  2092. { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
  2093. { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
  2094. { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
  2095. { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
  2096. { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
  2097. { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
  2098. { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
  2099. },
  2100. .ctlIndex_5G = {
  2101. 0x10, 0x16, 0x18, 0x40, 0x46,
  2102. 0x48, 0x30, 0x36, 0x38
  2103. },
  2104. .ctl_freqbin_5G = {
  2105. {
  2106. /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
  2107. /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
  2108. /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
  2109. /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
  2110. /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
  2111. /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
  2112. /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
  2113. /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
  2114. },
  2115. {
  2116. /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
  2117. /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
  2118. /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
  2119. /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
  2120. /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
  2121. /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
  2122. /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
  2123. /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
  2124. },
  2125. {
  2126. /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
  2127. /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
  2128. /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
  2129. /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
  2130. /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
  2131. /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
  2132. /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
  2133. /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
  2134. },
  2135. {
  2136. /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
  2137. /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
  2138. /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
  2139. /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
  2140. /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
  2141. /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
  2142. /* Data[3].ctledges[6].bchannel */ 0xFF,
  2143. /* Data[3].ctledges[7].bchannel */ 0xFF,
  2144. },
  2145. {
  2146. /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
  2147. /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
  2148. /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
  2149. /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
  2150. /* Data[4].ctledges[4].bchannel */ 0xFF,
  2151. /* Data[4].ctledges[5].bchannel */ 0xFF,
  2152. /* Data[4].ctledges[6].bchannel */ 0xFF,
  2153. /* Data[4].ctledges[7].bchannel */ 0xFF,
  2154. },
  2155. {
  2156. /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
  2157. /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
  2158. /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
  2159. /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
  2160. /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
  2161. /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
  2162. /* Data[5].ctledges[6].bchannel */ 0xFF,
  2163. /* Data[5].ctledges[7].bchannel */ 0xFF
  2164. },
  2165. {
  2166. /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
  2167. /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
  2168. /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
  2169. /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
  2170. /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
  2171. /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
  2172. /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
  2173. /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
  2174. },
  2175. {
  2176. /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
  2177. /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
  2178. /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
  2179. /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
  2180. /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
  2181. /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
  2182. /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
  2183. /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
  2184. },
  2185. {
  2186. /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
  2187. /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
  2188. /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
  2189. /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
  2190. /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
  2191. /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
  2192. /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
  2193. /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
  2194. }
  2195. },
  2196. .ctlPowerData_5G = {
  2197. {
  2198. {
  2199. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  2200. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  2201. }
  2202. },
  2203. {
  2204. {
  2205. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  2206. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  2207. }
  2208. },
  2209. {
  2210. {
  2211. CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  2212. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  2213. }
  2214. },
  2215. {
  2216. {
  2217. CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  2218. CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  2219. }
  2220. },
  2221. {
  2222. {
  2223. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  2224. CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  2225. }
  2226. },
  2227. {
  2228. {
  2229. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  2230. CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  2231. }
  2232. },
  2233. {
  2234. {
  2235. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  2236. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  2237. }
  2238. },
  2239. {
  2240. {
  2241. CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  2242. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  2243. }
  2244. },
  2245. {
  2246. {
  2247. CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
  2248. CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  2249. }
  2250. },
  2251. }
  2252. };
  2253. static const struct ar9300_eeprom ar9300_h116 = {
  2254. .eepromVersion = 2,
  2255. .templateVersion = 4,
  2256. .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
  2257. .custData = {"h116-041-f0000"},
  2258. .baseEepHeader = {
  2259. .regDmn = { LE16(0), LE16(0x1f) },
  2260. .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
  2261. .opCapFlags = {
  2262. .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
  2263. .eepMisc = 0,
  2264. },
  2265. .rfSilent = 0,
  2266. .blueToothOptions = 0,
  2267. .deviceCap = 0,
  2268. .deviceType = 5, /* takes lower byte in eeprom location */
  2269. .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  2270. .params_for_tuning_caps = {0, 0},
  2271. .featureEnable = 0x0d,
  2272. /*
  2273. * bit0 - enable tx temp comp - disabled
  2274. * bit1 - enable tx volt comp - disabled
  2275. * bit2 - enable fastClock - enabled
  2276. * bit3 - enable doubling - enabled
  2277. * bit4 - enable internal regulator - disabled
  2278. * bit5 - enable pa predistortion - disabled
  2279. */
  2280. .miscConfiguration = 0, /* bit0 - turn down drivestrength */
  2281. .eepromWriteEnableGpio = 6,
  2282. .wlanDisableGpio = 0,
  2283. .wlanLedGpio = 8,
  2284. .rxBandSelectGpio = 0xff,
  2285. .txrxgain = 0x10,
  2286. .swreg = 0,
  2287. },
  2288. .modalHeader2G = {
  2289. /* ar9300_modal_eep_header 2g */
  2290. /* 4 idle,t1,t2,b(4 bits per setting) */
  2291. .antCtrlCommon = LE32(0x110),
  2292. /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
  2293. .antCtrlCommon2 = LE32(0x44444),
  2294. /*
  2295. * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
  2296. * rx1, rx12, b (2 bits each)
  2297. */
  2298. .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
  2299. /*
  2300. * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
  2301. * for ar9280 (0xa20c/b20c 5:0)
  2302. */
  2303. .xatten1DB = {0x1f, 0x1f, 0x1f},
  2304. /*
  2305. * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
  2306. * for ar9280 (0xa20c/b20c 16:12
  2307. */
  2308. .xatten1Margin = {0x12, 0x12, 0x12},
  2309. .tempSlope = 25,
  2310. .voltSlope = 0,
  2311. /*
  2312. * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
  2313. * channels in usual fbin coding format
  2314. */
  2315. .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
  2316. /*
  2317. * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
  2318. * if the register is per chain
  2319. */
  2320. .noiseFloorThreshCh = {-1, 0, 0},
  2321. .ob = {1, 1, 1},/* 3 chain */
  2322. .db_stage2 = {1, 1, 1}, /* 3 chain */
  2323. .db_stage3 = {0, 0, 0},
  2324. .db_stage4 = {0, 0, 0},
  2325. .xpaBiasLvl = 0,
  2326. .txFrameToDataStart = 0x0e,
  2327. .txFrameToPaOn = 0x0e,
  2328. .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
  2329. .antennaGain = 0,
  2330. .switchSettling = 0x2c,
  2331. .adcDesiredSize = -30,
  2332. .txEndToXpaOff = 0,
  2333. .txEndToRxOn = 0x2,
  2334. .txFrameToXpaOn = 0xe,
  2335. .thresh62 = 28,
  2336. .papdRateMaskHt20 = LE32(0x0c80C080),
  2337. .papdRateMaskHt40 = LE32(0x0080C080),
  2338. .futureModal = {
  2339. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2340. },
  2341. },
  2342. .base_ext1 = {
  2343. .ant_div_control = 0,
  2344. .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
  2345. },
  2346. .calFreqPier2G = {
  2347. FREQ2FBIN(2412, 1),
  2348. FREQ2FBIN(2437, 1),
  2349. FREQ2FBIN(2472, 1),
  2350. },
  2351. /* ar9300_cal_data_per_freq_op_loop 2g */
  2352. .calPierData2G = {
  2353. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  2354. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  2355. { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
  2356. },
  2357. .calTarget_freqbin_Cck = {
  2358. FREQ2FBIN(2412, 1),
  2359. FREQ2FBIN(2472, 1),
  2360. },
  2361. .calTarget_freqbin_2G = {
  2362. FREQ2FBIN(2412, 1),
  2363. FREQ2FBIN(2437, 1),
  2364. FREQ2FBIN(2472, 1)
  2365. },
  2366. .calTarget_freqbin_2GHT20 = {
  2367. FREQ2FBIN(2412, 1),
  2368. FREQ2FBIN(2437, 1),
  2369. FREQ2FBIN(2472, 1)
  2370. },
  2371. .calTarget_freqbin_2GHT40 = {
  2372. FREQ2FBIN(2412, 1),
  2373. FREQ2FBIN(2437, 1),
  2374. FREQ2FBIN(2472, 1)
  2375. },
  2376. .calTargetPowerCck = {
  2377. /* 1L-5L,5S,11L,11S */
  2378. { {34, 34, 34, 34} },
  2379. { {34, 34, 34, 34} },
  2380. },
  2381. .calTargetPower2G = {
  2382. /* 6-24,36,48,54 */
  2383. { {34, 34, 32, 32} },
  2384. { {34, 34, 32, 32} },
  2385. { {34, 34, 32, 32} },
  2386. },
  2387. .calTargetPower2GHT20 = {
  2388. { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
  2389. { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
  2390. { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
  2391. },
  2392. .calTargetPower2GHT40 = {
  2393. { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
  2394. { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
  2395. { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
  2396. },
  2397. .ctlIndex_2G = {
  2398. 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
  2399. 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
  2400. },
  2401. .ctl_freqbin_2G = {
  2402. {
  2403. FREQ2FBIN(2412, 1),
  2404. FREQ2FBIN(2417, 1),
  2405. FREQ2FBIN(2457, 1),
  2406. FREQ2FBIN(2462, 1)
  2407. },
  2408. {
  2409. FREQ2FBIN(2412, 1),
  2410. FREQ2FBIN(2417, 1),
  2411. FREQ2FBIN(2462, 1),
  2412. 0xFF,
  2413. },
  2414. {
  2415. FREQ2FBIN(2412, 1),
  2416. FREQ2FBIN(2417, 1),
  2417. FREQ2FBIN(2462, 1),
  2418. 0xFF,
  2419. },
  2420. {
  2421. FREQ2FBIN(2422, 1),
  2422. FREQ2FBIN(2427, 1),
  2423. FREQ2FBIN(2447, 1),
  2424. FREQ2FBIN(2452, 1)
  2425. },
  2426. {
  2427. /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  2428. /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  2429. /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  2430. /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
  2431. },
  2432. {
  2433. /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  2434. /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  2435. /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  2436. 0,
  2437. },
  2438. {
  2439. /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  2440. /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  2441. FREQ2FBIN(2472, 1),
  2442. 0,
  2443. },
  2444. {
  2445. /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
  2446. /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
  2447. /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
  2448. /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
  2449. },
  2450. {
  2451. /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  2452. /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  2453. /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  2454. },
  2455. {
  2456. /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  2457. /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  2458. /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  2459. 0
  2460. },
  2461. {
  2462. /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
  2463. /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
  2464. /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
  2465. 0
  2466. },
  2467. {
  2468. /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
  2469. /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
  2470. /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
  2471. /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
  2472. }
  2473. },
  2474. .ctlPowerData_2G = {
  2475. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  2476. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  2477. { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
  2478. { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
  2479. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  2480. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  2481. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
  2482. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  2483. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  2484. { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
  2485. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
  2486. { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
  2487. },
  2488. .modalHeader5G = {
  2489. /* 4 idle,t1,t2,b (4 bits per setting) */
  2490. .antCtrlCommon = LE32(0x220),
  2491. /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
  2492. .antCtrlCommon2 = LE32(0x44444),
  2493. /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
  2494. .antCtrlChain = {
  2495. LE16(0x150), LE16(0x150), LE16(0x150),
  2496. },
  2497. /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
  2498. .xatten1DB = {0x19, 0x19, 0x19},
  2499. /*
  2500. * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
  2501. * for merlin (0xa20c/b20c 16:12
  2502. */
  2503. .xatten1Margin = {0x14, 0x14, 0x14},
  2504. .tempSlope = 70,
  2505. .voltSlope = 0,
  2506. /* spurChans spur channels in usual fbin coding format */
  2507. .spurChans = {0, 0, 0, 0, 0},
  2508. /* noiseFloorThreshCh Check if the register is per chain */
  2509. .noiseFloorThreshCh = {-1, 0, 0},
  2510. .ob = {3, 3, 3}, /* 3 chain */
  2511. .db_stage2 = {3, 3, 3}, /* 3 chain */
  2512. .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
  2513. .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
  2514. .xpaBiasLvl = 0,
  2515. .txFrameToDataStart = 0x0e,
  2516. .txFrameToPaOn = 0x0e,
  2517. .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
  2518. .antennaGain = 0,
  2519. .switchSettling = 0x2d,
  2520. .adcDesiredSize = -30,
  2521. .txEndToXpaOff = 0,
  2522. .txEndToRxOn = 0x2,
  2523. .txFrameToXpaOn = 0xe,
  2524. .thresh62 = 28,
  2525. .papdRateMaskHt20 = LE32(0x0cf0e0e0),
  2526. .papdRateMaskHt40 = LE32(0x6cf0e0e0),
  2527. .futureModal = {
  2528. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  2529. },
  2530. },
  2531. .base_ext2 = {
  2532. .tempSlopeLow = 35,
  2533. .tempSlopeHigh = 50,
  2534. .xatten1DBLow = {0, 0, 0},
  2535. .xatten1MarginLow = {0, 0, 0},
  2536. .xatten1DBHigh = {0, 0, 0},
  2537. .xatten1MarginHigh = {0, 0, 0}
  2538. },
  2539. .calFreqPier5G = {
  2540. FREQ2FBIN(5180, 0),
  2541. FREQ2FBIN(5220, 0),
  2542. FREQ2FBIN(5320, 0),
  2543. FREQ2FBIN(5400, 0),
  2544. FREQ2FBIN(5500, 0),
  2545. FREQ2FBIN(5600, 0),
  2546. FREQ2FBIN(5700, 0),
  2547. FREQ2FBIN(5785, 0)
  2548. },
  2549. .calPierData5G = {
  2550. {
  2551. {0, 0, 0, 0, 0},
  2552. {0, 0, 0, 0, 0},
  2553. {0, 0, 0, 0, 0},
  2554. {0, 0, 0, 0, 0},
  2555. {0, 0, 0, 0, 0},
  2556. {0, 0, 0, 0, 0},
  2557. {0, 0, 0, 0, 0},
  2558. {0, 0, 0, 0, 0},
  2559. },
  2560. {
  2561. {0, 0, 0, 0, 0},
  2562. {0, 0, 0, 0, 0},
  2563. {0, 0, 0, 0, 0},
  2564. {0, 0, 0, 0, 0},
  2565. {0, 0, 0, 0, 0},
  2566. {0, 0, 0, 0, 0},
  2567. {0, 0, 0, 0, 0},
  2568. {0, 0, 0, 0, 0},
  2569. },
  2570. {
  2571. {0, 0, 0, 0, 0},
  2572. {0, 0, 0, 0, 0},
  2573. {0, 0, 0, 0, 0},
  2574. {0, 0, 0, 0, 0},
  2575. {0, 0, 0, 0, 0},
  2576. {0, 0, 0, 0, 0},
  2577. {0, 0, 0, 0, 0},
  2578. {0, 0, 0, 0, 0},
  2579. },
  2580. },
  2581. .calTarget_freqbin_5G = {
  2582. FREQ2FBIN(5180, 0),
  2583. FREQ2FBIN(5240, 0),
  2584. FREQ2FBIN(5320, 0),
  2585. FREQ2FBIN(5400, 0),
  2586. FREQ2FBIN(5500, 0),
  2587. FREQ2FBIN(5600, 0),
  2588. FREQ2FBIN(5700, 0),
  2589. FREQ2FBIN(5825, 0)
  2590. },
  2591. .calTarget_freqbin_5GHT20 = {
  2592. FREQ2FBIN(5180, 0),
  2593. FREQ2FBIN(5240, 0),
  2594. FREQ2FBIN(5320, 0),
  2595. FREQ2FBIN(5400, 0),
  2596. FREQ2FBIN(5500, 0),
  2597. FREQ2FBIN(5700, 0),
  2598. FREQ2FBIN(5745, 0),
  2599. FREQ2FBIN(5825, 0)
  2600. },
  2601. .calTarget_freqbin_5GHT40 = {
  2602. FREQ2FBIN(5180, 0),
  2603. FREQ2FBIN(5240, 0),
  2604. FREQ2FBIN(5320, 0),
  2605. FREQ2FBIN(5400, 0),
  2606. FREQ2FBIN(5500, 0),
  2607. FREQ2FBIN(5700, 0),
  2608. FREQ2FBIN(5745, 0),
  2609. FREQ2FBIN(5825, 0)
  2610. },
  2611. .calTargetPower5G = {
  2612. /* 6-24,36,48,54 */
  2613. { {30, 30, 28, 24} },
  2614. { {30, 30, 28, 24} },
  2615. { {30, 30, 28, 24} },
  2616. { {30, 30, 28, 24} },
  2617. { {30, 30, 28, 24} },
  2618. { {30, 30, 28, 24} },
  2619. { {30, 30, 28, 24} },
  2620. { {30, 30, 28, 24} },
  2621. },
  2622. .calTargetPower5GHT20 = {
  2623. /*
  2624. * 0_8_16,1-3_9-11_17-19,
  2625. * 4,5,6,7,12,13,14,15,20,21,22,23
  2626. */
  2627. { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
  2628. { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
  2629. { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
  2630. { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
  2631. { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
  2632. { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
  2633. { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
  2634. { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
  2635. },
  2636. .calTargetPower5GHT40 = {
  2637. /*
  2638. * 0_8_16,1-3_9-11_17-19,
  2639. * 4,5,6,7,12,13,14,15,20,21,22,23
  2640. */
  2641. { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
  2642. { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
  2643. { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
  2644. { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
  2645. { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
  2646. { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
  2647. { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
  2648. { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
  2649. },
  2650. .ctlIndex_5G = {
  2651. 0x10, 0x16, 0x18, 0x40, 0x46,
  2652. 0x48, 0x30, 0x36, 0x38
  2653. },
  2654. .ctl_freqbin_5G = {
  2655. {
  2656. /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  2657. /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  2658. /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
  2659. /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
  2660. /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
  2661. /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  2662. /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
  2663. /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
  2664. },
  2665. {
  2666. /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  2667. /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  2668. /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
  2669. /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
  2670. /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
  2671. /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  2672. /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
  2673. /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
  2674. },
  2675. {
  2676. /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
  2677. /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
  2678. /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
  2679. /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
  2680. /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
  2681. /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
  2682. /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
  2683. /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
  2684. },
  2685. {
  2686. /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  2687. /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
  2688. /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
  2689. /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
  2690. /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
  2691. /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  2692. /* Data[3].ctlEdges[6].bChannel */ 0xFF,
  2693. /* Data[3].ctlEdges[7].bChannel */ 0xFF,
  2694. },
  2695. {
  2696. /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  2697. /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  2698. /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
  2699. /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
  2700. /* Data[4].ctlEdges[4].bChannel */ 0xFF,
  2701. /* Data[4].ctlEdges[5].bChannel */ 0xFF,
  2702. /* Data[4].ctlEdges[6].bChannel */ 0xFF,
  2703. /* Data[4].ctlEdges[7].bChannel */ 0xFF,
  2704. },
  2705. {
  2706. /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
  2707. /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
  2708. /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
  2709. /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
  2710. /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
  2711. /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
  2712. /* Data[5].ctlEdges[6].bChannel */ 0xFF,
  2713. /* Data[5].ctlEdges[7].bChannel */ 0xFF
  2714. },
  2715. {
  2716. /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  2717. /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
  2718. /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
  2719. /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
  2720. /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
  2721. /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
  2722. /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
  2723. /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
  2724. },
  2725. {
  2726. /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
  2727. /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
  2728. /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
  2729. /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
  2730. /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
  2731. /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
  2732. /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
  2733. /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
  2734. },
  2735. {
  2736. /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
  2737. /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
  2738. /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
  2739. /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
  2740. /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
  2741. /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
  2742. /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
  2743. /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
  2744. }
  2745. },
  2746. .ctlPowerData_5G = {
  2747. {
  2748. {
  2749. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  2750. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  2751. }
  2752. },
  2753. {
  2754. {
  2755. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  2756. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  2757. }
  2758. },
  2759. {
  2760. {
  2761. CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  2762. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  2763. }
  2764. },
  2765. {
  2766. {
  2767. CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  2768. CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  2769. }
  2770. },
  2771. {
  2772. {
  2773. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  2774. CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  2775. }
  2776. },
  2777. {
  2778. {
  2779. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  2780. CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
  2781. }
  2782. },
  2783. {
  2784. {
  2785. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  2786. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
  2787. }
  2788. },
  2789. {
  2790. {
  2791. CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  2792. CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
  2793. }
  2794. },
  2795. {
  2796. {
  2797. CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
  2798. CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
  2799. }
  2800. },
  2801. }
  2802. };
  2803. static const struct ar9300_eeprom *ar9300_eep_templates[] = {
  2804. &ar9300_default,
  2805. &ar9300_x112,
  2806. &ar9300_h116,
  2807. &ar9300_h112,
  2808. &ar9300_x113,
  2809. };
  2810. static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
  2811. {
  2812. #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
  2813. int it;
  2814. for (it = 0; it < N_LOOP; it++)
  2815. if (ar9300_eep_templates[it]->templateVersion == id)
  2816. return ar9300_eep_templates[it];
  2817. return NULL;
  2818. #undef N_LOOP
  2819. }
  2820. static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
  2821. {
  2822. if (fbin == AR9300_BCHAN_UNUSED)
  2823. return fbin;
  2824. return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
  2825. }
  2826. static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
  2827. {
  2828. return 0;
  2829. }
  2830. static int interpolate(int x, int xa, int xb, int ya, int yb)
  2831. {
  2832. int bf, factor, plus;
  2833. bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
  2834. factor = bf / 2;
  2835. plus = bf % 2;
  2836. return ya + factor + plus;
  2837. }
  2838. static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
  2839. enum eeprom_param param)
  2840. {
  2841. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  2842. struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
  2843. switch (param) {
  2844. case EEP_MAC_LSW:
  2845. return eep->macAddr[0] << 8 | eep->macAddr[1];
  2846. case EEP_MAC_MID:
  2847. return eep->macAddr[2] << 8 | eep->macAddr[3];
  2848. case EEP_MAC_MSW:
  2849. return eep->macAddr[4] << 8 | eep->macAddr[5];
  2850. case EEP_REG_0:
  2851. return le16_to_cpu(pBase->regDmn[0]);
  2852. case EEP_REG_1:
  2853. return le16_to_cpu(pBase->regDmn[1]);
  2854. case EEP_OP_CAP:
  2855. return pBase->deviceCap;
  2856. case EEP_OP_MODE:
  2857. return pBase->opCapFlags.opFlags;
  2858. case EEP_RF_SILENT:
  2859. return pBase->rfSilent;
  2860. case EEP_TX_MASK:
  2861. return (pBase->txrxMask >> 4) & 0xf;
  2862. case EEP_RX_MASK:
  2863. return pBase->txrxMask & 0xf;
  2864. case EEP_DRIVE_STRENGTH:
  2865. #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
  2866. return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
  2867. case EEP_INTERNAL_REGULATOR:
  2868. /* Bit 4 is internal regulator flag */
  2869. return (pBase->featureEnable & 0x10) >> 4;
  2870. case EEP_SWREG:
  2871. return le32_to_cpu(pBase->swreg);
  2872. case EEP_PAPRD:
  2873. return !!(pBase->featureEnable & BIT(5));
  2874. case EEP_CHAIN_MASK_REDUCE:
  2875. return (pBase->miscConfiguration >> 0x3) & 0x1;
  2876. case EEP_ANT_DIV_CTL1:
  2877. return le32_to_cpu(eep->base_ext1.ant_div_control);
  2878. default:
  2879. return 0;
  2880. }
  2881. }
  2882. static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
  2883. u8 *buffer)
  2884. {
  2885. u16 val;
  2886. if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
  2887. return false;
  2888. *buffer = (val >> (8 * (address % 2))) & 0xff;
  2889. return true;
  2890. }
  2891. static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
  2892. u8 *buffer)
  2893. {
  2894. u16 val;
  2895. if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
  2896. return false;
  2897. buffer[0] = val >> 8;
  2898. buffer[1] = val & 0xff;
  2899. return true;
  2900. }
  2901. static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
  2902. int count)
  2903. {
  2904. struct ath_common *common = ath9k_hw_common(ah);
  2905. int i;
  2906. if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
  2907. ath_dbg(common, ATH_DBG_EEPROM,
  2908. "eeprom address not in range\n");
  2909. return false;
  2910. }
  2911. /*
  2912. * Since we're reading the bytes in reverse order from a little-endian
  2913. * word stream, an even address means we only use the lower half of
  2914. * the 16-bit word at that address
  2915. */
  2916. if (address % 2 == 0) {
  2917. if (!ar9300_eeprom_read_byte(common, address--, buffer++))
  2918. goto error;
  2919. count--;
  2920. }
  2921. for (i = 0; i < count / 2; i++) {
  2922. if (!ar9300_eeprom_read_word(common, address, buffer))
  2923. goto error;
  2924. address -= 2;
  2925. buffer += 2;
  2926. }
  2927. if (count % 2)
  2928. if (!ar9300_eeprom_read_byte(common, address, buffer))
  2929. goto error;
  2930. return true;
  2931. error:
  2932. ath_dbg(common, ATH_DBG_EEPROM,
  2933. "unable to read eeprom region at offset %d\n", address);
  2934. return false;
  2935. }
  2936. static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
  2937. {
  2938. REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
  2939. if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
  2940. AR9300_OTP_STATUS_VALID, 1000))
  2941. return false;
  2942. *data = REG_READ(ah, AR9300_OTP_READ_DATA);
  2943. return true;
  2944. }
  2945. static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
  2946. int count)
  2947. {
  2948. u32 data;
  2949. int i;
  2950. for (i = 0; i < count; i++) {
  2951. int offset = 8 * ((address - i) % 4);
  2952. if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
  2953. return false;
  2954. buffer[i] = (data >> offset) & 0xff;
  2955. }
  2956. return true;
  2957. }
  2958. static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
  2959. int *length, int *major, int *minor)
  2960. {
  2961. unsigned long value[4];
  2962. value[0] = best[0];
  2963. value[1] = best[1];
  2964. value[2] = best[2];
  2965. value[3] = best[3];
  2966. *code = ((value[0] >> 5) & 0x0007);
  2967. *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
  2968. *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
  2969. *major = (value[2] & 0x000f);
  2970. *minor = (value[3] & 0x00ff);
  2971. }
  2972. static u16 ar9300_comp_cksum(u8 *data, int dsize)
  2973. {
  2974. int it, checksum = 0;
  2975. for (it = 0; it < dsize; it++) {
  2976. checksum += data[it];
  2977. checksum &= 0xffff;
  2978. }
  2979. return checksum;
  2980. }
  2981. static bool ar9300_uncompress_block(struct ath_hw *ah,
  2982. u8 *mptr,
  2983. int mdataSize,
  2984. u8 *block,
  2985. int size)
  2986. {
  2987. int it;
  2988. int spot;
  2989. int offset;
  2990. int length;
  2991. struct ath_common *common = ath9k_hw_common(ah);
  2992. spot = 0;
  2993. for (it = 0; it < size; it += (length+2)) {
  2994. offset = block[it];
  2995. offset &= 0xff;
  2996. spot += offset;
  2997. length = block[it+1];
  2998. length &= 0xff;
  2999. if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
  3000. ath_dbg(common, ATH_DBG_EEPROM,
  3001. "Restore at %d: spot=%d offset=%d length=%d\n",
  3002. it, spot, offset, length);
  3003. memcpy(&mptr[spot], &block[it+2], length);
  3004. spot += length;
  3005. } else if (length > 0) {
  3006. ath_dbg(common, ATH_DBG_EEPROM,
  3007. "Bad restore at %d: spot=%d offset=%d length=%d\n",
  3008. it, spot, offset, length);
  3009. return false;
  3010. }
  3011. }
  3012. return true;
  3013. }
  3014. static int ar9300_compress_decision(struct ath_hw *ah,
  3015. int it,
  3016. int code,
  3017. int reference,
  3018. u8 *mptr,
  3019. u8 *word, int length, int mdata_size)
  3020. {
  3021. struct ath_common *common = ath9k_hw_common(ah);
  3022. u8 *dptr;
  3023. const struct ar9300_eeprom *eep = NULL;
  3024. switch (code) {
  3025. case _CompressNone:
  3026. if (length != mdata_size) {
  3027. ath_dbg(common, ATH_DBG_EEPROM,
  3028. "EEPROM structure size mismatch memory=%d eeprom=%d\n",
  3029. mdata_size, length);
  3030. return -1;
  3031. }
  3032. memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
  3033. ath_dbg(common, ATH_DBG_EEPROM,
  3034. "restored eeprom %d: uncompressed, length %d\n",
  3035. it, length);
  3036. break;
  3037. case _CompressBlock:
  3038. if (reference == 0) {
  3039. dptr = mptr;
  3040. } else {
  3041. eep = ar9003_eeprom_struct_find_by_id(reference);
  3042. if (eep == NULL) {
  3043. ath_dbg(common, ATH_DBG_EEPROM,
  3044. "cant find reference eeprom struct %d\n",
  3045. reference);
  3046. return -1;
  3047. }
  3048. memcpy(mptr, eep, mdata_size);
  3049. }
  3050. ath_dbg(common, ATH_DBG_EEPROM,
  3051. "restore eeprom %d: block, reference %d, length %d\n",
  3052. it, reference, length);
  3053. ar9300_uncompress_block(ah, mptr, mdata_size,
  3054. (u8 *) (word + COMP_HDR_LEN), length);
  3055. break;
  3056. default:
  3057. ath_dbg(common, ATH_DBG_EEPROM,
  3058. "unknown compression code %d\n", code);
  3059. return -1;
  3060. }
  3061. return 0;
  3062. }
  3063. typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
  3064. int count);
  3065. static bool ar9300_check_header(void *data)
  3066. {
  3067. u32 *word = data;
  3068. return !(*word == 0 || *word == ~0);
  3069. }
  3070. static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
  3071. int base_addr)
  3072. {
  3073. u8 header[4];
  3074. if (!read(ah, base_addr, header, 4))
  3075. return false;
  3076. return ar9300_check_header(header);
  3077. }
  3078. static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
  3079. int mdata_size)
  3080. {
  3081. struct ath_common *common = ath9k_hw_common(ah);
  3082. u16 *data = (u16 *) mptr;
  3083. int i;
  3084. for (i = 0; i < mdata_size / 2; i++, data++)
  3085. ath9k_hw_nvram_read(common, i, data);
  3086. return 0;
  3087. }
  3088. /*
  3089. * Read the configuration data from the eeprom.
  3090. * The data can be put in any specified memory buffer.
  3091. *
  3092. * Returns -1 on error.
  3093. * Returns address of next memory location on success.
  3094. */
  3095. static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
  3096. u8 *mptr, int mdata_size)
  3097. {
  3098. #define MDEFAULT 15
  3099. #define MSTATE 100
  3100. int cptr;
  3101. u8 *word;
  3102. int code;
  3103. int reference, length, major, minor;
  3104. int osize;
  3105. int it;
  3106. u16 checksum, mchecksum;
  3107. struct ath_common *common = ath9k_hw_common(ah);
  3108. eeprom_read_op read;
  3109. if (ath9k_hw_use_flash(ah))
  3110. return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
  3111. word = kzalloc(2048, GFP_KERNEL);
  3112. if (!word)
  3113. return -1;
  3114. memcpy(mptr, &ar9300_default, mdata_size);
  3115. read = ar9300_read_eeprom;
  3116. if (AR_SREV_9485(ah))
  3117. cptr = AR9300_BASE_ADDR_4K;
  3118. else
  3119. cptr = AR9300_BASE_ADDR;
  3120. ath_dbg(common, ATH_DBG_EEPROM,
  3121. "Trying EEPROM accesss at Address 0x%04x\n", cptr);
  3122. if (ar9300_check_eeprom_header(ah, read, cptr))
  3123. goto found;
  3124. cptr = AR9300_BASE_ADDR_512;
  3125. ath_dbg(common, ATH_DBG_EEPROM,
  3126. "Trying EEPROM accesss at Address 0x%04x\n", cptr);
  3127. if (ar9300_check_eeprom_header(ah, read, cptr))
  3128. goto found;
  3129. read = ar9300_read_otp;
  3130. cptr = AR9300_BASE_ADDR;
  3131. ath_dbg(common, ATH_DBG_EEPROM,
  3132. "Trying OTP accesss at Address 0x%04x\n", cptr);
  3133. if (ar9300_check_eeprom_header(ah, read, cptr))
  3134. goto found;
  3135. cptr = AR9300_BASE_ADDR_512;
  3136. ath_dbg(common, ATH_DBG_EEPROM,
  3137. "Trying OTP accesss at Address 0x%04x\n", cptr);
  3138. if (ar9300_check_eeprom_header(ah, read, cptr))
  3139. goto found;
  3140. goto fail;
  3141. found:
  3142. ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
  3143. for (it = 0; it < MSTATE; it++) {
  3144. if (!read(ah, cptr, word, COMP_HDR_LEN))
  3145. goto fail;
  3146. if (!ar9300_check_header(word))
  3147. break;
  3148. ar9300_comp_hdr_unpack(word, &code, &reference,
  3149. &length, &major, &minor);
  3150. ath_dbg(common, ATH_DBG_EEPROM,
  3151. "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
  3152. cptr, code, reference, length, major, minor);
  3153. if ((!AR_SREV_9485(ah) && length >= 1024) ||
  3154. (AR_SREV_9485(ah) && length >= (4 * 1024))) {
  3155. ath_dbg(common, ATH_DBG_EEPROM,
  3156. "Skipping bad header\n");
  3157. cptr -= COMP_HDR_LEN;
  3158. continue;
  3159. }
  3160. osize = length;
  3161. read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
  3162. checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
  3163. mchecksum = word[COMP_HDR_LEN + osize] |
  3164. (word[COMP_HDR_LEN + osize + 1] << 8);
  3165. ath_dbg(common, ATH_DBG_EEPROM,
  3166. "checksum %x %x\n", checksum, mchecksum);
  3167. if (checksum == mchecksum) {
  3168. ar9300_compress_decision(ah, it, code, reference, mptr,
  3169. word, length, mdata_size);
  3170. } else {
  3171. ath_dbg(common, ATH_DBG_EEPROM,
  3172. "skipping block with bad checksum\n");
  3173. }
  3174. cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
  3175. }
  3176. kfree(word);
  3177. return cptr;
  3178. fail:
  3179. kfree(word);
  3180. return -1;
  3181. }
  3182. /*
  3183. * Restore the configuration structure by reading the eeprom.
  3184. * This function destroys any existing in-memory structure
  3185. * content.
  3186. */
  3187. static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
  3188. {
  3189. u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
  3190. if (ar9300_eeprom_restore_internal(ah, mptr,
  3191. sizeof(struct ar9300_eeprom)) < 0)
  3192. return false;
  3193. return true;
  3194. }
  3195. /* XXX: review hardware docs */
  3196. static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
  3197. {
  3198. return ah->eeprom.ar9300_eep.eepromVersion;
  3199. }
  3200. /* XXX: could be read from the eepromVersion, not sure yet */
  3201. static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
  3202. {
  3203. return 0;
  3204. }
  3205. static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
  3206. enum ath9k_hal_freq_band freq_band)
  3207. {
  3208. return 1;
  3209. }
  3210. static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
  3211. struct ath9k_channel *chan)
  3212. {
  3213. return -EINVAL;
  3214. }
  3215. static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
  3216. {
  3217. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3218. if (is2ghz)
  3219. return eep->modalHeader2G.xpaBiasLvl;
  3220. else
  3221. return eep->modalHeader5G.xpaBiasLvl;
  3222. }
  3223. static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
  3224. {
  3225. int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
  3226. if (AR_SREV_9485(ah))
  3227. REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
  3228. else {
  3229. REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
  3230. REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB,
  3231. bias >> 2);
  3232. REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
  3233. }
  3234. }
  3235. static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
  3236. {
  3237. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3238. __le32 val;
  3239. if (is2ghz)
  3240. val = eep->modalHeader2G.antCtrlCommon;
  3241. else
  3242. val = eep->modalHeader5G.antCtrlCommon;
  3243. return le32_to_cpu(val);
  3244. }
  3245. static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
  3246. {
  3247. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3248. __le32 val;
  3249. if (is2ghz)
  3250. val = eep->modalHeader2G.antCtrlCommon2;
  3251. else
  3252. val = eep->modalHeader5G.antCtrlCommon2;
  3253. return le32_to_cpu(val);
  3254. }
  3255. static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
  3256. int chain,
  3257. bool is2ghz)
  3258. {
  3259. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3260. __le16 val = 0;
  3261. if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
  3262. if (is2ghz)
  3263. val = eep->modalHeader2G.antCtrlChain[chain];
  3264. else
  3265. val = eep->modalHeader5G.antCtrlChain[chain];
  3266. }
  3267. return le16_to_cpu(val);
  3268. }
  3269. static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
  3270. {
  3271. u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
  3272. REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
  3273. value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
  3274. REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
  3275. value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
  3276. REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
  3277. if (!AR_SREV_9485(ah)) {
  3278. value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
  3279. REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL,
  3280. value);
  3281. value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
  3282. REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL,
  3283. value);
  3284. }
  3285. if (AR_SREV_9485(ah)) {
  3286. value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
  3287. REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_CTRL_ALL,
  3288. value);
  3289. REG_RMW_FIELD(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE,
  3290. value >> 6);
  3291. REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE,
  3292. value >> 7);
  3293. }
  3294. }
  3295. static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
  3296. {
  3297. int drive_strength;
  3298. unsigned long reg;
  3299. drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
  3300. if (!drive_strength)
  3301. return;
  3302. reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
  3303. reg &= ~0x00ffffc0;
  3304. reg |= 0x5 << 21;
  3305. reg |= 0x5 << 18;
  3306. reg |= 0x5 << 15;
  3307. reg |= 0x5 << 12;
  3308. reg |= 0x5 << 9;
  3309. reg |= 0x5 << 6;
  3310. REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
  3311. reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
  3312. reg &= ~0xffffffe0;
  3313. reg |= 0x5 << 29;
  3314. reg |= 0x5 << 26;
  3315. reg |= 0x5 << 23;
  3316. reg |= 0x5 << 20;
  3317. reg |= 0x5 << 17;
  3318. reg |= 0x5 << 14;
  3319. reg |= 0x5 << 11;
  3320. reg |= 0x5 << 8;
  3321. reg |= 0x5 << 5;
  3322. REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
  3323. reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
  3324. reg &= ~0xff800000;
  3325. reg |= 0x5 << 29;
  3326. reg |= 0x5 << 26;
  3327. reg |= 0x5 << 23;
  3328. REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
  3329. }
  3330. static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
  3331. struct ath9k_channel *chan)
  3332. {
  3333. int f[3], t[3];
  3334. u16 value;
  3335. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3336. if (chain >= 0 && chain < 3) {
  3337. if (IS_CHAN_2GHZ(chan))
  3338. return eep->modalHeader2G.xatten1DB[chain];
  3339. else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
  3340. t[0] = eep->base_ext2.xatten1DBLow[chain];
  3341. f[0] = 5180;
  3342. t[1] = eep->modalHeader5G.xatten1DB[chain];
  3343. f[1] = 5500;
  3344. t[2] = eep->base_ext2.xatten1DBHigh[chain];
  3345. f[2] = 5785;
  3346. value = ar9003_hw_power_interpolate((s32) chan->channel,
  3347. f, t, 3);
  3348. return value;
  3349. } else
  3350. return eep->modalHeader5G.xatten1DB[chain];
  3351. }
  3352. return 0;
  3353. }
  3354. static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
  3355. struct ath9k_channel *chan)
  3356. {
  3357. int f[3], t[3];
  3358. u16 value;
  3359. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3360. if (chain >= 0 && chain < 3) {
  3361. if (IS_CHAN_2GHZ(chan))
  3362. return eep->modalHeader2G.xatten1Margin[chain];
  3363. else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
  3364. t[0] = eep->base_ext2.xatten1MarginLow[chain];
  3365. f[0] = 5180;
  3366. t[1] = eep->modalHeader5G.xatten1Margin[chain];
  3367. f[1] = 5500;
  3368. t[2] = eep->base_ext2.xatten1MarginHigh[chain];
  3369. f[2] = 5785;
  3370. value = ar9003_hw_power_interpolate((s32) chan->channel,
  3371. f, t, 3);
  3372. return value;
  3373. } else
  3374. return eep->modalHeader5G.xatten1Margin[chain];
  3375. }
  3376. return 0;
  3377. }
  3378. static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
  3379. {
  3380. int i;
  3381. u16 value;
  3382. unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
  3383. AR_PHY_EXT_ATTEN_CTL_1,
  3384. AR_PHY_EXT_ATTEN_CTL_2,
  3385. };
  3386. /* Test value. if 0 then attenuation is unused. Don't load anything. */
  3387. for (i = 0; i < 3; i++) {
  3388. value = ar9003_hw_atten_chain_get(ah, i, chan);
  3389. REG_RMW_FIELD(ah, ext_atten_reg[i],
  3390. AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
  3391. value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
  3392. REG_RMW_FIELD(ah, ext_atten_reg[i],
  3393. AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value);
  3394. }
  3395. }
  3396. static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
  3397. {
  3398. int timeout = 100;
  3399. while (pmu_set != REG_READ(ah, pmu_reg)) {
  3400. if (timeout-- == 0)
  3401. return false;
  3402. REG_WRITE(ah, pmu_reg, pmu_set);
  3403. udelay(10);
  3404. }
  3405. return true;
  3406. }
  3407. static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
  3408. {
  3409. int internal_regulator =
  3410. ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
  3411. if (internal_regulator) {
  3412. if (AR_SREV_9485(ah)) {
  3413. int reg_pmu_set;
  3414. reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
  3415. REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
  3416. if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
  3417. return;
  3418. reg_pmu_set = (5 << 1) | (7 << 4) | (1 << 8) |
  3419. (7 << 14) | (6 << 17) | (1 << 20) |
  3420. (3 << 24) | (1 << 28);
  3421. REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
  3422. if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
  3423. return;
  3424. reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
  3425. | (4 << 26);
  3426. REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
  3427. if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
  3428. return;
  3429. reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
  3430. | (1 << 21);
  3431. REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
  3432. if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
  3433. return;
  3434. } else {
  3435. /* Internal regulator is ON. Write swreg register. */
  3436. int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
  3437. REG_WRITE(ah, AR_RTC_REG_CONTROL1,
  3438. REG_READ(ah, AR_RTC_REG_CONTROL1) &
  3439. (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
  3440. REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
  3441. /* Set REG_CONTROL1.SWREG_PROGRAM */
  3442. REG_WRITE(ah, AR_RTC_REG_CONTROL1,
  3443. REG_READ(ah,
  3444. AR_RTC_REG_CONTROL1) |
  3445. AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
  3446. }
  3447. } else {
  3448. if (AR_SREV_9485(ah)) {
  3449. REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
  3450. while (REG_READ_FIELD(ah, AR_PHY_PMU2,
  3451. AR_PHY_PMU2_PGM))
  3452. udelay(10);
  3453. REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
  3454. while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
  3455. AR_PHY_PMU1_PWD))
  3456. udelay(10);
  3457. REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
  3458. while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
  3459. AR_PHY_PMU2_PGM))
  3460. udelay(10);
  3461. } else
  3462. REG_WRITE(ah, AR_RTC_SLEEP_CLK,
  3463. (REG_READ(ah,
  3464. AR_RTC_SLEEP_CLK) |
  3465. AR_RTC_FORCE_SWREG_PRD));
  3466. }
  3467. }
  3468. static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
  3469. {
  3470. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3471. u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
  3472. if (eep->baseEepHeader.featureEnable & 0x40) {
  3473. tuning_caps_param &= 0x7f;
  3474. REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
  3475. tuning_caps_param);
  3476. REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
  3477. tuning_caps_param);
  3478. }
  3479. }
  3480. static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
  3481. struct ath9k_channel *chan)
  3482. {
  3483. ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
  3484. ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
  3485. ar9003_hw_drive_strength_apply(ah);
  3486. ar9003_hw_atten_apply(ah, chan);
  3487. ar9003_hw_internal_regulator_apply(ah);
  3488. if (AR_SREV_9485(ah))
  3489. ar9003_hw_apply_tuning_caps(ah);
  3490. }
  3491. static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
  3492. struct ath9k_channel *chan)
  3493. {
  3494. }
  3495. /*
  3496. * Returns the interpolated y value corresponding to the specified x value
  3497. * from the np ordered pairs of data (px,py).
  3498. * The pairs do not have to be in any order.
  3499. * If the specified x value is less than any of the px,
  3500. * the returned y value is equal to the py for the lowest px.
  3501. * If the specified x value is greater than any of the px,
  3502. * the returned y value is equal to the py for the highest px.
  3503. */
  3504. static int ar9003_hw_power_interpolate(int32_t x,
  3505. int32_t *px, int32_t *py, u_int16_t np)
  3506. {
  3507. int ip = 0;
  3508. int lx = 0, ly = 0, lhave = 0;
  3509. int hx = 0, hy = 0, hhave = 0;
  3510. int dx = 0;
  3511. int y = 0;
  3512. lhave = 0;
  3513. hhave = 0;
  3514. /* identify best lower and higher x calibration measurement */
  3515. for (ip = 0; ip < np; ip++) {
  3516. dx = x - px[ip];
  3517. /* this measurement is higher than our desired x */
  3518. if (dx <= 0) {
  3519. if (!hhave || dx > (x - hx)) {
  3520. /* new best higher x measurement */
  3521. hx = px[ip];
  3522. hy = py[ip];
  3523. hhave = 1;
  3524. }
  3525. }
  3526. /* this measurement is lower than our desired x */
  3527. if (dx >= 0) {
  3528. if (!lhave || dx < (x - lx)) {
  3529. /* new best lower x measurement */
  3530. lx = px[ip];
  3531. ly = py[ip];
  3532. lhave = 1;
  3533. }
  3534. }
  3535. }
  3536. /* the low x is good */
  3537. if (lhave) {
  3538. /* so is the high x */
  3539. if (hhave) {
  3540. /* they're the same, so just pick one */
  3541. if (hx == lx)
  3542. y = ly;
  3543. else /* interpolate */
  3544. y = interpolate(x, lx, hx, ly, hy);
  3545. } else /* only low is good, use it */
  3546. y = ly;
  3547. } else if (hhave) /* only high is good, use it */
  3548. y = hy;
  3549. else /* nothing is good,this should never happen unless np=0, ???? */
  3550. y = -(1 << 30);
  3551. return y;
  3552. }
  3553. static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
  3554. u16 rateIndex, u16 freq, bool is2GHz)
  3555. {
  3556. u16 numPiers, i;
  3557. s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
  3558. s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
  3559. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3560. struct cal_tgt_pow_legacy *pEepromTargetPwr;
  3561. u8 *pFreqBin;
  3562. if (is2GHz) {
  3563. numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
  3564. pEepromTargetPwr = eep->calTargetPower2G;
  3565. pFreqBin = eep->calTarget_freqbin_2G;
  3566. } else {
  3567. numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
  3568. pEepromTargetPwr = eep->calTargetPower5G;
  3569. pFreqBin = eep->calTarget_freqbin_5G;
  3570. }
  3571. /*
  3572. * create array of channels and targetpower from
  3573. * targetpower piers stored on eeprom
  3574. */
  3575. for (i = 0; i < numPiers; i++) {
  3576. freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
  3577. targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
  3578. }
  3579. /* interpolate to get target power for given frequency */
  3580. return (u8) ar9003_hw_power_interpolate((s32) freq,
  3581. freqArray,
  3582. targetPowerArray, numPiers);
  3583. }
  3584. static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
  3585. u16 rateIndex,
  3586. u16 freq, bool is2GHz)
  3587. {
  3588. u16 numPiers, i;
  3589. s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
  3590. s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
  3591. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3592. struct cal_tgt_pow_ht *pEepromTargetPwr;
  3593. u8 *pFreqBin;
  3594. if (is2GHz) {
  3595. numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
  3596. pEepromTargetPwr = eep->calTargetPower2GHT20;
  3597. pFreqBin = eep->calTarget_freqbin_2GHT20;
  3598. } else {
  3599. numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
  3600. pEepromTargetPwr = eep->calTargetPower5GHT20;
  3601. pFreqBin = eep->calTarget_freqbin_5GHT20;
  3602. }
  3603. /*
  3604. * create array of channels and targetpower
  3605. * from targetpower piers stored on eeprom
  3606. */
  3607. for (i = 0; i < numPiers; i++) {
  3608. freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
  3609. targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
  3610. }
  3611. /* interpolate to get target power for given frequency */
  3612. return (u8) ar9003_hw_power_interpolate((s32) freq,
  3613. freqArray,
  3614. targetPowerArray, numPiers);
  3615. }
  3616. static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
  3617. u16 rateIndex,
  3618. u16 freq, bool is2GHz)
  3619. {
  3620. u16 numPiers, i;
  3621. s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
  3622. s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
  3623. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3624. struct cal_tgt_pow_ht *pEepromTargetPwr;
  3625. u8 *pFreqBin;
  3626. if (is2GHz) {
  3627. numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
  3628. pEepromTargetPwr = eep->calTargetPower2GHT40;
  3629. pFreqBin = eep->calTarget_freqbin_2GHT40;
  3630. } else {
  3631. numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
  3632. pEepromTargetPwr = eep->calTargetPower5GHT40;
  3633. pFreqBin = eep->calTarget_freqbin_5GHT40;
  3634. }
  3635. /*
  3636. * create array of channels and targetpower from
  3637. * targetpower piers stored on eeprom
  3638. */
  3639. for (i = 0; i < numPiers; i++) {
  3640. freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
  3641. targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
  3642. }
  3643. /* interpolate to get target power for given frequency */
  3644. return (u8) ar9003_hw_power_interpolate((s32) freq,
  3645. freqArray,
  3646. targetPowerArray, numPiers);
  3647. }
  3648. static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
  3649. u16 rateIndex, u16 freq)
  3650. {
  3651. u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
  3652. s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
  3653. s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
  3654. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3655. struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
  3656. u8 *pFreqBin = eep->calTarget_freqbin_Cck;
  3657. /*
  3658. * create array of channels and targetpower from
  3659. * targetpower piers stored on eeprom
  3660. */
  3661. for (i = 0; i < numPiers; i++) {
  3662. freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
  3663. targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
  3664. }
  3665. /* interpolate to get target power for given frequency */
  3666. return (u8) ar9003_hw_power_interpolate((s32) freq,
  3667. freqArray,
  3668. targetPowerArray, numPiers);
  3669. }
  3670. /* Set tx power registers to array of values passed in */
  3671. static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
  3672. {
  3673. #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
  3674. /* make sure forced gain is not set */
  3675. REG_WRITE(ah, 0xa458, 0);
  3676. /* Write the OFDM power per rate set */
  3677. /* 6 (LSB), 9, 12, 18 (MSB) */
  3678. REG_WRITE(ah, 0xa3c0,
  3679. POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
  3680. POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
  3681. POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
  3682. POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
  3683. /* 24 (LSB), 36, 48, 54 (MSB) */
  3684. REG_WRITE(ah, 0xa3c4,
  3685. POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
  3686. POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
  3687. POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
  3688. POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
  3689. /* Write the CCK power per rate set */
  3690. /* 1L (LSB), reserved, 2L, 2S (MSB) */
  3691. REG_WRITE(ah, 0xa3c8,
  3692. POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
  3693. POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
  3694. /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
  3695. POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
  3696. /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
  3697. REG_WRITE(ah, 0xa3cc,
  3698. POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
  3699. POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
  3700. POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
  3701. POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
  3702. );
  3703. /* Write the HT20 power per rate set */
  3704. /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
  3705. REG_WRITE(ah, 0xa3d0,
  3706. POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
  3707. POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
  3708. POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
  3709. POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
  3710. );
  3711. /* 6 (LSB), 7, 12, 13 (MSB) */
  3712. REG_WRITE(ah, 0xa3d4,
  3713. POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
  3714. POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
  3715. POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
  3716. POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
  3717. );
  3718. /* 14 (LSB), 15, 20, 21 */
  3719. REG_WRITE(ah, 0xa3e4,
  3720. POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
  3721. POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
  3722. POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
  3723. POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
  3724. );
  3725. /* Mixed HT20 and HT40 rates */
  3726. /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
  3727. REG_WRITE(ah, 0xa3e8,
  3728. POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
  3729. POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
  3730. POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
  3731. POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
  3732. );
  3733. /*
  3734. * Write the HT40 power per rate set
  3735. * correct PAR difference between HT40 and HT20/LEGACY
  3736. * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
  3737. */
  3738. REG_WRITE(ah, 0xa3d8,
  3739. POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
  3740. POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
  3741. POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
  3742. POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
  3743. );
  3744. /* 6 (LSB), 7, 12, 13 (MSB) */
  3745. REG_WRITE(ah, 0xa3dc,
  3746. POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
  3747. POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
  3748. POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
  3749. POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
  3750. );
  3751. /* 14 (LSB), 15, 20, 21 */
  3752. REG_WRITE(ah, 0xa3ec,
  3753. POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
  3754. POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
  3755. POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
  3756. POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
  3757. );
  3758. return 0;
  3759. #undef POW_SM
  3760. }
  3761. static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
  3762. u8 *targetPowerValT2)
  3763. {
  3764. /* XXX: hard code for now, need to get from eeprom struct */
  3765. u8 ht40PowerIncForPdadc = 0;
  3766. bool is2GHz = false;
  3767. unsigned int i = 0;
  3768. struct ath_common *common = ath9k_hw_common(ah);
  3769. if (freq < 4000)
  3770. is2GHz = true;
  3771. targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
  3772. ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
  3773. is2GHz);
  3774. targetPowerValT2[ALL_TARGET_LEGACY_36] =
  3775. ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
  3776. is2GHz);
  3777. targetPowerValT2[ALL_TARGET_LEGACY_48] =
  3778. ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
  3779. is2GHz);
  3780. targetPowerValT2[ALL_TARGET_LEGACY_54] =
  3781. ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
  3782. is2GHz);
  3783. targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
  3784. ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
  3785. freq);
  3786. targetPowerValT2[ALL_TARGET_LEGACY_5S] =
  3787. ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
  3788. targetPowerValT2[ALL_TARGET_LEGACY_11L] =
  3789. ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
  3790. targetPowerValT2[ALL_TARGET_LEGACY_11S] =
  3791. ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
  3792. targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
  3793. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
  3794. is2GHz);
  3795. targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
  3796. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
  3797. freq, is2GHz);
  3798. targetPowerValT2[ALL_TARGET_HT20_4] =
  3799. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
  3800. is2GHz);
  3801. targetPowerValT2[ALL_TARGET_HT20_5] =
  3802. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
  3803. is2GHz);
  3804. targetPowerValT2[ALL_TARGET_HT20_6] =
  3805. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
  3806. is2GHz);
  3807. targetPowerValT2[ALL_TARGET_HT20_7] =
  3808. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
  3809. is2GHz);
  3810. targetPowerValT2[ALL_TARGET_HT20_12] =
  3811. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
  3812. is2GHz);
  3813. targetPowerValT2[ALL_TARGET_HT20_13] =
  3814. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
  3815. is2GHz);
  3816. targetPowerValT2[ALL_TARGET_HT20_14] =
  3817. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
  3818. is2GHz);
  3819. targetPowerValT2[ALL_TARGET_HT20_15] =
  3820. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
  3821. is2GHz);
  3822. targetPowerValT2[ALL_TARGET_HT20_20] =
  3823. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
  3824. is2GHz);
  3825. targetPowerValT2[ALL_TARGET_HT20_21] =
  3826. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
  3827. is2GHz);
  3828. targetPowerValT2[ALL_TARGET_HT20_22] =
  3829. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
  3830. is2GHz);
  3831. targetPowerValT2[ALL_TARGET_HT20_23] =
  3832. ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
  3833. is2GHz);
  3834. targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
  3835. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
  3836. is2GHz) + ht40PowerIncForPdadc;
  3837. targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
  3838. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
  3839. freq,
  3840. is2GHz) + ht40PowerIncForPdadc;
  3841. targetPowerValT2[ALL_TARGET_HT40_4] =
  3842. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
  3843. is2GHz) + ht40PowerIncForPdadc;
  3844. targetPowerValT2[ALL_TARGET_HT40_5] =
  3845. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
  3846. is2GHz) + ht40PowerIncForPdadc;
  3847. targetPowerValT2[ALL_TARGET_HT40_6] =
  3848. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
  3849. is2GHz) + ht40PowerIncForPdadc;
  3850. targetPowerValT2[ALL_TARGET_HT40_7] =
  3851. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
  3852. is2GHz) + ht40PowerIncForPdadc;
  3853. targetPowerValT2[ALL_TARGET_HT40_12] =
  3854. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
  3855. is2GHz) + ht40PowerIncForPdadc;
  3856. targetPowerValT2[ALL_TARGET_HT40_13] =
  3857. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
  3858. is2GHz) + ht40PowerIncForPdadc;
  3859. targetPowerValT2[ALL_TARGET_HT40_14] =
  3860. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
  3861. is2GHz) + ht40PowerIncForPdadc;
  3862. targetPowerValT2[ALL_TARGET_HT40_15] =
  3863. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
  3864. is2GHz) + ht40PowerIncForPdadc;
  3865. targetPowerValT2[ALL_TARGET_HT40_20] =
  3866. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
  3867. is2GHz) + ht40PowerIncForPdadc;
  3868. targetPowerValT2[ALL_TARGET_HT40_21] =
  3869. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
  3870. is2GHz) + ht40PowerIncForPdadc;
  3871. targetPowerValT2[ALL_TARGET_HT40_22] =
  3872. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
  3873. is2GHz) + ht40PowerIncForPdadc;
  3874. targetPowerValT2[ALL_TARGET_HT40_23] =
  3875. ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
  3876. is2GHz) + ht40PowerIncForPdadc;
  3877. for (i = 0; i < ar9300RateSize; i++) {
  3878. ath_dbg(common, ATH_DBG_EEPROM,
  3879. "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
  3880. }
  3881. }
  3882. static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
  3883. int mode,
  3884. int ipier,
  3885. int ichain,
  3886. int *pfrequency,
  3887. int *pcorrection,
  3888. int *ptemperature, int *pvoltage)
  3889. {
  3890. u8 *pCalPier;
  3891. struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
  3892. int is2GHz;
  3893. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3894. struct ath_common *common = ath9k_hw_common(ah);
  3895. if (ichain >= AR9300_MAX_CHAINS) {
  3896. ath_dbg(common, ATH_DBG_EEPROM,
  3897. "Invalid chain index, must be less than %d\n",
  3898. AR9300_MAX_CHAINS);
  3899. return -1;
  3900. }
  3901. if (mode) { /* 5GHz */
  3902. if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
  3903. ath_dbg(common, ATH_DBG_EEPROM,
  3904. "Invalid 5GHz cal pier index, must be less than %d\n",
  3905. AR9300_NUM_5G_CAL_PIERS);
  3906. return -1;
  3907. }
  3908. pCalPier = &(eep->calFreqPier5G[ipier]);
  3909. pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
  3910. is2GHz = 0;
  3911. } else {
  3912. if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
  3913. ath_dbg(common, ATH_DBG_EEPROM,
  3914. "Invalid 2GHz cal pier index, must be less than %d\n",
  3915. AR9300_NUM_2G_CAL_PIERS);
  3916. return -1;
  3917. }
  3918. pCalPier = &(eep->calFreqPier2G[ipier]);
  3919. pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
  3920. is2GHz = 1;
  3921. }
  3922. *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
  3923. *pcorrection = pCalPierStruct->refPower;
  3924. *ptemperature = pCalPierStruct->tempMeas;
  3925. *pvoltage = pCalPierStruct->voltMeas;
  3926. return 0;
  3927. }
  3928. static int ar9003_hw_power_control_override(struct ath_hw *ah,
  3929. int frequency,
  3930. int *correction,
  3931. int *voltage, int *temperature)
  3932. {
  3933. int tempSlope = 0;
  3934. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  3935. int f[3], t[3];
  3936. REG_RMW(ah, AR_PHY_TPC_11_B0,
  3937. (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
  3938. AR_PHY_TPC_OLPC_GAIN_DELTA);
  3939. if (ah->caps.tx_chainmask & BIT(1))
  3940. REG_RMW(ah, AR_PHY_TPC_11_B1,
  3941. (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
  3942. AR_PHY_TPC_OLPC_GAIN_DELTA);
  3943. if (ah->caps.tx_chainmask & BIT(2))
  3944. REG_RMW(ah, AR_PHY_TPC_11_B2,
  3945. (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
  3946. AR_PHY_TPC_OLPC_GAIN_DELTA);
  3947. /* enable open loop power control on chip */
  3948. REG_RMW(ah, AR_PHY_TPC_6_B0,
  3949. (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
  3950. AR_PHY_TPC_6_ERROR_EST_MODE);
  3951. if (ah->caps.tx_chainmask & BIT(1))
  3952. REG_RMW(ah, AR_PHY_TPC_6_B1,
  3953. (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
  3954. AR_PHY_TPC_6_ERROR_EST_MODE);
  3955. if (ah->caps.tx_chainmask & BIT(2))
  3956. REG_RMW(ah, AR_PHY_TPC_6_B2,
  3957. (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
  3958. AR_PHY_TPC_6_ERROR_EST_MODE);
  3959. /*
  3960. * enable temperature compensation
  3961. * Need to use register names
  3962. */
  3963. if (frequency < 4000)
  3964. tempSlope = eep->modalHeader2G.tempSlope;
  3965. else if (eep->base_ext2.tempSlopeLow != 0) {
  3966. t[0] = eep->base_ext2.tempSlopeLow;
  3967. f[0] = 5180;
  3968. t[1] = eep->modalHeader5G.tempSlope;
  3969. f[1] = 5500;
  3970. t[2] = eep->base_ext2.tempSlopeHigh;
  3971. f[2] = 5785;
  3972. tempSlope = ar9003_hw_power_interpolate((s32) frequency,
  3973. f, t, 3);
  3974. } else
  3975. tempSlope = eep->modalHeader5G.tempSlope;
  3976. REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
  3977. REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
  3978. temperature[0]);
  3979. return 0;
  3980. }
  3981. /* Apply the recorded correction values. */
  3982. static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
  3983. {
  3984. int ichain, ipier, npier;
  3985. int mode;
  3986. int lfrequency[AR9300_MAX_CHAINS],
  3987. lcorrection[AR9300_MAX_CHAINS],
  3988. ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
  3989. int hfrequency[AR9300_MAX_CHAINS],
  3990. hcorrection[AR9300_MAX_CHAINS],
  3991. htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
  3992. int fdiff;
  3993. int correction[AR9300_MAX_CHAINS],
  3994. voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
  3995. int pfrequency, pcorrection, ptemperature, pvoltage;
  3996. struct ath_common *common = ath9k_hw_common(ah);
  3997. mode = (frequency >= 4000);
  3998. if (mode)
  3999. npier = AR9300_NUM_5G_CAL_PIERS;
  4000. else
  4001. npier = AR9300_NUM_2G_CAL_PIERS;
  4002. for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
  4003. lfrequency[ichain] = 0;
  4004. hfrequency[ichain] = 100000;
  4005. }
  4006. /* identify best lower and higher frequency calibration measurement */
  4007. for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
  4008. for (ipier = 0; ipier < npier; ipier++) {
  4009. if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
  4010. &pfrequency, &pcorrection,
  4011. &ptemperature, &pvoltage)) {
  4012. fdiff = frequency - pfrequency;
  4013. /*
  4014. * this measurement is higher than
  4015. * our desired frequency
  4016. */
  4017. if (fdiff <= 0) {
  4018. if (hfrequency[ichain] <= 0 ||
  4019. hfrequency[ichain] >= 100000 ||
  4020. fdiff >
  4021. (frequency - hfrequency[ichain])) {
  4022. /*
  4023. * new best higher
  4024. * frequency measurement
  4025. */
  4026. hfrequency[ichain] = pfrequency;
  4027. hcorrection[ichain] =
  4028. pcorrection;
  4029. htemperature[ichain] =
  4030. ptemperature;
  4031. hvoltage[ichain] = pvoltage;
  4032. }
  4033. }
  4034. if (fdiff >= 0) {
  4035. if (lfrequency[ichain] <= 0
  4036. || fdiff <
  4037. (frequency - lfrequency[ichain])) {
  4038. /*
  4039. * new best lower
  4040. * frequency measurement
  4041. */
  4042. lfrequency[ichain] = pfrequency;
  4043. lcorrection[ichain] =
  4044. pcorrection;
  4045. ltemperature[ichain] =
  4046. ptemperature;
  4047. lvoltage[ichain] = pvoltage;
  4048. }
  4049. }
  4050. }
  4051. }
  4052. }
  4053. /* interpolate */
  4054. for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
  4055. ath_dbg(common, ATH_DBG_EEPROM,
  4056. "ch=%d f=%d low=%d %d h=%d %d\n",
  4057. ichain, frequency, lfrequency[ichain],
  4058. lcorrection[ichain], hfrequency[ichain],
  4059. hcorrection[ichain]);
  4060. /* they're the same, so just pick one */
  4061. if (hfrequency[ichain] == lfrequency[ichain]) {
  4062. correction[ichain] = lcorrection[ichain];
  4063. voltage[ichain] = lvoltage[ichain];
  4064. temperature[ichain] = ltemperature[ichain];
  4065. }
  4066. /* the low frequency is good */
  4067. else if (frequency - lfrequency[ichain] < 1000) {
  4068. /* so is the high frequency, interpolate */
  4069. if (hfrequency[ichain] - frequency < 1000) {
  4070. correction[ichain] = interpolate(frequency,
  4071. lfrequency[ichain],
  4072. hfrequency[ichain],
  4073. lcorrection[ichain],
  4074. hcorrection[ichain]);
  4075. temperature[ichain] = interpolate(frequency,
  4076. lfrequency[ichain],
  4077. hfrequency[ichain],
  4078. ltemperature[ichain],
  4079. htemperature[ichain]);
  4080. voltage[ichain] = interpolate(frequency,
  4081. lfrequency[ichain],
  4082. hfrequency[ichain],
  4083. lvoltage[ichain],
  4084. hvoltage[ichain]);
  4085. }
  4086. /* only low is good, use it */
  4087. else {
  4088. correction[ichain] = lcorrection[ichain];
  4089. temperature[ichain] = ltemperature[ichain];
  4090. voltage[ichain] = lvoltage[ichain];
  4091. }
  4092. }
  4093. /* only high is good, use it */
  4094. else if (hfrequency[ichain] - frequency < 1000) {
  4095. correction[ichain] = hcorrection[ichain];
  4096. temperature[ichain] = htemperature[ichain];
  4097. voltage[ichain] = hvoltage[ichain];
  4098. } else { /* nothing is good, presume 0???? */
  4099. correction[ichain] = 0;
  4100. temperature[ichain] = 0;
  4101. voltage[ichain] = 0;
  4102. }
  4103. }
  4104. ar9003_hw_power_control_override(ah, frequency, correction, voltage,
  4105. temperature);
  4106. ath_dbg(common, ATH_DBG_EEPROM,
  4107. "for frequency=%d, calibration correction = %d %d %d\n",
  4108. frequency, correction[0], correction[1], correction[2]);
  4109. return 0;
  4110. }
  4111. static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
  4112. int idx,
  4113. int edge,
  4114. bool is2GHz)
  4115. {
  4116. struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
  4117. struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
  4118. if (is2GHz)
  4119. return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
  4120. else
  4121. return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
  4122. }
  4123. static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
  4124. int idx,
  4125. unsigned int edge,
  4126. u16 freq,
  4127. bool is2GHz)
  4128. {
  4129. struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
  4130. struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
  4131. u8 *ctl_freqbin = is2GHz ?
  4132. &eep->ctl_freqbin_2G[idx][0] :
  4133. &eep->ctl_freqbin_5G[idx][0];
  4134. if (is2GHz) {
  4135. if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
  4136. CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
  4137. return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
  4138. } else {
  4139. if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
  4140. CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
  4141. return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
  4142. }
  4143. return AR9300_MAX_RATE_POWER;
  4144. }
  4145. /*
  4146. * Find the maximum conformance test limit for the given channel and CTL info
  4147. */
  4148. static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
  4149. u16 freq, int idx, bool is2GHz)
  4150. {
  4151. u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
  4152. u8 *ctl_freqbin = is2GHz ?
  4153. &eep->ctl_freqbin_2G[idx][0] :
  4154. &eep->ctl_freqbin_5G[idx][0];
  4155. u16 num_edges = is2GHz ?
  4156. AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
  4157. unsigned int edge;
  4158. /* Get the edge power */
  4159. for (edge = 0;
  4160. (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED);
  4161. edge++) {
  4162. /*
  4163. * If there's an exact channel match or an inband flag set
  4164. * on the lower channel use the given rdEdgePower
  4165. */
  4166. if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
  4167. twiceMaxEdgePower =
  4168. ar9003_hw_get_direct_edge_power(eep, idx,
  4169. edge, is2GHz);
  4170. break;
  4171. } else if ((edge > 0) &&
  4172. (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
  4173. is2GHz))) {
  4174. twiceMaxEdgePower =
  4175. ar9003_hw_get_indirect_edge_power(eep, idx,
  4176. edge, freq,
  4177. is2GHz);
  4178. /*
  4179. * Leave loop - no more affecting edges possible in
  4180. * this monotonic increasing list
  4181. */
  4182. break;
  4183. }
  4184. }
  4185. return twiceMaxEdgePower;
  4186. }
  4187. static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
  4188. struct ath9k_channel *chan,
  4189. u8 *pPwrArray, u16 cfgCtl,
  4190. u8 twiceAntennaReduction,
  4191. u8 twiceMaxRegulatoryPower,
  4192. u16 powerLimit)
  4193. {
  4194. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  4195. struct ath_common *common = ath9k_hw_common(ah);
  4196. struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
  4197. u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
  4198. static const u16 tpScaleReductionTable[5] = {
  4199. 0, 3, 6, 9, AR9300_MAX_RATE_POWER
  4200. };
  4201. int i;
  4202. int16_t twiceLargestAntenna;
  4203. u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
  4204. static const u16 ctlModesFor11a[] = {
  4205. CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
  4206. };
  4207. static const u16 ctlModesFor11g[] = {
  4208. CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
  4209. CTL_11G_EXT, CTL_2GHT40
  4210. };
  4211. u16 numCtlModes;
  4212. const u16 *pCtlMode;
  4213. u16 ctlMode, freq;
  4214. struct chan_centers centers;
  4215. u8 *ctlIndex;
  4216. u8 ctlNum;
  4217. u16 twiceMinEdgePower;
  4218. bool is2ghz = IS_CHAN_2GHZ(chan);
  4219. ath9k_hw_get_channel_centers(ah, chan, &centers);
  4220. /* Compute TxPower reduction due to Antenna Gain */
  4221. if (is2ghz)
  4222. twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
  4223. else
  4224. twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
  4225. twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
  4226. twiceLargestAntenna, 0);
  4227. /*
  4228. * scaledPower is the minimum of the user input power level
  4229. * and the regulatory allowed power level
  4230. */
  4231. maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
  4232. if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
  4233. maxRegAllowedPower -=
  4234. (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
  4235. }
  4236. scaledPower = min(powerLimit, maxRegAllowedPower);
  4237. /*
  4238. * Reduce scaled Power by number of chains active to get
  4239. * to per chain tx power level
  4240. */
  4241. switch (ar5416_get_ntxchains(ah->txchainmask)) {
  4242. case 1:
  4243. break;
  4244. case 2:
  4245. scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
  4246. break;
  4247. case 3:
  4248. scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
  4249. break;
  4250. }
  4251. scaledPower = max((u16)0, scaledPower);
  4252. /*
  4253. * Get target powers from EEPROM - our baseline for TX Power
  4254. */
  4255. if (is2ghz) {
  4256. /* Setup for CTL modes */
  4257. /* CTL_11B, CTL_11G, CTL_2GHT20 */
  4258. numCtlModes =
  4259. ARRAY_SIZE(ctlModesFor11g) -
  4260. SUB_NUM_CTL_MODES_AT_2G_40;
  4261. pCtlMode = ctlModesFor11g;
  4262. if (IS_CHAN_HT40(chan))
  4263. /* All 2G CTL's */
  4264. numCtlModes = ARRAY_SIZE(ctlModesFor11g);
  4265. } else {
  4266. /* Setup for CTL modes */
  4267. /* CTL_11A, CTL_5GHT20 */
  4268. numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
  4269. SUB_NUM_CTL_MODES_AT_5G_40;
  4270. pCtlMode = ctlModesFor11a;
  4271. if (IS_CHAN_HT40(chan))
  4272. /* All 5G CTL's */
  4273. numCtlModes = ARRAY_SIZE(ctlModesFor11a);
  4274. }
  4275. /*
  4276. * For MIMO, need to apply regulatory caps individually across
  4277. * dynamically running modes: CCK, OFDM, HT20, HT40
  4278. *
  4279. * The outer loop walks through each possible applicable runtime mode.
  4280. * The inner loop walks through each ctlIndex entry in EEPROM.
  4281. * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
  4282. */
  4283. for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
  4284. bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
  4285. (pCtlMode[ctlMode] == CTL_2GHT40);
  4286. if (isHt40CtlMode)
  4287. freq = centers.synth_center;
  4288. else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
  4289. freq = centers.ext_center;
  4290. else
  4291. freq = centers.ctl_center;
  4292. ath_dbg(common, ATH_DBG_REGULATORY,
  4293. "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
  4294. ctlMode, numCtlModes, isHt40CtlMode,
  4295. (pCtlMode[ctlMode] & EXT_ADDITIVE));
  4296. /* walk through each CTL index stored in EEPROM */
  4297. if (is2ghz) {
  4298. ctlIndex = pEepData->ctlIndex_2G;
  4299. ctlNum = AR9300_NUM_CTLS_2G;
  4300. } else {
  4301. ctlIndex = pEepData->ctlIndex_5G;
  4302. ctlNum = AR9300_NUM_CTLS_5G;
  4303. }
  4304. for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
  4305. ath_dbg(common, ATH_DBG_REGULATORY,
  4306. "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
  4307. i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
  4308. chan->channel);
  4309. /*
  4310. * compare test group from regulatory
  4311. * channel list with test mode from pCtlMode
  4312. * list
  4313. */
  4314. if ((((cfgCtl & ~CTL_MODE_M) |
  4315. (pCtlMode[ctlMode] & CTL_MODE_M)) ==
  4316. ctlIndex[i]) ||
  4317. (((cfgCtl & ~CTL_MODE_M) |
  4318. (pCtlMode[ctlMode] & CTL_MODE_M)) ==
  4319. ((ctlIndex[i] & CTL_MODE_M) |
  4320. SD_NO_CTL))) {
  4321. twiceMinEdgePower =
  4322. ar9003_hw_get_max_edge_power(pEepData,
  4323. freq, i,
  4324. is2ghz);
  4325. if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
  4326. /*
  4327. * Find the minimum of all CTL
  4328. * edge powers that apply to
  4329. * this channel
  4330. */
  4331. twiceMaxEdgePower =
  4332. min(twiceMaxEdgePower,
  4333. twiceMinEdgePower);
  4334. else {
  4335. /* specific */
  4336. twiceMaxEdgePower =
  4337. twiceMinEdgePower;
  4338. break;
  4339. }
  4340. }
  4341. }
  4342. minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
  4343. ath_dbg(common, ATH_DBG_REGULATORY,
  4344. "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
  4345. ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
  4346. scaledPower, minCtlPower);
  4347. /* Apply ctl mode to correct target power set */
  4348. switch (pCtlMode[ctlMode]) {
  4349. case CTL_11B:
  4350. for (i = ALL_TARGET_LEGACY_1L_5L;
  4351. i <= ALL_TARGET_LEGACY_11S; i++)
  4352. pPwrArray[i] =
  4353. (u8)min((u16)pPwrArray[i],
  4354. minCtlPower);
  4355. break;
  4356. case CTL_11A:
  4357. case CTL_11G:
  4358. for (i = ALL_TARGET_LEGACY_6_24;
  4359. i <= ALL_TARGET_LEGACY_54; i++)
  4360. pPwrArray[i] =
  4361. (u8)min((u16)pPwrArray[i],
  4362. minCtlPower);
  4363. break;
  4364. case CTL_5GHT20:
  4365. case CTL_2GHT20:
  4366. for (i = ALL_TARGET_HT20_0_8_16;
  4367. i <= ALL_TARGET_HT20_21; i++)
  4368. pPwrArray[i] =
  4369. (u8)min((u16)pPwrArray[i],
  4370. minCtlPower);
  4371. pPwrArray[ALL_TARGET_HT20_22] =
  4372. (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
  4373. minCtlPower);
  4374. pPwrArray[ALL_TARGET_HT20_23] =
  4375. (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
  4376. minCtlPower);
  4377. break;
  4378. case CTL_5GHT40:
  4379. case CTL_2GHT40:
  4380. for (i = ALL_TARGET_HT40_0_8_16;
  4381. i <= ALL_TARGET_HT40_23; i++)
  4382. pPwrArray[i] =
  4383. (u8)min((u16)pPwrArray[i],
  4384. minCtlPower);
  4385. break;
  4386. default:
  4387. break;
  4388. }
  4389. } /* end ctl mode checking */
  4390. }
  4391. static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
  4392. struct ath9k_channel *chan, u16 cfgCtl,
  4393. u8 twiceAntennaReduction,
  4394. u8 twiceMaxRegulatoryPower,
  4395. u8 powerLimit, bool test)
  4396. {
  4397. struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
  4398. struct ath_common *common = ath9k_hw_common(ah);
  4399. u8 targetPowerValT2[ar9300RateSize];
  4400. unsigned int i = 0;
  4401. ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
  4402. ar9003_hw_set_power_per_rate_table(ah, chan,
  4403. targetPowerValT2, cfgCtl,
  4404. twiceAntennaReduction,
  4405. twiceMaxRegulatoryPower,
  4406. powerLimit);
  4407. regulatory->max_power_level = 0;
  4408. for (i = 0; i < ar9300RateSize; i++) {
  4409. if (targetPowerValT2[i] > regulatory->max_power_level)
  4410. regulatory->max_power_level = targetPowerValT2[i];
  4411. }
  4412. if (test)
  4413. return;
  4414. for (i = 0; i < ar9300RateSize; i++) {
  4415. ath_dbg(common, ATH_DBG_EEPROM,
  4416. "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
  4417. }
  4418. /*
  4419. * This is the TX power we send back to driver core,
  4420. * and it can use to pass to userspace to display our
  4421. * currently configured TX power setting.
  4422. *
  4423. * Since power is rate dependent, use one of the indices
  4424. * from the AR9300_Rates enum to select an entry from
  4425. * targetPowerValT2[] to report. Currently returns the
  4426. * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
  4427. * as CCK power is less interesting (?).
  4428. */
  4429. i = ALL_TARGET_LEGACY_6_24; /* legacy */
  4430. if (IS_CHAN_HT40(chan))
  4431. i = ALL_TARGET_HT40_0_8_16; /* ht40 */
  4432. else if (IS_CHAN_HT20(chan))
  4433. i = ALL_TARGET_HT20_0_8_16; /* ht20 */
  4434. ah->txpower_limit = targetPowerValT2[i];
  4435. regulatory->max_power_level = targetPowerValT2[i];
  4436. /* Write target power array to registers */
  4437. ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
  4438. ar9003_hw_calibration_apply(ah, chan->channel);
  4439. }
  4440. static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
  4441. u16 i, bool is2GHz)
  4442. {
  4443. return AR_NO_SPUR;
  4444. }
  4445. s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
  4446. {
  4447. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  4448. return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
  4449. }
  4450. s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
  4451. {
  4452. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  4453. return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
  4454. }
  4455. u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
  4456. {
  4457. struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
  4458. if (is_2ghz)
  4459. return eep->modalHeader2G.spurChans;
  4460. else
  4461. return eep->modalHeader5G.spurChans;
  4462. }
  4463. const struct eeprom_ops eep_ar9300_ops = {
  4464. .check_eeprom = ath9k_hw_ar9300_check_eeprom,
  4465. .get_eeprom = ath9k_hw_ar9300_get_eeprom,
  4466. .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
  4467. .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
  4468. .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
  4469. .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
  4470. .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
  4471. .set_board_values = ath9k_hw_ar9300_set_board_values,
  4472. .set_addac = ath9k_hw_ar9300_set_addac,
  4473. .set_txpower = ath9k_hw_ar9300_set_txpower,
  4474. .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
  4475. };