resource_tracker.c 89 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/slab.h>
  41. #include <linux/mlx4/cmd.h>
  42. #include <linux/mlx4/qp.h>
  43. #include <linux/if_ether.h>
  44. #include <linux/etherdevice.h>
  45. #include "mlx4.h"
  46. #include "fw.h"
  47. #define MLX4_MAC_VALID (1ull << 63)
  48. struct mac_res {
  49. struct list_head list;
  50. u64 mac;
  51. u8 port;
  52. };
  53. struct res_common {
  54. struct list_head list;
  55. struct rb_node node;
  56. u64 res_id;
  57. int owner;
  58. int state;
  59. int from_state;
  60. int to_state;
  61. int removing;
  62. };
  63. enum {
  64. RES_ANY_BUSY = 1
  65. };
  66. struct res_gid {
  67. struct list_head list;
  68. u8 gid[16];
  69. enum mlx4_protocol prot;
  70. enum mlx4_steer_type steer;
  71. u64 reg_id;
  72. };
  73. enum res_qp_states {
  74. RES_QP_BUSY = RES_ANY_BUSY,
  75. /* QP number was allocated */
  76. RES_QP_RESERVED,
  77. /* ICM memory for QP context was mapped */
  78. RES_QP_MAPPED,
  79. /* QP is in hw ownership */
  80. RES_QP_HW
  81. };
  82. struct res_qp {
  83. struct res_common com;
  84. struct res_mtt *mtt;
  85. struct res_cq *rcq;
  86. struct res_cq *scq;
  87. struct res_srq *srq;
  88. struct list_head mcg_list;
  89. spinlock_t mcg_spl;
  90. int local_qpn;
  91. atomic_t ref_count;
  92. };
  93. enum res_mtt_states {
  94. RES_MTT_BUSY = RES_ANY_BUSY,
  95. RES_MTT_ALLOCATED,
  96. };
  97. static inline const char *mtt_states_str(enum res_mtt_states state)
  98. {
  99. switch (state) {
  100. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  101. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  102. default: return "Unknown";
  103. }
  104. }
  105. struct res_mtt {
  106. struct res_common com;
  107. int order;
  108. atomic_t ref_count;
  109. };
  110. enum res_mpt_states {
  111. RES_MPT_BUSY = RES_ANY_BUSY,
  112. RES_MPT_RESERVED,
  113. RES_MPT_MAPPED,
  114. RES_MPT_HW,
  115. };
  116. struct res_mpt {
  117. struct res_common com;
  118. struct res_mtt *mtt;
  119. int key;
  120. };
  121. enum res_eq_states {
  122. RES_EQ_BUSY = RES_ANY_BUSY,
  123. RES_EQ_RESERVED,
  124. RES_EQ_HW,
  125. };
  126. struct res_eq {
  127. struct res_common com;
  128. struct res_mtt *mtt;
  129. };
  130. enum res_cq_states {
  131. RES_CQ_BUSY = RES_ANY_BUSY,
  132. RES_CQ_ALLOCATED,
  133. RES_CQ_HW,
  134. };
  135. struct res_cq {
  136. struct res_common com;
  137. struct res_mtt *mtt;
  138. atomic_t ref_count;
  139. };
  140. enum res_srq_states {
  141. RES_SRQ_BUSY = RES_ANY_BUSY,
  142. RES_SRQ_ALLOCATED,
  143. RES_SRQ_HW,
  144. };
  145. struct res_srq {
  146. struct res_common com;
  147. struct res_mtt *mtt;
  148. struct res_cq *cq;
  149. atomic_t ref_count;
  150. };
  151. enum res_counter_states {
  152. RES_COUNTER_BUSY = RES_ANY_BUSY,
  153. RES_COUNTER_ALLOCATED,
  154. };
  155. struct res_counter {
  156. struct res_common com;
  157. int port;
  158. };
  159. enum res_xrcdn_states {
  160. RES_XRCD_BUSY = RES_ANY_BUSY,
  161. RES_XRCD_ALLOCATED,
  162. };
  163. struct res_xrcdn {
  164. struct res_common com;
  165. int port;
  166. };
  167. enum res_fs_rule_states {
  168. RES_FS_RULE_BUSY = RES_ANY_BUSY,
  169. RES_FS_RULE_ALLOCATED,
  170. };
  171. struct res_fs_rule {
  172. struct res_common com;
  173. int qpn;
  174. };
  175. static void *res_tracker_lookup(struct rb_root *root, u64 res_id)
  176. {
  177. struct rb_node *node = root->rb_node;
  178. while (node) {
  179. struct res_common *res = container_of(node, struct res_common,
  180. node);
  181. if (res_id < res->res_id)
  182. node = node->rb_left;
  183. else if (res_id > res->res_id)
  184. node = node->rb_right;
  185. else
  186. return res;
  187. }
  188. return NULL;
  189. }
  190. static int res_tracker_insert(struct rb_root *root, struct res_common *res)
  191. {
  192. struct rb_node **new = &(root->rb_node), *parent = NULL;
  193. /* Figure out where to put new node */
  194. while (*new) {
  195. struct res_common *this = container_of(*new, struct res_common,
  196. node);
  197. parent = *new;
  198. if (res->res_id < this->res_id)
  199. new = &((*new)->rb_left);
  200. else if (res->res_id > this->res_id)
  201. new = &((*new)->rb_right);
  202. else
  203. return -EEXIST;
  204. }
  205. /* Add new node and rebalance tree. */
  206. rb_link_node(&res->node, parent, new);
  207. rb_insert_color(&res->node, root);
  208. return 0;
  209. }
  210. enum qp_transition {
  211. QP_TRANS_INIT2RTR,
  212. QP_TRANS_RTR2RTS,
  213. QP_TRANS_RTS2RTS,
  214. QP_TRANS_SQERR2RTS,
  215. QP_TRANS_SQD2SQD,
  216. QP_TRANS_SQD2RTS
  217. };
  218. /* For Debug uses */
  219. static const char *ResourceType(enum mlx4_resource rt)
  220. {
  221. switch (rt) {
  222. case RES_QP: return "RES_QP";
  223. case RES_CQ: return "RES_CQ";
  224. case RES_SRQ: return "RES_SRQ";
  225. case RES_MPT: return "RES_MPT";
  226. case RES_MTT: return "RES_MTT";
  227. case RES_MAC: return "RES_MAC";
  228. case RES_EQ: return "RES_EQ";
  229. case RES_COUNTER: return "RES_COUNTER";
  230. case RES_FS_RULE: return "RES_FS_RULE";
  231. case RES_XRCD: return "RES_XRCD";
  232. default: return "Unknown resource type !!!";
  233. };
  234. }
  235. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  236. {
  237. struct mlx4_priv *priv = mlx4_priv(dev);
  238. int i;
  239. int t;
  240. priv->mfunc.master.res_tracker.slave_list =
  241. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  242. GFP_KERNEL);
  243. if (!priv->mfunc.master.res_tracker.slave_list)
  244. return -ENOMEM;
  245. for (i = 0 ; i < dev->num_slaves; i++) {
  246. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  247. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  248. slave_list[i].res_list[t]);
  249. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  250. }
  251. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  252. dev->num_slaves);
  253. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  254. priv->mfunc.master.res_tracker.res_tree[i] = RB_ROOT;
  255. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  256. return 0 ;
  257. }
  258. void mlx4_free_resource_tracker(struct mlx4_dev *dev,
  259. enum mlx4_res_tracker_free_type type)
  260. {
  261. struct mlx4_priv *priv = mlx4_priv(dev);
  262. int i;
  263. if (priv->mfunc.master.res_tracker.slave_list) {
  264. if (type != RES_TR_FREE_STRUCTS_ONLY)
  265. for (i = 0 ; i < dev->num_slaves; i++)
  266. if (type == RES_TR_FREE_ALL ||
  267. dev->caps.function != i)
  268. mlx4_delete_all_resources_for_slave(dev, i);
  269. if (type != RES_TR_FREE_SLAVES_ONLY) {
  270. kfree(priv->mfunc.master.res_tracker.slave_list);
  271. priv->mfunc.master.res_tracker.slave_list = NULL;
  272. }
  273. }
  274. }
  275. static void update_pkey_index(struct mlx4_dev *dev, int slave,
  276. struct mlx4_cmd_mailbox *inbox)
  277. {
  278. u8 sched = *(u8 *)(inbox->buf + 64);
  279. u8 orig_index = *(u8 *)(inbox->buf + 35);
  280. u8 new_index;
  281. struct mlx4_priv *priv = mlx4_priv(dev);
  282. int port;
  283. port = (sched >> 6 & 1) + 1;
  284. new_index = priv->virt2phys_pkey[slave][port - 1][orig_index];
  285. *(u8 *)(inbox->buf + 35) = new_index;
  286. }
  287. static void update_gid(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *inbox,
  288. u8 slave)
  289. {
  290. struct mlx4_qp_context *qp_ctx = inbox->buf + 8;
  291. enum mlx4_qp_optpar optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  292. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  293. if (MLX4_QP_ST_UD == ts)
  294. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  295. if (MLX4_QP_ST_RC == ts || MLX4_QP_ST_UC == ts) {
  296. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  297. qp_ctx->pri_path.mgid_index = slave & 0x7F;
  298. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  299. qp_ctx->alt_path.mgid_index = slave & 0x7F;
  300. }
  301. }
  302. static int update_vport_qp_param(struct mlx4_dev *dev,
  303. struct mlx4_cmd_mailbox *inbox,
  304. u8 slave)
  305. {
  306. struct mlx4_qp_context *qpc = inbox->buf + 8;
  307. struct mlx4_vport_oper_state *vp_oper;
  308. struct mlx4_priv *priv;
  309. u32 qp_type;
  310. int port;
  311. port = (qpc->pri_path.sched_queue & 0x40) ? 2 : 1;
  312. priv = mlx4_priv(dev);
  313. vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
  314. if (MLX4_VGT != vp_oper->state.default_vlan) {
  315. qp_type = (be32_to_cpu(qpc->flags) >> 16) & 0xff;
  316. if (MLX4_QP_ST_RC == qp_type)
  317. return -EINVAL;
  318. /* force strip vlan by clear vsd */
  319. qpc->param3 &= ~cpu_to_be32(MLX4_STRIP_VLAN);
  320. if (0 != vp_oper->state.default_vlan) {
  321. qpc->pri_path.vlan_control =
  322. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  323. MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED |
  324. MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED;
  325. } else { /* priority tagged */
  326. qpc->pri_path.vlan_control =
  327. MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED |
  328. MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED;
  329. }
  330. qpc->pri_path.fvl_rx |= MLX4_FVL_RX_FORCE_ETH_VLAN;
  331. qpc->pri_path.vlan_index = vp_oper->vlan_idx;
  332. qpc->pri_path.fl |= MLX4_FL_CV | MLX4_FL_ETH_HIDE_CQE_VLAN;
  333. qpc->pri_path.feup |= MLX4_FEUP_FORCE_ETH_UP | MLX4_FVL_FORCE_ETH_VLAN;
  334. qpc->pri_path.sched_queue &= 0xC7;
  335. qpc->pri_path.sched_queue |= (vp_oper->state.default_qos) << 3;
  336. }
  337. if (vp_oper->state.spoofchk) {
  338. qpc->pri_path.feup |= MLX4_FSM_FORCE_ETH_SRC_MAC;
  339. qpc->pri_path.grh_mylmc = (0x80 & qpc->pri_path.grh_mylmc) + vp_oper->mac_idx;
  340. }
  341. return 0;
  342. }
  343. static int mpt_mask(struct mlx4_dev *dev)
  344. {
  345. return dev->caps.num_mpts - 1;
  346. }
  347. static void *find_res(struct mlx4_dev *dev, u64 res_id,
  348. enum mlx4_resource type)
  349. {
  350. struct mlx4_priv *priv = mlx4_priv(dev);
  351. return res_tracker_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  352. res_id);
  353. }
  354. static int get_res(struct mlx4_dev *dev, int slave, u64 res_id,
  355. enum mlx4_resource type,
  356. void *res)
  357. {
  358. struct res_common *r;
  359. int err = 0;
  360. spin_lock_irq(mlx4_tlock(dev));
  361. r = find_res(dev, res_id, type);
  362. if (!r) {
  363. err = -ENONET;
  364. goto exit;
  365. }
  366. if (r->state == RES_ANY_BUSY) {
  367. err = -EBUSY;
  368. goto exit;
  369. }
  370. if (r->owner != slave) {
  371. err = -EPERM;
  372. goto exit;
  373. }
  374. r->from_state = r->state;
  375. r->state = RES_ANY_BUSY;
  376. if (res)
  377. *((struct res_common **)res) = r;
  378. exit:
  379. spin_unlock_irq(mlx4_tlock(dev));
  380. return err;
  381. }
  382. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  383. enum mlx4_resource type,
  384. u64 res_id, int *slave)
  385. {
  386. struct res_common *r;
  387. int err = -ENOENT;
  388. int id = res_id;
  389. if (type == RES_QP)
  390. id &= 0x7fffff;
  391. spin_lock(mlx4_tlock(dev));
  392. r = find_res(dev, id, type);
  393. if (r) {
  394. *slave = r->owner;
  395. err = 0;
  396. }
  397. spin_unlock(mlx4_tlock(dev));
  398. return err;
  399. }
  400. static void put_res(struct mlx4_dev *dev, int slave, u64 res_id,
  401. enum mlx4_resource type)
  402. {
  403. struct res_common *r;
  404. spin_lock_irq(mlx4_tlock(dev));
  405. r = find_res(dev, res_id, type);
  406. if (r)
  407. r->state = r->from_state;
  408. spin_unlock_irq(mlx4_tlock(dev));
  409. }
  410. static struct res_common *alloc_qp_tr(int id)
  411. {
  412. struct res_qp *ret;
  413. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  414. if (!ret)
  415. return NULL;
  416. ret->com.res_id = id;
  417. ret->com.state = RES_QP_RESERVED;
  418. ret->local_qpn = id;
  419. INIT_LIST_HEAD(&ret->mcg_list);
  420. spin_lock_init(&ret->mcg_spl);
  421. atomic_set(&ret->ref_count, 0);
  422. return &ret->com;
  423. }
  424. static struct res_common *alloc_mtt_tr(int id, int order)
  425. {
  426. struct res_mtt *ret;
  427. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  428. if (!ret)
  429. return NULL;
  430. ret->com.res_id = id;
  431. ret->order = order;
  432. ret->com.state = RES_MTT_ALLOCATED;
  433. atomic_set(&ret->ref_count, 0);
  434. return &ret->com;
  435. }
  436. static struct res_common *alloc_mpt_tr(int id, int key)
  437. {
  438. struct res_mpt *ret;
  439. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  440. if (!ret)
  441. return NULL;
  442. ret->com.res_id = id;
  443. ret->com.state = RES_MPT_RESERVED;
  444. ret->key = key;
  445. return &ret->com;
  446. }
  447. static struct res_common *alloc_eq_tr(int id)
  448. {
  449. struct res_eq *ret;
  450. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  451. if (!ret)
  452. return NULL;
  453. ret->com.res_id = id;
  454. ret->com.state = RES_EQ_RESERVED;
  455. return &ret->com;
  456. }
  457. static struct res_common *alloc_cq_tr(int id)
  458. {
  459. struct res_cq *ret;
  460. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  461. if (!ret)
  462. return NULL;
  463. ret->com.res_id = id;
  464. ret->com.state = RES_CQ_ALLOCATED;
  465. atomic_set(&ret->ref_count, 0);
  466. return &ret->com;
  467. }
  468. static struct res_common *alloc_srq_tr(int id)
  469. {
  470. struct res_srq *ret;
  471. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  472. if (!ret)
  473. return NULL;
  474. ret->com.res_id = id;
  475. ret->com.state = RES_SRQ_ALLOCATED;
  476. atomic_set(&ret->ref_count, 0);
  477. return &ret->com;
  478. }
  479. static struct res_common *alloc_counter_tr(int id)
  480. {
  481. struct res_counter *ret;
  482. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  483. if (!ret)
  484. return NULL;
  485. ret->com.res_id = id;
  486. ret->com.state = RES_COUNTER_ALLOCATED;
  487. return &ret->com;
  488. }
  489. static struct res_common *alloc_xrcdn_tr(int id)
  490. {
  491. struct res_xrcdn *ret;
  492. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  493. if (!ret)
  494. return NULL;
  495. ret->com.res_id = id;
  496. ret->com.state = RES_XRCD_ALLOCATED;
  497. return &ret->com;
  498. }
  499. static struct res_common *alloc_fs_rule_tr(u64 id, int qpn)
  500. {
  501. struct res_fs_rule *ret;
  502. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  503. if (!ret)
  504. return NULL;
  505. ret->com.res_id = id;
  506. ret->com.state = RES_FS_RULE_ALLOCATED;
  507. ret->qpn = qpn;
  508. return &ret->com;
  509. }
  510. static struct res_common *alloc_tr(u64 id, enum mlx4_resource type, int slave,
  511. int extra)
  512. {
  513. struct res_common *ret;
  514. switch (type) {
  515. case RES_QP:
  516. ret = alloc_qp_tr(id);
  517. break;
  518. case RES_MPT:
  519. ret = alloc_mpt_tr(id, extra);
  520. break;
  521. case RES_MTT:
  522. ret = alloc_mtt_tr(id, extra);
  523. break;
  524. case RES_EQ:
  525. ret = alloc_eq_tr(id);
  526. break;
  527. case RES_CQ:
  528. ret = alloc_cq_tr(id);
  529. break;
  530. case RES_SRQ:
  531. ret = alloc_srq_tr(id);
  532. break;
  533. case RES_MAC:
  534. printk(KERN_ERR "implementation missing\n");
  535. return NULL;
  536. case RES_COUNTER:
  537. ret = alloc_counter_tr(id);
  538. break;
  539. case RES_XRCD:
  540. ret = alloc_xrcdn_tr(id);
  541. break;
  542. case RES_FS_RULE:
  543. ret = alloc_fs_rule_tr(id, extra);
  544. break;
  545. default:
  546. return NULL;
  547. }
  548. if (ret)
  549. ret->owner = slave;
  550. return ret;
  551. }
  552. static int add_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  553. enum mlx4_resource type, int extra)
  554. {
  555. int i;
  556. int err;
  557. struct mlx4_priv *priv = mlx4_priv(dev);
  558. struct res_common **res_arr;
  559. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  560. struct rb_root *root = &tracker->res_tree[type];
  561. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  562. if (!res_arr)
  563. return -ENOMEM;
  564. for (i = 0; i < count; ++i) {
  565. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  566. if (!res_arr[i]) {
  567. for (--i; i >= 0; --i)
  568. kfree(res_arr[i]);
  569. kfree(res_arr);
  570. return -ENOMEM;
  571. }
  572. }
  573. spin_lock_irq(mlx4_tlock(dev));
  574. for (i = 0; i < count; ++i) {
  575. if (find_res(dev, base + i, type)) {
  576. err = -EEXIST;
  577. goto undo;
  578. }
  579. err = res_tracker_insert(root, res_arr[i]);
  580. if (err)
  581. goto undo;
  582. list_add_tail(&res_arr[i]->list,
  583. &tracker->slave_list[slave].res_list[type]);
  584. }
  585. spin_unlock_irq(mlx4_tlock(dev));
  586. kfree(res_arr);
  587. return 0;
  588. undo:
  589. for (--i; i >= base; --i)
  590. rb_erase(&res_arr[i]->node, root);
  591. spin_unlock_irq(mlx4_tlock(dev));
  592. for (i = 0; i < count; ++i)
  593. kfree(res_arr[i]);
  594. kfree(res_arr);
  595. return err;
  596. }
  597. static int remove_qp_ok(struct res_qp *res)
  598. {
  599. if (res->com.state == RES_QP_BUSY || atomic_read(&res->ref_count) ||
  600. !list_empty(&res->mcg_list)) {
  601. pr_err("resource tracker: fail to remove qp, state %d, ref_count %d\n",
  602. res->com.state, atomic_read(&res->ref_count));
  603. return -EBUSY;
  604. } else if (res->com.state != RES_QP_RESERVED) {
  605. return -EPERM;
  606. }
  607. return 0;
  608. }
  609. static int remove_mtt_ok(struct res_mtt *res, int order)
  610. {
  611. if (res->com.state == RES_MTT_BUSY ||
  612. atomic_read(&res->ref_count)) {
  613. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  614. __func__, __LINE__,
  615. mtt_states_str(res->com.state),
  616. atomic_read(&res->ref_count));
  617. return -EBUSY;
  618. } else if (res->com.state != RES_MTT_ALLOCATED)
  619. return -EPERM;
  620. else if (res->order != order)
  621. return -EINVAL;
  622. return 0;
  623. }
  624. static int remove_mpt_ok(struct res_mpt *res)
  625. {
  626. if (res->com.state == RES_MPT_BUSY)
  627. return -EBUSY;
  628. else if (res->com.state != RES_MPT_RESERVED)
  629. return -EPERM;
  630. return 0;
  631. }
  632. static int remove_eq_ok(struct res_eq *res)
  633. {
  634. if (res->com.state == RES_MPT_BUSY)
  635. return -EBUSY;
  636. else if (res->com.state != RES_MPT_RESERVED)
  637. return -EPERM;
  638. return 0;
  639. }
  640. static int remove_counter_ok(struct res_counter *res)
  641. {
  642. if (res->com.state == RES_COUNTER_BUSY)
  643. return -EBUSY;
  644. else if (res->com.state != RES_COUNTER_ALLOCATED)
  645. return -EPERM;
  646. return 0;
  647. }
  648. static int remove_xrcdn_ok(struct res_xrcdn *res)
  649. {
  650. if (res->com.state == RES_XRCD_BUSY)
  651. return -EBUSY;
  652. else if (res->com.state != RES_XRCD_ALLOCATED)
  653. return -EPERM;
  654. return 0;
  655. }
  656. static int remove_fs_rule_ok(struct res_fs_rule *res)
  657. {
  658. if (res->com.state == RES_FS_RULE_BUSY)
  659. return -EBUSY;
  660. else if (res->com.state != RES_FS_RULE_ALLOCATED)
  661. return -EPERM;
  662. return 0;
  663. }
  664. static int remove_cq_ok(struct res_cq *res)
  665. {
  666. if (res->com.state == RES_CQ_BUSY)
  667. return -EBUSY;
  668. else if (res->com.state != RES_CQ_ALLOCATED)
  669. return -EPERM;
  670. return 0;
  671. }
  672. static int remove_srq_ok(struct res_srq *res)
  673. {
  674. if (res->com.state == RES_SRQ_BUSY)
  675. return -EBUSY;
  676. else if (res->com.state != RES_SRQ_ALLOCATED)
  677. return -EPERM;
  678. return 0;
  679. }
  680. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  681. {
  682. switch (type) {
  683. case RES_QP:
  684. return remove_qp_ok((struct res_qp *)res);
  685. case RES_CQ:
  686. return remove_cq_ok((struct res_cq *)res);
  687. case RES_SRQ:
  688. return remove_srq_ok((struct res_srq *)res);
  689. case RES_MPT:
  690. return remove_mpt_ok((struct res_mpt *)res);
  691. case RES_MTT:
  692. return remove_mtt_ok((struct res_mtt *)res, extra);
  693. case RES_MAC:
  694. return -ENOSYS;
  695. case RES_EQ:
  696. return remove_eq_ok((struct res_eq *)res);
  697. case RES_COUNTER:
  698. return remove_counter_ok((struct res_counter *)res);
  699. case RES_XRCD:
  700. return remove_xrcdn_ok((struct res_xrcdn *)res);
  701. case RES_FS_RULE:
  702. return remove_fs_rule_ok((struct res_fs_rule *)res);
  703. default:
  704. return -EINVAL;
  705. }
  706. }
  707. static int rem_res_range(struct mlx4_dev *dev, int slave, u64 base, int count,
  708. enum mlx4_resource type, int extra)
  709. {
  710. u64 i;
  711. int err;
  712. struct mlx4_priv *priv = mlx4_priv(dev);
  713. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  714. struct res_common *r;
  715. spin_lock_irq(mlx4_tlock(dev));
  716. for (i = base; i < base + count; ++i) {
  717. r = res_tracker_lookup(&tracker->res_tree[type], i);
  718. if (!r) {
  719. err = -ENOENT;
  720. goto out;
  721. }
  722. if (r->owner != slave) {
  723. err = -EPERM;
  724. goto out;
  725. }
  726. err = remove_ok(r, type, extra);
  727. if (err)
  728. goto out;
  729. }
  730. for (i = base; i < base + count; ++i) {
  731. r = res_tracker_lookup(&tracker->res_tree[type], i);
  732. rb_erase(&r->node, &tracker->res_tree[type]);
  733. list_del(&r->list);
  734. kfree(r);
  735. }
  736. err = 0;
  737. out:
  738. spin_unlock_irq(mlx4_tlock(dev));
  739. return err;
  740. }
  741. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  742. enum res_qp_states state, struct res_qp **qp,
  743. int alloc)
  744. {
  745. struct mlx4_priv *priv = mlx4_priv(dev);
  746. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  747. struct res_qp *r;
  748. int err = 0;
  749. spin_lock_irq(mlx4_tlock(dev));
  750. r = res_tracker_lookup(&tracker->res_tree[RES_QP], qpn);
  751. if (!r)
  752. err = -ENOENT;
  753. else if (r->com.owner != slave)
  754. err = -EPERM;
  755. else {
  756. switch (state) {
  757. case RES_QP_BUSY:
  758. mlx4_dbg(dev, "%s: failed RES_QP, 0x%llx\n",
  759. __func__, r->com.res_id);
  760. err = -EBUSY;
  761. break;
  762. case RES_QP_RESERVED:
  763. if (r->com.state == RES_QP_MAPPED && !alloc)
  764. break;
  765. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n", r->com.res_id);
  766. err = -EINVAL;
  767. break;
  768. case RES_QP_MAPPED:
  769. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  770. r->com.state == RES_QP_HW)
  771. break;
  772. else {
  773. mlx4_dbg(dev, "failed RES_QP, 0x%llx\n",
  774. r->com.res_id);
  775. err = -EINVAL;
  776. }
  777. break;
  778. case RES_QP_HW:
  779. if (r->com.state != RES_QP_MAPPED)
  780. err = -EINVAL;
  781. break;
  782. default:
  783. err = -EINVAL;
  784. }
  785. if (!err) {
  786. r->com.from_state = r->com.state;
  787. r->com.to_state = state;
  788. r->com.state = RES_QP_BUSY;
  789. if (qp)
  790. *qp = r;
  791. }
  792. }
  793. spin_unlock_irq(mlx4_tlock(dev));
  794. return err;
  795. }
  796. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  797. enum res_mpt_states state, struct res_mpt **mpt)
  798. {
  799. struct mlx4_priv *priv = mlx4_priv(dev);
  800. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  801. struct res_mpt *r;
  802. int err = 0;
  803. spin_lock_irq(mlx4_tlock(dev));
  804. r = res_tracker_lookup(&tracker->res_tree[RES_MPT], index);
  805. if (!r)
  806. err = -ENOENT;
  807. else if (r->com.owner != slave)
  808. err = -EPERM;
  809. else {
  810. switch (state) {
  811. case RES_MPT_BUSY:
  812. err = -EINVAL;
  813. break;
  814. case RES_MPT_RESERVED:
  815. if (r->com.state != RES_MPT_MAPPED)
  816. err = -EINVAL;
  817. break;
  818. case RES_MPT_MAPPED:
  819. if (r->com.state != RES_MPT_RESERVED &&
  820. r->com.state != RES_MPT_HW)
  821. err = -EINVAL;
  822. break;
  823. case RES_MPT_HW:
  824. if (r->com.state != RES_MPT_MAPPED)
  825. err = -EINVAL;
  826. break;
  827. default:
  828. err = -EINVAL;
  829. }
  830. if (!err) {
  831. r->com.from_state = r->com.state;
  832. r->com.to_state = state;
  833. r->com.state = RES_MPT_BUSY;
  834. if (mpt)
  835. *mpt = r;
  836. }
  837. }
  838. spin_unlock_irq(mlx4_tlock(dev));
  839. return err;
  840. }
  841. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  842. enum res_eq_states state, struct res_eq **eq)
  843. {
  844. struct mlx4_priv *priv = mlx4_priv(dev);
  845. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  846. struct res_eq *r;
  847. int err = 0;
  848. spin_lock_irq(mlx4_tlock(dev));
  849. r = res_tracker_lookup(&tracker->res_tree[RES_EQ], index);
  850. if (!r)
  851. err = -ENOENT;
  852. else if (r->com.owner != slave)
  853. err = -EPERM;
  854. else {
  855. switch (state) {
  856. case RES_EQ_BUSY:
  857. err = -EINVAL;
  858. break;
  859. case RES_EQ_RESERVED:
  860. if (r->com.state != RES_EQ_HW)
  861. err = -EINVAL;
  862. break;
  863. case RES_EQ_HW:
  864. if (r->com.state != RES_EQ_RESERVED)
  865. err = -EINVAL;
  866. break;
  867. default:
  868. err = -EINVAL;
  869. }
  870. if (!err) {
  871. r->com.from_state = r->com.state;
  872. r->com.to_state = state;
  873. r->com.state = RES_EQ_BUSY;
  874. if (eq)
  875. *eq = r;
  876. }
  877. }
  878. spin_unlock_irq(mlx4_tlock(dev));
  879. return err;
  880. }
  881. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  882. enum res_cq_states state, struct res_cq **cq)
  883. {
  884. struct mlx4_priv *priv = mlx4_priv(dev);
  885. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  886. struct res_cq *r;
  887. int err;
  888. spin_lock_irq(mlx4_tlock(dev));
  889. r = res_tracker_lookup(&tracker->res_tree[RES_CQ], cqn);
  890. if (!r)
  891. err = -ENOENT;
  892. else if (r->com.owner != slave)
  893. err = -EPERM;
  894. else {
  895. switch (state) {
  896. case RES_CQ_BUSY:
  897. err = -EBUSY;
  898. break;
  899. case RES_CQ_ALLOCATED:
  900. if (r->com.state != RES_CQ_HW)
  901. err = -EINVAL;
  902. else if (atomic_read(&r->ref_count))
  903. err = -EBUSY;
  904. else
  905. err = 0;
  906. break;
  907. case RES_CQ_HW:
  908. if (r->com.state != RES_CQ_ALLOCATED)
  909. err = -EINVAL;
  910. else
  911. err = 0;
  912. break;
  913. default:
  914. err = -EINVAL;
  915. }
  916. if (!err) {
  917. r->com.from_state = r->com.state;
  918. r->com.to_state = state;
  919. r->com.state = RES_CQ_BUSY;
  920. if (cq)
  921. *cq = r;
  922. }
  923. }
  924. spin_unlock_irq(mlx4_tlock(dev));
  925. return err;
  926. }
  927. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  928. enum res_cq_states state, struct res_srq **srq)
  929. {
  930. struct mlx4_priv *priv = mlx4_priv(dev);
  931. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  932. struct res_srq *r;
  933. int err = 0;
  934. spin_lock_irq(mlx4_tlock(dev));
  935. r = res_tracker_lookup(&tracker->res_tree[RES_SRQ], index);
  936. if (!r)
  937. err = -ENOENT;
  938. else if (r->com.owner != slave)
  939. err = -EPERM;
  940. else {
  941. switch (state) {
  942. case RES_SRQ_BUSY:
  943. err = -EINVAL;
  944. break;
  945. case RES_SRQ_ALLOCATED:
  946. if (r->com.state != RES_SRQ_HW)
  947. err = -EINVAL;
  948. else if (atomic_read(&r->ref_count))
  949. err = -EBUSY;
  950. break;
  951. case RES_SRQ_HW:
  952. if (r->com.state != RES_SRQ_ALLOCATED)
  953. err = -EINVAL;
  954. break;
  955. default:
  956. err = -EINVAL;
  957. }
  958. if (!err) {
  959. r->com.from_state = r->com.state;
  960. r->com.to_state = state;
  961. r->com.state = RES_SRQ_BUSY;
  962. if (srq)
  963. *srq = r;
  964. }
  965. }
  966. spin_unlock_irq(mlx4_tlock(dev));
  967. return err;
  968. }
  969. static void res_abort_move(struct mlx4_dev *dev, int slave,
  970. enum mlx4_resource type, int id)
  971. {
  972. struct mlx4_priv *priv = mlx4_priv(dev);
  973. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  974. struct res_common *r;
  975. spin_lock_irq(mlx4_tlock(dev));
  976. r = res_tracker_lookup(&tracker->res_tree[type], id);
  977. if (r && (r->owner == slave))
  978. r->state = r->from_state;
  979. spin_unlock_irq(mlx4_tlock(dev));
  980. }
  981. static void res_end_move(struct mlx4_dev *dev, int slave,
  982. enum mlx4_resource type, int id)
  983. {
  984. struct mlx4_priv *priv = mlx4_priv(dev);
  985. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  986. struct res_common *r;
  987. spin_lock_irq(mlx4_tlock(dev));
  988. r = res_tracker_lookup(&tracker->res_tree[type], id);
  989. if (r && (r->owner == slave))
  990. r->state = r->to_state;
  991. spin_unlock_irq(mlx4_tlock(dev));
  992. }
  993. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  994. {
  995. return mlx4_is_qp_reserved(dev, qpn) &&
  996. (mlx4_is_master(dev) || mlx4_is_guest_proxy(dev, slave, qpn));
  997. }
  998. static int fw_reserved(struct mlx4_dev *dev, int qpn)
  999. {
  1000. return qpn < dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
  1001. }
  1002. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1003. u64 in_param, u64 *out_param)
  1004. {
  1005. int err;
  1006. int count;
  1007. int align;
  1008. int base;
  1009. int qpn;
  1010. switch (op) {
  1011. case RES_OP_RESERVE:
  1012. count = get_param_l(&in_param);
  1013. align = get_param_h(&in_param);
  1014. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  1015. if (err)
  1016. return err;
  1017. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  1018. if (err) {
  1019. __mlx4_qp_release_range(dev, base, count);
  1020. return err;
  1021. }
  1022. set_param_l(out_param, base);
  1023. break;
  1024. case RES_OP_MAP_ICM:
  1025. qpn = get_param_l(&in_param) & 0x7fffff;
  1026. if (valid_reserved(dev, slave, qpn)) {
  1027. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1028. if (err)
  1029. return err;
  1030. }
  1031. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  1032. NULL, 1);
  1033. if (err)
  1034. return err;
  1035. if (!fw_reserved(dev, qpn)) {
  1036. err = __mlx4_qp_alloc_icm(dev, qpn);
  1037. if (err) {
  1038. res_abort_move(dev, slave, RES_QP, qpn);
  1039. return err;
  1040. }
  1041. }
  1042. res_end_move(dev, slave, RES_QP, qpn);
  1043. break;
  1044. default:
  1045. err = -EINVAL;
  1046. break;
  1047. }
  1048. return err;
  1049. }
  1050. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1051. u64 in_param, u64 *out_param)
  1052. {
  1053. int err = -EINVAL;
  1054. int base;
  1055. int order;
  1056. if (op != RES_OP_RESERVE_AND_MAP)
  1057. return err;
  1058. order = get_param_l(&in_param);
  1059. base = __mlx4_alloc_mtt_range(dev, order);
  1060. if (base == -1)
  1061. return -ENOMEM;
  1062. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  1063. if (err)
  1064. __mlx4_free_mtt_range(dev, base, order);
  1065. else
  1066. set_param_l(out_param, base);
  1067. return err;
  1068. }
  1069. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1070. u64 in_param, u64 *out_param)
  1071. {
  1072. int err = -EINVAL;
  1073. int index;
  1074. int id;
  1075. struct res_mpt *mpt;
  1076. switch (op) {
  1077. case RES_OP_RESERVE:
  1078. index = __mlx4_mpt_reserve(dev);
  1079. if (index == -1)
  1080. break;
  1081. id = index & mpt_mask(dev);
  1082. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  1083. if (err) {
  1084. __mlx4_mpt_release(dev, index);
  1085. break;
  1086. }
  1087. set_param_l(out_param, index);
  1088. break;
  1089. case RES_OP_MAP_ICM:
  1090. index = get_param_l(&in_param);
  1091. id = index & mpt_mask(dev);
  1092. err = mr_res_start_move_to(dev, slave, id,
  1093. RES_MPT_MAPPED, &mpt);
  1094. if (err)
  1095. return err;
  1096. err = __mlx4_mpt_alloc_icm(dev, mpt->key);
  1097. if (err) {
  1098. res_abort_move(dev, slave, RES_MPT, id);
  1099. return err;
  1100. }
  1101. res_end_move(dev, slave, RES_MPT, id);
  1102. break;
  1103. }
  1104. return err;
  1105. }
  1106. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1107. u64 in_param, u64 *out_param)
  1108. {
  1109. int cqn;
  1110. int err;
  1111. switch (op) {
  1112. case RES_OP_RESERVE_AND_MAP:
  1113. err = __mlx4_cq_alloc_icm(dev, &cqn);
  1114. if (err)
  1115. break;
  1116. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1117. if (err) {
  1118. __mlx4_cq_free_icm(dev, cqn);
  1119. break;
  1120. }
  1121. set_param_l(out_param, cqn);
  1122. break;
  1123. default:
  1124. err = -EINVAL;
  1125. }
  1126. return err;
  1127. }
  1128. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1129. u64 in_param, u64 *out_param)
  1130. {
  1131. int srqn;
  1132. int err;
  1133. switch (op) {
  1134. case RES_OP_RESERVE_AND_MAP:
  1135. err = __mlx4_srq_alloc_icm(dev, &srqn);
  1136. if (err)
  1137. break;
  1138. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1139. if (err) {
  1140. __mlx4_srq_free_icm(dev, srqn);
  1141. break;
  1142. }
  1143. set_param_l(out_param, srqn);
  1144. break;
  1145. default:
  1146. err = -EINVAL;
  1147. }
  1148. return err;
  1149. }
  1150. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  1151. {
  1152. struct mlx4_priv *priv = mlx4_priv(dev);
  1153. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1154. struct mac_res *res;
  1155. res = kzalloc(sizeof *res, GFP_KERNEL);
  1156. if (!res)
  1157. return -ENOMEM;
  1158. res->mac = mac;
  1159. res->port = (u8) port;
  1160. list_add_tail(&res->list,
  1161. &tracker->slave_list[slave].res_list[RES_MAC]);
  1162. return 0;
  1163. }
  1164. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1165. int port)
  1166. {
  1167. struct mlx4_priv *priv = mlx4_priv(dev);
  1168. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1169. struct list_head *mac_list =
  1170. &tracker->slave_list[slave].res_list[RES_MAC];
  1171. struct mac_res *res, *tmp;
  1172. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1173. if (res->mac == mac && res->port == (u8) port) {
  1174. list_del(&res->list);
  1175. kfree(res);
  1176. break;
  1177. }
  1178. }
  1179. }
  1180. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1181. {
  1182. struct mlx4_priv *priv = mlx4_priv(dev);
  1183. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1184. struct list_head *mac_list =
  1185. &tracker->slave_list[slave].res_list[RES_MAC];
  1186. struct mac_res *res, *tmp;
  1187. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1188. list_del(&res->list);
  1189. __mlx4_unregister_mac(dev, res->port, res->mac);
  1190. kfree(res);
  1191. }
  1192. }
  1193. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1194. u64 in_param, u64 *out_param)
  1195. {
  1196. int err = -EINVAL;
  1197. int port;
  1198. u64 mac;
  1199. if (op != RES_OP_RESERVE_AND_MAP)
  1200. return err;
  1201. port = get_param_l(out_param);
  1202. mac = in_param;
  1203. err = __mlx4_register_mac(dev, port, mac);
  1204. if (err >= 0) {
  1205. set_param_l(out_param, err);
  1206. err = 0;
  1207. }
  1208. if (!err) {
  1209. err = mac_add_to_slave(dev, slave, mac, port);
  1210. if (err)
  1211. __mlx4_unregister_mac(dev, port, mac);
  1212. }
  1213. return err;
  1214. }
  1215. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1216. u64 in_param, u64 *out_param)
  1217. {
  1218. return 0;
  1219. }
  1220. static int counter_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1221. u64 in_param, u64 *out_param)
  1222. {
  1223. u32 index;
  1224. int err;
  1225. if (op != RES_OP_RESERVE)
  1226. return -EINVAL;
  1227. err = __mlx4_counter_alloc(dev, &index);
  1228. if (err)
  1229. return err;
  1230. err = add_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1231. if (err)
  1232. __mlx4_counter_free(dev, index);
  1233. else
  1234. set_param_l(out_param, index);
  1235. return err;
  1236. }
  1237. static int xrcdn_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1238. u64 in_param, u64 *out_param)
  1239. {
  1240. u32 xrcdn;
  1241. int err;
  1242. if (op != RES_OP_RESERVE)
  1243. return -EINVAL;
  1244. err = __mlx4_xrcd_alloc(dev, &xrcdn);
  1245. if (err)
  1246. return err;
  1247. err = add_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1248. if (err)
  1249. __mlx4_xrcd_free(dev, xrcdn);
  1250. else
  1251. set_param_l(out_param, xrcdn);
  1252. return err;
  1253. }
  1254. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1255. struct mlx4_vhcr *vhcr,
  1256. struct mlx4_cmd_mailbox *inbox,
  1257. struct mlx4_cmd_mailbox *outbox,
  1258. struct mlx4_cmd_info *cmd)
  1259. {
  1260. int err;
  1261. int alop = vhcr->op_modifier;
  1262. switch (vhcr->in_modifier) {
  1263. case RES_QP:
  1264. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1265. vhcr->in_param, &vhcr->out_param);
  1266. break;
  1267. case RES_MTT:
  1268. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1269. vhcr->in_param, &vhcr->out_param);
  1270. break;
  1271. case RES_MPT:
  1272. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1273. vhcr->in_param, &vhcr->out_param);
  1274. break;
  1275. case RES_CQ:
  1276. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1277. vhcr->in_param, &vhcr->out_param);
  1278. break;
  1279. case RES_SRQ:
  1280. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1281. vhcr->in_param, &vhcr->out_param);
  1282. break;
  1283. case RES_MAC:
  1284. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1285. vhcr->in_param, &vhcr->out_param);
  1286. break;
  1287. case RES_VLAN:
  1288. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1289. vhcr->in_param, &vhcr->out_param);
  1290. break;
  1291. case RES_COUNTER:
  1292. err = counter_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1293. vhcr->in_param, &vhcr->out_param);
  1294. break;
  1295. case RES_XRCD:
  1296. err = xrcdn_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1297. vhcr->in_param, &vhcr->out_param);
  1298. break;
  1299. default:
  1300. err = -EINVAL;
  1301. break;
  1302. }
  1303. return err;
  1304. }
  1305. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1306. u64 in_param)
  1307. {
  1308. int err;
  1309. int count;
  1310. int base;
  1311. int qpn;
  1312. switch (op) {
  1313. case RES_OP_RESERVE:
  1314. base = get_param_l(&in_param) & 0x7fffff;
  1315. count = get_param_h(&in_param);
  1316. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1317. if (err)
  1318. break;
  1319. __mlx4_qp_release_range(dev, base, count);
  1320. break;
  1321. case RES_OP_MAP_ICM:
  1322. qpn = get_param_l(&in_param) & 0x7fffff;
  1323. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1324. NULL, 0);
  1325. if (err)
  1326. return err;
  1327. if (!fw_reserved(dev, qpn))
  1328. __mlx4_qp_free_icm(dev, qpn);
  1329. res_end_move(dev, slave, RES_QP, qpn);
  1330. if (valid_reserved(dev, slave, qpn))
  1331. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1332. break;
  1333. default:
  1334. err = -EINVAL;
  1335. break;
  1336. }
  1337. return err;
  1338. }
  1339. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1340. u64 in_param, u64 *out_param)
  1341. {
  1342. int err = -EINVAL;
  1343. int base;
  1344. int order;
  1345. if (op != RES_OP_RESERVE_AND_MAP)
  1346. return err;
  1347. base = get_param_l(&in_param);
  1348. order = get_param_h(&in_param);
  1349. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1350. if (!err)
  1351. __mlx4_free_mtt_range(dev, base, order);
  1352. return err;
  1353. }
  1354. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1355. u64 in_param)
  1356. {
  1357. int err = -EINVAL;
  1358. int index;
  1359. int id;
  1360. struct res_mpt *mpt;
  1361. switch (op) {
  1362. case RES_OP_RESERVE:
  1363. index = get_param_l(&in_param);
  1364. id = index & mpt_mask(dev);
  1365. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1366. if (err)
  1367. break;
  1368. index = mpt->key;
  1369. put_res(dev, slave, id, RES_MPT);
  1370. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1371. if (err)
  1372. break;
  1373. __mlx4_mpt_release(dev, index);
  1374. break;
  1375. case RES_OP_MAP_ICM:
  1376. index = get_param_l(&in_param);
  1377. id = index & mpt_mask(dev);
  1378. err = mr_res_start_move_to(dev, slave, id,
  1379. RES_MPT_RESERVED, &mpt);
  1380. if (err)
  1381. return err;
  1382. __mlx4_mpt_free_icm(dev, mpt->key);
  1383. res_end_move(dev, slave, RES_MPT, id);
  1384. return err;
  1385. break;
  1386. default:
  1387. err = -EINVAL;
  1388. break;
  1389. }
  1390. return err;
  1391. }
  1392. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1393. u64 in_param, u64 *out_param)
  1394. {
  1395. int cqn;
  1396. int err;
  1397. switch (op) {
  1398. case RES_OP_RESERVE_AND_MAP:
  1399. cqn = get_param_l(&in_param);
  1400. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1401. if (err)
  1402. break;
  1403. __mlx4_cq_free_icm(dev, cqn);
  1404. break;
  1405. default:
  1406. err = -EINVAL;
  1407. break;
  1408. }
  1409. return err;
  1410. }
  1411. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1412. u64 in_param, u64 *out_param)
  1413. {
  1414. int srqn;
  1415. int err;
  1416. switch (op) {
  1417. case RES_OP_RESERVE_AND_MAP:
  1418. srqn = get_param_l(&in_param);
  1419. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1420. if (err)
  1421. break;
  1422. __mlx4_srq_free_icm(dev, srqn);
  1423. break;
  1424. default:
  1425. err = -EINVAL;
  1426. break;
  1427. }
  1428. return err;
  1429. }
  1430. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1431. u64 in_param, u64 *out_param)
  1432. {
  1433. int port;
  1434. int err = 0;
  1435. switch (op) {
  1436. case RES_OP_RESERVE_AND_MAP:
  1437. port = get_param_l(out_param);
  1438. mac_del_from_slave(dev, slave, in_param, port);
  1439. __mlx4_unregister_mac(dev, port, in_param);
  1440. break;
  1441. default:
  1442. err = -EINVAL;
  1443. break;
  1444. }
  1445. return err;
  1446. }
  1447. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1448. u64 in_param, u64 *out_param)
  1449. {
  1450. return 0;
  1451. }
  1452. static int counter_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1453. u64 in_param, u64 *out_param)
  1454. {
  1455. int index;
  1456. int err;
  1457. if (op != RES_OP_RESERVE)
  1458. return -EINVAL;
  1459. index = get_param_l(&in_param);
  1460. err = rem_res_range(dev, slave, index, 1, RES_COUNTER, 0);
  1461. if (err)
  1462. return err;
  1463. __mlx4_counter_free(dev, index);
  1464. return err;
  1465. }
  1466. static int xrcdn_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1467. u64 in_param, u64 *out_param)
  1468. {
  1469. int xrcdn;
  1470. int err;
  1471. if (op != RES_OP_RESERVE)
  1472. return -EINVAL;
  1473. xrcdn = get_param_l(&in_param);
  1474. err = rem_res_range(dev, slave, xrcdn, 1, RES_XRCD, 0);
  1475. if (err)
  1476. return err;
  1477. __mlx4_xrcd_free(dev, xrcdn);
  1478. return err;
  1479. }
  1480. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1481. struct mlx4_vhcr *vhcr,
  1482. struct mlx4_cmd_mailbox *inbox,
  1483. struct mlx4_cmd_mailbox *outbox,
  1484. struct mlx4_cmd_info *cmd)
  1485. {
  1486. int err = -EINVAL;
  1487. int alop = vhcr->op_modifier;
  1488. switch (vhcr->in_modifier) {
  1489. case RES_QP:
  1490. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1491. vhcr->in_param);
  1492. break;
  1493. case RES_MTT:
  1494. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1495. vhcr->in_param, &vhcr->out_param);
  1496. break;
  1497. case RES_MPT:
  1498. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1499. vhcr->in_param);
  1500. break;
  1501. case RES_CQ:
  1502. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1503. vhcr->in_param, &vhcr->out_param);
  1504. break;
  1505. case RES_SRQ:
  1506. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1507. vhcr->in_param, &vhcr->out_param);
  1508. break;
  1509. case RES_MAC:
  1510. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1511. vhcr->in_param, &vhcr->out_param);
  1512. break;
  1513. case RES_VLAN:
  1514. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1515. vhcr->in_param, &vhcr->out_param);
  1516. break;
  1517. case RES_COUNTER:
  1518. err = counter_free_res(dev, slave, vhcr->op_modifier, alop,
  1519. vhcr->in_param, &vhcr->out_param);
  1520. break;
  1521. case RES_XRCD:
  1522. err = xrcdn_free_res(dev, slave, vhcr->op_modifier, alop,
  1523. vhcr->in_param, &vhcr->out_param);
  1524. default:
  1525. break;
  1526. }
  1527. return err;
  1528. }
  1529. /* ugly but other choices are uglier */
  1530. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1531. {
  1532. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1533. }
  1534. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1535. {
  1536. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1537. }
  1538. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1539. {
  1540. return be32_to_cpu(mpt->mtt_sz);
  1541. }
  1542. static u32 mr_get_pd(struct mlx4_mpt_entry *mpt)
  1543. {
  1544. return be32_to_cpu(mpt->pd_flags) & 0x00ffffff;
  1545. }
  1546. static int mr_is_fmr(struct mlx4_mpt_entry *mpt)
  1547. {
  1548. return be32_to_cpu(mpt->pd_flags) & MLX4_MPT_PD_FLAG_FAST_REG;
  1549. }
  1550. static int mr_is_bind_enabled(struct mlx4_mpt_entry *mpt)
  1551. {
  1552. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_BIND_ENABLE;
  1553. }
  1554. static int mr_is_region(struct mlx4_mpt_entry *mpt)
  1555. {
  1556. return be32_to_cpu(mpt->flags) & MLX4_MPT_FLAG_REGION;
  1557. }
  1558. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1559. {
  1560. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1561. }
  1562. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1563. {
  1564. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1565. }
  1566. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1567. {
  1568. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1569. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1570. int log_sq_sride = qpc->sq_size_stride & 7;
  1571. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1572. int log_rq_stride = qpc->rq_size_stride & 7;
  1573. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1574. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1575. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1576. int sq_size;
  1577. int rq_size;
  1578. int total_pages;
  1579. int total_mem;
  1580. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1581. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1582. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1583. total_mem = sq_size + rq_size;
  1584. total_pages =
  1585. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1586. page_shift);
  1587. return total_pages;
  1588. }
  1589. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1590. int size, struct res_mtt *mtt)
  1591. {
  1592. int res_start = mtt->com.res_id;
  1593. int res_size = (1 << mtt->order);
  1594. if (start < res_start || start + size > res_start + res_size)
  1595. return -EPERM;
  1596. return 0;
  1597. }
  1598. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1599. struct mlx4_vhcr *vhcr,
  1600. struct mlx4_cmd_mailbox *inbox,
  1601. struct mlx4_cmd_mailbox *outbox,
  1602. struct mlx4_cmd_info *cmd)
  1603. {
  1604. int err;
  1605. int index = vhcr->in_modifier;
  1606. struct res_mtt *mtt;
  1607. struct res_mpt *mpt;
  1608. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1609. int phys;
  1610. int id;
  1611. u32 pd;
  1612. int pd_slave;
  1613. id = index & mpt_mask(dev);
  1614. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1615. if (err)
  1616. return err;
  1617. /* Disable memory windows for VFs. */
  1618. if (!mr_is_region(inbox->buf)) {
  1619. err = -EPERM;
  1620. goto ex_abort;
  1621. }
  1622. /* Make sure that the PD bits related to the slave id are zeros. */
  1623. pd = mr_get_pd(inbox->buf);
  1624. pd_slave = (pd >> 17) & 0x7f;
  1625. if (pd_slave != 0 && pd_slave != slave) {
  1626. err = -EPERM;
  1627. goto ex_abort;
  1628. }
  1629. if (mr_is_fmr(inbox->buf)) {
  1630. /* FMR and Bind Enable are forbidden in slave devices. */
  1631. if (mr_is_bind_enabled(inbox->buf)) {
  1632. err = -EPERM;
  1633. goto ex_abort;
  1634. }
  1635. /* FMR and Memory Windows are also forbidden. */
  1636. if (!mr_is_region(inbox->buf)) {
  1637. err = -EPERM;
  1638. goto ex_abort;
  1639. }
  1640. }
  1641. phys = mr_phys_mpt(inbox->buf);
  1642. if (!phys) {
  1643. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1644. if (err)
  1645. goto ex_abort;
  1646. err = check_mtt_range(dev, slave, mtt_base,
  1647. mr_get_mtt_size(inbox->buf), mtt);
  1648. if (err)
  1649. goto ex_put;
  1650. mpt->mtt = mtt;
  1651. }
  1652. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1653. if (err)
  1654. goto ex_put;
  1655. if (!phys) {
  1656. atomic_inc(&mtt->ref_count);
  1657. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1658. }
  1659. res_end_move(dev, slave, RES_MPT, id);
  1660. return 0;
  1661. ex_put:
  1662. if (!phys)
  1663. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1664. ex_abort:
  1665. res_abort_move(dev, slave, RES_MPT, id);
  1666. return err;
  1667. }
  1668. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1669. struct mlx4_vhcr *vhcr,
  1670. struct mlx4_cmd_mailbox *inbox,
  1671. struct mlx4_cmd_mailbox *outbox,
  1672. struct mlx4_cmd_info *cmd)
  1673. {
  1674. int err;
  1675. int index = vhcr->in_modifier;
  1676. struct res_mpt *mpt;
  1677. int id;
  1678. id = index & mpt_mask(dev);
  1679. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1680. if (err)
  1681. return err;
  1682. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1683. if (err)
  1684. goto ex_abort;
  1685. if (mpt->mtt)
  1686. atomic_dec(&mpt->mtt->ref_count);
  1687. res_end_move(dev, slave, RES_MPT, id);
  1688. return 0;
  1689. ex_abort:
  1690. res_abort_move(dev, slave, RES_MPT, id);
  1691. return err;
  1692. }
  1693. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1694. struct mlx4_vhcr *vhcr,
  1695. struct mlx4_cmd_mailbox *inbox,
  1696. struct mlx4_cmd_mailbox *outbox,
  1697. struct mlx4_cmd_info *cmd)
  1698. {
  1699. int err;
  1700. int index = vhcr->in_modifier;
  1701. struct res_mpt *mpt;
  1702. int id;
  1703. id = index & mpt_mask(dev);
  1704. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1705. if (err)
  1706. return err;
  1707. if (mpt->com.from_state != RES_MPT_HW) {
  1708. err = -EBUSY;
  1709. goto out;
  1710. }
  1711. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1712. out:
  1713. put_res(dev, slave, id, RES_MPT);
  1714. return err;
  1715. }
  1716. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1717. {
  1718. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1719. }
  1720. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1721. {
  1722. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1723. }
  1724. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1725. {
  1726. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1727. }
  1728. static void adjust_proxy_tun_qkey(struct mlx4_dev *dev, struct mlx4_vhcr *vhcr,
  1729. struct mlx4_qp_context *context)
  1730. {
  1731. u32 qpn = vhcr->in_modifier & 0xffffff;
  1732. u32 qkey = 0;
  1733. if (mlx4_get_parav_qkey(dev, qpn, &qkey))
  1734. return;
  1735. /* adjust qkey in qp context */
  1736. context->qkey = cpu_to_be32(qkey);
  1737. }
  1738. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1739. struct mlx4_vhcr *vhcr,
  1740. struct mlx4_cmd_mailbox *inbox,
  1741. struct mlx4_cmd_mailbox *outbox,
  1742. struct mlx4_cmd_info *cmd)
  1743. {
  1744. int err;
  1745. int qpn = vhcr->in_modifier & 0x7fffff;
  1746. struct res_mtt *mtt;
  1747. struct res_qp *qp;
  1748. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1749. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1750. int mtt_size = qp_get_mtt_size(qpc);
  1751. struct res_cq *rcq;
  1752. struct res_cq *scq;
  1753. int rcqn = qp_get_rcqn(qpc);
  1754. int scqn = qp_get_scqn(qpc);
  1755. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1756. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1757. struct res_srq *srq;
  1758. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1759. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1760. if (err)
  1761. return err;
  1762. qp->local_qpn = local_qpn;
  1763. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1764. if (err)
  1765. goto ex_abort;
  1766. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1767. if (err)
  1768. goto ex_put_mtt;
  1769. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1770. if (err)
  1771. goto ex_put_mtt;
  1772. if (scqn != rcqn) {
  1773. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1774. if (err)
  1775. goto ex_put_rcq;
  1776. } else
  1777. scq = rcq;
  1778. if (use_srq) {
  1779. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1780. if (err)
  1781. goto ex_put_scq;
  1782. }
  1783. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  1784. update_pkey_index(dev, slave, inbox);
  1785. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1786. if (err)
  1787. goto ex_put_srq;
  1788. atomic_inc(&mtt->ref_count);
  1789. qp->mtt = mtt;
  1790. atomic_inc(&rcq->ref_count);
  1791. qp->rcq = rcq;
  1792. atomic_inc(&scq->ref_count);
  1793. qp->scq = scq;
  1794. if (scqn != rcqn)
  1795. put_res(dev, slave, scqn, RES_CQ);
  1796. if (use_srq) {
  1797. atomic_inc(&srq->ref_count);
  1798. put_res(dev, slave, srqn, RES_SRQ);
  1799. qp->srq = srq;
  1800. }
  1801. put_res(dev, slave, rcqn, RES_CQ);
  1802. put_res(dev, slave, mtt_base, RES_MTT);
  1803. res_end_move(dev, slave, RES_QP, qpn);
  1804. return 0;
  1805. ex_put_srq:
  1806. if (use_srq)
  1807. put_res(dev, slave, srqn, RES_SRQ);
  1808. ex_put_scq:
  1809. if (scqn != rcqn)
  1810. put_res(dev, slave, scqn, RES_CQ);
  1811. ex_put_rcq:
  1812. put_res(dev, slave, rcqn, RES_CQ);
  1813. ex_put_mtt:
  1814. put_res(dev, slave, mtt_base, RES_MTT);
  1815. ex_abort:
  1816. res_abort_move(dev, slave, RES_QP, qpn);
  1817. return err;
  1818. }
  1819. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1820. {
  1821. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1822. }
  1823. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1824. {
  1825. int log_eq_size = eqc->log_eq_size & 0x1f;
  1826. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1827. if (log_eq_size + 5 < page_shift)
  1828. return 1;
  1829. return 1 << (log_eq_size + 5 - page_shift);
  1830. }
  1831. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1832. {
  1833. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1834. }
  1835. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1836. {
  1837. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1838. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1839. if (log_cq_size + 5 < page_shift)
  1840. return 1;
  1841. return 1 << (log_cq_size + 5 - page_shift);
  1842. }
  1843. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1844. struct mlx4_vhcr *vhcr,
  1845. struct mlx4_cmd_mailbox *inbox,
  1846. struct mlx4_cmd_mailbox *outbox,
  1847. struct mlx4_cmd_info *cmd)
  1848. {
  1849. int err;
  1850. int eqn = vhcr->in_modifier;
  1851. int res_id = (slave << 8) | eqn;
  1852. struct mlx4_eq_context *eqc = inbox->buf;
  1853. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1854. int mtt_size = eq_get_mtt_size(eqc);
  1855. struct res_eq *eq;
  1856. struct res_mtt *mtt;
  1857. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1858. if (err)
  1859. return err;
  1860. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1861. if (err)
  1862. goto out_add;
  1863. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1864. if (err)
  1865. goto out_move;
  1866. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1867. if (err)
  1868. goto out_put;
  1869. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1870. if (err)
  1871. goto out_put;
  1872. atomic_inc(&mtt->ref_count);
  1873. eq->mtt = mtt;
  1874. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1875. res_end_move(dev, slave, RES_EQ, res_id);
  1876. return 0;
  1877. out_put:
  1878. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1879. out_move:
  1880. res_abort_move(dev, slave, RES_EQ, res_id);
  1881. out_add:
  1882. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1883. return err;
  1884. }
  1885. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1886. int len, struct res_mtt **res)
  1887. {
  1888. struct mlx4_priv *priv = mlx4_priv(dev);
  1889. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1890. struct res_mtt *mtt;
  1891. int err = -EINVAL;
  1892. spin_lock_irq(mlx4_tlock(dev));
  1893. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1894. com.list) {
  1895. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1896. *res = mtt;
  1897. mtt->com.from_state = mtt->com.state;
  1898. mtt->com.state = RES_MTT_BUSY;
  1899. err = 0;
  1900. break;
  1901. }
  1902. }
  1903. spin_unlock_irq(mlx4_tlock(dev));
  1904. return err;
  1905. }
  1906. static int verify_qp_parameters(struct mlx4_dev *dev,
  1907. struct mlx4_cmd_mailbox *inbox,
  1908. enum qp_transition transition, u8 slave)
  1909. {
  1910. u32 qp_type;
  1911. struct mlx4_qp_context *qp_ctx;
  1912. enum mlx4_qp_optpar optpar;
  1913. qp_ctx = inbox->buf + 8;
  1914. qp_type = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  1915. optpar = be32_to_cpu(*(__be32 *) inbox->buf);
  1916. switch (qp_type) {
  1917. case MLX4_QP_ST_RC:
  1918. case MLX4_QP_ST_UC:
  1919. switch (transition) {
  1920. case QP_TRANS_INIT2RTR:
  1921. case QP_TRANS_RTR2RTS:
  1922. case QP_TRANS_RTS2RTS:
  1923. case QP_TRANS_SQD2SQD:
  1924. case QP_TRANS_SQD2RTS:
  1925. if (slave != mlx4_master_func_num(dev))
  1926. /* slaves have only gid index 0 */
  1927. if (optpar & MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH)
  1928. if (qp_ctx->pri_path.mgid_index)
  1929. return -EINVAL;
  1930. if (optpar & MLX4_QP_OPTPAR_ALT_ADDR_PATH)
  1931. if (qp_ctx->alt_path.mgid_index)
  1932. return -EINVAL;
  1933. break;
  1934. default:
  1935. break;
  1936. }
  1937. break;
  1938. default:
  1939. break;
  1940. }
  1941. return 0;
  1942. }
  1943. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1944. struct mlx4_vhcr *vhcr,
  1945. struct mlx4_cmd_mailbox *inbox,
  1946. struct mlx4_cmd_mailbox *outbox,
  1947. struct mlx4_cmd_info *cmd)
  1948. {
  1949. struct mlx4_mtt mtt;
  1950. __be64 *page_list = inbox->buf;
  1951. u64 *pg_list = (u64 *)page_list;
  1952. int i;
  1953. struct res_mtt *rmtt = NULL;
  1954. int start = be64_to_cpu(page_list[0]);
  1955. int npages = vhcr->in_modifier;
  1956. int err;
  1957. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1958. if (err)
  1959. return err;
  1960. /* Call the SW implementation of write_mtt:
  1961. * - Prepare a dummy mtt struct
  1962. * - Translate inbox contents to simple addresses in host endianess */
  1963. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1964. we don't really use it */
  1965. mtt.order = 0;
  1966. mtt.page_shift = 0;
  1967. for (i = 0; i < npages; ++i)
  1968. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1969. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1970. ((u64 *)page_list + 2));
  1971. if (rmtt)
  1972. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1973. return err;
  1974. }
  1975. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1976. struct mlx4_vhcr *vhcr,
  1977. struct mlx4_cmd_mailbox *inbox,
  1978. struct mlx4_cmd_mailbox *outbox,
  1979. struct mlx4_cmd_info *cmd)
  1980. {
  1981. int eqn = vhcr->in_modifier;
  1982. int res_id = eqn | (slave << 8);
  1983. struct res_eq *eq;
  1984. int err;
  1985. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1986. if (err)
  1987. return err;
  1988. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1989. if (err)
  1990. goto ex_abort;
  1991. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1992. if (err)
  1993. goto ex_put;
  1994. atomic_dec(&eq->mtt->ref_count);
  1995. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1996. res_end_move(dev, slave, RES_EQ, res_id);
  1997. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1998. return 0;
  1999. ex_put:
  2000. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  2001. ex_abort:
  2002. res_abort_move(dev, slave, RES_EQ, res_id);
  2003. return err;
  2004. }
  2005. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  2006. {
  2007. struct mlx4_priv *priv = mlx4_priv(dev);
  2008. struct mlx4_slave_event_eq_info *event_eq;
  2009. struct mlx4_cmd_mailbox *mailbox;
  2010. u32 in_modifier = 0;
  2011. int err;
  2012. int res_id;
  2013. struct res_eq *req;
  2014. if (!priv->mfunc.master.slave_state)
  2015. return -EINVAL;
  2016. event_eq = &priv->mfunc.master.slave_state[slave].event_eq[eqe->type];
  2017. /* Create the event only if the slave is registered */
  2018. if (event_eq->eqn < 0)
  2019. return 0;
  2020. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2021. res_id = (slave << 8) | event_eq->eqn;
  2022. err = get_res(dev, slave, res_id, RES_EQ, &req);
  2023. if (err)
  2024. goto unlock;
  2025. if (req->com.from_state != RES_EQ_HW) {
  2026. err = -EINVAL;
  2027. goto put;
  2028. }
  2029. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2030. if (IS_ERR(mailbox)) {
  2031. err = PTR_ERR(mailbox);
  2032. goto put;
  2033. }
  2034. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  2035. ++event_eq->token;
  2036. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  2037. }
  2038. memcpy(mailbox->buf, (u8 *) eqe, 28);
  2039. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  2040. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  2041. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  2042. MLX4_CMD_NATIVE);
  2043. put_res(dev, slave, res_id, RES_EQ);
  2044. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2045. mlx4_free_cmd_mailbox(dev, mailbox);
  2046. return err;
  2047. put:
  2048. put_res(dev, slave, res_id, RES_EQ);
  2049. unlock:
  2050. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  2051. return err;
  2052. }
  2053. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  2054. struct mlx4_vhcr *vhcr,
  2055. struct mlx4_cmd_mailbox *inbox,
  2056. struct mlx4_cmd_mailbox *outbox,
  2057. struct mlx4_cmd_info *cmd)
  2058. {
  2059. int eqn = vhcr->in_modifier;
  2060. int res_id = eqn | (slave << 8);
  2061. struct res_eq *eq;
  2062. int err;
  2063. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  2064. if (err)
  2065. return err;
  2066. if (eq->com.from_state != RES_EQ_HW) {
  2067. err = -EINVAL;
  2068. goto ex_put;
  2069. }
  2070. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2071. ex_put:
  2072. put_res(dev, slave, res_id, RES_EQ);
  2073. return err;
  2074. }
  2075. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2076. struct mlx4_vhcr *vhcr,
  2077. struct mlx4_cmd_mailbox *inbox,
  2078. struct mlx4_cmd_mailbox *outbox,
  2079. struct mlx4_cmd_info *cmd)
  2080. {
  2081. int err;
  2082. int cqn = vhcr->in_modifier;
  2083. struct mlx4_cq_context *cqc = inbox->buf;
  2084. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2085. struct res_cq *cq;
  2086. struct res_mtt *mtt;
  2087. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  2088. if (err)
  2089. return err;
  2090. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2091. if (err)
  2092. goto out_move;
  2093. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2094. if (err)
  2095. goto out_put;
  2096. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2097. if (err)
  2098. goto out_put;
  2099. atomic_inc(&mtt->ref_count);
  2100. cq->mtt = mtt;
  2101. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2102. res_end_move(dev, slave, RES_CQ, cqn);
  2103. return 0;
  2104. out_put:
  2105. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2106. out_move:
  2107. res_abort_move(dev, slave, RES_CQ, cqn);
  2108. return err;
  2109. }
  2110. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2111. struct mlx4_vhcr *vhcr,
  2112. struct mlx4_cmd_mailbox *inbox,
  2113. struct mlx4_cmd_mailbox *outbox,
  2114. struct mlx4_cmd_info *cmd)
  2115. {
  2116. int err;
  2117. int cqn = vhcr->in_modifier;
  2118. struct res_cq *cq;
  2119. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  2120. if (err)
  2121. return err;
  2122. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2123. if (err)
  2124. goto out_move;
  2125. atomic_dec(&cq->mtt->ref_count);
  2126. res_end_move(dev, slave, RES_CQ, cqn);
  2127. return 0;
  2128. out_move:
  2129. res_abort_move(dev, slave, RES_CQ, cqn);
  2130. return err;
  2131. }
  2132. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2133. struct mlx4_vhcr *vhcr,
  2134. struct mlx4_cmd_mailbox *inbox,
  2135. struct mlx4_cmd_mailbox *outbox,
  2136. struct mlx4_cmd_info *cmd)
  2137. {
  2138. int cqn = vhcr->in_modifier;
  2139. struct res_cq *cq;
  2140. int err;
  2141. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2142. if (err)
  2143. return err;
  2144. if (cq->com.from_state != RES_CQ_HW)
  2145. goto ex_put;
  2146. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2147. ex_put:
  2148. put_res(dev, slave, cqn, RES_CQ);
  2149. return err;
  2150. }
  2151. static int handle_resize(struct mlx4_dev *dev, int slave,
  2152. struct mlx4_vhcr *vhcr,
  2153. struct mlx4_cmd_mailbox *inbox,
  2154. struct mlx4_cmd_mailbox *outbox,
  2155. struct mlx4_cmd_info *cmd,
  2156. struct res_cq *cq)
  2157. {
  2158. int err;
  2159. struct res_mtt *orig_mtt;
  2160. struct res_mtt *mtt;
  2161. struct mlx4_cq_context *cqc = inbox->buf;
  2162. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  2163. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  2164. if (err)
  2165. return err;
  2166. if (orig_mtt != cq->mtt) {
  2167. err = -EINVAL;
  2168. goto ex_put;
  2169. }
  2170. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2171. if (err)
  2172. goto ex_put;
  2173. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  2174. if (err)
  2175. goto ex_put1;
  2176. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2177. if (err)
  2178. goto ex_put1;
  2179. atomic_dec(&orig_mtt->ref_count);
  2180. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2181. atomic_inc(&mtt->ref_count);
  2182. cq->mtt = mtt;
  2183. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2184. return 0;
  2185. ex_put1:
  2186. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2187. ex_put:
  2188. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  2189. return err;
  2190. }
  2191. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  2192. struct mlx4_vhcr *vhcr,
  2193. struct mlx4_cmd_mailbox *inbox,
  2194. struct mlx4_cmd_mailbox *outbox,
  2195. struct mlx4_cmd_info *cmd)
  2196. {
  2197. int cqn = vhcr->in_modifier;
  2198. struct res_cq *cq;
  2199. int err;
  2200. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  2201. if (err)
  2202. return err;
  2203. if (cq->com.from_state != RES_CQ_HW)
  2204. goto ex_put;
  2205. if (vhcr->op_modifier == 0) {
  2206. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  2207. goto ex_put;
  2208. }
  2209. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2210. ex_put:
  2211. put_res(dev, slave, cqn, RES_CQ);
  2212. return err;
  2213. }
  2214. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  2215. {
  2216. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  2217. int log_rq_stride = srqc->logstride & 7;
  2218. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  2219. if (log_srq_size + log_rq_stride + 4 < page_shift)
  2220. return 1;
  2221. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  2222. }
  2223. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2224. struct mlx4_vhcr *vhcr,
  2225. struct mlx4_cmd_mailbox *inbox,
  2226. struct mlx4_cmd_mailbox *outbox,
  2227. struct mlx4_cmd_info *cmd)
  2228. {
  2229. int err;
  2230. int srqn = vhcr->in_modifier;
  2231. struct res_mtt *mtt;
  2232. struct res_srq *srq;
  2233. struct mlx4_srq_context *srqc = inbox->buf;
  2234. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  2235. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  2236. return -EINVAL;
  2237. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  2238. if (err)
  2239. return err;
  2240. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  2241. if (err)
  2242. goto ex_abort;
  2243. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  2244. mtt);
  2245. if (err)
  2246. goto ex_put_mtt;
  2247. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2248. if (err)
  2249. goto ex_put_mtt;
  2250. atomic_inc(&mtt->ref_count);
  2251. srq->mtt = mtt;
  2252. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2253. res_end_move(dev, slave, RES_SRQ, srqn);
  2254. return 0;
  2255. ex_put_mtt:
  2256. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  2257. ex_abort:
  2258. res_abort_move(dev, slave, RES_SRQ, srqn);
  2259. return err;
  2260. }
  2261. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2262. struct mlx4_vhcr *vhcr,
  2263. struct mlx4_cmd_mailbox *inbox,
  2264. struct mlx4_cmd_mailbox *outbox,
  2265. struct mlx4_cmd_info *cmd)
  2266. {
  2267. int err;
  2268. int srqn = vhcr->in_modifier;
  2269. struct res_srq *srq;
  2270. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  2271. if (err)
  2272. return err;
  2273. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2274. if (err)
  2275. goto ex_abort;
  2276. atomic_dec(&srq->mtt->ref_count);
  2277. if (srq->cq)
  2278. atomic_dec(&srq->cq->ref_count);
  2279. res_end_move(dev, slave, RES_SRQ, srqn);
  2280. return 0;
  2281. ex_abort:
  2282. res_abort_move(dev, slave, RES_SRQ, srqn);
  2283. return err;
  2284. }
  2285. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2286. struct mlx4_vhcr *vhcr,
  2287. struct mlx4_cmd_mailbox *inbox,
  2288. struct mlx4_cmd_mailbox *outbox,
  2289. struct mlx4_cmd_info *cmd)
  2290. {
  2291. int err;
  2292. int srqn = vhcr->in_modifier;
  2293. struct res_srq *srq;
  2294. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2295. if (err)
  2296. return err;
  2297. if (srq->com.from_state != RES_SRQ_HW) {
  2298. err = -EBUSY;
  2299. goto out;
  2300. }
  2301. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2302. out:
  2303. put_res(dev, slave, srqn, RES_SRQ);
  2304. return err;
  2305. }
  2306. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2307. struct mlx4_vhcr *vhcr,
  2308. struct mlx4_cmd_mailbox *inbox,
  2309. struct mlx4_cmd_mailbox *outbox,
  2310. struct mlx4_cmd_info *cmd)
  2311. {
  2312. int err;
  2313. int srqn = vhcr->in_modifier;
  2314. struct res_srq *srq;
  2315. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2316. if (err)
  2317. return err;
  2318. if (srq->com.from_state != RES_SRQ_HW) {
  2319. err = -EBUSY;
  2320. goto out;
  2321. }
  2322. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2323. out:
  2324. put_res(dev, slave, srqn, RES_SRQ);
  2325. return err;
  2326. }
  2327. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2328. struct mlx4_vhcr *vhcr,
  2329. struct mlx4_cmd_mailbox *inbox,
  2330. struct mlx4_cmd_mailbox *outbox,
  2331. struct mlx4_cmd_info *cmd)
  2332. {
  2333. int err;
  2334. int qpn = vhcr->in_modifier & 0x7fffff;
  2335. struct res_qp *qp;
  2336. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2337. if (err)
  2338. return err;
  2339. if (qp->com.from_state != RES_QP_HW) {
  2340. err = -EBUSY;
  2341. goto out;
  2342. }
  2343. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2344. out:
  2345. put_res(dev, slave, qpn, RES_QP);
  2346. return err;
  2347. }
  2348. int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  2349. struct mlx4_vhcr *vhcr,
  2350. struct mlx4_cmd_mailbox *inbox,
  2351. struct mlx4_cmd_mailbox *outbox,
  2352. struct mlx4_cmd_info *cmd)
  2353. {
  2354. struct mlx4_qp_context *context = inbox->buf + 8;
  2355. adjust_proxy_tun_qkey(dev, vhcr, context);
  2356. update_pkey_index(dev, slave, inbox);
  2357. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2358. }
  2359. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2360. struct mlx4_vhcr *vhcr,
  2361. struct mlx4_cmd_mailbox *inbox,
  2362. struct mlx4_cmd_mailbox *outbox,
  2363. struct mlx4_cmd_info *cmd)
  2364. {
  2365. int err;
  2366. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2367. err = verify_qp_parameters(dev, inbox, QP_TRANS_INIT2RTR, slave);
  2368. if (err)
  2369. return err;
  2370. update_pkey_index(dev, slave, inbox);
  2371. update_gid(dev, inbox, (u8)slave);
  2372. adjust_proxy_tun_qkey(dev, vhcr, qpc);
  2373. err = update_vport_qp_param(dev, inbox, slave);
  2374. if (err)
  2375. return err;
  2376. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2377. }
  2378. int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2379. struct mlx4_vhcr *vhcr,
  2380. struct mlx4_cmd_mailbox *inbox,
  2381. struct mlx4_cmd_mailbox *outbox,
  2382. struct mlx4_cmd_info *cmd)
  2383. {
  2384. int err;
  2385. struct mlx4_qp_context *context = inbox->buf + 8;
  2386. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTR2RTS, slave);
  2387. if (err)
  2388. return err;
  2389. update_pkey_index(dev, slave, inbox);
  2390. update_gid(dev, inbox, (u8)slave);
  2391. adjust_proxy_tun_qkey(dev, vhcr, context);
  2392. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2393. }
  2394. int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2395. struct mlx4_vhcr *vhcr,
  2396. struct mlx4_cmd_mailbox *inbox,
  2397. struct mlx4_cmd_mailbox *outbox,
  2398. struct mlx4_cmd_info *cmd)
  2399. {
  2400. int err;
  2401. struct mlx4_qp_context *context = inbox->buf + 8;
  2402. err = verify_qp_parameters(dev, inbox, QP_TRANS_RTS2RTS, slave);
  2403. if (err)
  2404. return err;
  2405. update_pkey_index(dev, slave, inbox);
  2406. update_gid(dev, inbox, (u8)slave);
  2407. adjust_proxy_tun_qkey(dev, vhcr, context);
  2408. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2409. }
  2410. int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2411. struct mlx4_vhcr *vhcr,
  2412. struct mlx4_cmd_mailbox *inbox,
  2413. struct mlx4_cmd_mailbox *outbox,
  2414. struct mlx4_cmd_info *cmd)
  2415. {
  2416. struct mlx4_qp_context *context = inbox->buf + 8;
  2417. adjust_proxy_tun_qkey(dev, vhcr, context);
  2418. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2419. }
  2420. int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
  2421. struct mlx4_vhcr *vhcr,
  2422. struct mlx4_cmd_mailbox *inbox,
  2423. struct mlx4_cmd_mailbox *outbox,
  2424. struct mlx4_cmd_info *cmd)
  2425. {
  2426. int err;
  2427. struct mlx4_qp_context *context = inbox->buf + 8;
  2428. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2SQD, slave);
  2429. if (err)
  2430. return err;
  2431. adjust_proxy_tun_qkey(dev, vhcr, context);
  2432. update_gid(dev, inbox, (u8)slave);
  2433. update_pkey_index(dev, slave, inbox);
  2434. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2435. }
  2436. int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
  2437. struct mlx4_vhcr *vhcr,
  2438. struct mlx4_cmd_mailbox *inbox,
  2439. struct mlx4_cmd_mailbox *outbox,
  2440. struct mlx4_cmd_info *cmd)
  2441. {
  2442. int err;
  2443. struct mlx4_qp_context *context = inbox->buf + 8;
  2444. err = verify_qp_parameters(dev, inbox, QP_TRANS_SQD2RTS, slave);
  2445. if (err)
  2446. return err;
  2447. adjust_proxy_tun_qkey(dev, vhcr, context);
  2448. update_gid(dev, inbox, (u8)slave);
  2449. update_pkey_index(dev, slave, inbox);
  2450. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2451. }
  2452. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2453. struct mlx4_vhcr *vhcr,
  2454. struct mlx4_cmd_mailbox *inbox,
  2455. struct mlx4_cmd_mailbox *outbox,
  2456. struct mlx4_cmd_info *cmd)
  2457. {
  2458. int err;
  2459. int qpn = vhcr->in_modifier & 0x7fffff;
  2460. struct res_qp *qp;
  2461. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2462. if (err)
  2463. return err;
  2464. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2465. if (err)
  2466. goto ex_abort;
  2467. atomic_dec(&qp->mtt->ref_count);
  2468. atomic_dec(&qp->rcq->ref_count);
  2469. atomic_dec(&qp->scq->ref_count);
  2470. if (qp->srq)
  2471. atomic_dec(&qp->srq->ref_count);
  2472. res_end_move(dev, slave, RES_QP, qpn);
  2473. return 0;
  2474. ex_abort:
  2475. res_abort_move(dev, slave, RES_QP, qpn);
  2476. return err;
  2477. }
  2478. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2479. struct res_qp *rqp, u8 *gid)
  2480. {
  2481. struct res_gid *res;
  2482. list_for_each_entry(res, &rqp->mcg_list, list) {
  2483. if (!memcmp(res->gid, gid, 16))
  2484. return res;
  2485. }
  2486. return NULL;
  2487. }
  2488. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2489. u8 *gid, enum mlx4_protocol prot,
  2490. enum mlx4_steer_type steer, u64 reg_id)
  2491. {
  2492. struct res_gid *res;
  2493. int err;
  2494. res = kzalloc(sizeof *res, GFP_KERNEL);
  2495. if (!res)
  2496. return -ENOMEM;
  2497. spin_lock_irq(&rqp->mcg_spl);
  2498. if (find_gid(dev, slave, rqp, gid)) {
  2499. kfree(res);
  2500. err = -EEXIST;
  2501. } else {
  2502. memcpy(res->gid, gid, 16);
  2503. res->prot = prot;
  2504. res->steer = steer;
  2505. res->reg_id = reg_id;
  2506. list_add_tail(&res->list, &rqp->mcg_list);
  2507. err = 0;
  2508. }
  2509. spin_unlock_irq(&rqp->mcg_spl);
  2510. return err;
  2511. }
  2512. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2513. u8 *gid, enum mlx4_protocol prot,
  2514. enum mlx4_steer_type steer, u64 *reg_id)
  2515. {
  2516. struct res_gid *res;
  2517. int err;
  2518. spin_lock_irq(&rqp->mcg_spl);
  2519. res = find_gid(dev, slave, rqp, gid);
  2520. if (!res || res->prot != prot || res->steer != steer)
  2521. err = -EINVAL;
  2522. else {
  2523. *reg_id = res->reg_id;
  2524. list_del(&res->list);
  2525. kfree(res);
  2526. err = 0;
  2527. }
  2528. spin_unlock_irq(&rqp->mcg_spl);
  2529. return err;
  2530. }
  2531. static int qp_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  2532. int block_loopback, enum mlx4_protocol prot,
  2533. enum mlx4_steer_type type, u64 *reg_id)
  2534. {
  2535. switch (dev->caps.steering_mode) {
  2536. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  2537. return mlx4_trans_to_dmfs_attach(dev, qp, gid, gid[5],
  2538. block_loopback, prot,
  2539. reg_id);
  2540. case MLX4_STEERING_MODE_B0:
  2541. return mlx4_qp_attach_common(dev, qp, gid,
  2542. block_loopback, prot, type);
  2543. default:
  2544. return -EINVAL;
  2545. }
  2546. }
  2547. static int qp_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
  2548. enum mlx4_protocol prot, enum mlx4_steer_type type,
  2549. u64 reg_id)
  2550. {
  2551. switch (dev->caps.steering_mode) {
  2552. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  2553. return mlx4_flow_detach(dev, reg_id);
  2554. case MLX4_STEERING_MODE_B0:
  2555. return mlx4_qp_detach_common(dev, qp, gid, prot, type);
  2556. default:
  2557. return -EINVAL;
  2558. }
  2559. }
  2560. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2561. struct mlx4_vhcr *vhcr,
  2562. struct mlx4_cmd_mailbox *inbox,
  2563. struct mlx4_cmd_mailbox *outbox,
  2564. struct mlx4_cmd_info *cmd)
  2565. {
  2566. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2567. u8 *gid = inbox->buf;
  2568. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2569. int err;
  2570. int qpn;
  2571. struct res_qp *rqp;
  2572. u64 reg_id = 0;
  2573. int attach = vhcr->op_modifier;
  2574. int block_loopback = vhcr->in_modifier >> 31;
  2575. u8 steer_type_mask = 2;
  2576. enum mlx4_steer_type type = (gid[7] & steer_type_mask) >> 1;
  2577. qpn = vhcr->in_modifier & 0xffffff;
  2578. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2579. if (err)
  2580. return err;
  2581. qp.qpn = qpn;
  2582. if (attach) {
  2583. err = qp_attach(dev, &qp, gid, block_loopback, prot,
  2584. type, &reg_id);
  2585. if (err) {
  2586. pr_err("Fail to attach rule to qp 0x%x\n", qpn);
  2587. goto ex_put;
  2588. }
  2589. err = add_mcg_res(dev, slave, rqp, gid, prot, type, reg_id);
  2590. if (err)
  2591. goto ex_detach;
  2592. } else {
  2593. err = rem_mcg_res(dev, slave, rqp, gid, prot, type, &reg_id);
  2594. if (err)
  2595. goto ex_put;
  2596. err = qp_detach(dev, &qp, gid, prot, type, reg_id);
  2597. if (err)
  2598. pr_err("Fail to detach rule from qp 0x%x reg_id = 0x%llx\n",
  2599. qpn, reg_id);
  2600. }
  2601. put_res(dev, slave, qpn, RES_QP);
  2602. return err;
  2603. ex_detach:
  2604. qp_detach(dev, &qp, gid, prot, type, reg_id);
  2605. ex_put:
  2606. put_res(dev, slave, qpn, RES_QP);
  2607. return err;
  2608. }
  2609. /*
  2610. * MAC validation for Flow Steering rules.
  2611. * VF can attach rules only with a mac address which is assigned to it.
  2612. */
  2613. static int validate_eth_header_mac(int slave, struct _rule_hw *eth_header,
  2614. struct list_head *rlist)
  2615. {
  2616. struct mac_res *res, *tmp;
  2617. __be64 be_mac;
  2618. /* make sure it isn't multicast or broadcast mac*/
  2619. if (!is_multicast_ether_addr(eth_header->eth.dst_mac) &&
  2620. !is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
  2621. list_for_each_entry_safe(res, tmp, rlist, list) {
  2622. be_mac = cpu_to_be64(res->mac << 16);
  2623. if (!memcmp(&be_mac, eth_header->eth.dst_mac, ETH_ALEN))
  2624. return 0;
  2625. }
  2626. pr_err("MAC %pM doesn't belong to VF %d, Steering rule rejected\n",
  2627. eth_header->eth.dst_mac, slave);
  2628. return -EINVAL;
  2629. }
  2630. return 0;
  2631. }
  2632. /*
  2633. * In case of missing eth header, append eth header with a MAC address
  2634. * assigned to the VF.
  2635. */
  2636. static int add_eth_header(struct mlx4_dev *dev, int slave,
  2637. struct mlx4_cmd_mailbox *inbox,
  2638. struct list_head *rlist, int header_id)
  2639. {
  2640. struct mac_res *res, *tmp;
  2641. u8 port;
  2642. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  2643. struct mlx4_net_trans_rule_hw_eth *eth_header;
  2644. struct mlx4_net_trans_rule_hw_ipv4 *ip_header;
  2645. struct mlx4_net_trans_rule_hw_tcp_udp *l4_header;
  2646. __be64 be_mac = 0;
  2647. __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
  2648. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  2649. port = ctrl->port;
  2650. eth_header = (struct mlx4_net_trans_rule_hw_eth *)(ctrl + 1);
  2651. /* Clear a space in the inbox for eth header */
  2652. switch (header_id) {
  2653. case MLX4_NET_TRANS_RULE_ID_IPV4:
  2654. ip_header =
  2655. (struct mlx4_net_trans_rule_hw_ipv4 *)(eth_header + 1);
  2656. memmove(ip_header, eth_header,
  2657. sizeof(*ip_header) + sizeof(*l4_header));
  2658. break;
  2659. case MLX4_NET_TRANS_RULE_ID_TCP:
  2660. case MLX4_NET_TRANS_RULE_ID_UDP:
  2661. l4_header = (struct mlx4_net_trans_rule_hw_tcp_udp *)
  2662. (eth_header + 1);
  2663. memmove(l4_header, eth_header, sizeof(*l4_header));
  2664. break;
  2665. default:
  2666. return -EINVAL;
  2667. }
  2668. list_for_each_entry_safe(res, tmp, rlist, list) {
  2669. if (port == res->port) {
  2670. be_mac = cpu_to_be64(res->mac << 16);
  2671. break;
  2672. }
  2673. }
  2674. if (!be_mac) {
  2675. pr_err("Failed adding eth header to FS rule, Can't find matching MAC for port %d .\n",
  2676. port);
  2677. return -EINVAL;
  2678. }
  2679. memset(eth_header, 0, sizeof(*eth_header));
  2680. eth_header->size = sizeof(*eth_header) >> 2;
  2681. eth_header->id = cpu_to_be16(__sw_id_hw[MLX4_NET_TRANS_RULE_ID_ETH]);
  2682. memcpy(eth_header->dst_mac, &be_mac, ETH_ALEN);
  2683. memcpy(eth_header->dst_mac_msk, &mac_msk, ETH_ALEN);
  2684. return 0;
  2685. }
  2686. int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2687. struct mlx4_vhcr *vhcr,
  2688. struct mlx4_cmd_mailbox *inbox,
  2689. struct mlx4_cmd_mailbox *outbox,
  2690. struct mlx4_cmd_info *cmd)
  2691. {
  2692. struct mlx4_priv *priv = mlx4_priv(dev);
  2693. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2694. struct list_head *rlist = &tracker->slave_list[slave].res_list[RES_MAC];
  2695. int err;
  2696. int qpn;
  2697. struct res_qp *rqp;
  2698. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  2699. struct _rule_hw *rule_header;
  2700. int header_id;
  2701. if (dev->caps.steering_mode !=
  2702. MLX4_STEERING_MODE_DEVICE_MANAGED)
  2703. return -EOPNOTSUPP;
  2704. ctrl = (struct mlx4_net_trans_rule_hw_ctrl *)inbox->buf;
  2705. qpn = be32_to_cpu(ctrl->qpn) & 0xffffff;
  2706. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2707. if (err) {
  2708. pr_err("Steering rule with qpn 0x%x rejected.\n", qpn);
  2709. return err;
  2710. }
  2711. rule_header = (struct _rule_hw *)(ctrl + 1);
  2712. header_id = map_hw_to_sw_id(be16_to_cpu(rule_header->id));
  2713. switch (header_id) {
  2714. case MLX4_NET_TRANS_RULE_ID_ETH:
  2715. if (validate_eth_header_mac(slave, rule_header, rlist)) {
  2716. err = -EINVAL;
  2717. goto err_put;
  2718. }
  2719. break;
  2720. case MLX4_NET_TRANS_RULE_ID_IB:
  2721. break;
  2722. case MLX4_NET_TRANS_RULE_ID_IPV4:
  2723. case MLX4_NET_TRANS_RULE_ID_TCP:
  2724. case MLX4_NET_TRANS_RULE_ID_UDP:
  2725. pr_warn("Can't attach FS rule without L2 headers, adding L2 header.\n");
  2726. if (add_eth_header(dev, slave, inbox, rlist, header_id)) {
  2727. err = -EINVAL;
  2728. goto err_put;
  2729. }
  2730. vhcr->in_modifier +=
  2731. sizeof(struct mlx4_net_trans_rule_hw_eth) >> 2;
  2732. break;
  2733. default:
  2734. pr_err("Corrupted mailbox.\n");
  2735. err = -EINVAL;
  2736. goto err_put;
  2737. }
  2738. err = mlx4_cmd_imm(dev, inbox->dma, &vhcr->out_param,
  2739. vhcr->in_modifier, 0,
  2740. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  2741. MLX4_CMD_NATIVE);
  2742. if (err)
  2743. goto err_put;
  2744. err = add_res_range(dev, slave, vhcr->out_param, 1, RES_FS_RULE, qpn);
  2745. if (err) {
  2746. mlx4_err(dev, "Fail to add flow steering resources.\n ");
  2747. /* detach rule*/
  2748. mlx4_cmd(dev, vhcr->out_param, 0, 0,
  2749. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  2750. MLX4_CMD_NATIVE);
  2751. goto err_put;
  2752. }
  2753. atomic_inc(&rqp->ref_count);
  2754. err_put:
  2755. put_res(dev, slave, qpn, RES_QP);
  2756. return err;
  2757. }
  2758. int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
  2759. struct mlx4_vhcr *vhcr,
  2760. struct mlx4_cmd_mailbox *inbox,
  2761. struct mlx4_cmd_mailbox *outbox,
  2762. struct mlx4_cmd_info *cmd)
  2763. {
  2764. int err;
  2765. struct res_qp *rqp;
  2766. struct res_fs_rule *rrule;
  2767. if (dev->caps.steering_mode !=
  2768. MLX4_STEERING_MODE_DEVICE_MANAGED)
  2769. return -EOPNOTSUPP;
  2770. err = get_res(dev, slave, vhcr->in_param, RES_FS_RULE, &rrule);
  2771. if (err)
  2772. return err;
  2773. /* Release the rule form busy state before removal */
  2774. put_res(dev, slave, vhcr->in_param, RES_FS_RULE);
  2775. err = get_res(dev, slave, rrule->qpn, RES_QP, &rqp);
  2776. if (err)
  2777. return err;
  2778. err = rem_res_range(dev, slave, vhcr->in_param, 1, RES_FS_RULE, 0);
  2779. if (err) {
  2780. mlx4_err(dev, "Fail to remove flow steering resources.\n ");
  2781. goto out;
  2782. }
  2783. err = mlx4_cmd(dev, vhcr->in_param, 0, 0,
  2784. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  2785. MLX4_CMD_NATIVE);
  2786. if (!err)
  2787. atomic_dec(&rqp->ref_count);
  2788. out:
  2789. put_res(dev, slave, rrule->qpn, RES_QP);
  2790. return err;
  2791. }
  2792. enum {
  2793. BUSY_MAX_RETRIES = 10
  2794. };
  2795. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2796. struct mlx4_vhcr *vhcr,
  2797. struct mlx4_cmd_mailbox *inbox,
  2798. struct mlx4_cmd_mailbox *outbox,
  2799. struct mlx4_cmd_info *cmd)
  2800. {
  2801. int err;
  2802. int index = vhcr->in_modifier & 0xffff;
  2803. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2804. if (err)
  2805. return err;
  2806. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2807. put_res(dev, slave, index, RES_COUNTER);
  2808. return err;
  2809. }
  2810. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2811. {
  2812. struct res_gid *rgid;
  2813. struct res_gid *tmp;
  2814. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2815. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2816. switch (dev->caps.steering_mode) {
  2817. case MLX4_STEERING_MODE_DEVICE_MANAGED:
  2818. mlx4_flow_detach(dev, rgid->reg_id);
  2819. break;
  2820. case MLX4_STEERING_MODE_B0:
  2821. qp.qpn = rqp->local_qpn;
  2822. (void) mlx4_qp_detach_common(dev, &qp, rgid->gid,
  2823. rgid->prot, rgid->steer);
  2824. break;
  2825. }
  2826. list_del(&rgid->list);
  2827. kfree(rgid);
  2828. }
  2829. }
  2830. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2831. enum mlx4_resource type, int print)
  2832. {
  2833. struct mlx4_priv *priv = mlx4_priv(dev);
  2834. struct mlx4_resource_tracker *tracker =
  2835. &priv->mfunc.master.res_tracker;
  2836. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2837. struct res_common *r;
  2838. struct res_common *tmp;
  2839. int busy;
  2840. busy = 0;
  2841. spin_lock_irq(mlx4_tlock(dev));
  2842. list_for_each_entry_safe(r, tmp, rlist, list) {
  2843. if (r->owner == slave) {
  2844. if (!r->removing) {
  2845. if (r->state == RES_ANY_BUSY) {
  2846. if (print)
  2847. mlx4_dbg(dev,
  2848. "%s id 0x%llx is busy\n",
  2849. ResourceType(type),
  2850. r->res_id);
  2851. ++busy;
  2852. } else {
  2853. r->from_state = r->state;
  2854. r->state = RES_ANY_BUSY;
  2855. r->removing = 1;
  2856. }
  2857. }
  2858. }
  2859. }
  2860. spin_unlock_irq(mlx4_tlock(dev));
  2861. return busy;
  2862. }
  2863. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2864. enum mlx4_resource type)
  2865. {
  2866. unsigned long begin;
  2867. int busy;
  2868. begin = jiffies;
  2869. do {
  2870. busy = _move_all_busy(dev, slave, type, 0);
  2871. if (time_after(jiffies, begin + 5 * HZ))
  2872. break;
  2873. if (busy)
  2874. cond_resched();
  2875. } while (busy);
  2876. if (busy)
  2877. busy = _move_all_busy(dev, slave, type, 1);
  2878. return busy;
  2879. }
  2880. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2881. {
  2882. struct mlx4_priv *priv = mlx4_priv(dev);
  2883. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2884. struct list_head *qp_list =
  2885. &tracker->slave_list[slave].res_list[RES_QP];
  2886. struct res_qp *qp;
  2887. struct res_qp *tmp;
  2888. int state;
  2889. u64 in_param;
  2890. int qpn;
  2891. int err;
  2892. err = move_all_busy(dev, slave, RES_QP);
  2893. if (err)
  2894. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2895. "for slave %d\n", slave);
  2896. spin_lock_irq(mlx4_tlock(dev));
  2897. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2898. spin_unlock_irq(mlx4_tlock(dev));
  2899. if (qp->com.owner == slave) {
  2900. qpn = qp->com.res_id;
  2901. detach_qp(dev, slave, qp);
  2902. state = qp->com.from_state;
  2903. while (state != 0) {
  2904. switch (state) {
  2905. case RES_QP_RESERVED:
  2906. spin_lock_irq(mlx4_tlock(dev));
  2907. rb_erase(&qp->com.node,
  2908. &tracker->res_tree[RES_QP]);
  2909. list_del(&qp->com.list);
  2910. spin_unlock_irq(mlx4_tlock(dev));
  2911. kfree(qp);
  2912. state = 0;
  2913. break;
  2914. case RES_QP_MAPPED:
  2915. if (!valid_reserved(dev, slave, qpn))
  2916. __mlx4_qp_free_icm(dev, qpn);
  2917. state = RES_QP_RESERVED;
  2918. break;
  2919. case RES_QP_HW:
  2920. in_param = slave;
  2921. err = mlx4_cmd(dev, in_param,
  2922. qp->local_qpn, 2,
  2923. MLX4_CMD_2RST_QP,
  2924. MLX4_CMD_TIME_CLASS_A,
  2925. MLX4_CMD_NATIVE);
  2926. if (err)
  2927. mlx4_dbg(dev, "rem_slave_qps: failed"
  2928. " to move slave %d qpn %d to"
  2929. " reset\n", slave,
  2930. qp->local_qpn);
  2931. atomic_dec(&qp->rcq->ref_count);
  2932. atomic_dec(&qp->scq->ref_count);
  2933. atomic_dec(&qp->mtt->ref_count);
  2934. if (qp->srq)
  2935. atomic_dec(&qp->srq->ref_count);
  2936. state = RES_QP_MAPPED;
  2937. break;
  2938. default:
  2939. state = 0;
  2940. }
  2941. }
  2942. }
  2943. spin_lock_irq(mlx4_tlock(dev));
  2944. }
  2945. spin_unlock_irq(mlx4_tlock(dev));
  2946. }
  2947. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2948. {
  2949. struct mlx4_priv *priv = mlx4_priv(dev);
  2950. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2951. struct list_head *srq_list =
  2952. &tracker->slave_list[slave].res_list[RES_SRQ];
  2953. struct res_srq *srq;
  2954. struct res_srq *tmp;
  2955. int state;
  2956. u64 in_param;
  2957. LIST_HEAD(tlist);
  2958. int srqn;
  2959. int err;
  2960. err = move_all_busy(dev, slave, RES_SRQ);
  2961. if (err)
  2962. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2963. "busy for slave %d\n", slave);
  2964. spin_lock_irq(mlx4_tlock(dev));
  2965. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2966. spin_unlock_irq(mlx4_tlock(dev));
  2967. if (srq->com.owner == slave) {
  2968. srqn = srq->com.res_id;
  2969. state = srq->com.from_state;
  2970. while (state != 0) {
  2971. switch (state) {
  2972. case RES_SRQ_ALLOCATED:
  2973. __mlx4_srq_free_icm(dev, srqn);
  2974. spin_lock_irq(mlx4_tlock(dev));
  2975. rb_erase(&srq->com.node,
  2976. &tracker->res_tree[RES_SRQ]);
  2977. list_del(&srq->com.list);
  2978. spin_unlock_irq(mlx4_tlock(dev));
  2979. kfree(srq);
  2980. state = 0;
  2981. break;
  2982. case RES_SRQ_HW:
  2983. in_param = slave;
  2984. err = mlx4_cmd(dev, in_param, srqn, 1,
  2985. MLX4_CMD_HW2SW_SRQ,
  2986. MLX4_CMD_TIME_CLASS_A,
  2987. MLX4_CMD_NATIVE);
  2988. if (err)
  2989. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2990. " to move slave %d srq %d to"
  2991. " SW ownership\n",
  2992. slave, srqn);
  2993. atomic_dec(&srq->mtt->ref_count);
  2994. if (srq->cq)
  2995. atomic_dec(&srq->cq->ref_count);
  2996. state = RES_SRQ_ALLOCATED;
  2997. break;
  2998. default:
  2999. state = 0;
  3000. }
  3001. }
  3002. }
  3003. spin_lock_irq(mlx4_tlock(dev));
  3004. }
  3005. spin_unlock_irq(mlx4_tlock(dev));
  3006. }
  3007. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  3008. {
  3009. struct mlx4_priv *priv = mlx4_priv(dev);
  3010. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3011. struct list_head *cq_list =
  3012. &tracker->slave_list[slave].res_list[RES_CQ];
  3013. struct res_cq *cq;
  3014. struct res_cq *tmp;
  3015. int state;
  3016. u64 in_param;
  3017. LIST_HEAD(tlist);
  3018. int cqn;
  3019. int err;
  3020. err = move_all_busy(dev, slave, RES_CQ);
  3021. if (err)
  3022. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  3023. "busy for slave %d\n", slave);
  3024. spin_lock_irq(mlx4_tlock(dev));
  3025. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  3026. spin_unlock_irq(mlx4_tlock(dev));
  3027. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  3028. cqn = cq->com.res_id;
  3029. state = cq->com.from_state;
  3030. while (state != 0) {
  3031. switch (state) {
  3032. case RES_CQ_ALLOCATED:
  3033. __mlx4_cq_free_icm(dev, cqn);
  3034. spin_lock_irq(mlx4_tlock(dev));
  3035. rb_erase(&cq->com.node,
  3036. &tracker->res_tree[RES_CQ]);
  3037. list_del(&cq->com.list);
  3038. spin_unlock_irq(mlx4_tlock(dev));
  3039. kfree(cq);
  3040. state = 0;
  3041. break;
  3042. case RES_CQ_HW:
  3043. in_param = slave;
  3044. err = mlx4_cmd(dev, in_param, cqn, 1,
  3045. MLX4_CMD_HW2SW_CQ,
  3046. MLX4_CMD_TIME_CLASS_A,
  3047. MLX4_CMD_NATIVE);
  3048. if (err)
  3049. mlx4_dbg(dev, "rem_slave_cqs: failed"
  3050. " to move slave %d cq %d to"
  3051. " SW ownership\n",
  3052. slave, cqn);
  3053. atomic_dec(&cq->mtt->ref_count);
  3054. state = RES_CQ_ALLOCATED;
  3055. break;
  3056. default:
  3057. state = 0;
  3058. }
  3059. }
  3060. }
  3061. spin_lock_irq(mlx4_tlock(dev));
  3062. }
  3063. spin_unlock_irq(mlx4_tlock(dev));
  3064. }
  3065. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  3066. {
  3067. struct mlx4_priv *priv = mlx4_priv(dev);
  3068. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3069. struct list_head *mpt_list =
  3070. &tracker->slave_list[slave].res_list[RES_MPT];
  3071. struct res_mpt *mpt;
  3072. struct res_mpt *tmp;
  3073. int state;
  3074. u64 in_param;
  3075. LIST_HEAD(tlist);
  3076. int mptn;
  3077. int err;
  3078. err = move_all_busy(dev, slave, RES_MPT);
  3079. if (err)
  3080. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  3081. "busy for slave %d\n", slave);
  3082. spin_lock_irq(mlx4_tlock(dev));
  3083. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  3084. spin_unlock_irq(mlx4_tlock(dev));
  3085. if (mpt->com.owner == slave) {
  3086. mptn = mpt->com.res_id;
  3087. state = mpt->com.from_state;
  3088. while (state != 0) {
  3089. switch (state) {
  3090. case RES_MPT_RESERVED:
  3091. __mlx4_mpt_release(dev, mpt->key);
  3092. spin_lock_irq(mlx4_tlock(dev));
  3093. rb_erase(&mpt->com.node,
  3094. &tracker->res_tree[RES_MPT]);
  3095. list_del(&mpt->com.list);
  3096. spin_unlock_irq(mlx4_tlock(dev));
  3097. kfree(mpt);
  3098. state = 0;
  3099. break;
  3100. case RES_MPT_MAPPED:
  3101. __mlx4_mpt_free_icm(dev, mpt->key);
  3102. state = RES_MPT_RESERVED;
  3103. break;
  3104. case RES_MPT_HW:
  3105. in_param = slave;
  3106. err = mlx4_cmd(dev, in_param, mptn, 0,
  3107. MLX4_CMD_HW2SW_MPT,
  3108. MLX4_CMD_TIME_CLASS_A,
  3109. MLX4_CMD_NATIVE);
  3110. if (err)
  3111. mlx4_dbg(dev, "rem_slave_mrs: failed"
  3112. " to move slave %d mpt %d to"
  3113. " SW ownership\n",
  3114. slave, mptn);
  3115. if (mpt->mtt)
  3116. atomic_dec(&mpt->mtt->ref_count);
  3117. state = RES_MPT_MAPPED;
  3118. break;
  3119. default:
  3120. state = 0;
  3121. }
  3122. }
  3123. }
  3124. spin_lock_irq(mlx4_tlock(dev));
  3125. }
  3126. spin_unlock_irq(mlx4_tlock(dev));
  3127. }
  3128. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  3129. {
  3130. struct mlx4_priv *priv = mlx4_priv(dev);
  3131. struct mlx4_resource_tracker *tracker =
  3132. &priv->mfunc.master.res_tracker;
  3133. struct list_head *mtt_list =
  3134. &tracker->slave_list[slave].res_list[RES_MTT];
  3135. struct res_mtt *mtt;
  3136. struct res_mtt *tmp;
  3137. int state;
  3138. LIST_HEAD(tlist);
  3139. int base;
  3140. int err;
  3141. err = move_all_busy(dev, slave, RES_MTT);
  3142. if (err)
  3143. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  3144. "busy for slave %d\n", slave);
  3145. spin_lock_irq(mlx4_tlock(dev));
  3146. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  3147. spin_unlock_irq(mlx4_tlock(dev));
  3148. if (mtt->com.owner == slave) {
  3149. base = mtt->com.res_id;
  3150. state = mtt->com.from_state;
  3151. while (state != 0) {
  3152. switch (state) {
  3153. case RES_MTT_ALLOCATED:
  3154. __mlx4_free_mtt_range(dev, base,
  3155. mtt->order);
  3156. spin_lock_irq(mlx4_tlock(dev));
  3157. rb_erase(&mtt->com.node,
  3158. &tracker->res_tree[RES_MTT]);
  3159. list_del(&mtt->com.list);
  3160. spin_unlock_irq(mlx4_tlock(dev));
  3161. kfree(mtt);
  3162. state = 0;
  3163. break;
  3164. default:
  3165. state = 0;
  3166. }
  3167. }
  3168. }
  3169. spin_lock_irq(mlx4_tlock(dev));
  3170. }
  3171. spin_unlock_irq(mlx4_tlock(dev));
  3172. }
  3173. static void rem_slave_fs_rule(struct mlx4_dev *dev, int slave)
  3174. {
  3175. struct mlx4_priv *priv = mlx4_priv(dev);
  3176. struct mlx4_resource_tracker *tracker =
  3177. &priv->mfunc.master.res_tracker;
  3178. struct list_head *fs_rule_list =
  3179. &tracker->slave_list[slave].res_list[RES_FS_RULE];
  3180. struct res_fs_rule *fs_rule;
  3181. struct res_fs_rule *tmp;
  3182. int state;
  3183. u64 base;
  3184. int err;
  3185. err = move_all_busy(dev, slave, RES_FS_RULE);
  3186. if (err)
  3187. mlx4_warn(dev, "rem_slave_fs_rule: Could not move all mtts to busy for slave %d\n",
  3188. slave);
  3189. spin_lock_irq(mlx4_tlock(dev));
  3190. list_for_each_entry_safe(fs_rule, tmp, fs_rule_list, com.list) {
  3191. spin_unlock_irq(mlx4_tlock(dev));
  3192. if (fs_rule->com.owner == slave) {
  3193. base = fs_rule->com.res_id;
  3194. state = fs_rule->com.from_state;
  3195. while (state != 0) {
  3196. switch (state) {
  3197. case RES_FS_RULE_ALLOCATED:
  3198. /* detach rule */
  3199. err = mlx4_cmd(dev, base, 0, 0,
  3200. MLX4_QP_FLOW_STEERING_DETACH,
  3201. MLX4_CMD_TIME_CLASS_A,
  3202. MLX4_CMD_NATIVE);
  3203. spin_lock_irq(mlx4_tlock(dev));
  3204. rb_erase(&fs_rule->com.node,
  3205. &tracker->res_tree[RES_FS_RULE]);
  3206. list_del(&fs_rule->com.list);
  3207. spin_unlock_irq(mlx4_tlock(dev));
  3208. kfree(fs_rule);
  3209. state = 0;
  3210. break;
  3211. default:
  3212. state = 0;
  3213. }
  3214. }
  3215. }
  3216. spin_lock_irq(mlx4_tlock(dev));
  3217. }
  3218. spin_unlock_irq(mlx4_tlock(dev));
  3219. }
  3220. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  3221. {
  3222. struct mlx4_priv *priv = mlx4_priv(dev);
  3223. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3224. struct list_head *eq_list =
  3225. &tracker->slave_list[slave].res_list[RES_EQ];
  3226. struct res_eq *eq;
  3227. struct res_eq *tmp;
  3228. int err;
  3229. int state;
  3230. LIST_HEAD(tlist);
  3231. int eqn;
  3232. struct mlx4_cmd_mailbox *mailbox;
  3233. err = move_all_busy(dev, slave, RES_EQ);
  3234. if (err)
  3235. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  3236. "busy for slave %d\n", slave);
  3237. spin_lock_irq(mlx4_tlock(dev));
  3238. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  3239. spin_unlock_irq(mlx4_tlock(dev));
  3240. if (eq->com.owner == slave) {
  3241. eqn = eq->com.res_id;
  3242. state = eq->com.from_state;
  3243. while (state != 0) {
  3244. switch (state) {
  3245. case RES_EQ_RESERVED:
  3246. spin_lock_irq(mlx4_tlock(dev));
  3247. rb_erase(&eq->com.node,
  3248. &tracker->res_tree[RES_EQ]);
  3249. list_del(&eq->com.list);
  3250. spin_unlock_irq(mlx4_tlock(dev));
  3251. kfree(eq);
  3252. state = 0;
  3253. break;
  3254. case RES_EQ_HW:
  3255. mailbox = mlx4_alloc_cmd_mailbox(dev);
  3256. if (IS_ERR(mailbox)) {
  3257. cond_resched();
  3258. continue;
  3259. }
  3260. err = mlx4_cmd_box(dev, slave, 0,
  3261. eqn & 0xff, 0,
  3262. MLX4_CMD_HW2SW_EQ,
  3263. MLX4_CMD_TIME_CLASS_A,
  3264. MLX4_CMD_NATIVE);
  3265. if (err)
  3266. mlx4_dbg(dev, "rem_slave_eqs: failed"
  3267. " to move slave %d eqs %d to"
  3268. " SW ownership\n", slave, eqn);
  3269. mlx4_free_cmd_mailbox(dev, mailbox);
  3270. atomic_dec(&eq->mtt->ref_count);
  3271. state = RES_EQ_RESERVED;
  3272. break;
  3273. default:
  3274. state = 0;
  3275. }
  3276. }
  3277. }
  3278. spin_lock_irq(mlx4_tlock(dev));
  3279. }
  3280. spin_unlock_irq(mlx4_tlock(dev));
  3281. }
  3282. static void rem_slave_counters(struct mlx4_dev *dev, int slave)
  3283. {
  3284. struct mlx4_priv *priv = mlx4_priv(dev);
  3285. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3286. struct list_head *counter_list =
  3287. &tracker->slave_list[slave].res_list[RES_COUNTER];
  3288. struct res_counter *counter;
  3289. struct res_counter *tmp;
  3290. int err;
  3291. int index;
  3292. err = move_all_busy(dev, slave, RES_COUNTER);
  3293. if (err)
  3294. mlx4_warn(dev, "rem_slave_counters: Could not move all counters to "
  3295. "busy for slave %d\n", slave);
  3296. spin_lock_irq(mlx4_tlock(dev));
  3297. list_for_each_entry_safe(counter, tmp, counter_list, com.list) {
  3298. if (counter->com.owner == slave) {
  3299. index = counter->com.res_id;
  3300. rb_erase(&counter->com.node,
  3301. &tracker->res_tree[RES_COUNTER]);
  3302. list_del(&counter->com.list);
  3303. kfree(counter);
  3304. __mlx4_counter_free(dev, index);
  3305. }
  3306. }
  3307. spin_unlock_irq(mlx4_tlock(dev));
  3308. }
  3309. static void rem_slave_xrcdns(struct mlx4_dev *dev, int slave)
  3310. {
  3311. struct mlx4_priv *priv = mlx4_priv(dev);
  3312. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  3313. struct list_head *xrcdn_list =
  3314. &tracker->slave_list[slave].res_list[RES_XRCD];
  3315. struct res_xrcdn *xrcd;
  3316. struct res_xrcdn *tmp;
  3317. int err;
  3318. int xrcdn;
  3319. err = move_all_busy(dev, slave, RES_XRCD);
  3320. if (err)
  3321. mlx4_warn(dev, "rem_slave_xrcdns: Could not move all xrcdns to "
  3322. "busy for slave %d\n", slave);
  3323. spin_lock_irq(mlx4_tlock(dev));
  3324. list_for_each_entry_safe(xrcd, tmp, xrcdn_list, com.list) {
  3325. if (xrcd->com.owner == slave) {
  3326. xrcdn = xrcd->com.res_id;
  3327. rb_erase(&xrcd->com.node, &tracker->res_tree[RES_XRCD]);
  3328. list_del(&xrcd->com.list);
  3329. kfree(xrcd);
  3330. __mlx4_xrcd_free(dev, xrcdn);
  3331. }
  3332. }
  3333. spin_unlock_irq(mlx4_tlock(dev));
  3334. }
  3335. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  3336. {
  3337. struct mlx4_priv *priv = mlx4_priv(dev);
  3338. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3339. /*VLAN*/
  3340. rem_slave_macs(dev, slave);
  3341. rem_slave_fs_rule(dev, slave);
  3342. rem_slave_qps(dev, slave);
  3343. rem_slave_srqs(dev, slave);
  3344. rem_slave_cqs(dev, slave);
  3345. rem_slave_mrs(dev, slave);
  3346. rem_slave_eqs(dev, slave);
  3347. rem_slave_mtts(dev, slave);
  3348. rem_slave_counters(dev, slave);
  3349. rem_slave_xrcdns(dev, slave);
  3350. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  3351. }