vmxnet3_drv.c 86 KB

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  1. /*
  2. * Linux driver for VMware's vmxnet3 ethernet NIC.
  3. *
  4. * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; version 2 of the License and no later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  13. * NON INFRINGEMENT. See the GNU General Public License for more
  14. * details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19. *
  20. * The full GNU General Public License is included in this distribution in
  21. * the file called "COPYING".
  22. *
  23. * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
  24. *
  25. */
  26. #include <net/ip6_checksum.h>
  27. #include "vmxnet3_int.h"
  28. char vmxnet3_driver_name[] = "vmxnet3";
  29. #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
  30. /*
  31. * PCI Device ID Table
  32. * Last entry must be all 0s
  33. */
  34. static DEFINE_PCI_DEVICE_TABLE(vmxnet3_pciid_table) = {
  35. {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
  36. {0}
  37. };
  38. MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
  39. static atomic_t devices_found;
  40. #define VMXNET3_MAX_DEVICES 10
  41. static int enable_mq = 1;
  42. static int irq_share_mode;
  43. /*
  44. * Enable/Disable the given intr
  45. */
  46. static void
  47. vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
  48. {
  49. VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
  50. }
  51. static void
  52. vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
  53. {
  54. VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
  55. }
  56. /*
  57. * Enable/Disable all intrs used by the device
  58. */
  59. static void
  60. vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
  61. {
  62. int i;
  63. for (i = 0; i < adapter->intr.num_intrs; i++)
  64. vmxnet3_enable_intr(adapter, i);
  65. adapter->shared->devRead.intrConf.intrCtrl &=
  66. cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
  67. }
  68. static void
  69. vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
  70. {
  71. int i;
  72. adapter->shared->devRead.intrConf.intrCtrl |=
  73. cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
  74. for (i = 0; i < adapter->intr.num_intrs; i++)
  75. vmxnet3_disable_intr(adapter, i);
  76. }
  77. static void
  78. vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
  79. {
  80. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
  81. }
  82. static bool
  83. vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
  84. {
  85. return tq->stopped;
  86. }
  87. static void
  88. vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
  89. {
  90. tq->stopped = false;
  91. netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
  92. }
  93. static void
  94. vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
  95. {
  96. tq->stopped = false;
  97. netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
  98. }
  99. static void
  100. vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
  101. {
  102. tq->stopped = true;
  103. tq->num_stop++;
  104. netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
  105. }
  106. /*
  107. * Check the link state. This may start or stop the tx queue.
  108. */
  109. static void
  110. vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
  111. {
  112. u32 ret;
  113. int i;
  114. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
  115. ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
  116. adapter->link_speed = ret >> 16;
  117. if (ret & 1) { /* Link is up. */
  118. printk(KERN_INFO "%s: NIC Link is Up %d Mbps\n",
  119. adapter->netdev->name, adapter->link_speed);
  120. if (!netif_carrier_ok(adapter->netdev))
  121. netif_carrier_on(adapter->netdev);
  122. if (affectTxQueue) {
  123. for (i = 0; i < adapter->num_tx_queues; i++)
  124. vmxnet3_tq_start(&adapter->tx_queue[i],
  125. adapter);
  126. }
  127. } else {
  128. printk(KERN_INFO "%s: NIC Link is Down\n",
  129. adapter->netdev->name);
  130. if (netif_carrier_ok(adapter->netdev))
  131. netif_carrier_off(adapter->netdev);
  132. if (affectTxQueue) {
  133. for (i = 0; i < adapter->num_tx_queues; i++)
  134. vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
  135. }
  136. }
  137. }
  138. static void
  139. vmxnet3_process_events(struct vmxnet3_adapter *adapter)
  140. {
  141. int i;
  142. u32 events = le32_to_cpu(adapter->shared->ecr);
  143. if (!events)
  144. return;
  145. vmxnet3_ack_events(adapter, events);
  146. /* Check if link state has changed */
  147. if (events & VMXNET3_ECR_LINK)
  148. vmxnet3_check_link(adapter, true);
  149. /* Check if there is an error on xmit/recv queues */
  150. if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
  151. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  152. VMXNET3_CMD_GET_QUEUE_STATUS);
  153. for (i = 0; i < adapter->num_tx_queues; i++)
  154. if (adapter->tqd_start[i].status.stopped)
  155. dev_err(&adapter->netdev->dev,
  156. "%s: tq[%d] error 0x%x\n",
  157. adapter->netdev->name, i, le32_to_cpu(
  158. adapter->tqd_start[i].status.error));
  159. for (i = 0; i < adapter->num_rx_queues; i++)
  160. if (adapter->rqd_start[i].status.stopped)
  161. dev_err(&adapter->netdev->dev,
  162. "%s: rq[%d] error 0x%x\n",
  163. adapter->netdev->name, i,
  164. adapter->rqd_start[i].status.error);
  165. schedule_work(&adapter->work);
  166. }
  167. }
  168. #ifdef __BIG_ENDIAN_BITFIELD
  169. /*
  170. * The device expects the bitfields in shared structures to be written in
  171. * little endian. When CPU is big endian, the following routines are used to
  172. * correctly read and write into ABI.
  173. * The general technique used here is : double word bitfields are defined in
  174. * opposite order for big endian architecture. Then before reading them in
  175. * driver the complete double word is translated using le32_to_cpu. Similarly
  176. * After the driver writes into bitfields, cpu_to_le32 is used to translate the
  177. * double words into required format.
  178. * In order to avoid touching bits in shared structure more than once, temporary
  179. * descriptors are used. These are passed as srcDesc to following functions.
  180. */
  181. static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
  182. struct Vmxnet3_RxDesc *dstDesc)
  183. {
  184. u32 *src = (u32 *)srcDesc + 2;
  185. u32 *dst = (u32 *)dstDesc + 2;
  186. dstDesc->addr = le64_to_cpu(srcDesc->addr);
  187. *dst = le32_to_cpu(*src);
  188. dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
  189. }
  190. static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
  191. struct Vmxnet3_TxDesc *dstDesc)
  192. {
  193. int i;
  194. u32 *src = (u32 *)(srcDesc + 1);
  195. u32 *dst = (u32 *)(dstDesc + 1);
  196. /* Working backwards so that the gen bit is set at the end. */
  197. for (i = 2; i > 0; i--) {
  198. src--;
  199. dst--;
  200. *dst = cpu_to_le32(*src);
  201. }
  202. }
  203. static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
  204. struct Vmxnet3_RxCompDesc *dstDesc)
  205. {
  206. int i = 0;
  207. u32 *src = (u32 *)srcDesc;
  208. u32 *dst = (u32 *)dstDesc;
  209. for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
  210. *dst = le32_to_cpu(*src);
  211. src++;
  212. dst++;
  213. }
  214. }
  215. /* Used to read bitfield values from double words. */
  216. static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
  217. {
  218. u32 temp = le32_to_cpu(*bitfield);
  219. u32 mask = ((1 << size) - 1) << pos;
  220. temp &= mask;
  221. temp >>= pos;
  222. return temp;
  223. }
  224. #endif /* __BIG_ENDIAN_BITFIELD */
  225. #ifdef __BIG_ENDIAN_BITFIELD
  226. # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
  227. txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
  228. VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
  229. # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
  230. txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
  231. VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
  232. # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
  233. VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
  234. VMXNET3_TCD_GEN_SIZE)
  235. # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
  236. VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
  237. # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
  238. (dstrcd) = (tmp); \
  239. vmxnet3_RxCompToCPU((rcd), (tmp)); \
  240. } while (0)
  241. # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
  242. (dstrxd) = (tmp); \
  243. vmxnet3_RxDescToCPU((rxd), (tmp)); \
  244. } while (0)
  245. #else
  246. # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
  247. # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
  248. # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
  249. # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
  250. # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
  251. # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
  252. #endif /* __BIG_ENDIAN_BITFIELD */
  253. static void
  254. vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
  255. struct pci_dev *pdev)
  256. {
  257. if (tbi->map_type == VMXNET3_MAP_SINGLE)
  258. pci_unmap_single(pdev, tbi->dma_addr, tbi->len,
  259. PCI_DMA_TODEVICE);
  260. else if (tbi->map_type == VMXNET3_MAP_PAGE)
  261. pci_unmap_page(pdev, tbi->dma_addr, tbi->len,
  262. PCI_DMA_TODEVICE);
  263. else
  264. BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
  265. tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
  266. }
  267. static int
  268. vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
  269. struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
  270. {
  271. struct sk_buff *skb;
  272. int entries = 0;
  273. /* no out of order completion */
  274. BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
  275. BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
  276. skb = tq->buf_info[eop_idx].skb;
  277. BUG_ON(skb == NULL);
  278. tq->buf_info[eop_idx].skb = NULL;
  279. VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
  280. while (tq->tx_ring.next2comp != eop_idx) {
  281. vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
  282. pdev);
  283. /* update next2comp w/o tx_lock. Since we are marking more,
  284. * instead of less, tx ring entries avail, the worst case is
  285. * that the tx routine incorrectly re-queues a pkt due to
  286. * insufficient tx ring entries.
  287. */
  288. vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
  289. entries++;
  290. }
  291. dev_kfree_skb_any(skb);
  292. return entries;
  293. }
  294. static int
  295. vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
  296. struct vmxnet3_adapter *adapter)
  297. {
  298. int completed = 0;
  299. union Vmxnet3_GenericDesc *gdesc;
  300. gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
  301. while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
  302. completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
  303. &gdesc->tcd), tq, adapter->pdev,
  304. adapter);
  305. vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
  306. gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
  307. }
  308. if (completed) {
  309. spin_lock(&tq->tx_lock);
  310. if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
  311. vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
  312. VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
  313. netif_carrier_ok(adapter->netdev))) {
  314. vmxnet3_tq_wake(tq, adapter);
  315. }
  316. spin_unlock(&tq->tx_lock);
  317. }
  318. return completed;
  319. }
  320. static void
  321. vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
  322. struct vmxnet3_adapter *adapter)
  323. {
  324. int i;
  325. while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
  326. struct vmxnet3_tx_buf_info *tbi;
  327. union Vmxnet3_GenericDesc *gdesc;
  328. tbi = tq->buf_info + tq->tx_ring.next2comp;
  329. gdesc = tq->tx_ring.base + tq->tx_ring.next2comp;
  330. vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
  331. if (tbi->skb) {
  332. dev_kfree_skb_any(tbi->skb);
  333. tbi->skb = NULL;
  334. }
  335. vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
  336. }
  337. /* sanity check, verify all buffers are indeed unmapped and freed */
  338. for (i = 0; i < tq->tx_ring.size; i++) {
  339. BUG_ON(tq->buf_info[i].skb != NULL ||
  340. tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
  341. }
  342. tq->tx_ring.gen = VMXNET3_INIT_GEN;
  343. tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
  344. tq->comp_ring.gen = VMXNET3_INIT_GEN;
  345. tq->comp_ring.next2proc = 0;
  346. }
  347. static void
  348. vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
  349. struct vmxnet3_adapter *adapter)
  350. {
  351. if (tq->tx_ring.base) {
  352. pci_free_consistent(adapter->pdev, tq->tx_ring.size *
  353. sizeof(struct Vmxnet3_TxDesc),
  354. tq->tx_ring.base, tq->tx_ring.basePA);
  355. tq->tx_ring.base = NULL;
  356. }
  357. if (tq->data_ring.base) {
  358. pci_free_consistent(adapter->pdev, tq->data_ring.size *
  359. sizeof(struct Vmxnet3_TxDataDesc),
  360. tq->data_ring.base, tq->data_ring.basePA);
  361. tq->data_ring.base = NULL;
  362. }
  363. if (tq->comp_ring.base) {
  364. pci_free_consistent(adapter->pdev, tq->comp_ring.size *
  365. sizeof(struct Vmxnet3_TxCompDesc),
  366. tq->comp_ring.base, tq->comp_ring.basePA);
  367. tq->comp_ring.base = NULL;
  368. }
  369. kfree(tq->buf_info);
  370. tq->buf_info = NULL;
  371. }
  372. /* Destroy all tx queues */
  373. void
  374. vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
  375. {
  376. int i;
  377. for (i = 0; i < adapter->num_tx_queues; i++)
  378. vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
  379. }
  380. static void
  381. vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
  382. struct vmxnet3_adapter *adapter)
  383. {
  384. int i;
  385. /* reset the tx ring contents to 0 and reset the tx ring states */
  386. memset(tq->tx_ring.base, 0, tq->tx_ring.size *
  387. sizeof(struct Vmxnet3_TxDesc));
  388. tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
  389. tq->tx_ring.gen = VMXNET3_INIT_GEN;
  390. memset(tq->data_ring.base, 0, tq->data_ring.size *
  391. sizeof(struct Vmxnet3_TxDataDesc));
  392. /* reset the tx comp ring contents to 0 and reset comp ring states */
  393. memset(tq->comp_ring.base, 0, tq->comp_ring.size *
  394. sizeof(struct Vmxnet3_TxCompDesc));
  395. tq->comp_ring.next2proc = 0;
  396. tq->comp_ring.gen = VMXNET3_INIT_GEN;
  397. /* reset the bookkeeping data */
  398. memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
  399. for (i = 0; i < tq->tx_ring.size; i++)
  400. tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
  401. /* stats are not reset */
  402. }
  403. static int
  404. vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
  405. struct vmxnet3_adapter *adapter)
  406. {
  407. BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
  408. tq->comp_ring.base || tq->buf_info);
  409. tq->tx_ring.base = pci_alloc_consistent(adapter->pdev, tq->tx_ring.size
  410. * sizeof(struct Vmxnet3_TxDesc),
  411. &tq->tx_ring.basePA);
  412. if (!tq->tx_ring.base) {
  413. printk(KERN_ERR "%s: failed to allocate tx ring\n",
  414. adapter->netdev->name);
  415. goto err;
  416. }
  417. tq->data_ring.base = pci_alloc_consistent(adapter->pdev,
  418. tq->data_ring.size *
  419. sizeof(struct Vmxnet3_TxDataDesc),
  420. &tq->data_ring.basePA);
  421. if (!tq->data_ring.base) {
  422. printk(KERN_ERR "%s: failed to allocate data ring\n",
  423. adapter->netdev->name);
  424. goto err;
  425. }
  426. tq->comp_ring.base = pci_alloc_consistent(adapter->pdev,
  427. tq->comp_ring.size *
  428. sizeof(struct Vmxnet3_TxCompDesc),
  429. &tq->comp_ring.basePA);
  430. if (!tq->comp_ring.base) {
  431. printk(KERN_ERR "%s: failed to allocate tx comp ring\n",
  432. adapter->netdev->name);
  433. goto err;
  434. }
  435. tq->buf_info = kcalloc(tq->tx_ring.size, sizeof(tq->buf_info[0]),
  436. GFP_KERNEL);
  437. if (!tq->buf_info) {
  438. printk(KERN_ERR "%s: failed to allocate tx bufinfo\n",
  439. adapter->netdev->name);
  440. goto err;
  441. }
  442. return 0;
  443. err:
  444. vmxnet3_tq_destroy(tq, adapter);
  445. return -ENOMEM;
  446. }
  447. static void
  448. vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
  449. {
  450. int i;
  451. for (i = 0; i < adapter->num_tx_queues; i++)
  452. vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
  453. }
  454. /*
  455. * starting from ring->next2fill, allocate rx buffers for the given ring
  456. * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
  457. * are allocated or allocation fails
  458. */
  459. static int
  460. vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
  461. int num_to_alloc, struct vmxnet3_adapter *adapter)
  462. {
  463. int num_allocated = 0;
  464. struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
  465. struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
  466. u32 val;
  467. while (num_allocated < num_to_alloc) {
  468. struct vmxnet3_rx_buf_info *rbi;
  469. union Vmxnet3_GenericDesc *gd;
  470. rbi = rbi_base + ring->next2fill;
  471. gd = ring->base + ring->next2fill;
  472. if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
  473. if (rbi->skb == NULL) {
  474. rbi->skb = dev_alloc_skb(rbi->len +
  475. NET_IP_ALIGN);
  476. if (unlikely(rbi->skb == NULL)) {
  477. rq->stats.rx_buf_alloc_failure++;
  478. break;
  479. }
  480. rbi->skb->dev = adapter->netdev;
  481. skb_reserve(rbi->skb, NET_IP_ALIGN);
  482. rbi->dma_addr = pci_map_single(adapter->pdev,
  483. rbi->skb->data, rbi->len,
  484. PCI_DMA_FROMDEVICE);
  485. } else {
  486. /* rx buffer skipped by the device */
  487. }
  488. val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
  489. } else {
  490. BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
  491. rbi->len != PAGE_SIZE);
  492. if (rbi->page == NULL) {
  493. rbi->page = alloc_page(GFP_ATOMIC);
  494. if (unlikely(rbi->page == NULL)) {
  495. rq->stats.rx_buf_alloc_failure++;
  496. break;
  497. }
  498. rbi->dma_addr = pci_map_page(adapter->pdev,
  499. rbi->page, 0, PAGE_SIZE,
  500. PCI_DMA_FROMDEVICE);
  501. } else {
  502. /* rx buffers skipped by the device */
  503. }
  504. val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
  505. }
  506. BUG_ON(rbi->dma_addr == 0);
  507. gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
  508. gd->dword[2] = cpu_to_le32((ring->gen << VMXNET3_RXD_GEN_SHIFT)
  509. | val | rbi->len);
  510. num_allocated++;
  511. vmxnet3_cmd_ring_adv_next2fill(ring);
  512. }
  513. rq->uncommitted[ring_idx] += num_allocated;
  514. dev_dbg(&adapter->netdev->dev,
  515. "alloc_rx_buf: %d allocated, next2fill %u, next2comp "
  516. "%u, uncommited %u\n", num_allocated, ring->next2fill,
  517. ring->next2comp, rq->uncommitted[ring_idx]);
  518. /* so that the device can distinguish a full ring and an empty ring */
  519. BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
  520. return num_allocated;
  521. }
  522. static void
  523. vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
  524. struct vmxnet3_rx_buf_info *rbi)
  525. {
  526. struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
  527. skb_shinfo(skb)->nr_frags;
  528. BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
  529. frag->page = rbi->page;
  530. frag->page_offset = 0;
  531. frag->size = rcd->len;
  532. skb->data_len += frag->size;
  533. skb_shinfo(skb)->nr_frags++;
  534. }
  535. static void
  536. vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
  537. struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
  538. struct vmxnet3_adapter *adapter)
  539. {
  540. u32 dw2, len;
  541. unsigned long buf_offset;
  542. int i;
  543. union Vmxnet3_GenericDesc *gdesc;
  544. struct vmxnet3_tx_buf_info *tbi = NULL;
  545. BUG_ON(ctx->copy_size > skb_headlen(skb));
  546. /* use the previous gen bit for the SOP desc */
  547. dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
  548. ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
  549. gdesc = ctx->sop_txd; /* both loops below can be skipped */
  550. /* no need to map the buffer if headers are copied */
  551. if (ctx->copy_size) {
  552. ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
  553. tq->tx_ring.next2fill *
  554. sizeof(struct Vmxnet3_TxDataDesc));
  555. ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
  556. ctx->sop_txd->dword[3] = 0;
  557. tbi = tq->buf_info + tq->tx_ring.next2fill;
  558. tbi->map_type = VMXNET3_MAP_NONE;
  559. dev_dbg(&adapter->netdev->dev,
  560. "txd[%u]: 0x%Lx 0x%x 0x%x\n",
  561. tq->tx_ring.next2fill,
  562. le64_to_cpu(ctx->sop_txd->txd.addr),
  563. ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
  564. vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
  565. /* use the right gen for non-SOP desc */
  566. dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
  567. }
  568. /* linear part can use multiple tx desc if it's big */
  569. len = skb_headlen(skb) - ctx->copy_size;
  570. buf_offset = ctx->copy_size;
  571. while (len) {
  572. u32 buf_size;
  573. if (len < VMXNET3_MAX_TX_BUF_SIZE) {
  574. buf_size = len;
  575. dw2 |= len;
  576. } else {
  577. buf_size = VMXNET3_MAX_TX_BUF_SIZE;
  578. /* spec says that for TxDesc.len, 0 == 2^14 */
  579. }
  580. tbi = tq->buf_info + tq->tx_ring.next2fill;
  581. tbi->map_type = VMXNET3_MAP_SINGLE;
  582. tbi->dma_addr = pci_map_single(adapter->pdev,
  583. skb->data + buf_offset, buf_size,
  584. PCI_DMA_TODEVICE);
  585. tbi->len = buf_size;
  586. gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
  587. BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
  588. gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
  589. gdesc->dword[2] = cpu_to_le32(dw2);
  590. gdesc->dword[3] = 0;
  591. dev_dbg(&adapter->netdev->dev,
  592. "txd[%u]: 0x%Lx 0x%x 0x%x\n",
  593. tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
  594. le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
  595. vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
  596. dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
  597. len -= buf_size;
  598. buf_offset += buf_size;
  599. }
  600. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  601. struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
  602. tbi = tq->buf_info + tq->tx_ring.next2fill;
  603. tbi->map_type = VMXNET3_MAP_PAGE;
  604. tbi->dma_addr = pci_map_page(adapter->pdev, frag->page,
  605. frag->page_offset, frag->size,
  606. PCI_DMA_TODEVICE);
  607. tbi->len = frag->size;
  608. gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
  609. BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
  610. gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
  611. gdesc->dword[2] = cpu_to_le32(dw2 | frag->size);
  612. gdesc->dword[3] = 0;
  613. dev_dbg(&adapter->netdev->dev,
  614. "txd[%u]: 0x%llu %u %u\n",
  615. tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
  616. le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
  617. vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
  618. dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
  619. }
  620. ctx->eop_txd = gdesc;
  621. /* set the last buf_info for the pkt */
  622. tbi->skb = skb;
  623. tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
  624. }
  625. /* Init all tx queues */
  626. static void
  627. vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
  628. {
  629. int i;
  630. for (i = 0; i < adapter->num_tx_queues; i++)
  631. vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
  632. }
  633. /*
  634. * parse and copy relevant protocol headers:
  635. * For a tso pkt, relevant headers are L2/3/4 including options
  636. * For a pkt requesting csum offloading, they are L2/3 and may include L4
  637. * if it's a TCP/UDP pkt
  638. *
  639. * Returns:
  640. * -1: error happens during parsing
  641. * 0: protocol headers parsed, but too big to be copied
  642. * 1: protocol headers parsed and copied
  643. *
  644. * Other effects:
  645. * 1. related *ctx fields are updated.
  646. * 2. ctx->copy_size is # of bytes copied
  647. * 3. the portion copied is guaranteed to be in the linear part
  648. *
  649. */
  650. static int
  651. vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
  652. struct vmxnet3_tx_ctx *ctx,
  653. struct vmxnet3_adapter *adapter)
  654. {
  655. struct Vmxnet3_TxDataDesc *tdd;
  656. if (ctx->mss) { /* TSO */
  657. ctx->eth_ip_hdr_size = skb_transport_offset(skb);
  658. ctx->l4_hdr_size = ((struct tcphdr *)
  659. skb_transport_header(skb))->doff * 4;
  660. ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
  661. } else {
  662. unsigned int pull_size;
  663. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  664. ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
  665. if (ctx->ipv4) {
  666. struct iphdr *iph = (struct iphdr *)
  667. skb_network_header(skb);
  668. if (iph->protocol == IPPROTO_TCP) {
  669. pull_size = ctx->eth_ip_hdr_size +
  670. sizeof(struct tcphdr);
  671. if (unlikely(!pskb_may_pull(skb,
  672. pull_size))) {
  673. goto err;
  674. }
  675. ctx->l4_hdr_size = ((struct tcphdr *)
  676. skb_transport_header(skb))->doff * 4;
  677. } else if (iph->protocol == IPPROTO_UDP) {
  678. ctx->l4_hdr_size =
  679. sizeof(struct udphdr);
  680. } else {
  681. ctx->l4_hdr_size = 0;
  682. }
  683. } else {
  684. /* for simplicity, don't copy L4 headers */
  685. ctx->l4_hdr_size = 0;
  686. }
  687. ctx->copy_size = ctx->eth_ip_hdr_size +
  688. ctx->l4_hdr_size;
  689. } else {
  690. ctx->eth_ip_hdr_size = 0;
  691. ctx->l4_hdr_size = 0;
  692. /* copy as much as allowed */
  693. ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE
  694. , skb_headlen(skb));
  695. }
  696. /* make sure headers are accessible directly */
  697. if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
  698. goto err;
  699. }
  700. if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) {
  701. tq->stats.oversized_hdr++;
  702. ctx->copy_size = 0;
  703. return 0;
  704. }
  705. tdd = tq->data_ring.base + tq->tx_ring.next2fill;
  706. memcpy(tdd->data, skb->data, ctx->copy_size);
  707. dev_dbg(&adapter->netdev->dev,
  708. "copy %u bytes to dataRing[%u]\n",
  709. ctx->copy_size, tq->tx_ring.next2fill);
  710. return 1;
  711. err:
  712. return -1;
  713. }
  714. static void
  715. vmxnet3_prepare_tso(struct sk_buff *skb,
  716. struct vmxnet3_tx_ctx *ctx)
  717. {
  718. struct tcphdr *tcph = (struct tcphdr *)skb_transport_header(skb);
  719. if (ctx->ipv4) {
  720. struct iphdr *iph = (struct iphdr *)skb_network_header(skb);
  721. iph->check = 0;
  722. tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
  723. IPPROTO_TCP, 0);
  724. } else {
  725. struct ipv6hdr *iph = (struct ipv6hdr *)skb_network_header(skb);
  726. tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
  727. IPPROTO_TCP, 0);
  728. }
  729. }
  730. /*
  731. * Transmits a pkt thru a given tq
  732. * Returns:
  733. * NETDEV_TX_OK: descriptors are setup successfully
  734. * NETDEV_TX_OK: error occured, the pkt is dropped
  735. * NETDEV_TX_BUSY: tx ring is full, queue is stopped
  736. *
  737. * Side-effects:
  738. * 1. tx ring may be changed
  739. * 2. tq stats may be updated accordingly
  740. * 3. shared->txNumDeferred may be updated
  741. */
  742. static int
  743. vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
  744. struct vmxnet3_adapter *adapter, struct net_device *netdev)
  745. {
  746. int ret;
  747. u32 count;
  748. unsigned long flags;
  749. struct vmxnet3_tx_ctx ctx;
  750. union Vmxnet3_GenericDesc *gdesc;
  751. #ifdef __BIG_ENDIAN_BITFIELD
  752. /* Use temporary descriptor to avoid touching bits multiple times */
  753. union Vmxnet3_GenericDesc tempTxDesc;
  754. #endif
  755. /* conservatively estimate # of descriptors to use */
  756. count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) +
  757. skb_shinfo(skb)->nr_frags + 1;
  758. ctx.ipv4 = (skb->protocol == cpu_to_be16(ETH_P_IP));
  759. ctx.mss = skb_shinfo(skb)->gso_size;
  760. if (ctx.mss) {
  761. if (skb_header_cloned(skb)) {
  762. if (unlikely(pskb_expand_head(skb, 0, 0,
  763. GFP_ATOMIC) != 0)) {
  764. tq->stats.drop_tso++;
  765. goto drop_pkt;
  766. }
  767. tq->stats.copy_skb_header++;
  768. }
  769. vmxnet3_prepare_tso(skb, &ctx);
  770. } else {
  771. if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
  772. /* non-tso pkts must not use more than
  773. * VMXNET3_MAX_TXD_PER_PKT entries
  774. */
  775. if (skb_linearize(skb) != 0) {
  776. tq->stats.drop_too_many_frags++;
  777. goto drop_pkt;
  778. }
  779. tq->stats.linearized++;
  780. /* recalculate the # of descriptors to use */
  781. count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
  782. }
  783. }
  784. spin_lock_irqsave(&tq->tx_lock, flags);
  785. if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
  786. tq->stats.tx_ring_full++;
  787. dev_dbg(&adapter->netdev->dev,
  788. "tx queue stopped on %s, next2comp %u"
  789. " next2fill %u\n", adapter->netdev->name,
  790. tq->tx_ring.next2comp, tq->tx_ring.next2fill);
  791. vmxnet3_tq_stop(tq, adapter);
  792. spin_unlock_irqrestore(&tq->tx_lock, flags);
  793. return NETDEV_TX_BUSY;
  794. }
  795. ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter);
  796. if (ret >= 0) {
  797. BUG_ON(ret <= 0 && ctx.copy_size != 0);
  798. /* hdrs parsed, check against other limits */
  799. if (ctx.mss) {
  800. if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
  801. VMXNET3_MAX_TX_BUF_SIZE)) {
  802. goto hdr_too_big;
  803. }
  804. } else {
  805. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  806. if (unlikely(ctx.eth_ip_hdr_size +
  807. skb->csum_offset >
  808. VMXNET3_MAX_CSUM_OFFSET)) {
  809. goto hdr_too_big;
  810. }
  811. }
  812. }
  813. } else {
  814. tq->stats.drop_hdr_inspect_err++;
  815. goto unlock_drop_pkt;
  816. }
  817. /* fill tx descs related to addr & len */
  818. vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter);
  819. /* setup the EOP desc */
  820. ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
  821. /* setup the SOP desc */
  822. #ifdef __BIG_ENDIAN_BITFIELD
  823. gdesc = &tempTxDesc;
  824. gdesc->dword[2] = ctx.sop_txd->dword[2];
  825. gdesc->dword[3] = ctx.sop_txd->dword[3];
  826. #else
  827. gdesc = ctx.sop_txd;
  828. #endif
  829. if (ctx.mss) {
  830. gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
  831. gdesc->txd.om = VMXNET3_OM_TSO;
  832. gdesc->txd.msscof = ctx.mss;
  833. le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
  834. gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
  835. } else {
  836. if (skb->ip_summed == CHECKSUM_PARTIAL) {
  837. gdesc->txd.hlen = ctx.eth_ip_hdr_size;
  838. gdesc->txd.om = VMXNET3_OM_CSUM;
  839. gdesc->txd.msscof = ctx.eth_ip_hdr_size +
  840. skb->csum_offset;
  841. } else {
  842. gdesc->txd.om = 0;
  843. gdesc->txd.msscof = 0;
  844. }
  845. le32_add_cpu(&tq->shared->txNumDeferred, 1);
  846. }
  847. if (vlan_tx_tag_present(skb)) {
  848. gdesc->txd.ti = 1;
  849. gdesc->txd.tci = vlan_tx_tag_get(skb);
  850. }
  851. /* finally flips the GEN bit of the SOP desc. */
  852. gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
  853. VMXNET3_TXD_GEN);
  854. #ifdef __BIG_ENDIAN_BITFIELD
  855. /* Finished updating in bitfields of Tx Desc, so write them in original
  856. * place.
  857. */
  858. vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
  859. (struct Vmxnet3_TxDesc *)ctx.sop_txd);
  860. gdesc = ctx.sop_txd;
  861. #endif
  862. dev_dbg(&adapter->netdev->dev,
  863. "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
  864. (u32)((union Vmxnet3_GenericDesc *)ctx.sop_txd -
  865. tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
  866. le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
  867. spin_unlock_irqrestore(&tq->tx_lock, flags);
  868. if (le32_to_cpu(tq->shared->txNumDeferred) >=
  869. le32_to_cpu(tq->shared->txThreshold)) {
  870. tq->shared->txNumDeferred = 0;
  871. VMXNET3_WRITE_BAR0_REG(adapter,
  872. VMXNET3_REG_TXPROD + tq->qid * 8,
  873. tq->tx_ring.next2fill);
  874. }
  875. return NETDEV_TX_OK;
  876. hdr_too_big:
  877. tq->stats.drop_oversized_hdr++;
  878. unlock_drop_pkt:
  879. spin_unlock_irqrestore(&tq->tx_lock, flags);
  880. drop_pkt:
  881. tq->stats.drop_total++;
  882. dev_kfree_skb(skb);
  883. return NETDEV_TX_OK;
  884. }
  885. static netdev_tx_t
  886. vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  887. {
  888. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  889. BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
  890. return vmxnet3_tq_xmit(skb,
  891. &adapter->tx_queue[skb->queue_mapping],
  892. adapter, netdev);
  893. }
  894. static void
  895. vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
  896. struct sk_buff *skb,
  897. union Vmxnet3_GenericDesc *gdesc)
  898. {
  899. if (!gdesc->rcd.cnc && adapter->rxcsum) {
  900. /* typical case: TCP/UDP over IP and both csums are correct */
  901. if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) ==
  902. VMXNET3_RCD_CSUM_OK) {
  903. skb->ip_summed = CHECKSUM_UNNECESSARY;
  904. BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
  905. BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
  906. BUG_ON(gdesc->rcd.frg);
  907. } else {
  908. if (gdesc->rcd.csum) {
  909. skb->csum = htons(gdesc->rcd.csum);
  910. skb->ip_summed = CHECKSUM_PARTIAL;
  911. } else {
  912. skb_checksum_none_assert(skb);
  913. }
  914. }
  915. } else {
  916. skb_checksum_none_assert(skb);
  917. }
  918. }
  919. static void
  920. vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
  921. struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
  922. {
  923. rq->stats.drop_err++;
  924. if (!rcd->fcs)
  925. rq->stats.drop_fcs++;
  926. rq->stats.drop_total++;
  927. /*
  928. * We do not unmap and chain the rx buffer to the skb.
  929. * We basically pretend this buffer is not used and will be recycled
  930. * by vmxnet3_rq_alloc_rx_buf()
  931. */
  932. /*
  933. * ctx->skb may be NULL if this is the first and the only one
  934. * desc for the pkt
  935. */
  936. if (ctx->skb)
  937. dev_kfree_skb_irq(ctx->skb);
  938. ctx->skb = NULL;
  939. }
  940. static int
  941. vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
  942. struct vmxnet3_adapter *adapter, int quota)
  943. {
  944. static const u32 rxprod_reg[2] = {
  945. VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
  946. };
  947. u32 num_rxd = 0;
  948. struct Vmxnet3_RxCompDesc *rcd;
  949. struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
  950. #ifdef __BIG_ENDIAN_BITFIELD
  951. struct Vmxnet3_RxDesc rxCmdDesc;
  952. struct Vmxnet3_RxCompDesc rxComp;
  953. #endif
  954. vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
  955. &rxComp);
  956. while (rcd->gen == rq->comp_ring.gen) {
  957. struct vmxnet3_rx_buf_info *rbi;
  958. struct sk_buff *skb;
  959. int num_to_alloc;
  960. struct Vmxnet3_RxDesc *rxd;
  961. u32 idx, ring_idx;
  962. if (num_rxd >= quota) {
  963. /* we may stop even before we see the EOP desc of
  964. * the current pkt
  965. */
  966. break;
  967. }
  968. num_rxd++;
  969. BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2);
  970. idx = rcd->rxdIdx;
  971. ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1;
  972. vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
  973. &rxCmdDesc);
  974. rbi = rq->buf_info[ring_idx] + idx;
  975. BUG_ON(rxd->addr != rbi->dma_addr ||
  976. rxd->len != rbi->len);
  977. if (unlikely(rcd->eop && rcd->err)) {
  978. vmxnet3_rx_error(rq, rcd, ctx, adapter);
  979. goto rcd_done;
  980. }
  981. if (rcd->sop) { /* first buf of the pkt */
  982. BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
  983. rcd->rqID != rq->qid);
  984. BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
  985. BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
  986. if (unlikely(rcd->len == 0)) {
  987. /* Pretend the rx buffer is skipped. */
  988. BUG_ON(!(rcd->sop && rcd->eop));
  989. dev_dbg(&adapter->netdev->dev,
  990. "rxRing[%u][%u] 0 length\n",
  991. ring_idx, idx);
  992. goto rcd_done;
  993. }
  994. ctx->skb = rbi->skb;
  995. rbi->skb = NULL;
  996. pci_unmap_single(adapter->pdev, rbi->dma_addr, rbi->len,
  997. PCI_DMA_FROMDEVICE);
  998. skb_put(ctx->skb, rcd->len);
  999. } else {
  1000. BUG_ON(ctx->skb == NULL);
  1001. /* non SOP buffer must be type 1 in most cases */
  1002. if (rbi->buf_type == VMXNET3_RX_BUF_PAGE) {
  1003. BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
  1004. if (rcd->len) {
  1005. pci_unmap_page(adapter->pdev,
  1006. rbi->dma_addr, rbi->len,
  1007. PCI_DMA_FROMDEVICE);
  1008. vmxnet3_append_frag(ctx->skb, rcd, rbi);
  1009. rbi->page = NULL;
  1010. }
  1011. } else {
  1012. /*
  1013. * The only time a non-SOP buffer is type 0 is
  1014. * when it's EOP and error flag is raised, which
  1015. * has already been handled.
  1016. */
  1017. BUG_ON(true);
  1018. }
  1019. }
  1020. skb = ctx->skb;
  1021. if (rcd->eop) {
  1022. skb->len += skb->data_len;
  1023. skb->truesize += skb->data_len;
  1024. vmxnet3_rx_csum(adapter, skb,
  1025. (union Vmxnet3_GenericDesc *)rcd);
  1026. skb->protocol = eth_type_trans(skb, adapter->netdev);
  1027. if (unlikely(adapter->vlan_grp && rcd->ts)) {
  1028. vlan_hwaccel_receive_skb(skb,
  1029. adapter->vlan_grp, rcd->tci);
  1030. } else {
  1031. netif_receive_skb(skb);
  1032. }
  1033. ctx->skb = NULL;
  1034. }
  1035. rcd_done:
  1036. /* device may skip some rx descs */
  1037. rq->rx_ring[ring_idx].next2comp = idx;
  1038. VMXNET3_INC_RING_IDX_ONLY(rq->rx_ring[ring_idx].next2comp,
  1039. rq->rx_ring[ring_idx].size);
  1040. /* refill rx buffers frequently to avoid starving the h/w */
  1041. num_to_alloc = vmxnet3_cmd_ring_desc_avail(rq->rx_ring +
  1042. ring_idx);
  1043. if (unlikely(num_to_alloc > VMXNET3_RX_ALLOC_THRESHOLD(rq,
  1044. ring_idx, adapter))) {
  1045. vmxnet3_rq_alloc_rx_buf(rq, ring_idx, num_to_alloc,
  1046. adapter);
  1047. /* if needed, update the register */
  1048. if (unlikely(rq->shared->updateRxProd)) {
  1049. VMXNET3_WRITE_BAR0_REG(adapter,
  1050. rxprod_reg[ring_idx] + rq->qid * 8,
  1051. rq->rx_ring[ring_idx].next2fill);
  1052. rq->uncommitted[ring_idx] = 0;
  1053. }
  1054. }
  1055. vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
  1056. vmxnet3_getRxComp(rcd,
  1057. &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
  1058. }
  1059. return num_rxd;
  1060. }
  1061. static void
  1062. vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
  1063. struct vmxnet3_adapter *adapter)
  1064. {
  1065. u32 i, ring_idx;
  1066. struct Vmxnet3_RxDesc *rxd;
  1067. for (ring_idx = 0; ring_idx < 2; ring_idx++) {
  1068. for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
  1069. #ifdef __BIG_ENDIAN_BITFIELD
  1070. struct Vmxnet3_RxDesc rxDesc;
  1071. #endif
  1072. vmxnet3_getRxDesc(rxd,
  1073. &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
  1074. if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
  1075. rq->buf_info[ring_idx][i].skb) {
  1076. pci_unmap_single(adapter->pdev, rxd->addr,
  1077. rxd->len, PCI_DMA_FROMDEVICE);
  1078. dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
  1079. rq->buf_info[ring_idx][i].skb = NULL;
  1080. } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
  1081. rq->buf_info[ring_idx][i].page) {
  1082. pci_unmap_page(adapter->pdev, rxd->addr,
  1083. rxd->len, PCI_DMA_FROMDEVICE);
  1084. put_page(rq->buf_info[ring_idx][i].page);
  1085. rq->buf_info[ring_idx][i].page = NULL;
  1086. }
  1087. }
  1088. rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
  1089. rq->rx_ring[ring_idx].next2fill =
  1090. rq->rx_ring[ring_idx].next2comp = 0;
  1091. rq->uncommitted[ring_idx] = 0;
  1092. }
  1093. rq->comp_ring.gen = VMXNET3_INIT_GEN;
  1094. rq->comp_ring.next2proc = 0;
  1095. }
  1096. static void
  1097. vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
  1098. {
  1099. int i;
  1100. for (i = 0; i < adapter->num_rx_queues; i++)
  1101. vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
  1102. }
  1103. void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
  1104. struct vmxnet3_adapter *adapter)
  1105. {
  1106. int i;
  1107. int j;
  1108. /* all rx buffers must have already been freed */
  1109. for (i = 0; i < 2; i++) {
  1110. if (rq->buf_info[i]) {
  1111. for (j = 0; j < rq->rx_ring[i].size; j++)
  1112. BUG_ON(rq->buf_info[i][j].page != NULL);
  1113. }
  1114. }
  1115. kfree(rq->buf_info[0]);
  1116. for (i = 0; i < 2; i++) {
  1117. if (rq->rx_ring[i].base) {
  1118. pci_free_consistent(adapter->pdev, rq->rx_ring[i].size
  1119. * sizeof(struct Vmxnet3_RxDesc),
  1120. rq->rx_ring[i].base,
  1121. rq->rx_ring[i].basePA);
  1122. rq->rx_ring[i].base = NULL;
  1123. }
  1124. rq->buf_info[i] = NULL;
  1125. }
  1126. if (rq->comp_ring.base) {
  1127. pci_free_consistent(adapter->pdev, rq->comp_ring.size *
  1128. sizeof(struct Vmxnet3_RxCompDesc),
  1129. rq->comp_ring.base, rq->comp_ring.basePA);
  1130. rq->comp_ring.base = NULL;
  1131. }
  1132. }
  1133. static int
  1134. vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
  1135. struct vmxnet3_adapter *adapter)
  1136. {
  1137. int i;
  1138. /* initialize buf_info */
  1139. for (i = 0; i < rq->rx_ring[0].size; i++) {
  1140. /* 1st buf for a pkt is skbuff */
  1141. if (i % adapter->rx_buf_per_pkt == 0) {
  1142. rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
  1143. rq->buf_info[0][i].len = adapter->skb_buf_size;
  1144. } else { /* subsequent bufs for a pkt is frag */
  1145. rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
  1146. rq->buf_info[0][i].len = PAGE_SIZE;
  1147. }
  1148. }
  1149. for (i = 0; i < rq->rx_ring[1].size; i++) {
  1150. rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
  1151. rq->buf_info[1][i].len = PAGE_SIZE;
  1152. }
  1153. /* reset internal state and allocate buffers for both rings */
  1154. for (i = 0; i < 2; i++) {
  1155. rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
  1156. rq->uncommitted[i] = 0;
  1157. memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
  1158. sizeof(struct Vmxnet3_RxDesc));
  1159. rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
  1160. }
  1161. if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
  1162. adapter) == 0) {
  1163. /* at least has 1 rx buffer for the 1st ring */
  1164. return -ENOMEM;
  1165. }
  1166. vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
  1167. /* reset the comp ring */
  1168. rq->comp_ring.next2proc = 0;
  1169. memset(rq->comp_ring.base, 0, rq->comp_ring.size *
  1170. sizeof(struct Vmxnet3_RxCompDesc));
  1171. rq->comp_ring.gen = VMXNET3_INIT_GEN;
  1172. /* reset rxctx */
  1173. rq->rx_ctx.skb = NULL;
  1174. /* stats are not reset */
  1175. return 0;
  1176. }
  1177. static int
  1178. vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
  1179. {
  1180. int i, err = 0;
  1181. for (i = 0; i < adapter->num_rx_queues; i++) {
  1182. err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
  1183. if (unlikely(err)) {
  1184. dev_err(&adapter->netdev->dev, "%s: failed to "
  1185. "initialize rx queue%i\n",
  1186. adapter->netdev->name, i);
  1187. break;
  1188. }
  1189. }
  1190. return err;
  1191. }
  1192. static int
  1193. vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
  1194. {
  1195. int i;
  1196. size_t sz;
  1197. struct vmxnet3_rx_buf_info *bi;
  1198. for (i = 0; i < 2; i++) {
  1199. sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
  1200. rq->rx_ring[i].base = pci_alloc_consistent(adapter->pdev, sz,
  1201. &rq->rx_ring[i].basePA);
  1202. if (!rq->rx_ring[i].base) {
  1203. printk(KERN_ERR "%s: failed to allocate rx ring %d\n",
  1204. adapter->netdev->name, i);
  1205. goto err;
  1206. }
  1207. }
  1208. sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
  1209. rq->comp_ring.base = pci_alloc_consistent(adapter->pdev, sz,
  1210. &rq->comp_ring.basePA);
  1211. if (!rq->comp_ring.base) {
  1212. printk(KERN_ERR "%s: failed to allocate rx comp ring\n",
  1213. adapter->netdev->name);
  1214. goto err;
  1215. }
  1216. sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
  1217. rq->rx_ring[1].size);
  1218. bi = kzalloc(sz, GFP_KERNEL);
  1219. if (!bi) {
  1220. printk(KERN_ERR "%s: failed to allocate rx bufinfo\n",
  1221. adapter->netdev->name);
  1222. goto err;
  1223. }
  1224. rq->buf_info[0] = bi;
  1225. rq->buf_info[1] = bi + rq->rx_ring[0].size;
  1226. return 0;
  1227. err:
  1228. vmxnet3_rq_destroy(rq, adapter);
  1229. return -ENOMEM;
  1230. }
  1231. static int
  1232. vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
  1233. {
  1234. int i, err = 0;
  1235. for (i = 0; i < adapter->num_rx_queues; i++) {
  1236. err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
  1237. if (unlikely(err)) {
  1238. dev_err(&adapter->netdev->dev,
  1239. "%s: failed to create rx queue%i\n",
  1240. adapter->netdev->name, i);
  1241. goto err_out;
  1242. }
  1243. }
  1244. return err;
  1245. err_out:
  1246. vmxnet3_rq_destroy_all(adapter);
  1247. return err;
  1248. }
  1249. /* Multiple queue aware polling function for tx and rx */
  1250. static int
  1251. vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
  1252. {
  1253. int rcd_done = 0, i;
  1254. if (unlikely(adapter->shared->ecr))
  1255. vmxnet3_process_events(adapter);
  1256. for (i = 0; i < adapter->num_tx_queues; i++)
  1257. vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
  1258. for (i = 0; i < adapter->num_rx_queues; i++)
  1259. rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
  1260. adapter, budget);
  1261. return rcd_done;
  1262. }
  1263. static int
  1264. vmxnet3_poll(struct napi_struct *napi, int budget)
  1265. {
  1266. struct vmxnet3_rx_queue *rx_queue = container_of(napi,
  1267. struct vmxnet3_rx_queue, napi);
  1268. int rxd_done;
  1269. rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
  1270. if (rxd_done < budget) {
  1271. napi_complete(napi);
  1272. vmxnet3_enable_all_intrs(rx_queue->adapter);
  1273. }
  1274. return rxd_done;
  1275. }
  1276. /*
  1277. * NAPI polling function for MSI-X mode with multiple Rx queues
  1278. * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
  1279. */
  1280. static int
  1281. vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
  1282. {
  1283. struct vmxnet3_rx_queue *rq = container_of(napi,
  1284. struct vmxnet3_rx_queue, napi);
  1285. struct vmxnet3_adapter *adapter = rq->adapter;
  1286. int rxd_done;
  1287. /* When sharing interrupt with corresponding tx queue, process
  1288. * tx completions in that queue as well
  1289. */
  1290. if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
  1291. struct vmxnet3_tx_queue *tq =
  1292. &adapter->tx_queue[rq - adapter->rx_queue];
  1293. vmxnet3_tq_tx_complete(tq, adapter);
  1294. }
  1295. rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
  1296. if (rxd_done < budget) {
  1297. napi_complete(napi);
  1298. vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
  1299. }
  1300. return rxd_done;
  1301. }
  1302. #ifdef CONFIG_PCI_MSI
  1303. /*
  1304. * Handle completion interrupts on tx queues
  1305. * Returns whether or not the intr is handled
  1306. */
  1307. static irqreturn_t
  1308. vmxnet3_msix_tx(int irq, void *data)
  1309. {
  1310. struct vmxnet3_tx_queue *tq = data;
  1311. struct vmxnet3_adapter *adapter = tq->adapter;
  1312. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1313. vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
  1314. /* Handle the case where only one irq is allocate for all tx queues */
  1315. if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
  1316. int i;
  1317. for (i = 0; i < adapter->num_tx_queues; i++) {
  1318. struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
  1319. vmxnet3_tq_tx_complete(txq, adapter);
  1320. }
  1321. } else {
  1322. vmxnet3_tq_tx_complete(tq, adapter);
  1323. }
  1324. vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
  1325. return IRQ_HANDLED;
  1326. }
  1327. /*
  1328. * Handle completion interrupts on rx queues. Returns whether or not the
  1329. * intr is handled
  1330. */
  1331. static irqreturn_t
  1332. vmxnet3_msix_rx(int irq, void *data)
  1333. {
  1334. struct vmxnet3_rx_queue *rq = data;
  1335. struct vmxnet3_adapter *adapter = rq->adapter;
  1336. /* disable intr if needed */
  1337. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1338. vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
  1339. napi_schedule(&rq->napi);
  1340. return IRQ_HANDLED;
  1341. }
  1342. /*
  1343. *----------------------------------------------------------------------------
  1344. *
  1345. * vmxnet3_msix_event --
  1346. *
  1347. * vmxnet3 msix event intr handler
  1348. *
  1349. * Result:
  1350. * whether or not the intr is handled
  1351. *
  1352. *----------------------------------------------------------------------------
  1353. */
  1354. static irqreturn_t
  1355. vmxnet3_msix_event(int irq, void *data)
  1356. {
  1357. struct net_device *dev = data;
  1358. struct vmxnet3_adapter *adapter = netdev_priv(dev);
  1359. /* disable intr if needed */
  1360. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1361. vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
  1362. if (adapter->shared->ecr)
  1363. vmxnet3_process_events(adapter);
  1364. vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
  1365. return IRQ_HANDLED;
  1366. }
  1367. #endif /* CONFIG_PCI_MSI */
  1368. /* Interrupt handler for vmxnet3 */
  1369. static irqreturn_t
  1370. vmxnet3_intr(int irq, void *dev_id)
  1371. {
  1372. struct net_device *dev = dev_id;
  1373. struct vmxnet3_adapter *adapter = netdev_priv(dev);
  1374. if (adapter->intr.type == VMXNET3_IT_INTX) {
  1375. u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
  1376. if (unlikely(icr == 0))
  1377. /* not ours */
  1378. return IRQ_NONE;
  1379. }
  1380. /* disable intr if needed */
  1381. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1382. vmxnet3_disable_all_intrs(adapter);
  1383. napi_schedule(&adapter->rx_queue[0].napi);
  1384. return IRQ_HANDLED;
  1385. }
  1386. #ifdef CONFIG_NET_POLL_CONTROLLER
  1387. /* netpoll callback. */
  1388. static void
  1389. vmxnet3_netpoll(struct net_device *netdev)
  1390. {
  1391. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1392. if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
  1393. vmxnet3_disable_all_intrs(adapter);
  1394. vmxnet3_do_poll(adapter, adapter->rx_queue[0].rx_ring[0].size);
  1395. vmxnet3_enable_all_intrs(adapter);
  1396. }
  1397. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1398. static int
  1399. vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
  1400. {
  1401. struct vmxnet3_intr *intr = &adapter->intr;
  1402. int err = 0, i;
  1403. int vector = 0;
  1404. #ifdef CONFIG_PCI_MSI
  1405. if (adapter->intr.type == VMXNET3_IT_MSIX) {
  1406. for (i = 0; i < adapter->num_tx_queues; i++) {
  1407. if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
  1408. sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
  1409. adapter->netdev->name, vector);
  1410. err = request_irq(
  1411. intr->msix_entries[vector].vector,
  1412. vmxnet3_msix_tx, 0,
  1413. adapter->tx_queue[i].name,
  1414. &adapter->tx_queue[i]);
  1415. } else {
  1416. sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
  1417. adapter->netdev->name, vector);
  1418. }
  1419. if (err) {
  1420. dev_err(&adapter->netdev->dev,
  1421. "Failed to request irq for MSIX, %s, "
  1422. "error %d\n",
  1423. adapter->tx_queue[i].name, err);
  1424. return err;
  1425. }
  1426. /* Handle the case where only 1 MSIx was allocated for
  1427. * all tx queues */
  1428. if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
  1429. for (; i < adapter->num_tx_queues; i++)
  1430. adapter->tx_queue[i].comp_ring.intr_idx
  1431. = vector;
  1432. vector++;
  1433. break;
  1434. } else {
  1435. adapter->tx_queue[i].comp_ring.intr_idx
  1436. = vector++;
  1437. }
  1438. }
  1439. if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
  1440. vector = 0;
  1441. for (i = 0; i < adapter->num_rx_queues; i++) {
  1442. if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
  1443. sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
  1444. adapter->netdev->name, vector);
  1445. else
  1446. sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
  1447. adapter->netdev->name, vector);
  1448. err = request_irq(intr->msix_entries[vector].vector,
  1449. vmxnet3_msix_rx, 0,
  1450. adapter->rx_queue[i].name,
  1451. &(adapter->rx_queue[i]));
  1452. if (err) {
  1453. printk(KERN_ERR "Failed to request irq for MSIX"
  1454. ", %s, error %d\n",
  1455. adapter->rx_queue[i].name, err);
  1456. return err;
  1457. }
  1458. adapter->rx_queue[i].comp_ring.intr_idx = vector++;
  1459. }
  1460. sprintf(intr->event_msi_vector_name, "%s-event-%d",
  1461. adapter->netdev->name, vector);
  1462. err = request_irq(intr->msix_entries[vector].vector,
  1463. vmxnet3_msix_event, 0,
  1464. intr->event_msi_vector_name, adapter->netdev);
  1465. intr->event_intr_idx = vector;
  1466. } else if (intr->type == VMXNET3_IT_MSI) {
  1467. adapter->num_rx_queues = 1;
  1468. err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
  1469. adapter->netdev->name, adapter->netdev);
  1470. } else {
  1471. #endif
  1472. adapter->num_rx_queues = 1;
  1473. err = request_irq(adapter->pdev->irq, vmxnet3_intr,
  1474. IRQF_SHARED, adapter->netdev->name,
  1475. adapter->netdev);
  1476. #ifdef CONFIG_PCI_MSI
  1477. }
  1478. #endif
  1479. intr->num_intrs = vector + 1;
  1480. if (err) {
  1481. printk(KERN_ERR "Failed to request irq %s (intr type:%d), error"
  1482. ":%d\n", adapter->netdev->name, intr->type, err);
  1483. } else {
  1484. /* Number of rx queues will not change after this */
  1485. for (i = 0; i < adapter->num_rx_queues; i++) {
  1486. struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
  1487. rq->qid = i;
  1488. rq->qid2 = i + adapter->num_rx_queues;
  1489. }
  1490. /* init our intr settings */
  1491. for (i = 0; i < intr->num_intrs; i++)
  1492. intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
  1493. if (adapter->intr.type != VMXNET3_IT_MSIX) {
  1494. adapter->intr.event_intr_idx = 0;
  1495. for (i = 0; i < adapter->num_tx_queues; i++)
  1496. adapter->tx_queue[i].comp_ring.intr_idx = 0;
  1497. adapter->rx_queue[0].comp_ring.intr_idx = 0;
  1498. }
  1499. printk(KERN_INFO "%s: intr type %u, mode %u, %u vectors "
  1500. "allocated\n", adapter->netdev->name, intr->type,
  1501. intr->mask_mode, intr->num_intrs);
  1502. }
  1503. return err;
  1504. }
  1505. static void
  1506. vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
  1507. {
  1508. struct vmxnet3_intr *intr = &adapter->intr;
  1509. BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
  1510. switch (intr->type) {
  1511. #ifdef CONFIG_PCI_MSI
  1512. case VMXNET3_IT_MSIX:
  1513. {
  1514. int i, vector = 0;
  1515. if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
  1516. for (i = 0; i < adapter->num_tx_queues; i++) {
  1517. free_irq(intr->msix_entries[vector++].vector,
  1518. &(adapter->tx_queue[i]));
  1519. if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
  1520. break;
  1521. }
  1522. }
  1523. for (i = 0; i < adapter->num_rx_queues; i++) {
  1524. free_irq(intr->msix_entries[vector++].vector,
  1525. &(adapter->rx_queue[i]));
  1526. }
  1527. free_irq(intr->msix_entries[vector].vector,
  1528. adapter->netdev);
  1529. BUG_ON(vector >= intr->num_intrs);
  1530. break;
  1531. }
  1532. #endif
  1533. case VMXNET3_IT_MSI:
  1534. free_irq(adapter->pdev->irq, adapter->netdev);
  1535. break;
  1536. case VMXNET3_IT_INTX:
  1537. free_irq(adapter->pdev->irq, adapter->netdev);
  1538. break;
  1539. default:
  1540. BUG_ON(true);
  1541. }
  1542. }
  1543. static void
  1544. vmxnet3_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
  1545. {
  1546. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1547. struct Vmxnet3_DriverShared *shared = adapter->shared;
  1548. u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
  1549. if (grp) {
  1550. /* add vlan rx stripping. */
  1551. if (adapter->netdev->features & NETIF_F_HW_VLAN_RX) {
  1552. int i;
  1553. struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
  1554. adapter->vlan_grp = grp;
  1555. /* update FEATURES to device */
  1556. devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
  1557. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1558. VMXNET3_CMD_UPDATE_FEATURE);
  1559. /*
  1560. * Clear entire vfTable; then enable untagged pkts.
  1561. * Note: setting one entry in vfTable to non-zero turns
  1562. * on VLAN rx filtering.
  1563. */
  1564. for (i = 0; i < VMXNET3_VFT_SIZE; i++)
  1565. vfTable[i] = 0;
  1566. VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
  1567. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1568. VMXNET3_CMD_UPDATE_VLAN_FILTERS);
  1569. } else {
  1570. printk(KERN_ERR "%s: vlan_rx_register when device has "
  1571. "no NETIF_F_HW_VLAN_RX\n", netdev->name);
  1572. }
  1573. } else {
  1574. /* remove vlan rx stripping. */
  1575. struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
  1576. adapter->vlan_grp = NULL;
  1577. if (devRead->misc.uptFeatures & UPT1_F_RXVLAN) {
  1578. int i;
  1579. for (i = 0; i < VMXNET3_VFT_SIZE; i++) {
  1580. /* clear entire vfTable; this also disables
  1581. * VLAN rx filtering
  1582. */
  1583. vfTable[i] = 0;
  1584. }
  1585. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1586. VMXNET3_CMD_UPDATE_VLAN_FILTERS);
  1587. /* update FEATURES to device */
  1588. devRead->misc.uptFeatures &= ~UPT1_F_RXVLAN;
  1589. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1590. VMXNET3_CMD_UPDATE_FEATURE);
  1591. }
  1592. }
  1593. }
  1594. static void
  1595. vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
  1596. {
  1597. if (adapter->vlan_grp) {
  1598. u16 vid;
  1599. u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
  1600. bool activeVlan = false;
  1601. for (vid = 0; vid < VLAN_N_VID; vid++) {
  1602. if (vlan_group_get_device(adapter->vlan_grp, vid)) {
  1603. VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
  1604. activeVlan = true;
  1605. }
  1606. }
  1607. if (activeVlan) {
  1608. /* continue to allow untagged pkts */
  1609. VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
  1610. }
  1611. }
  1612. }
  1613. static void
  1614. vmxnet3_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
  1615. {
  1616. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1617. u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
  1618. VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
  1619. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1620. VMXNET3_CMD_UPDATE_VLAN_FILTERS);
  1621. }
  1622. static void
  1623. vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
  1624. {
  1625. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1626. u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
  1627. VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
  1628. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1629. VMXNET3_CMD_UPDATE_VLAN_FILTERS);
  1630. }
  1631. static u8 *
  1632. vmxnet3_copy_mc(struct net_device *netdev)
  1633. {
  1634. u8 *buf = NULL;
  1635. u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
  1636. /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
  1637. if (sz <= 0xffff) {
  1638. /* We may be called with BH disabled */
  1639. buf = kmalloc(sz, GFP_ATOMIC);
  1640. if (buf) {
  1641. struct netdev_hw_addr *ha;
  1642. int i = 0;
  1643. netdev_for_each_mc_addr(ha, netdev)
  1644. memcpy(buf + i++ * ETH_ALEN, ha->addr,
  1645. ETH_ALEN);
  1646. }
  1647. }
  1648. return buf;
  1649. }
  1650. static void
  1651. vmxnet3_set_mc(struct net_device *netdev)
  1652. {
  1653. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1654. struct Vmxnet3_RxFilterConf *rxConf =
  1655. &adapter->shared->devRead.rxFilterConf;
  1656. u8 *new_table = NULL;
  1657. u32 new_mode = VMXNET3_RXM_UCAST;
  1658. if (netdev->flags & IFF_PROMISC)
  1659. new_mode |= VMXNET3_RXM_PROMISC;
  1660. if (netdev->flags & IFF_BROADCAST)
  1661. new_mode |= VMXNET3_RXM_BCAST;
  1662. if (netdev->flags & IFF_ALLMULTI)
  1663. new_mode |= VMXNET3_RXM_ALL_MULTI;
  1664. else
  1665. if (!netdev_mc_empty(netdev)) {
  1666. new_table = vmxnet3_copy_mc(netdev);
  1667. if (new_table) {
  1668. new_mode |= VMXNET3_RXM_MCAST;
  1669. rxConf->mfTableLen = cpu_to_le16(
  1670. netdev_mc_count(netdev) * ETH_ALEN);
  1671. rxConf->mfTablePA = cpu_to_le64(virt_to_phys(
  1672. new_table));
  1673. } else {
  1674. printk(KERN_INFO "%s: failed to copy mcast list"
  1675. ", setting ALL_MULTI\n", netdev->name);
  1676. new_mode |= VMXNET3_RXM_ALL_MULTI;
  1677. }
  1678. }
  1679. if (!(new_mode & VMXNET3_RXM_MCAST)) {
  1680. rxConf->mfTableLen = 0;
  1681. rxConf->mfTablePA = 0;
  1682. }
  1683. if (new_mode != rxConf->rxMode) {
  1684. rxConf->rxMode = cpu_to_le32(new_mode);
  1685. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1686. VMXNET3_CMD_UPDATE_RX_MODE);
  1687. }
  1688. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1689. VMXNET3_CMD_UPDATE_MAC_FILTERS);
  1690. kfree(new_table);
  1691. }
  1692. void
  1693. vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
  1694. {
  1695. int i;
  1696. for (i = 0; i < adapter->num_rx_queues; i++)
  1697. vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
  1698. }
  1699. /*
  1700. * Set up driver_shared based on settings in adapter.
  1701. */
  1702. static void
  1703. vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
  1704. {
  1705. struct Vmxnet3_DriverShared *shared = adapter->shared;
  1706. struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
  1707. struct Vmxnet3_TxQueueConf *tqc;
  1708. struct Vmxnet3_RxQueueConf *rqc;
  1709. int i;
  1710. memset(shared, 0, sizeof(*shared));
  1711. /* driver settings */
  1712. shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
  1713. devRead->misc.driverInfo.version = cpu_to_le32(
  1714. VMXNET3_DRIVER_VERSION_NUM);
  1715. devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
  1716. VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
  1717. devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
  1718. *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
  1719. *((u32 *)&devRead->misc.driverInfo.gos));
  1720. devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
  1721. devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
  1722. devRead->misc.ddPA = cpu_to_le64(virt_to_phys(adapter));
  1723. devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
  1724. /* set up feature flags */
  1725. if (adapter->rxcsum)
  1726. devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
  1727. if (adapter->lro) {
  1728. devRead->misc.uptFeatures |= UPT1_F_LRO;
  1729. devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
  1730. }
  1731. if ((adapter->netdev->features & NETIF_F_HW_VLAN_RX) &&
  1732. adapter->vlan_grp) {
  1733. devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
  1734. }
  1735. devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
  1736. devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
  1737. devRead->misc.queueDescLen = cpu_to_le32(
  1738. adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
  1739. adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
  1740. /* tx queue settings */
  1741. devRead->misc.numTxQueues = adapter->num_tx_queues;
  1742. for (i = 0; i < adapter->num_tx_queues; i++) {
  1743. struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
  1744. BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
  1745. tqc = &adapter->tqd_start[i].conf;
  1746. tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
  1747. tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
  1748. tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
  1749. tqc->ddPA = cpu_to_le64(virt_to_phys(tq->buf_info));
  1750. tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
  1751. tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
  1752. tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
  1753. tqc->ddLen = cpu_to_le32(
  1754. sizeof(struct vmxnet3_tx_buf_info) *
  1755. tqc->txRingSize);
  1756. tqc->intrIdx = tq->comp_ring.intr_idx;
  1757. }
  1758. /* rx queue settings */
  1759. devRead->misc.numRxQueues = adapter->num_rx_queues;
  1760. for (i = 0; i < adapter->num_rx_queues; i++) {
  1761. struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
  1762. rqc = &adapter->rqd_start[i].conf;
  1763. rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
  1764. rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
  1765. rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
  1766. rqc->ddPA = cpu_to_le64(virt_to_phys(
  1767. rq->buf_info));
  1768. rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
  1769. rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
  1770. rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
  1771. rqc->ddLen = cpu_to_le32(
  1772. sizeof(struct vmxnet3_rx_buf_info) *
  1773. (rqc->rxRingSize[0] +
  1774. rqc->rxRingSize[1]));
  1775. rqc->intrIdx = rq->comp_ring.intr_idx;
  1776. }
  1777. #ifdef VMXNET3_RSS
  1778. memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
  1779. if (adapter->rss) {
  1780. struct UPT1_RSSConf *rssConf = adapter->rss_conf;
  1781. devRead->misc.uptFeatures |= UPT1_F_RSS;
  1782. devRead->misc.numRxQueues = adapter->num_rx_queues;
  1783. rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
  1784. UPT1_RSS_HASH_TYPE_IPV4 |
  1785. UPT1_RSS_HASH_TYPE_TCP_IPV6 |
  1786. UPT1_RSS_HASH_TYPE_IPV6;
  1787. rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
  1788. rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
  1789. rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
  1790. get_random_bytes(&rssConf->hashKey[0], rssConf->hashKeySize);
  1791. for (i = 0; i < rssConf->indTableSize; i++)
  1792. rssConf->indTable[i] = i % adapter->num_rx_queues;
  1793. devRead->rssConfDesc.confVer = 1;
  1794. devRead->rssConfDesc.confLen = sizeof(*rssConf);
  1795. devRead->rssConfDesc.confPA = virt_to_phys(rssConf);
  1796. }
  1797. #endif /* VMXNET3_RSS */
  1798. /* intr settings */
  1799. devRead->intrConf.autoMask = adapter->intr.mask_mode ==
  1800. VMXNET3_IMM_AUTO;
  1801. devRead->intrConf.numIntrs = adapter->intr.num_intrs;
  1802. for (i = 0; i < adapter->intr.num_intrs; i++)
  1803. devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
  1804. devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
  1805. devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
  1806. /* rx filter settings */
  1807. devRead->rxFilterConf.rxMode = 0;
  1808. vmxnet3_restore_vlan(adapter);
  1809. /* the rest are already zeroed */
  1810. }
  1811. int
  1812. vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
  1813. {
  1814. int err, i;
  1815. u32 ret;
  1816. dev_dbg(&adapter->netdev->dev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
  1817. " ring sizes %u %u %u\n", adapter->netdev->name,
  1818. adapter->skb_buf_size, adapter->rx_buf_per_pkt,
  1819. adapter->tx_queue[0].tx_ring.size,
  1820. adapter->rx_queue[0].rx_ring[0].size,
  1821. adapter->rx_queue[0].rx_ring[1].size);
  1822. vmxnet3_tq_init_all(adapter);
  1823. err = vmxnet3_rq_init_all(adapter);
  1824. if (err) {
  1825. printk(KERN_ERR "Failed to init rx queue for %s: error %d\n",
  1826. adapter->netdev->name, err);
  1827. goto rq_err;
  1828. }
  1829. err = vmxnet3_request_irqs(adapter);
  1830. if (err) {
  1831. printk(KERN_ERR "Failed to setup irq for %s: error %d\n",
  1832. adapter->netdev->name, err);
  1833. goto irq_err;
  1834. }
  1835. vmxnet3_setup_driver_shared(adapter);
  1836. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
  1837. adapter->shared_pa));
  1838. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
  1839. adapter->shared_pa));
  1840. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1841. VMXNET3_CMD_ACTIVATE_DEV);
  1842. ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
  1843. if (ret != 0) {
  1844. printk(KERN_ERR "Failed to activate dev %s: error %u\n",
  1845. adapter->netdev->name, ret);
  1846. err = -EINVAL;
  1847. goto activate_err;
  1848. }
  1849. for (i = 0; i < adapter->num_rx_queues; i++) {
  1850. VMXNET3_WRITE_BAR0_REG(adapter,
  1851. VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
  1852. adapter->rx_queue[i].rx_ring[0].next2fill);
  1853. VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
  1854. (i * VMXNET3_REG_ALIGN)),
  1855. adapter->rx_queue[i].rx_ring[1].next2fill);
  1856. }
  1857. /* Apply the rx filter settins last. */
  1858. vmxnet3_set_mc(adapter->netdev);
  1859. /*
  1860. * Check link state when first activating device. It will start the
  1861. * tx queue if the link is up.
  1862. */
  1863. vmxnet3_check_link(adapter, true);
  1864. for (i = 0; i < adapter->num_rx_queues; i++)
  1865. napi_enable(&adapter->rx_queue[i].napi);
  1866. vmxnet3_enable_all_intrs(adapter);
  1867. clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
  1868. return 0;
  1869. activate_err:
  1870. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
  1871. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
  1872. vmxnet3_free_irqs(adapter);
  1873. irq_err:
  1874. rq_err:
  1875. /* free up buffers we allocated */
  1876. vmxnet3_rq_cleanup_all(adapter);
  1877. return err;
  1878. }
  1879. void
  1880. vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
  1881. {
  1882. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
  1883. }
  1884. int
  1885. vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
  1886. {
  1887. int i;
  1888. if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
  1889. return 0;
  1890. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  1891. VMXNET3_CMD_QUIESCE_DEV);
  1892. vmxnet3_disable_all_intrs(adapter);
  1893. for (i = 0; i < adapter->num_rx_queues; i++)
  1894. napi_disable(&adapter->rx_queue[i].napi);
  1895. netif_tx_disable(adapter->netdev);
  1896. adapter->link_speed = 0;
  1897. netif_carrier_off(adapter->netdev);
  1898. vmxnet3_tq_cleanup_all(adapter);
  1899. vmxnet3_rq_cleanup_all(adapter);
  1900. vmxnet3_free_irqs(adapter);
  1901. return 0;
  1902. }
  1903. static void
  1904. vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
  1905. {
  1906. u32 tmp;
  1907. tmp = *(u32 *)mac;
  1908. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
  1909. tmp = (mac[5] << 8) | mac[4];
  1910. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
  1911. }
  1912. static int
  1913. vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
  1914. {
  1915. struct sockaddr *addr = p;
  1916. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  1917. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  1918. vmxnet3_write_mac_addr(adapter, addr->sa_data);
  1919. return 0;
  1920. }
  1921. /* ==================== initialization and cleanup routines ============ */
  1922. static int
  1923. vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
  1924. {
  1925. int err;
  1926. unsigned long mmio_start, mmio_len;
  1927. struct pci_dev *pdev = adapter->pdev;
  1928. err = pci_enable_device(pdev);
  1929. if (err) {
  1930. printk(KERN_ERR "Failed to enable adapter %s: error %d\n",
  1931. pci_name(pdev), err);
  1932. return err;
  1933. }
  1934. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
  1935. if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
  1936. printk(KERN_ERR "pci_set_consistent_dma_mask failed "
  1937. "for adapter %s\n", pci_name(pdev));
  1938. err = -EIO;
  1939. goto err_set_mask;
  1940. }
  1941. *dma64 = true;
  1942. } else {
  1943. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
  1944. printk(KERN_ERR "pci_set_dma_mask failed for adapter "
  1945. "%s\n", pci_name(pdev));
  1946. err = -EIO;
  1947. goto err_set_mask;
  1948. }
  1949. *dma64 = false;
  1950. }
  1951. err = pci_request_selected_regions(pdev, (1 << 2) - 1,
  1952. vmxnet3_driver_name);
  1953. if (err) {
  1954. printk(KERN_ERR "Failed to request region for adapter %s: "
  1955. "error %d\n", pci_name(pdev), err);
  1956. goto err_set_mask;
  1957. }
  1958. pci_set_master(pdev);
  1959. mmio_start = pci_resource_start(pdev, 0);
  1960. mmio_len = pci_resource_len(pdev, 0);
  1961. adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
  1962. if (!adapter->hw_addr0) {
  1963. printk(KERN_ERR "Failed to map bar0 for adapter %s\n",
  1964. pci_name(pdev));
  1965. err = -EIO;
  1966. goto err_ioremap;
  1967. }
  1968. mmio_start = pci_resource_start(pdev, 1);
  1969. mmio_len = pci_resource_len(pdev, 1);
  1970. adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
  1971. if (!adapter->hw_addr1) {
  1972. printk(KERN_ERR "Failed to map bar1 for adapter %s\n",
  1973. pci_name(pdev));
  1974. err = -EIO;
  1975. goto err_bar1;
  1976. }
  1977. return 0;
  1978. err_bar1:
  1979. iounmap(adapter->hw_addr0);
  1980. err_ioremap:
  1981. pci_release_selected_regions(pdev, (1 << 2) - 1);
  1982. err_set_mask:
  1983. pci_disable_device(pdev);
  1984. return err;
  1985. }
  1986. static void
  1987. vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
  1988. {
  1989. BUG_ON(!adapter->pdev);
  1990. iounmap(adapter->hw_addr0);
  1991. iounmap(adapter->hw_addr1);
  1992. pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
  1993. pci_disable_device(adapter->pdev);
  1994. }
  1995. static void
  1996. vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
  1997. {
  1998. size_t sz, i, ring0_size, ring1_size, comp_size;
  1999. struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
  2000. if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
  2001. VMXNET3_MAX_ETH_HDR_SIZE) {
  2002. adapter->skb_buf_size = adapter->netdev->mtu +
  2003. VMXNET3_MAX_ETH_HDR_SIZE;
  2004. if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
  2005. adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
  2006. adapter->rx_buf_per_pkt = 1;
  2007. } else {
  2008. adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
  2009. sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
  2010. VMXNET3_MAX_ETH_HDR_SIZE;
  2011. adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
  2012. }
  2013. /*
  2014. * for simplicity, force the ring0 size to be a multiple of
  2015. * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
  2016. */
  2017. sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
  2018. ring0_size = adapter->rx_queue[0].rx_ring[0].size;
  2019. ring0_size = (ring0_size + sz - 1) / sz * sz;
  2020. ring0_size = min_t(u32, rq->rx_ring[0].size, VMXNET3_RX_RING_MAX_SIZE /
  2021. sz * sz);
  2022. ring1_size = adapter->rx_queue[0].rx_ring[1].size;
  2023. comp_size = ring0_size + ring1_size;
  2024. for (i = 0; i < adapter->num_rx_queues; i++) {
  2025. rq = &adapter->rx_queue[i];
  2026. rq->rx_ring[0].size = ring0_size;
  2027. rq->rx_ring[1].size = ring1_size;
  2028. rq->comp_ring.size = comp_size;
  2029. }
  2030. }
  2031. int
  2032. vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
  2033. u32 rx_ring_size, u32 rx_ring2_size)
  2034. {
  2035. int err = 0, i;
  2036. for (i = 0; i < adapter->num_tx_queues; i++) {
  2037. struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
  2038. tq->tx_ring.size = tx_ring_size;
  2039. tq->data_ring.size = tx_ring_size;
  2040. tq->comp_ring.size = tx_ring_size;
  2041. tq->shared = &adapter->tqd_start[i].ctrl;
  2042. tq->stopped = true;
  2043. tq->adapter = adapter;
  2044. tq->qid = i;
  2045. err = vmxnet3_tq_create(tq, adapter);
  2046. /*
  2047. * Too late to change num_tx_queues. We cannot do away with
  2048. * lesser number of queues than what we asked for
  2049. */
  2050. if (err)
  2051. goto queue_err;
  2052. }
  2053. adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
  2054. adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
  2055. vmxnet3_adjust_rx_ring_size(adapter);
  2056. for (i = 0; i < adapter->num_rx_queues; i++) {
  2057. struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
  2058. /* qid and qid2 for rx queues will be assigned later when num
  2059. * of rx queues is finalized after allocating intrs */
  2060. rq->shared = &adapter->rqd_start[i].ctrl;
  2061. rq->adapter = adapter;
  2062. err = vmxnet3_rq_create(rq, adapter);
  2063. if (err) {
  2064. if (i == 0) {
  2065. printk(KERN_ERR "Could not allocate any rx"
  2066. "queues. Aborting.\n");
  2067. goto queue_err;
  2068. } else {
  2069. printk(KERN_INFO "Number of rx queues changed "
  2070. "to : %d.\n", i);
  2071. adapter->num_rx_queues = i;
  2072. err = 0;
  2073. break;
  2074. }
  2075. }
  2076. }
  2077. return err;
  2078. queue_err:
  2079. vmxnet3_tq_destroy_all(adapter);
  2080. return err;
  2081. }
  2082. static int
  2083. vmxnet3_open(struct net_device *netdev)
  2084. {
  2085. struct vmxnet3_adapter *adapter;
  2086. int err, i;
  2087. adapter = netdev_priv(netdev);
  2088. for (i = 0; i < adapter->num_tx_queues; i++)
  2089. spin_lock_init(&adapter->tx_queue[i].tx_lock);
  2090. err = vmxnet3_create_queues(adapter, VMXNET3_DEF_TX_RING_SIZE,
  2091. VMXNET3_DEF_RX_RING_SIZE,
  2092. VMXNET3_DEF_RX_RING_SIZE);
  2093. if (err)
  2094. goto queue_err;
  2095. err = vmxnet3_activate_dev(adapter);
  2096. if (err)
  2097. goto activate_err;
  2098. return 0;
  2099. activate_err:
  2100. vmxnet3_rq_destroy_all(adapter);
  2101. vmxnet3_tq_destroy_all(adapter);
  2102. queue_err:
  2103. return err;
  2104. }
  2105. static int
  2106. vmxnet3_close(struct net_device *netdev)
  2107. {
  2108. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2109. /*
  2110. * Reset_work may be in the middle of resetting the device, wait for its
  2111. * completion.
  2112. */
  2113. while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
  2114. msleep(1);
  2115. vmxnet3_quiesce_dev(adapter);
  2116. vmxnet3_rq_destroy_all(adapter);
  2117. vmxnet3_tq_destroy_all(adapter);
  2118. clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
  2119. return 0;
  2120. }
  2121. void
  2122. vmxnet3_force_close(struct vmxnet3_adapter *adapter)
  2123. {
  2124. int i;
  2125. /*
  2126. * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
  2127. * vmxnet3_close() will deadlock.
  2128. */
  2129. BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
  2130. /* we need to enable NAPI, otherwise dev_close will deadlock */
  2131. for (i = 0; i < adapter->num_rx_queues; i++)
  2132. napi_enable(&adapter->rx_queue[i].napi);
  2133. dev_close(adapter->netdev);
  2134. }
  2135. static int
  2136. vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
  2137. {
  2138. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2139. int err = 0;
  2140. if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU)
  2141. return -EINVAL;
  2142. if (new_mtu > 1500 && !adapter->jumbo_frame)
  2143. return -EINVAL;
  2144. netdev->mtu = new_mtu;
  2145. /*
  2146. * Reset_work may be in the middle of resetting the device, wait for its
  2147. * completion.
  2148. */
  2149. while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
  2150. msleep(1);
  2151. if (netif_running(netdev)) {
  2152. vmxnet3_quiesce_dev(adapter);
  2153. vmxnet3_reset_dev(adapter);
  2154. /* we need to re-create the rx queue based on the new mtu */
  2155. vmxnet3_rq_destroy_all(adapter);
  2156. vmxnet3_adjust_rx_ring_size(adapter);
  2157. err = vmxnet3_rq_create_all(adapter);
  2158. if (err) {
  2159. printk(KERN_ERR "%s: failed to re-create rx queues,"
  2160. " error %d. Closing it.\n", netdev->name, err);
  2161. goto out;
  2162. }
  2163. err = vmxnet3_activate_dev(adapter);
  2164. if (err) {
  2165. printk(KERN_ERR "%s: failed to re-activate, error %d. "
  2166. "Closing it\n", netdev->name, err);
  2167. goto out;
  2168. }
  2169. }
  2170. out:
  2171. clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
  2172. if (err)
  2173. vmxnet3_force_close(adapter);
  2174. return err;
  2175. }
  2176. static void
  2177. vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
  2178. {
  2179. struct net_device *netdev = adapter->netdev;
  2180. netdev->features = NETIF_F_SG |
  2181. NETIF_F_HW_CSUM |
  2182. NETIF_F_HW_VLAN_TX |
  2183. NETIF_F_HW_VLAN_RX |
  2184. NETIF_F_HW_VLAN_FILTER |
  2185. NETIF_F_TSO |
  2186. NETIF_F_TSO6 |
  2187. NETIF_F_LRO;
  2188. printk(KERN_INFO "features: sg csum vlan jf tso tsoIPv6 lro");
  2189. adapter->rxcsum = true;
  2190. adapter->jumbo_frame = true;
  2191. adapter->lro = true;
  2192. if (dma64) {
  2193. netdev->features |= NETIF_F_HIGHDMA;
  2194. printk(" highDMA");
  2195. }
  2196. netdev->vlan_features = netdev->features;
  2197. printk("\n");
  2198. }
  2199. static void
  2200. vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
  2201. {
  2202. u32 tmp;
  2203. tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
  2204. *(u32 *)mac = tmp;
  2205. tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
  2206. mac[4] = tmp & 0xff;
  2207. mac[5] = (tmp >> 8) & 0xff;
  2208. }
  2209. #ifdef CONFIG_PCI_MSI
  2210. /*
  2211. * Enable MSIx vectors.
  2212. * Returns :
  2213. * 0 on successful enabling of required vectors,
  2214. * VMXNET3_LINUX_MIN_MSIX_VECT when only minumum number of vectors required
  2215. * could be enabled.
  2216. * number of vectors which can be enabled otherwise (this number is smaller
  2217. * than VMXNET3_LINUX_MIN_MSIX_VECT)
  2218. */
  2219. static int
  2220. vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter,
  2221. int vectors)
  2222. {
  2223. int err = 0, vector_threshold;
  2224. vector_threshold = VMXNET3_LINUX_MIN_MSIX_VECT;
  2225. while (vectors >= vector_threshold) {
  2226. err = pci_enable_msix(adapter->pdev, adapter->intr.msix_entries,
  2227. vectors);
  2228. if (!err) {
  2229. adapter->intr.num_intrs = vectors;
  2230. return 0;
  2231. } else if (err < 0) {
  2232. printk(KERN_ERR "Failed to enable MSI-X for %s, error"
  2233. " %d\n", adapter->netdev->name, err);
  2234. vectors = 0;
  2235. } else if (err < vector_threshold) {
  2236. break;
  2237. } else {
  2238. /* If fails to enable required number of MSI-x vectors
  2239. * try enabling 3 of them. One each for rx, tx and event
  2240. */
  2241. vectors = vector_threshold;
  2242. printk(KERN_ERR "Failed to enable %d MSI-X for %s, try"
  2243. " %d instead\n", vectors, adapter->netdev->name,
  2244. vector_threshold);
  2245. }
  2246. }
  2247. printk(KERN_INFO "Number of MSI-X interrupts which can be allocatedi"
  2248. " are lower than min threshold required.\n");
  2249. return err;
  2250. }
  2251. #endif /* CONFIG_PCI_MSI */
  2252. static void
  2253. vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
  2254. {
  2255. u32 cfg;
  2256. /* intr settings */
  2257. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  2258. VMXNET3_CMD_GET_CONF_INTR);
  2259. cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
  2260. adapter->intr.type = cfg & 0x3;
  2261. adapter->intr.mask_mode = (cfg >> 2) & 0x3;
  2262. if (adapter->intr.type == VMXNET3_IT_AUTO) {
  2263. adapter->intr.type = VMXNET3_IT_MSIX;
  2264. }
  2265. #ifdef CONFIG_PCI_MSI
  2266. if (adapter->intr.type == VMXNET3_IT_MSIX) {
  2267. int vector, err = 0;
  2268. adapter->intr.num_intrs = (adapter->share_intr ==
  2269. VMXNET3_INTR_TXSHARE) ? 1 :
  2270. adapter->num_tx_queues;
  2271. adapter->intr.num_intrs += (adapter->share_intr ==
  2272. VMXNET3_INTR_BUDDYSHARE) ? 0 :
  2273. adapter->num_rx_queues;
  2274. adapter->intr.num_intrs += 1; /* for link event */
  2275. adapter->intr.num_intrs = (adapter->intr.num_intrs >
  2276. VMXNET3_LINUX_MIN_MSIX_VECT
  2277. ? adapter->intr.num_intrs :
  2278. VMXNET3_LINUX_MIN_MSIX_VECT);
  2279. for (vector = 0; vector < adapter->intr.num_intrs; vector++)
  2280. adapter->intr.msix_entries[vector].entry = vector;
  2281. err = vmxnet3_acquire_msix_vectors(adapter,
  2282. adapter->intr.num_intrs);
  2283. /* If we cannot allocate one MSIx vector per queue
  2284. * then limit the number of rx queues to 1
  2285. */
  2286. if (err == VMXNET3_LINUX_MIN_MSIX_VECT) {
  2287. if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
  2288. || adapter->num_rx_queues != 2) {
  2289. adapter->share_intr = VMXNET3_INTR_TXSHARE;
  2290. printk(KERN_ERR "Number of rx queues : 1\n");
  2291. adapter->num_rx_queues = 1;
  2292. adapter->intr.num_intrs =
  2293. VMXNET3_LINUX_MIN_MSIX_VECT;
  2294. }
  2295. return;
  2296. }
  2297. if (!err)
  2298. return;
  2299. /* If we cannot allocate MSIx vectors use only one rx queue */
  2300. printk(KERN_INFO "Failed to enable MSI-X for %s, error %d."
  2301. "#rx queues : 1, try MSI\n", adapter->netdev->name, err);
  2302. adapter->intr.type = VMXNET3_IT_MSI;
  2303. }
  2304. if (adapter->intr.type == VMXNET3_IT_MSI) {
  2305. int err;
  2306. err = pci_enable_msi(adapter->pdev);
  2307. if (!err) {
  2308. adapter->num_rx_queues = 1;
  2309. adapter->intr.num_intrs = 1;
  2310. return;
  2311. }
  2312. }
  2313. #endif /* CONFIG_PCI_MSI */
  2314. adapter->num_rx_queues = 1;
  2315. printk(KERN_INFO "Using INTx interrupt, #Rx queues: 1.\n");
  2316. adapter->intr.type = VMXNET3_IT_INTX;
  2317. /* INT-X related setting */
  2318. adapter->intr.num_intrs = 1;
  2319. }
  2320. static void
  2321. vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
  2322. {
  2323. if (adapter->intr.type == VMXNET3_IT_MSIX)
  2324. pci_disable_msix(adapter->pdev);
  2325. else if (adapter->intr.type == VMXNET3_IT_MSI)
  2326. pci_disable_msi(adapter->pdev);
  2327. else
  2328. BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
  2329. }
  2330. static void
  2331. vmxnet3_tx_timeout(struct net_device *netdev)
  2332. {
  2333. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2334. adapter->tx_timeout_count++;
  2335. printk(KERN_ERR "%s: tx hang\n", adapter->netdev->name);
  2336. schedule_work(&adapter->work);
  2337. netif_wake_queue(adapter->netdev);
  2338. }
  2339. static void
  2340. vmxnet3_reset_work(struct work_struct *data)
  2341. {
  2342. struct vmxnet3_adapter *adapter;
  2343. adapter = container_of(data, struct vmxnet3_adapter, work);
  2344. /* if another thread is resetting the device, no need to proceed */
  2345. if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
  2346. return;
  2347. /* if the device is closed, we must leave it alone */
  2348. rtnl_lock();
  2349. if (netif_running(adapter->netdev)) {
  2350. printk(KERN_INFO "%s: resetting\n", adapter->netdev->name);
  2351. vmxnet3_quiesce_dev(adapter);
  2352. vmxnet3_reset_dev(adapter);
  2353. vmxnet3_activate_dev(adapter);
  2354. } else {
  2355. printk(KERN_INFO "%s: already closed\n", adapter->netdev->name);
  2356. }
  2357. rtnl_unlock();
  2358. clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
  2359. }
  2360. static int __devinit
  2361. vmxnet3_probe_device(struct pci_dev *pdev,
  2362. const struct pci_device_id *id)
  2363. {
  2364. static const struct net_device_ops vmxnet3_netdev_ops = {
  2365. .ndo_open = vmxnet3_open,
  2366. .ndo_stop = vmxnet3_close,
  2367. .ndo_start_xmit = vmxnet3_xmit_frame,
  2368. .ndo_set_mac_address = vmxnet3_set_mac_addr,
  2369. .ndo_change_mtu = vmxnet3_change_mtu,
  2370. .ndo_get_stats = vmxnet3_get_stats,
  2371. .ndo_tx_timeout = vmxnet3_tx_timeout,
  2372. .ndo_set_multicast_list = vmxnet3_set_mc,
  2373. .ndo_vlan_rx_register = vmxnet3_vlan_rx_register,
  2374. .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
  2375. .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
  2376. #ifdef CONFIG_NET_POLL_CONTROLLER
  2377. .ndo_poll_controller = vmxnet3_netpoll,
  2378. #endif
  2379. };
  2380. int err;
  2381. bool dma64 = false; /* stupid gcc */
  2382. u32 ver;
  2383. struct net_device *netdev;
  2384. struct vmxnet3_adapter *adapter;
  2385. u8 mac[ETH_ALEN];
  2386. int size;
  2387. int num_tx_queues;
  2388. int num_rx_queues;
  2389. #ifdef VMXNET3_RSS
  2390. if (enable_mq)
  2391. num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
  2392. (int)num_online_cpus());
  2393. else
  2394. #endif
  2395. num_rx_queues = 1;
  2396. if (enable_mq)
  2397. num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
  2398. (int)num_online_cpus());
  2399. else
  2400. num_tx_queues = 1;
  2401. netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
  2402. max(num_tx_queues, num_rx_queues));
  2403. printk(KERN_INFO "# of Tx queues : %d, # of Rx queues : %d\n",
  2404. num_tx_queues, num_rx_queues);
  2405. if (!netdev) {
  2406. printk(KERN_ERR "Failed to alloc ethernet device for adapter "
  2407. "%s\n", pci_name(pdev));
  2408. return -ENOMEM;
  2409. }
  2410. pci_set_drvdata(pdev, netdev);
  2411. adapter = netdev_priv(netdev);
  2412. adapter->netdev = netdev;
  2413. adapter->pdev = pdev;
  2414. adapter->shared = pci_alloc_consistent(adapter->pdev,
  2415. sizeof(struct Vmxnet3_DriverShared),
  2416. &adapter->shared_pa);
  2417. if (!adapter->shared) {
  2418. printk(KERN_ERR "Failed to allocate memory for %s\n",
  2419. pci_name(pdev));
  2420. err = -ENOMEM;
  2421. goto err_alloc_shared;
  2422. }
  2423. adapter->num_rx_queues = num_rx_queues;
  2424. adapter->num_tx_queues = num_tx_queues;
  2425. size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
  2426. size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
  2427. adapter->tqd_start = pci_alloc_consistent(adapter->pdev, size,
  2428. &adapter->queue_desc_pa);
  2429. if (!adapter->tqd_start) {
  2430. printk(KERN_ERR "Failed to allocate memory for %s\n",
  2431. pci_name(pdev));
  2432. err = -ENOMEM;
  2433. goto err_alloc_queue_desc;
  2434. }
  2435. adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
  2436. adapter->num_tx_queues);
  2437. adapter->pm_conf = kmalloc(sizeof(struct Vmxnet3_PMConf), GFP_KERNEL);
  2438. if (adapter->pm_conf == NULL) {
  2439. printk(KERN_ERR "Failed to allocate memory for %s\n",
  2440. pci_name(pdev));
  2441. err = -ENOMEM;
  2442. goto err_alloc_pm;
  2443. }
  2444. #ifdef VMXNET3_RSS
  2445. adapter->rss_conf = kmalloc(sizeof(struct UPT1_RSSConf), GFP_KERNEL);
  2446. if (adapter->rss_conf == NULL) {
  2447. printk(KERN_ERR "Failed to allocate memory for %s\n",
  2448. pci_name(pdev));
  2449. err = -ENOMEM;
  2450. goto err_alloc_rss;
  2451. }
  2452. #endif /* VMXNET3_RSS */
  2453. err = vmxnet3_alloc_pci_resources(adapter, &dma64);
  2454. if (err < 0)
  2455. goto err_alloc_pci;
  2456. ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
  2457. if (ver & 1) {
  2458. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1);
  2459. } else {
  2460. printk(KERN_ERR "Incompatible h/w version (0x%x) for adapter"
  2461. " %s\n", ver, pci_name(pdev));
  2462. err = -EBUSY;
  2463. goto err_ver;
  2464. }
  2465. ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
  2466. if (ver & 1) {
  2467. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
  2468. } else {
  2469. printk(KERN_ERR "Incompatible upt version (0x%x) for "
  2470. "adapter %s\n", ver, pci_name(pdev));
  2471. err = -EBUSY;
  2472. goto err_ver;
  2473. }
  2474. vmxnet3_declare_features(adapter, dma64);
  2475. adapter->dev_number = atomic_read(&devices_found);
  2476. adapter->share_intr = irq_share_mode;
  2477. if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE &&
  2478. adapter->num_tx_queues != adapter->num_rx_queues)
  2479. adapter->share_intr = VMXNET3_INTR_DONTSHARE;
  2480. vmxnet3_alloc_intr_resources(adapter);
  2481. #ifdef VMXNET3_RSS
  2482. if (adapter->num_rx_queues > 1 &&
  2483. adapter->intr.type == VMXNET3_IT_MSIX) {
  2484. adapter->rss = true;
  2485. printk(KERN_INFO "RSS is enabled.\n");
  2486. } else {
  2487. adapter->rss = false;
  2488. }
  2489. #endif
  2490. vmxnet3_read_mac_addr(adapter, mac);
  2491. memcpy(netdev->dev_addr, mac, netdev->addr_len);
  2492. netdev->netdev_ops = &vmxnet3_netdev_ops;
  2493. vmxnet3_set_ethtool_ops(netdev);
  2494. netdev->watchdog_timeo = 5 * HZ;
  2495. INIT_WORK(&adapter->work, vmxnet3_reset_work);
  2496. if (adapter->intr.type == VMXNET3_IT_MSIX) {
  2497. int i;
  2498. for (i = 0; i < adapter->num_rx_queues; i++) {
  2499. netif_napi_add(adapter->netdev,
  2500. &adapter->rx_queue[i].napi,
  2501. vmxnet3_poll_rx_only, 64);
  2502. }
  2503. } else {
  2504. netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
  2505. vmxnet3_poll, 64);
  2506. }
  2507. netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
  2508. netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
  2509. SET_NETDEV_DEV(netdev, &pdev->dev);
  2510. err = register_netdev(netdev);
  2511. if (err) {
  2512. printk(KERN_ERR "Failed to register adapter %s\n",
  2513. pci_name(pdev));
  2514. goto err_register;
  2515. }
  2516. set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
  2517. vmxnet3_check_link(adapter, false);
  2518. atomic_inc(&devices_found);
  2519. return 0;
  2520. err_register:
  2521. vmxnet3_free_intr_resources(adapter);
  2522. err_ver:
  2523. vmxnet3_free_pci_resources(adapter);
  2524. err_alloc_pci:
  2525. #ifdef VMXNET3_RSS
  2526. kfree(adapter->rss_conf);
  2527. err_alloc_rss:
  2528. #endif
  2529. kfree(adapter->pm_conf);
  2530. err_alloc_pm:
  2531. pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
  2532. adapter->queue_desc_pa);
  2533. err_alloc_queue_desc:
  2534. pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
  2535. adapter->shared, adapter->shared_pa);
  2536. err_alloc_shared:
  2537. pci_set_drvdata(pdev, NULL);
  2538. free_netdev(netdev);
  2539. return err;
  2540. }
  2541. static void __devexit
  2542. vmxnet3_remove_device(struct pci_dev *pdev)
  2543. {
  2544. struct net_device *netdev = pci_get_drvdata(pdev);
  2545. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2546. int size = 0;
  2547. int num_rx_queues;
  2548. #ifdef VMXNET3_RSS
  2549. if (enable_mq)
  2550. num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
  2551. (int)num_online_cpus());
  2552. else
  2553. #endif
  2554. num_rx_queues = 1;
  2555. cancel_work_sync(&adapter->work);
  2556. unregister_netdev(netdev);
  2557. vmxnet3_free_intr_resources(adapter);
  2558. vmxnet3_free_pci_resources(adapter);
  2559. #ifdef VMXNET3_RSS
  2560. kfree(adapter->rss_conf);
  2561. #endif
  2562. kfree(adapter->pm_conf);
  2563. size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
  2564. size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
  2565. pci_free_consistent(adapter->pdev, size, adapter->tqd_start,
  2566. adapter->queue_desc_pa);
  2567. pci_free_consistent(adapter->pdev, sizeof(struct Vmxnet3_DriverShared),
  2568. adapter->shared, adapter->shared_pa);
  2569. free_netdev(netdev);
  2570. }
  2571. #ifdef CONFIG_PM
  2572. static int
  2573. vmxnet3_suspend(struct device *device)
  2574. {
  2575. struct pci_dev *pdev = to_pci_dev(device);
  2576. struct net_device *netdev = pci_get_drvdata(pdev);
  2577. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2578. struct Vmxnet3_PMConf *pmConf;
  2579. struct ethhdr *ehdr;
  2580. struct arphdr *ahdr;
  2581. u8 *arpreq;
  2582. struct in_device *in_dev;
  2583. struct in_ifaddr *ifa;
  2584. int i = 0;
  2585. if (!netif_running(netdev))
  2586. return 0;
  2587. vmxnet3_disable_all_intrs(adapter);
  2588. vmxnet3_free_irqs(adapter);
  2589. vmxnet3_free_intr_resources(adapter);
  2590. netif_device_detach(netdev);
  2591. netif_tx_stop_all_queues(netdev);
  2592. /* Create wake-up filters. */
  2593. pmConf = adapter->pm_conf;
  2594. memset(pmConf, 0, sizeof(*pmConf));
  2595. if (adapter->wol & WAKE_UCAST) {
  2596. pmConf->filters[i].patternSize = ETH_ALEN;
  2597. pmConf->filters[i].maskSize = 1;
  2598. memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
  2599. pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
  2600. pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
  2601. i++;
  2602. }
  2603. if (adapter->wol & WAKE_ARP) {
  2604. in_dev = in_dev_get(netdev);
  2605. if (!in_dev)
  2606. goto skip_arp;
  2607. ifa = (struct in_ifaddr *)in_dev->ifa_list;
  2608. if (!ifa)
  2609. goto skip_arp;
  2610. pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
  2611. sizeof(struct arphdr) + /* ARP header */
  2612. 2 * ETH_ALEN + /* 2 Ethernet addresses*/
  2613. 2 * sizeof(u32); /*2 IPv4 addresses */
  2614. pmConf->filters[i].maskSize =
  2615. (pmConf->filters[i].patternSize - 1) / 8 + 1;
  2616. /* ETH_P_ARP in Ethernet header. */
  2617. ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
  2618. ehdr->h_proto = htons(ETH_P_ARP);
  2619. /* ARPOP_REQUEST in ARP header. */
  2620. ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
  2621. ahdr->ar_op = htons(ARPOP_REQUEST);
  2622. arpreq = (u8 *)(ahdr + 1);
  2623. /* The Unicast IPv4 address in 'tip' field. */
  2624. arpreq += 2 * ETH_ALEN + sizeof(u32);
  2625. *(u32 *)arpreq = ifa->ifa_address;
  2626. /* The mask for the relevant bits. */
  2627. pmConf->filters[i].mask[0] = 0x00;
  2628. pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
  2629. pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
  2630. pmConf->filters[i].mask[3] = 0x00;
  2631. pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
  2632. pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
  2633. in_dev_put(in_dev);
  2634. pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
  2635. i++;
  2636. }
  2637. skip_arp:
  2638. if (adapter->wol & WAKE_MAGIC)
  2639. pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
  2640. pmConf->numFilters = i;
  2641. adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
  2642. adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
  2643. *pmConf));
  2644. adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
  2645. pmConf));
  2646. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  2647. VMXNET3_CMD_UPDATE_PMCFG);
  2648. pci_save_state(pdev);
  2649. pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
  2650. adapter->wol);
  2651. pci_disable_device(pdev);
  2652. pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
  2653. return 0;
  2654. }
  2655. static int
  2656. vmxnet3_resume(struct device *device)
  2657. {
  2658. int err;
  2659. struct pci_dev *pdev = to_pci_dev(device);
  2660. struct net_device *netdev = pci_get_drvdata(pdev);
  2661. struct vmxnet3_adapter *adapter = netdev_priv(netdev);
  2662. struct Vmxnet3_PMConf *pmConf;
  2663. if (!netif_running(netdev))
  2664. return 0;
  2665. /* Destroy wake-up filters. */
  2666. pmConf = adapter->pm_conf;
  2667. memset(pmConf, 0, sizeof(*pmConf));
  2668. adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
  2669. adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
  2670. *pmConf));
  2671. adapter->shared->devRead.pmConfDesc.confPA = cpu_to_le64(virt_to_phys(
  2672. pmConf));
  2673. netif_device_attach(netdev);
  2674. pci_set_power_state(pdev, PCI_D0);
  2675. pci_restore_state(pdev);
  2676. err = pci_enable_device_mem(pdev);
  2677. if (err != 0)
  2678. return err;
  2679. pci_enable_wake(pdev, PCI_D0, 0);
  2680. VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
  2681. VMXNET3_CMD_UPDATE_PMCFG);
  2682. vmxnet3_alloc_intr_resources(adapter);
  2683. vmxnet3_request_irqs(adapter);
  2684. vmxnet3_enable_all_intrs(adapter);
  2685. return 0;
  2686. }
  2687. static const struct dev_pm_ops vmxnet3_pm_ops = {
  2688. .suspend = vmxnet3_suspend,
  2689. .resume = vmxnet3_resume,
  2690. };
  2691. #endif
  2692. static struct pci_driver vmxnet3_driver = {
  2693. .name = vmxnet3_driver_name,
  2694. .id_table = vmxnet3_pciid_table,
  2695. .probe = vmxnet3_probe_device,
  2696. .remove = __devexit_p(vmxnet3_remove_device),
  2697. #ifdef CONFIG_PM
  2698. .driver.pm = &vmxnet3_pm_ops,
  2699. #endif
  2700. };
  2701. static int __init
  2702. vmxnet3_init_module(void)
  2703. {
  2704. printk(KERN_INFO "%s - version %s\n", VMXNET3_DRIVER_DESC,
  2705. VMXNET3_DRIVER_VERSION_REPORT);
  2706. return pci_register_driver(&vmxnet3_driver);
  2707. }
  2708. module_init(vmxnet3_init_module);
  2709. static void
  2710. vmxnet3_exit_module(void)
  2711. {
  2712. pci_unregister_driver(&vmxnet3_driver);
  2713. }
  2714. module_exit(vmxnet3_exit_module);
  2715. MODULE_AUTHOR("VMware, Inc.");
  2716. MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
  2717. MODULE_LICENSE("GPL v2");
  2718. MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);