tifm_sd.c 26 KB

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  1. /*
  2. * tifm_sd.c - TI FlashMedia driver
  3. *
  4. * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/tifm.h>
  12. #include <linux/mmc/protocol.h>
  13. #include <linux/mmc/host.h>
  14. #include <linux/highmem.h>
  15. #include <asm/io.h>
  16. #define DRIVER_NAME "tifm_sd"
  17. #define DRIVER_VERSION "0.7"
  18. static int no_dma = 0;
  19. static int fixed_timeout = 0;
  20. module_param(no_dma, bool, 0644);
  21. module_param(fixed_timeout, bool, 0644);
  22. /* Constants here are mostly from OMAP5912 datasheet */
  23. #define TIFM_MMCSD_RESET 0x0002
  24. #define TIFM_MMCSD_CLKMASK 0x03ff
  25. #define TIFM_MMCSD_POWER 0x0800
  26. #define TIFM_MMCSD_4BBUS 0x8000
  27. #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
  28. #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
  29. #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
  30. #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
  31. #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
  32. #define TIFM_MMCSD_READ 0x8000
  33. #define TIFM_MMCSD_DATAMASK 0x001d /* set bits: EOFB, BRS, CB, EOC */
  34. #define TIFM_MMCSD_ERRMASK 0x41e0 /* set bits: CERR, CCRC, CTO, DCRC, DTO */
  35. #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
  36. #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
  37. #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
  38. #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
  39. #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
  40. #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
  41. #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
  42. #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
  43. #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
  44. #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
  45. #define TIFM_MMCSD_CERR 0x4000 /* card status error */
  46. #define TIFM_MMCSD_FIFO_SIZE 0x0020
  47. #define TIFM_MMCSD_RSP_R0 0x0000
  48. #define TIFM_MMCSD_RSP_R1 0x0100
  49. #define TIFM_MMCSD_RSP_R2 0x0200
  50. #define TIFM_MMCSD_RSP_R3 0x0300
  51. #define TIFM_MMCSD_RSP_R4 0x0400
  52. #define TIFM_MMCSD_RSP_R5 0x0500
  53. #define TIFM_MMCSD_RSP_R6 0x0600
  54. #define TIFM_MMCSD_RSP_BUSY 0x0800
  55. #define TIFM_MMCSD_CMD_BC 0x0000
  56. #define TIFM_MMCSD_CMD_BCR 0x1000
  57. #define TIFM_MMCSD_CMD_AC 0x2000
  58. #define TIFM_MMCSD_CMD_ADTC 0x3000
  59. typedef enum {
  60. IDLE = 0,
  61. CMD, /* main command ended */
  62. BRS, /* block transfer finished */
  63. SCMD, /* stop command ended */
  64. CARD, /* card left busy state */
  65. FIFO, /* FIFO operation completed (uncertain) */
  66. READY
  67. } card_state_t;
  68. enum {
  69. FIFO_RDY = 0x0001, /* hardware dependent value */
  70. EJECT = 0x0004,
  71. EJECT_DONE = 0x0008,
  72. CARD_BUSY = 0x0010,
  73. OPENDRAIN = 0x0040, /* hardware dependent value */
  74. CARD_EVENT = 0x0100, /* hardware dependent value */
  75. CARD_RO = 0x0200, /* hardware dependent value */
  76. FIFO_EVENT = 0x10000 }; /* hardware dependent value */
  77. struct tifm_sd {
  78. struct tifm_dev *dev;
  79. unsigned int flags;
  80. card_state_t state;
  81. unsigned int clk_freq;
  82. unsigned int clk_div;
  83. unsigned long timeout_jiffies;
  84. struct tasklet_struct finish_tasklet;
  85. struct timer_list timer;
  86. struct mmc_request *req;
  87. wait_queue_head_t notify;
  88. size_t written_blocks;
  89. size_t buffer_size;
  90. size_t buffer_pos;
  91. };
  92. static char* tifm_sd_kmap_atomic(struct mmc_data *data)
  93. {
  94. return kmap_atomic(data->sg->page, KM_BIO_SRC_IRQ) + data->sg->offset;
  95. }
  96. static void tifm_sd_kunmap_atomic(char *buffer, struct mmc_data *data)
  97. {
  98. kunmap_atomic(buffer - data->sg->offset, KM_BIO_SRC_IRQ);
  99. }
  100. static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
  101. unsigned int host_status)
  102. {
  103. struct mmc_command *cmd = host->req->cmd;
  104. unsigned int t_val = 0, cnt = 0;
  105. char *buffer;
  106. if (host_status & TIFM_MMCSD_BRS) {
  107. /* in non-dma rx mode BRS fires when fifo is still not empty */
  108. if (no_dma && (cmd->data->flags & MMC_DATA_READ)) {
  109. buffer = tifm_sd_kmap_atomic(host->req->data);
  110. while (host->buffer_size > host->buffer_pos) {
  111. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  112. buffer[host->buffer_pos++] = t_val & 0xff;
  113. buffer[host->buffer_pos++] =
  114. (t_val >> 8) & 0xff;
  115. }
  116. tifm_sd_kunmap_atomic(buffer, host->req->data);
  117. }
  118. return 1;
  119. } else if (no_dma) {
  120. buffer = tifm_sd_kmap_atomic(host->req->data);
  121. if ((cmd->data->flags & MMC_DATA_READ) &&
  122. (host_status & TIFM_MMCSD_AF)) {
  123. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  124. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  125. if (host->buffer_size > host->buffer_pos) {
  126. buffer[host->buffer_pos++] =
  127. t_val & 0xff;
  128. buffer[host->buffer_pos++] =
  129. (t_val >> 8) & 0xff;
  130. }
  131. }
  132. } else if ((cmd->data->flags & MMC_DATA_WRITE)
  133. && (host_status & TIFM_MMCSD_AE)) {
  134. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  135. if (host->buffer_size > host->buffer_pos) {
  136. t_val = buffer[host->buffer_pos++]
  137. & 0x00ff;
  138. t_val |= ((buffer[host->buffer_pos++])
  139. << 8) & 0xff00;
  140. writel(t_val,
  141. sock->addr + SOCK_MMCSD_DATA);
  142. }
  143. }
  144. }
  145. tifm_sd_kunmap_atomic(buffer, host->req->data);
  146. }
  147. return 0;
  148. }
  149. static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
  150. {
  151. unsigned int rc = 0;
  152. switch (mmc_resp_type(cmd)) {
  153. case MMC_RSP_NONE:
  154. rc |= TIFM_MMCSD_RSP_R0;
  155. break;
  156. case MMC_RSP_R1B:
  157. rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
  158. case MMC_RSP_R1:
  159. rc |= TIFM_MMCSD_RSP_R1;
  160. break;
  161. case MMC_RSP_R2:
  162. rc |= TIFM_MMCSD_RSP_R2;
  163. break;
  164. case MMC_RSP_R3:
  165. rc |= TIFM_MMCSD_RSP_R3;
  166. break;
  167. default:
  168. BUG();
  169. }
  170. switch (mmc_cmd_type(cmd)) {
  171. case MMC_CMD_BC:
  172. rc |= TIFM_MMCSD_CMD_BC;
  173. break;
  174. case MMC_CMD_BCR:
  175. rc |= TIFM_MMCSD_CMD_BCR;
  176. break;
  177. case MMC_CMD_AC:
  178. rc |= TIFM_MMCSD_CMD_AC;
  179. break;
  180. case MMC_CMD_ADTC:
  181. rc |= TIFM_MMCSD_CMD_ADTC;
  182. break;
  183. default:
  184. BUG();
  185. }
  186. return rc;
  187. }
  188. static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
  189. {
  190. struct tifm_dev *sock = host->dev;
  191. unsigned int cmd_mask = tifm_sd_op_flags(cmd) |
  192. (host->flags & OPENDRAIN);
  193. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  194. cmd_mask |= TIFM_MMCSD_READ;
  195. dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
  196. cmd->opcode, cmd->arg, cmd_mask);
  197. writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
  198. writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
  199. writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
  200. }
  201. static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
  202. {
  203. cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
  204. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
  205. cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
  206. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
  207. cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
  208. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
  209. cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
  210. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
  211. }
  212. static void tifm_sd_process_cmd(struct tifm_dev *sock, struct tifm_sd *host,
  213. unsigned int host_status)
  214. {
  215. struct mmc_command *cmd = host->req->cmd;
  216. change_state:
  217. switch (host->state) {
  218. case IDLE:
  219. return;
  220. case CMD:
  221. if (host_status & TIFM_MMCSD_EOC) {
  222. tifm_sd_fetch_resp(cmd, sock);
  223. if (cmd->data) {
  224. host->state = BRS;
  225. } else {
  226. host->state = READY;
  227. }
  228. goto change_state;
  229. }
  230. break;
  231. case BRS:
  232. if (tifm_sd_transfer_data(sock, host, host_status)) {
  233. if (cmd->data->flags & MMC_DATA_WRITE) {
  234. host->state = CARD;
  235. } else {
  236. if (no_dma) {
  237. if (host->req->stop) {
  238. tifm_sd_exec(host, host->req->stop);
  239. host->state = SCMD;
  240. } else {
  241. host->state = READY;
  242. }
  243. } else {
  244. host->state = FIFO;
  245. }
  246. }
  247. goto change_state;
  248. }
  249. break;
  250. case SCMD:
  251. if (host_status & TIFM_MMCSD_EOC) {
  252. tifm_sd_fetch_resp(host->req->stop, sock);
  253. host->state = READY;
  254. goto change_state;
  255. }
  256. break;
  257. case CARD:
  258. dev_dbg(&sock->dev, "waiting for CARD, have %zd blocks\n",
  259. host->written_blocks);
  260. if (!(host->flags & CARD_BUSY)
  261. && (host->written_blocks == cmd->data->blocks)) {
  262. if (no_dma) {
  263. if (host->req->stop) {
  264. tifm_sd_exec(host, host->req->stop);
  265. host->state = SCMD;
  266. } else {
  267. host->state = READY;
  268. }
  269. } else {
  270. host->state = FIFO;
  271. }
  272. goto change_state;
  273. }
  274. break;
  275. case FIFO:
  276. if (host->flags & FIFO_RDY) {
  277. host->flags &= ~FIFO_RDY;
  278. if (host->req->stop) {
  279. tifm_sd_exec(host, host->req->stop);
  280. host->state = SCMD;
  281. } else {
  282. host->state = READY;
  283. }
  284. goto change_state;
  285. }
  286. break;
  287. case READY:
  288. tasklet_schedule(&host->finish_tasklet);
  289. return;
  290. }
  291. }
  292. /* Called from interrupt handler */
  293. static void tifm_sd_signal_irq(struct tifm_dev *sock,
  294. unsigned int sock_irq_status)
  295. {
  296. struct tifm_sd *host;
  297. unsigned int host_status = 0, fifo_status = 0;
  298. int error_code = 0;
  299. spin_lock(&sock->lock);
  300. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  301. if (sock_irq_status & FIFO_EVENT) {
  302. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  303. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  304. host->flags |= fifo_status & FIFO_RDY;
  305. }
  306. if (sock_irq_status & CARD_EVENT) {
  307. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  308. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  309. if (!host->req)
  310. goto done;
  311. if (host_status & TIFM_MMCSD_ERRMASK) {
  312. if (host_status & TIFM_MMCSD_CERR)
  313. error_code = MMC_ERR_FAILED;
  314. else if (host_status
  315. & (TIFM_MMCSD_CTO | TIFM_MMCSD_DTO))
  316. error_code = MMC_ERR_TIMEOUT;
  317. else if (host_status
  318. & (TIFM_MMCSD_CCRC | TIFM_MMCSD_DCRC))
  319. error_code = MMC_ERR_BADCRC;
  320. writel(TIFM_FIFO_INT_SETALL,
  321. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  322. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  323. if (host->req->stop) {
  324. if (host->state == SCMD) {
  325. host->req->stop->error = error_code;
  326. } else if (host->state == BRS
  327. || host->state == CARD
  328. || host->state == FIFO) {
  329. host->req->cmd->error = error_code;
  330. tifm_sd_exec(host, host->req->stop);
  331. host->state = SCMD;
  332. goto done;
  333. } else {
  334. host->req->cmd->error = error_code;
  335. }
  336. } else {
  337. host->req->cmd->error = error_code;
  338. }
  339. host->state = READY;
  340. }
  341. if (host_status & TIFM_MMCSD_CB)
  342. host->flags |= CARD_BUSY;
  343. if ((host_status & TIFM_MMCSD_EOFB)
  344. && (host->flags & CARD_BUSY)) {
  345. host->written_blocks++;
  346. host->flags &= ~CARD_BUSY;
  347. }
  348. }
  349. if (host->req)
  350. tifm_sd_process_cmd(sock, host, host_status);
  351. done:
  352. dev_dbg(&sock->dev, "host_status %x, fifo_status %x\n",
  353. host_status, fifo_status);
  354. spin_unlock(&sock->lock);
  355. }
  356. static void tifm_sd_prepare_data(struct tifm_sd *host, struct mmc_command *cmd)
  357. {
  358. struct tifm_dev *sock = host->dev;
  359. unsigned int dest_cnt;
  360. /* DMA style IO */
  361. dev_dbg(&sock->dev, "setting dma for %d blocks\n",
  362. cmd->data->blocks);
  363. writel(TIFM_FIFO_INT_SETALL,
  364. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  365. writel(ilog2(cmd->data->blksz) - 2,
  366. sock->addr + SOCK_FIFO_PAGE_SIZE);
  367. writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
  368. writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  369. dest_cnt = (cmd->data->blocks) << 8;
  370. writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
  371. writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  372. writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  373. if (cmd->data->flags & MMC_DATA_WRITE) {
  374. writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  375. writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
  376. sock->addr + SOCK_DMA_CONTROL);
  377. } else {
  378. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  379. writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
  380. }
  381. }
  382. static void tifm_sd_set_data_timeout(struct tifm_sd *host,
  383. struct mmc_data *data)
  384. {
  385. struct tifm_dev *sock = host->dev;
  386. unsigned int data_timeout = data->timeout_clks;
  387. if (fixed_timeout)
  388. return;
  389. data_timeout += data->timeout_ns /
  390. ((1000000000UL / host->clk_freq) * host->clk_div);
  391. if (data_timeout < 0xffff) {
  392. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  393. writel((~TIFM_MMCSD_DPE)
  394. & readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  395. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  396. } else {
  397. data_timeout = (data_timeout >> 10) + 1;
  398. if (data_timeout > 0xffff)
  399. data_timeout = 0; /* set to unlimited */
  400. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  401. writel(TIFM_MMCSD_DPE
  402. | readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  403. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  404. }
  405. }
  406. static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  407. {
  408. struct tifm_sd *host = mmc_priv(mmc);
  409. struct tifm_dev *sock = host->dev;
  410. unsigned long flags;
  411. int sg_count = 0;
  412. struct mmc_data *r_data = mrq->cmd->data;
  413. spin_lock_irqsave(&sock->lock, flags);
  414. if (host->flags & EJECT) {
  415. spin_unlock_irqrestore(&sock->lock, flags);
  416. goto err_out;
  417. }
  418. if (host->req) {
  419. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  420. spin_unlock_irqrestore(&sock->lock, flags);
  421. goto err_out;
  422. }
  423. if (r_data) {
  424. tifm_sd_set_data_timeout(host, r_data);
  425. sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
  426. mrq->cmd->flags & MMC_DATA_WRITE
  427. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  428. if (sg_count != 1) {
  429. printk(KERN_ERR DRIVER_NAME
  430. ": scatterlist map failed\n");
  431. spin_unlock_irqrestore(&sock->lock, flags);
  432. goto err_out;
  433. }
  434. host->written_blocks = 0;
  435. host->flags &= ~CARD_BUSY;
  436. tifm_sd_prepare_data(host, mrq->cmd);
  437. }
  438. host->req = mrq;
  439. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  440. host->state = CMD;
  441. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  442. sock->addr + SOCK_CONTROL);
  443. tifm_sd_exec(host, mrq->cmd);
  444. spin_unlock_irqrestore(&sock->lock, flags);
  445. return;
  446. err_out:
  447. if (sg_count > 0)
  448. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  449. (r_data->flags & MMC_DATA_WRITE)
  450. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  451. mrq->cmd->error = MMC_ERR_TIMEOUT;
  452. mmc_request_done(mmc, mrq);
  453. }
  454. static void tifm_sd_end_cmd(unsigned long data)
  455. {
  456. struct tifm_sd *host = (struct tifm_sd*)data;
  457. struct tifm_dev *sock = host->dev;
  458. struct mmc_host *mmc = tifm_get_drvdata(sock);
  459. struct mmc_request *mrq;
  460. struct mmc_data *r_data = NULL;
  461. unsigned long flags;
  462. spin_lock_irqsave(&sock->lock, flags);
  463. del_timer(&host->timer);
  464. mrq = host->req;
  465. host->req = NULL;
  466. host->state = IDLE;
  467. if (!mrq) {
  468. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  469. spin_unlock_irqrestore(&sock->lock, flags);
  470. return;
  471. }
  472. r_data = mrq->cmd->data;
  473. if (r_data) {
  474. if (r_data->flags & MMC_DATA_WRITE) {
  475. r_data->bytes_xfered = host->written_blocks
  476. * r_data->blksz;
  477. } else {
  478. r_data->bytes_xfered = r_data->blocks -
  479. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  480. r_data->bytes_xfered *= r_data->blksz;
  481. r_data->bytes_xfered += r_data->blksz -
  482. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  483. }
  484. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  485. (r_data->flags & MMC_DATA_WRITE)
  486. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  487. }
  488. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  489. sock->addr + SOCK_CONTROL);
  490. spin_unlock_irqrestore(&sock->lock, flags);
  491. mmc_request_done(mmc, mrq);
  492. }
  493. static void tifm_sd_request_nodma(struct mmc_host *mmc, struct mmc_request *mrq)
  494. {
  495. struct tifm_sd *host = mmc_priv(mmc);
  496. struct tifm_dev *sock = host->dev;
  497. unsigned long flags;
  498. struct mmc_data *r_data = mrq->cmd->data;
  499. spin_lock_irqsave(&sock->lock, flags);
  500. if (host->flags & EJECT) {
  501. spin_unlock_irqrestore(&sock->lock, flags);
  502. goto err_out;
  503. }
  504. if (host->req) {
  505. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  506. spin_unlock_irqrestore(&sock->lock, flags);
  507. goto err_out;
  508. }
  509. if (r_data) {
  510. tifm_sd_set_data_timeout(host, r_data);
  511. host->buffer_size = mrq->cmd->data->blocks
  512. * mrq->cmd->data->blksz;
  513. writel(TIFM_MMCSD_BUFINT
  514. | readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  515. sock->addr + SOCK_MMCSD_INT_ENABLE);
  516. writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8)
  517. | (TIFM_MMCSD_FIFO_SIZE - 1),
  518. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  519. host->written_blocks = 0;
  520. host->flags &= ~CARD_BUSY;
  521. host->buffer_pos = 0;
  522. writel(r_data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  523. writel(r_data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  524. }
  525. host->req = mrq;
  526. mod_timer(&host->timer, jiffies + host->timeout_jiffies);
  527. host->state = CMD;
  528. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  529. sock->addr + SOCK_CONTROL);
  530. tifm_sd_exec(host, mrq->cmd);
  531. spin_unlock_irqrestore(&sock->lock, flags);
  532. return;
  533. err_out:
  534. mrq->cmd->error = MMC_ERR_TIMEOUT;
  535. mmc_request_done(mmc, mrq);
  536. }
  537. static void tifm_sd_end_cmd_nodma(unsigned long data)
  538. {
  539. struct tifm_sd *host = (struct tifm_sd*)data;
  540. struct tifm_dev *sock = host->dev;
  541. struct mmc_host *mmc = tifm_get_drvdata(sock);
  542. struct mmc_request *mrq;
  543. struct mmc_data *r_data = NULL;
  544. unsigned long flags;
  545. spin_lock_irqsave(&sock->lock, flags);
  546. del_timer(&host->timer);
  547. mrq = host->req;
  548. host->req = NULL;
  549. host->state = IDLE;
  550. if (!mrq) {
  551. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  552. spin_unlock_irqrestore(&sock->lock, flags);
  553. return;
  554. }
  555. r_data = mrq->cmd->data;
  556. if (r_data) {
  557. writel((~TIFM_MMCSD_BUFINT) &
  558. readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  559. sock->addr + SOCK_MMCSD_INT_ENABLE);
  560. if (r_data->flags & MMC_DATA_WRITE) {
  561. r_data->bytes_xfered = host->written_blocks
  562. * r_data->blksz;
  563. } else {
  564. r_data->bytes_xfered = r_data->blocks -
  565. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  566. r_data->bytes_xfered *= r_data->blksz;
  567. r_data->bytes_xfered += r_data->blksz -
  568. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  569. }
  570. host->buffer_pos = 0;
  571. host->buffer_size = 0;
  572. }
  573. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  574. sock->addr + SOCK_CONTROL);
  575. spin_unlock_irqrestore(&sock->lock, flags);
  576. mmc_request_done(mmc, mrq);
  577. }
  578. static void tifm_sd_terminate(struct tifm_sd *host)
  579. {
  580. struct tifm_dev *sock = host->dev;
  581. unsigned long flags;
  582. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  583. mmiowb();
  584. spin_lock_irqsave(&sock->lock, flags);
  585. host->flags |= EJECT;
  586. if (host->req) {
  587. writel(TIFM_FIFO_INT_SETALL,
  588. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  589. writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  590. tasklet_schedule(&host->finish_tasklet);
  591. }
  592. spin_unlock_irqrestore(&sock->lock, flags);
  593. }
  594. static void tifm_sd_abort(unsigned long data)
  595. {
  596. struct tifm_sd *host = (struct tifm_sd*)data;
  597. printk(KERN_ERR DRIVER_NAME
  598. ": card failed to respond for a long period of time");
  599. tifm_sd_terminate(host);
  600. tifm_eject(host->dev);
  601. }
  602. static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  603. {
  604. struct tifm_sd *host = mmc_priv(mmc);
  605. struct tifm_dev *sock = host->dev;
  606. unsigned int clk_div1, clk_div2;
  607. unsigned long flags;
  608. spin_lock_irqsave(&sock->lock, flags);
  609. dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
  610. ios->power_mode);
  611. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  612. writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
  613. sock->addr + SOCK_MMCSD_CONFIG);
  614. } else {
  615. writel((~TIFM_MMCSD_4BBUS)
  616. & readl(sock->addr + SOCK_MMCSD_CONFIG),
  617. sock->addr + SOCK_MMCSD_CONFIG);
  618. }
  619. if (ios->clock) {
  620. clk_div1 = 20000000 / ios->clock;
  621. if (!clk_div1)
  622. clk_div1 = 1;
  623. clk_div2 = 24000000 / ios->clock;
  624. if (!clk_div2)
  625. clk_div2 = 1;
  626. if ((20000000 / clk_div1) > ios->clock)
  627. clk_div1++;
  628. if ((24000000 / clk_div2) > ios->clock)
  629. clk_div2++;
  630. if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
  631. host->clk_freq = 20000000;
  632. host->clk_div = clk_div1;
  633. writel((~TIFM_CTRL_FAST_CLK)
  634. & readl(sock->addr + SOCK_CONTROL),
  635. sock->addr + SOCK_CONTROL);
  636. } else {
  637. host->clk_freq = 24000000;
  638. host->clk_div = clk_div2;
  639. writel(TIFM_CTRL_FAST_CLK
  640. | readl(sock->addr + SOCK_CONTROL),
  641. sock->addr + SOCK_CONTROL);
  642. }
  643. } else {
  644. host->clk_div = 0;
  645. }
  646. host->clk_div &= TIFM_MMCSD_CLKMASK;
  647. writel(host->clk_div
  648. | ((~TIFM_MMCSD_CLKMASK)
  649. & readl(sock->addr + SOCK_MMCSD_CONFIG)),
  650. sock->addr + SOCK_MMCSD_CONFIG);
  651. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  652. host->flags |= OPENDRAIN;
  653. else
  654. host->flags &= ~OPENDRAIN;
  655. /* chip_select : maybe later */
  656. //vdd
  657. //power is set before probe / after remove
  658. //I believe, power_off when already marked for eject is sufficient to
  659. // allow removal.
  660. if ((host->flags & EJECT) && ios->power_mode == MMC_POWER_OFF) {
  661. host->flags |= EJECT_DONE;
  662. wake_up_all(&host->notify);
  663. }
  664. spin_unlock_irqrestore(&sock->lock, flags);
  665. }
  666. static int tifm_sd_ro(struct mmc_host *mmc)
  667. {
  668. int rc;
  669. struct tifm_sd *host = mmc_priv(mmc);
  670. struct tifm_dev *sock = host->dev;
  671. unsigned long flags;
  672. spin_lock_irqsave(&sock->lock, flags);
  673. host->flags |= (CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE));
  674. rc = (host->flags & CARD_RO) ? 1 : 0;
  675. spin_unlock_irqrestore(&sock->lock, flags);
  676. return rc;
  677. }
  678. static struct mmc_host_ops tifm_sd_ops = {
  679. .request = tifm_sd_request,
  680. .set_ios = tifm_sd_ios,
  681. .get_ro = tifm_sd_ro
  682. };
  683. static int tifm_sd_initialize_host(struct tifm_sd *host)
  684. {
  685. int rc;
  686. unsigned int host_status = 0;
  687. struct tifm_dev *sock = host->dev;
  688. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  689. mmiowb();
  690. host->clk_div = 61;
  691. host->clk_freq = 20000000;
  692. writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
  693. writel(host->clk_div | TIFM_MMCSD_POWER,
  694. sock->addr + SOCK_MMCSD_CONFIG);
  695. /* wait up to 0.51 sec for reset */
  696. for (rc = 2; rc <= 256; rc <<= 1) {
  697. if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
  698. rc = 0;
  699. break;
  700. }
  701. msleep(rc);
  702. }
  703. if (rc) {
  704. printk(KERN_ERR DRIVER_NAME
  705. ": controller failed to reset\n");
  706. return -ENODEV;
  707. }
  708. writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  709. writel(host->clk_div | TIFM_MMCSD_POWER,
  710. sock->addr + SOCK_MMCSD_CONFIG);
  711. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  712. // command timeout fixed to 64 clocks for now
  713. writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO);
  714. writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
  715. /* INAB should take much less than reset */
  716. for (rc = 1; rc <= 16; rc <<= 1) {
  717. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  718. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  719. if (!(host_status & TIFM_MMCSD_ERRMASK)
  720. && (host_status & TIFM_MMCSD_EOC)) {
  721. rc = 0;
  722. break;
  723. }
  724. msleep(rc);
  725. }
  726. if (rc) {
  727. printk(KERN_ERR DRIVER_NAME
  728. ": card not ready - probe failed on initialization\n");
  729. return -ENODEV;
  730. }
  731. writel(TIFM_MMCSD_DATAMASK | TIFM_MMCSD_ERRMASK,
  732. sock->addr + SOCK_MMCSD_INT_ENABLE);
  733. mmiowb();
  734. return 0;
  735. }
  736. static int tifm_sd_probe(struct tifm_dev *sock)
  737. {
  738. struct mmc_host *mmc;
  739. struct tifm_sd *host;
  740. int rc = -EIO;
  741. if (!(TIFM_SOCK_STATE_OCCUPIED
  742. & readl(sock->addr + SOCK_PRESENT_STATE))) {
  743. printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
  744. return rc;
  745. }
  746. mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
  747. if (!mmc)
  748. return -ENOMEM;
  749. host = mmc_priv(mmc);
  750. tifm_set_drvdata(sock, mmc);
  751. host->dev = sock;
  752. host->timeout_jiffies = msecs_to_jiffies(1000);
  753. init_waitqueue_head(&host->notify);
  754. tasklet_init(&host->finish_tasklet,
  755. no_dma ? tifm_sd_end_cmd_nodma : tifm_sd_end_cmd,
  756. (unsigned long)host);
  757. setup_timer(&host->timer, tifm_sd_abort, (unsigned long)host);
  758. tifm_sd_ops.request = no_dma ? tifm_sd_request_nodma : tifm_sd_request;
  759. mmc->ops = &tifm_sd_ops;
  760. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  761. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE;
  762. mmc->f_min = 20000000 / 60;
  763. mmc->f_max = 24000000;
  764. mmc->max_hw_segs = 1;
  765. mmc->max_phys_segs = 1;
  766. mmc->max_sectors = 127;
  767. mmc->max_seg_size = mmc->max_sectors << 11; //2k maximum hw block length
  768. sock->signal_irq = tifm_sd_signal_irq;
  769. rc = tifm_sd_initialize_host(host);
  770. if (!rc)
  771. rc = mmc_add_host(mmc);
  772. if (rc)
  773. goto out_free_mmc;
  774. return 0;
  775. out_free_mmc:
  776. mmc_free_host(mmc);
  777. return rc;
  778. }
  779. static void tifm_sd_remove(struct tifm_dev *sock)
  780. {
  781. struct mmc_host *mmc = tifm_get_drvdata(sock);
  782. struct tifm_sd *host = mmc_priv(mmc);
  783. del_timer_sync(&host->timer);
  784. tifm_sd_terminate(host);
  785. wait_event_timeout(host->notify, host->flags & EJECT_DONE,
  786. host->timeout_jiffies);
  787. tasklet_kill(&host->finish_tasklet);
  788. mmc_remove_host(mmc);
  789. /* The meaning of the bit majority in this constant is unknown. */
  790. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  791. sock->addr + SOCK_CONTROL);
  792. tifm_set_drvdata(sock, NULL);
  793. mmc_free_host(mmc);
  794. }
  795. #ifdef CONFIG_PM
  796. static int tifm_sd_suspend(struct tifm_dev *sock, pm_message_t state)
  797. {
  798. struct mmc_host *mmc = tifm_get_drvdata(sock);
  799. int rc;
  800. rc = mmc_suspend_host(mmc, state);
  801. /* The meaning of the bit majority in this constant is unknown. */
  802. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  803. sock->addr + SOCK_CONTROL);
  804. return rc;
  805. }
  806. static int tifm_sd_resume(struct tifm_dev *sock)
  807. {
  808. struct mmc_host *mmc = tifm_get_drvdata(sock);
  809. struct tifm_sd *host = mmc_priv(mmc);
  810. if (sock->media_id != FM_SD
  811. || tifm_sd_initialize_host(host)) {
  812. tifm_eject(sock);
  813. return 0;
  814. } else {
  815. return mmc_resume_host(mmc);
  816. }
  817. }
  818. #else
  819. #define tifm_sd_suspend NULL
  820. #define tifm_sd_resume NULL
  821. #endif /* CONFIG_PM */
  822. static tifm_media_id tifm_sd_id_tbl[] = {
  823. FM_SD, 0
  824. };
  825. static struct tifm_driver tifm_sd_driver = {
  826. .driver = {
  827. .name = DRIVER_NAME,
  828. .owner = THIS_MODULE
  829. },
  830. .id_table = tifm_sd_id_tbl,
  831. .probe = tifm_sd_probe,
  832. .remove = tifm_sd_remove,
  833. .suspend = tifm_sd_suspend,
  834. .resume = tifm_sd_resume
  835. };
  836. static int __init tifm_sd_init(void)
  837. {
  838. return tifm_register_driver(&tifm_sd_driver);
  839. }
  840. static void __exit tifm_sd_exit(void)
  841. {
  842. tifm_unregister_driver(&tifm_sd_driver);
  843. }
  844. MODULE_AUTHOR("Alex Dubov");
  845. MODULE_DESCRIPTION("TI FlashMedia SD driver");
  846. MODULE_LICENSE("GPL");
  847. MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
  848. MODULE_VERSION(DRIVER_VERSION);
  849. module_init(tifm_sd_init);
  850. module_exit(tifm_sd_exit);