base.c 86 KB

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  1. /*-
  2. * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
  3. * Copyright (c) 2004-2005 Atheros Communications, Inc.
  4. * Copyright (c) 2006 Devicescape Software, Inc.
  5. * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
  6. * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
  7. *
  8. * All rights reserved.
  9. *
  10. * Redistribution and use in source and binary forms, with or without
  11. * modification, are permitted provided that the following conditions
  12. * are met:
  13. * 1. Redistributions of source code must retain the above copyright
  14. * notice, this list of conditions and the following disclaimer,
  15. * without modification.
  16. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17. * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  18. * redistribution must be conditioned upon including a substantially
  19. * similar Disclaimer requirement for further binary redistribution.
  20. * 3. Neither the names of the above-listed copyright holders nor the names
  21. * of any contributors may be used to endorse or promote products derived
  22. * from this software without specific prior written permission.
  23. *
  24. * Alternatively, this software may be distributed under the terms of the
  25. * GNU General Public License ("GPL") version 2 as published by the Free
  26. * Software Foundation.
  27. *
  28. * NO WARRANTY
  29. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31. * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  32. * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  33. * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  34. * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  35. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  36. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  37. * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  38. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  39. * THE POSSIBILITY OF SUCH DAMAGES.
  40. *
  41. */
  42. #include <linux/module.h>
  43. #include <linux/delay.h>
  44. #include <linux/hardirq.h>
  45. #include <linux/if.h>
  46. #include <linux/io.h>
  47. #include <linux/netdevice.h>
  48. #include <linux/cache.h>
  49. #include <linux/pci.h>
  50. #include <linux/ethtool.h>
  51. #include <linux/uaccess.h>
  52. #include <net/ieee80211_radiotap.h>
  53. #include <asm/unaligned.h>
  54. #include "base.h"
  55. #include "reg.h"
  56. #include "debug.h"
  57. static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
  58. static int modparam_nohwcrypt;
  59. module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  60. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  61. static int modparam_all_channels;
  62. module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
  63. MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
  64. /******************\
  65. * Internal defines *
  66. \******************/
  67. /* Module info */
  68. MODULE_AUTHOR("Jiri Slaby");
  69. MODULE_AUTHOR("Nick Kossifidis");
  70. MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
  71. MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
  72. MODULE_LICENSE("Dual BSD/GPL");
  73. MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
  74. /* Known PCI ids */
  75. static const struct pci_device_id ath5k_pci_id_table[] = {
  76. { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
  77. { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
  78. { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
  79. { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
  80. { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
  81. { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
  82. { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
  83. { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
  84. { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
  85. { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
  86. { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
  87. { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
  88. { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
  89. { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
  90. { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
  91. { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
  92. { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
  93. { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
  94. { 0 }
  95. };
  96. MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
  97. /* Known SREVs */
  98. static const struct ath5k_srev_name srev_names[] = {
  99. { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
  100. { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
  101. { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
  102. { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
  103. { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
  104. { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
  105. { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
  106. { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
  107. { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
  108. { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
  109. { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
  110. { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
  111. { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
  112. { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
  113. { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
  114. { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
  115. { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
  116. { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
  117. { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
  118. { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
  119. { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
  120. { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
  121. { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
  122. { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
  123. { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
  124. { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
  125. { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
  126. { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
  127. { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
  128. { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
  129. { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
  130. { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
  131. { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
  132. { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
  133. { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
  134. { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
  135. };
  136. static const struct ieee80211_rate ath5k_rates[] = {
  137. { .bitrate = 10,
  138. .hw_value = ATH5K_RATE_CODE_1M, },
  139. { .bitrate = 20,
  140. .hw_value = ATH5K_RATE_CODE_2M,
  141. .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
  142. .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  143. { .bitrate = 55,
  144. .hw_value = ATH5K_RATE_CODE_5_5M,
  145. .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
  146. .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  147. { .bitrate = 110,
  148. .hw_value = ATH5K_RATE_CODE_11M,
  149. .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
  150. .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  151. { .bitrate = 60,
  152. .hw_value = ATH5K_RATE_CODE_6M,
  153. .flags = 0 },
  154. { .bitrate = 90,
  155. .hw_value = ATH5K_RATE_CODE_9M,
  156. .flags = 0 },
  157. { .bitrate = 120,
  158. .hw_value = ATH5K_RATE_CODE_12M,
  159. .flags = 0 },
  160. { .bitrate = 180,
  161. .hw_value = ATH5K_RATE_CODE_18M,
  162. .flags = 0 },
  163. { .bitrate = 240,
  164. .hw_value = ATH5K_RATE_CODE_24M,
  165. .flags = 0 },
  166. { .bitrate = 360,
  167. .hw_value = ATH5K_RATE_CODE_36M,
  168. .flags = 0 },
  169. { .bitrate = 480,
  170. .hw_value = ATH5K_RATE_CODE_48M,
  171. .flags = 0 },
  172. { .bitrate = 540,
  173. .hw_value = ATH5K_RATE_CODE_54M,
  174. .flags = 0 },
  175. /* XR missing */
  176. };
  177. /*
  178. * Prototypes - PCI stack related functions
  179. */
  180. static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
  181. const struct pci_device_id *id);
  182. static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
  183. #ifdef CONFIG_PM
  184. static int ath5k_pci_suspend(struct pci_dev *pdev,
  185. pm_message_t state);
  186. static int ath5k_pci_resume(struct pci_dev *pdev);
  187. #else
  188. #define ath5k_pci_suspend NULL
  189. #define ath5k_pci_resume NULL
  190. #endif /* CONFIG_PM */
  191. static struct pci_driver ath5k_pci_driver = {
  192. .name = KBUILD_MODNAME,
  193. .id_table = ath5k_pci_id_table,
  194. .probe = ath5k_pci_probe,
  195. .remove = __devexit_p(ath5k_pci_remove),
  196. .suspend = ath5k_pci_suspend,
  197. .resume = ath5k_pci_resume,
  198. };
  199. /*
  200. * Prototypes - MAC 802.11 stack related functions
  201. */
  202. static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
  203. static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
  204. struct ath5k_txq *txq);
  205. static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
  206. static int ath5k_reset_wake(struct ath5k_softc *sc);
  207. static int ath5k_start(struct ieee80211_hw *hw);
  208. static void ath5k_stop(struct ieee80211_hw *hw);
  209. static int ath5k_add_interface(struct ieee80211_hw *hw,
  210. struct ieee80211_if_init_conf *conf);
  211. static void ath5k_remove_interface(struct ieee80211_hw *hw,
  212. struct ieee80211_if_init_conf *conf);
  213. static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
  214. static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
  215. int mc_count, struct dev_addr_list *mc_list);
  216. static void ath5k_configure_filter(struct ieee80211_hw *hw,
  217. unsigned int changed_flags,
  218. unsigned int *new_flags,
  219. u64 multicast);
  220. static int ath5k_set_key(struct ieee80211_hw *hw,
  221. enum set_key_cmd cmd,
  222. struct ieee80211_vif *vif, struct ieee80211_sta *sta,
  223. struct ieee80211_key_conf *key);
  224. static int ath5k_get_stats(struct ieee80211_hw *hw,
  225. struct ieee80211_low_level_stats *stats);
  226. static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
  227. struct ieee80211_tx_queue_stats *stats);
  228. static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
  229. static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
  230. static void ath5k_reset_tsf(struct ieee80211_hw *hw);
  231. static int ath5k_beacon_update(struct ieee80211_hw *hw,
  232. struct ieee80211_vif *vif);
  233. static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
  234. struct ieee80211_vif *vif,
  235. struct ieee80211_bss_conf *bss_conf,
  236. u32 changes);
  237. static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
  238. static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
  239. static const struct ieee80211_ops ath5k_hw_ops = {
  240. .tx = ath5k_tx,
  241. .start = ath5k_start,
  242. .stop = ath5k_stop,
  243. .add_interface = ath5k_add_interface,
  244. .remove_interface = ath5k_remove_interface,
  245. .config = ath5k_config,
  246. .prepare_multicast = ath5k_prepare_multicast,
  247. .configure_filter = ath5k_configure_filter,
  248. .set_key = ath5k_set_key,
  249. .get_stats = ath5k_get_stats,
  250. .conf_tx = NULL,
  251. .get_tx_stats = ath5k_get_tx_stats,
  252. .get_tsf = ath5k_get_tsf,
  253. .set_tsf = ath5k_set_tsf,
  254. .reset_tsf = ath5k_reset_tsf,
  255. .bss_info_changed = ath5k_bss_info_changed,
  256. .sw_scan_start = ath5k_sw_scan_start,
  257. .sw_scan_complete = ath5k_sw_scan_complete,
  258. };
  259. /*
  260. * Prototypes - Internal functions
  261. */
  262. /* Attach detach */
  263. static int ath5k_attach(struct pci_dev *pdev,
  264. struct ieee80211_hw *hw);
  265. static void ath5k_detach(struct pci_dev *pdev,
  266. struct ieee80211_hw *hw);
  267. /* Channel/mode setup */
  268. static inline short ath5k_ieee2mhz(short chan);
  269. static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
  270. struct ieee80211_channel *channels,
  271. unsigned int mode,
  272. unsigned int max);
  273. static int ath5k_setup_bands(struct ieee80211_hw *hw);
  274. static int ath5k_chan_set(struct ath5k_softc *sc,
  275. struct ieee80211_channel *chan);
  276. static void ath5k_setcurmode(struct ath5k_softc *sc,
  277. unsigned int mode);
  278. static void ath5k_mode_setup(struct ath5k_softc *sc);
  279. /* Descriptor setup */
  280. static int ath5k_desc_alloc(struct ath5k_softc *sc,
  281. struct pci_dev *pdev);
  282. static void ath5k_desc_free(struct ath5k_softc *sc,
  283. struct pci_dev *pdev);
  284. /* Buffers setup */
  285. static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
  286. struct ath5k_buf *bf);
  287. static int ath5k_txbuf_setup(struct ath5k_softc *sc,
  288. struct ath5k_buf *bf,
  289. struct ath5k_txq *txq);
  290. static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
  291. struct ath5k_buf *bf)
  292. {
  293. BUG_ON(!bf);
  294. if (!bf->skb)
  295. return;
  296. pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
  297. PCI_DMA_TODEVICE);
  298. dev_kfree_skb_any(bf->skb);
  299. bf->skb = NULL;
  300. }
  301. static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
  302. struct ath5k_buf *bf)
  303. {
  304. BUG_ON(!bf);
  305. if (!bf->skb)
  306. return;
  307. pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
  308. PCI_DMA_FROMDEVICE);
  309. dev_kfree_skb_any(bf->skb);
  310. bf->skb = NULL;
  311. }
  312. /* Queues setup */
  313. static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
  314. int qtype, int subtype);
  315. static int ath5k_beaconq_setup(struct ath5k_hw *ah);
  316. static int ath5k_beaconq_config(struct ath5k_softc *sc);
  317. static void ath5k_txq_drainq(struct ath5k_softc *sc,
  318. struct ath5k_txq *txq);
  319. static void ath5k_txq_cleanup(struct ath5k_softc *sc);
  320. static void ath5k_txq_release(struct ath5k_softc *sc);
  321. /* Rx handling */
  322. static int ath5k_rx_start(struct ath5k_softc *sc);
  323. static void ath5k_rx_stop(struct ath5k_softc *sc);
  324. static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
  325. struct ath5k_desc *ds,
  326. struct sk_buff *skb,
  327. struct ath5k_rx_status *rs);
  328. static void ath5k_tasklet_rx(unsigned long data);
  329. /* Tx handling */
  330. static void ath5k_tx_processq(struct ath5k_softc *sc,
  331. struct ath5k_txq *txq);
  332. static void ath5k_tasklet_tx(unsigned long data);
  333. /* Beacon handling */
  334. static int ath5k_beacon_setup(struct ath5k_softc *sc,
  335. struct ath5k_buf *bf);
  336. static void ath5k_beacon_send(struct ath5k_softc *sc);
  337. static void ath5k_beacon_config(struct ath5k_softc *sc);
  338. static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
  339. static void ath5k_tasklet_beacon(unsigned long data);
  340. static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
  341. {
  342. u64 tsf = ath5k_hw_get_tsf64(ah);
  343. if ((tsf & 0x7fff) < rstamp)
  344. tsf -= 0x8000;
  345. return (tsf & ~0x7fff) | rstamp;
  346. }
  347. /* Interrupt handling */
  348. static int ath5k_init(struct ath5k_softc *sc);
  349. static int ath5k_stop_locked(struct ath5k_softc *sc);
  350. static int ath5k_stop_hw(struct ath5k_softc *sc);
  351. static irqreturn_t ath5k_intr(int irq, void *dev_id);
  352. static void ath5k_tasklet_reset(unsigned long data);
  353. static void ath5k_tasklet_calibrate(unsigned long data);
  354. /*
  355. * Module init/exit functions
  356. */
  357. static int __init
  358. init_ath5k_pci(void)
  359. {
  360. int ret;
  361. ath5k_debug_init();
  362. ret = pci_register_driver(&ath5k_pci_driver);
  363. if (ret) {
  364. printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
  365. return ret;
  366. }
  367. return 0;
  368. }
  369. static void __exit
  370. exit_ath5k_pci(void)
  371. {
  372. pci_unregister_driver(&ath5k_pci_driver);
  373. ath5k_debug_finish();
  374. }
  375. module_init(init_ath5k_pci);
  376. module_exit(exit_ath5k_pci);
  377. /********************\
  378. * PCI Initialization *
  379. \********************/
  380. static const char *
  381. ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
  382. {
  383. const char *name = "xxxxx";
  384. unsigned int i;
  385. for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
  386. if (srev_names[i].sr_type != type)
  387. continue;
  388. if ((val & 0xf0) == srev_names[i].sr_val)
  389. name = srev_names[i].sr_name;
  390. if ((val & 0xff) == srev_names[i].sr_val) {
  391. name = srev_names[i].sr_name;
  392. break;
  393. }
  394. }
  395. return name;
  396. }
  397. static int __devinit
  398. ath5k_pci_probe(struct pci_dev *pdev,
  399. const struct pci_device_id *id)
  400. {
  401. void __iomem *mem;
  402. struct ath5k_softc *sc;
  403. struct ath_common *common;
  404. struct ieee80211_hw *hw;
  405. int ret;
  406. u8 csz;
  407. ret = pci_enable_device(pdev);
  408. if (ret) {
  409. dev_err(&pdev->dev, "can't enable device\n");
  410. goto err;
  411. }
  412. /* XXX 32-bit addressing only */
  413. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  414. if (ret) {
  415. dev_err(&pdev->dev, "32-bit DMA not available\n");
  416. goto err_dis;
  417. }
  418. /*
  419. * Cache line size is used to size and align various
  420. * structures used to communicate with the hardware.
  421. */
  422. pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
  423. if (csz == 0) {
  424. /*
  425. * Linux 2.4.18 (at least) writes the cache line size
  426. * register as a 16-bit wide register which is wrong.
  427. * We must have this setup properly for rx buffer
  428. * DMA to work so force a reasonable value here if it
  429. * comes up zero.
  430. */
  431. csz = L1_CACHE_BYTES >> 2;
  432. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
  433. }
  434. /*
  435. * The default setting of latency timer yields poor results,
  436. * set it to the value used by other systems. It may be worth
  437. * tweaking this setting more.
  438. */
  439. pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
  440. /* Enable bus mastering */
  441. pci_set_master(pdev);
  442. /*
  443. * Disable the RETRY_TIMEOUT register (0x41) to keep
  444. * PCI Tx retries from interfering with C3 CPU state.
  445. */
  446. pci_write_config_byte(pdev, 0x41, 0);
  447. ret = pci_request_region(pdev, 0, "ath5k");
  448. if (ret) {
  449. dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
  450. goto err_dis;
  451. }
  452. mem = pci_iomap(pdev, 0, 0);
  453. if (!mem) {
  454. dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
  455. ret = -EIO;
  456. goto err_reg;
  457. }
  458. /*
  459. * Allocate hw (mac80211 main struct)
  460. * and hw->priv (driver private data)
  461. */
  462. hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
  463. if (hw == NULL) {
  464. dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
  465. ret = -ENOMEM;
  466. goto err_map;
  467. }
  468. dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
  469. /* Initialize driver private data */
  470. SET_IEEE80211_DEV(hw, &pdev->dev);
  471. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  472. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  473. IEEE80211_HW_SIGNAL_DBM |
  474. IEEE80211_HW_NOISE_DBM;
  475. hw->wiphy->interface_modes =
  476. BIT(NL80211_IFTYPE_AP) |
  477. BIT(NL80211_IFTYPE_STATION) |
  478. BIT(NL80211_IFTYPE_ADHOC) |
  479. BIT(NL80211_IFTYPE_MESH_POINT);
  480. hw->extra_tx_headroom = 2;
  481. hw->channel_change_time = 5000;
  482. sc = hw->priv;
  483. sc->hw = hw;
  484. sc->pdev = pdev;
  485. ath5k_debug_init_device(sc);
  486. /*
  487. * Mark the device as detached to avoid processing
  488. * interrupts until setup is complete.
  489. */
  490. __set_bit(ATH_STAT_INVALID, sc->status);
  491. sc->iobase = mem; /* So we can unmap it on detach */
  492. sc->opmode = NL80211_IFTYPE_STATION;
  493. sc->bintval = 1000;
  494. mutex_init(&sc->lock);
  495. spin_lock_init(&sc->rxbuflock);
  496. spin_lock_init(&sc->txbuflock);
  497. spin_lock_init(&sc->block);
  498. /* Set private data */
  499. pci_set_drvdata(pdev, hw);
  500. /* Setup interrupt handler */
  501. ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
  502. if (ret) {
  503. ATH5K_ERR(sc, "request_irq failed\n");
  504. goto err_free;
  505. }
  506. /* Initialize device */
  507. sc->ah = ath5k_hw_attach(sc);
  508. if (IS_ERR(sc->ah)) {
  509. ret = PTR_ERR(sc->ah);
  510. goto err_irq;
  511. }
  512. common = ath5k_hw_common(sc->ah);
  513. common->cachelsz = csz << 2; /* convert to bytes */
  514. /* set up multi-rate retry capabilities */
  515. if (sc->ah->ah_version == AR5K_AR5212) {
  516. hw->max_rates = 4;
  517. hw->max_rate_tries = 11;
  518. }
  519. /* Finish private driver data initialization */
  520. ret = ath5k_attach(pdev, hw);
  521. if (ret)
  522. goto err_ah;
  523. ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
  524. ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
  525. sc->ah->ah_mac_srev,
  526. sc->ah->ah_phy_revision);
  527. if (!sc->ah->ah_single_chip) {
  528. /* Single chip radio (!RF5111) */
  529. if (sc->ah->ah_radio_5ghz_revision &&
  530. !sc->ah->ah_radio_2ghz_revision) {
  531. /* No 5GHz support -> report 2GHz radio */
  532. if (!test_bit(AR5K_MODE_11A,
  533. sc->ah->ah_capabilities.cap_mode)) {
  534. ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
  535. ath5k_chip_name(AR5K_VERSION_RAD,
  536. sc->ah->ah_radio_5ghz_revision),
  537. sc->ah->ah_radio_5ghz_revision);
  538. /* No 2GHz support (5110 and some
  539. * 5Ghz only cards) -> report 5Ghz radio */
  540. } else if (!test_bit(AR5K_MODE_11B,
  541. sc->ah->ah_capabilities.cap_mode)) {
  542. ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
  543. ath5k_chip_name(AR5K_VERSION_RAD,
  544. sc->ah->ah_radio_5ghz_revision),
  545. sc->ah->ah_radio_5ghz_revision);
  546. /* Multiband radio */
  547. } else {
  548. ATH5K_INFO(sc, "RF%s multiband radio found"
  549. " (0x%x)\n",
  550. ath5k_chip_name(AR5K_VERSION_RAD,
  551. sc->ah->ah_radio_5ghz_revision),
  552. sc->ah->ah_radio_5ghz_revision);
  553. }
  554. }
  555. /* Multi chip radio (RF5111 - RF2111) ->
  556. * report both 2GHz/5GHz radios */
  557. else if (sc->ah->ah_radio_5ghz_revision &&
  558. sc->ah->ah_radio_2ghz_revision){
  559. ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
  560. ath5k_chip_name(AR5K_VERSION_RAD,
  561. sc->ah->ah_radio_5ghz_revision),
  562. sc->ah->ah_radio_5ghz_revision);
  563. ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
  564. ath5k_chip_name(AR5K_VERSION_RAD,
  565. sc->ah->ah_radio_2ghz_revision),
  566. sc->ah->ah_radio_2ghz_revision);
  567. }
  568. }
  569. /* ready to process interrupts */
  570. __clear_bit(ATH_STAT_INVALID, sc->status);
  571. return 0;
  572. err_ah:
  573. ath5k_hw_detach(sc->ah);
  574. err_irq:
  575. free_irq(pdev->irq, sc);
  576. err_free:
  577. ieee80211_free_hw(hw);
  578. err_map:
  579. pci_iounmap(pdev, mem);
  580. err_reg:
  581. pci_release_region(pdev, 0);
  582. err_dis:
  583. pci_disable_device(pdev);
  584. err:
  585. return ret;
  586. }
  587. static void __devexit
  588. ath5k_pci_remove(struct pci_dev *pdev)
  589. {
  590. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  591. struct ath5k_softc *sc = hw->priv;
  592. ath5k_debug_finish_device(sc);
  593. ath5k_detach(pdev, hw);
  594. ath5k_hw_detach(sc->ah);
  595. free_irq(pdev->irq, sc);
  596. pci_iounmap(pdev, sc->iobase);
  597. pci_release_region(pdev, 0);
  598. pci_disable_device(pdev);
  599. ieee80211_free_hw(hw);
  600. }
  601. #ifdef CONFIG_PM
  602. static int
  603. ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  604. {
  605. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  606. struct ath5k_softc *sc = hw->priv;
  607. ath5k_led_off(sc);
  608. pci_save_state(pdev);
  609. pci_disable_device(pdev);
  610. pci_set_power_state(pdev, PCI_D3hot);
  611. return 0;
  612. }
  613. static int
  614. ath5k_pci_resume(struct pci_dev *pdev)
  615. {
  616. struct ieee80211_hw *hw = pci_get_drvdata(pdev);
  617. struct ath5k_softc *sc = hw->priv;
  618. int err;
  619. pci_restore_state(pdev);
  620. err = pci_enable_device(pdev);
  621. if (err)
  622. return err;
  623. /*
  624. * Suspend/Resume resets the PCI configuration space, so we have to
  625. * re-disable the RETRY_TIMEOUT register (0x41) to keep
  626. * PCI Tx retries from interfering with C3 CPU state
  627. */
  628. pci_write_config_byte(pdev, 0x41, 0);
  629. ath5k_led_enable(sc);
  630. return 0;
  631. }
  632. #endif /* CONFIG_PM */
  633. /***********************\
  634. * Driver Initialization *
  635. \***********************/
  636. static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
  637. {
  638. struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
  639. struct ath5k_softc *sc = hw->priv;
  640. struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
  641. return ath_reg_notifier_apply(wiphy, request, regulatory);
  642. }
  643. static int
  644. ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
  645. {
  646. struct ath5k_softc *sc = hw->priv;
  647. struct ath5k_hw *ah = sc->ah;
  648. struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
  649. u8 mac[ETH_ALEN] = {};
  650. int ret;
  651. ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
  652. /*
  653. * Check if the MAC has multi-rate retry support.
  654. * We do this by trying to setup a fake extended
  655. * descriptor. MAC's that don't have support will
  656. * return false w/o doing anything. MAC's that do
  657. * support it will return true w/o doing anything.
  658. */
  659. ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
  660. if (ret < 0)
  661. goto err;
  662. if (ret > 0)
  663. __set_bit(ATH_STAT_MRRETRY, sc->status);
  664. /*
  665. * Collect the channel list. The 802.11 layer
  666. * is resposible for filtering this list based
  667. * on settings like the phy mode and regulatory
  668. * domain restrictions.
  669. */
  670. ret = ath5k_setup_bands(hw);
  671. if (ret) {
  672. ATH5K_ERR(sc, "can't get channels\n");
  673. goto err;
  674. }
  675. /* NB: setup here so ath5k_rate_update is happy */
  676. if (test_bit(AR5K_MODE_11A, ah->ah_modes))
  677. ath5k_setcurmode(sc, AR5K_MODE_11A);
  678. else
  679. ath5k_setcurmode(sc, AR5K_MODE_11B);
  680. /*
  681. * Allocate tx+rx descriptors and populate the lists.
  682. */
  683. ret = ath5k_desc_alloc(sc, pdev);
  684. if (ret) {
  685. ATH5K_ERR(sc, "can't allocate descriptors\n");
  686. goto err;
  687. }
  688. /*
  689. * Allocate hardware transmit queues: one queue for
  690. * beacon frames and one data queue for each QoS
  691. * priority. Note that hw functions handle reseting
  692. * these queues at the needed time.
  693. */
  694. ret = ath5k_beaconq_setup(ah);
  695. if (ret < 0) {
  696. ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
  697. goto err_desc;
  698. }
  699. sc->bhalq = ret;
  700. sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
  701. if (IS_ERR(sc->cabq)) {
  702. ATH5K_ERR(sc, "can't setup cab queue\n");
  703. ret = PTR_ERR(sc->cabq);
  704. goto err_bhal;
  705. }
  706. sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
  707. if (IS_ERR(sc->txq)) {
  708. ATH5K_ERR(sc, "can't setup xmit queue\n");
  709. ret = PTR_ERR(sc->txq);
  710. goto err_queues;
  711. }
  712. tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
  713. tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
  714. tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
  715. tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
  716. tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
  717. ret = ath5k_eeprom_read_mac(ah, mac);
  718. if (ret) {
  719. ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
  720. sc->pdev->device);
  721. goto err_queues;
  722. }
  723. SET_IEEE80211_PERM_ADDR(hw, mac);
  724. /* All MAC address bits matter for ACKs */
  725. memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
  726. ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
  727. regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
  728. ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
  729. if (ret) {
  730. ATH5K_ERR(sc, "can't initialize regulatory system\n");
  731. goto err_queues;
  732. }
  733. ret = ieee80211_register_hw(hw);
  734. if (ret) {
  735. ATH5K_ERR(sc, "can't register ieee80211 hw\n");
  736. goto err_queues;
  737. }
  738. if (!ath_is_world_regd(regulatory))
  739. regulatory_hint(hw->wiphy, regulatory->alpha2);
  740. ath5k_init_leds(sc);
  741. return 0;
  742. err_queues:
  743. ath5k_txq_release(sc);
  744. err_bhal:
  745. ath5k_hw_release_tx_queue(ah, sc->bhalq);
  746. err_desc:
  747. ath5k_desc_free(sc, pdev);
  748. err:
  749. return ret;
  750. }
  751. static void
  752. ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
  753. {
  754. struct ath5k_softc *sc = hw->priv;
  755. /*
  756. * NB: the order of these is important:
  757. * o call the 802.11 layer before detaching ath5k_hw to
  758. * insure callbacks into the driver to delete global
  759. * key cache entries can be handled
  760. * o reclaim the tx queue data structures after calling
  761. * the 802.11 layer as we'll get called back to reclaim
  762. * node state and potentially want to use them
  763. * o to cleanup the tx queues the hal is called, so detach
  764. * it last
  765. * XXX: ??? detach ath5k_hw ???
  766. * Other than that, it's straightforward...
  767. */
  768. ieee80211_unregister_hw(hw);
  769. ath5k_desc_free(sc, pdev);
  770. ath5k_txq_release(sc);
  771. ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
  772. ath5k_unregister_leds(sc);
  773. /*
  774. * NB: can't reclaim these until after ieee80211_ifdetach
  775. * returns because we'll get called back to reclaim node
  776. * state and potentially want to use them.
  777. */
  778. }
  779. /********************\
  780. * Channel/mode setup *
  781. \********************/
  782. /*
  783. * Convert IEEE channel number to MHz frequency.
  784. */
  785. static inline short
  786. ath5k_ieee2mhz(short chan)
  787. {
  788. if (chan <= 14 || chan >= 27)
  789. return ieee80211chan2mhz(chan);
  790. else
  791. return 2212 + chan * 20;
  792. }
  793. /*
  794. * Returns true for the channel numbers used without all_channels modparam.
  795. */
  796. static bool ath5k_is_standard_channel(short chan)
  797. {
  798. return ((chan <= 14) ||
  799. /* UNII 1,2 */
  800. ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
  801. /* midband */
  802. ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
  803. /* UNII-3 */
  804. ((chan & 3) == 1 && chan >= 149 && chan <= 165));
  805. }
  806. static unsigned int
  807. ath5k_copy_channels(struct ath5k_hw *ah,
  808. struct ieee80211_channel *channels,
  809. unsigned int mode,
  810. unsigned int max)
  811. {
  812. unsigned int i, count, size, chfreq, freq, ch;
  813. if (!test_bit(mode, ah->ah_modes))
  814. return 0;
  815. switch (mode) {
  816. case AR5K_MODE_11A:
  817. case AR5K_MODE_11A_TURBO:
  818. /* 1..220, but 2GHz frequencies are filtered by check_channel */
  819. size = 220 ;
  820. chfreq = CHANNEL_5GHZ;
  821. break;
  822. case AR5K_MODE_11B:
  823. case AR5K_MODE_11G:
  824. case AR5K_MODE_11G_TURBO:
  825. size = 26;
  826. chfreq = CHANNEL_2GHZ;
  827. break;
  828. default:
  829. ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
  830. return 0;
  831. }
  832. for (i = 0, count = 0; i < size && max > 0; i++) {
  833. ch = i + 1 ;
  834. freq = ath5k_ieee2mhz(ch);
  835. /* Check if channel is supported by the chipset */
  836. if (!ath5k_channel_ok(ah, freq, chfreq))
  837. continue;
  838. if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
  839. continue;
  840. /* Write channel info and increment counter */
  841. channels[count].center_freq = freq;
  842. channels[count].band = (chfreq == CHANNEL_2GHZ) ?
  843. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  844. switch (mode) {
  845. case AR5K_MODE_11A:
  846. case AR5K_MODE_11G:
  847. channels[count].hw_value = chfreq | CHANNEL_OFDM;
  848. break;
  849. case AR5K_MODE_11A_TURBO:
  850. case AR5K_MODE_11G_TURBO:
  851. channels[count].hw_value = chfreq |
  852. CHANNEL_OFDM | CHANNEL_TURBO;
  853. break;
  854. case AR5K_MODE_11B:
  855. channels[count].hw_value = CHANNEL_B;
  856. }
  857. count++;
  858. max--;
  859. }
  860. return count;
  861. }
  862. static void
  863. ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
  864. {
  865. u8 i;
  866. for (i = 0; i < AR5K_MAX_RATES; i++)
  867. sc->rate_idx[b->band][i] = -1;
  868. for (i = 0; i < b->n_bitrates; i++) {
  869. sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
  870. if (b->bitrates[i].hw_value_short)
  871. sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
  872. }
  873. }
  874. static int
  875. ath5k_setup_bands(struct ieee80211_hw *hw)
  876. {
  877. struct ath5k_softc *sc = hw->priv;
  878. struct ath5k_hw *ah = sc->ah;
  879. struct ieee80211_supported_band *sband;
  880. int max_c, count_c = 0;
  881. int i;
  882. BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
  883. max_c = ARRAY_SIZE(sc->channels);
  884. /* 2GHz band */
  885. sband = &sc->sbands[IEEE80211_BAND_2GHZ];
  886. sband->band = IEEE80211_BAND_2GHZ;
  887. sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
  888. if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
  889. /* G mode */
  890. memcpy(sband->bitrates, &ath5k_rates[0],
  891. sizeof(struct ieee80211_rate) * 12);
  892. sband->n_bitrates = 12;
  893. sband->channels = sc->channels;
  894. sband->n_channels = ath5k_copy_channels(ah, sband->channels,
  895. AR5K_MODE_11G, max_c);
  896. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
  897. count_c = sband->n_channels;
  898. max_c -= count_c;
  899. } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
  900. /* B mode */
  901. memcpy(sband->bitrates, &ath5k_rates[0],
  902. sizeof(struct ieee80211_rate) * 4);
  903. sband->n_bitrates = 4;
  904. /* 5211 only supports B rates and uses 4bit rate codes
  905. * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
  906. * fix them up here:
  907. */
  908. if (ah->ah_version == AR5K_AR5211) {
  909. for (i = 0; i < 4; i++) {
  910. sband->bitrates[i].hw_value =
  911. sband->bitrates[i].hw_value & 0xF;
  912. sband->bitrates[i].hw_value_short =
  913. sband->bitrates[i].hw_value_short & 0xF;
  914. }
  915. }
  916. sband->channels = sc->channels;
  917. sband->n_channels = ath5k_copy_channels(ah, sband->channels,
  918. AR5K_MODE_11B, max_c);
  919. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
  920. count_c = sband->n_channels;
  921. max_c -= count_c;
  922. }
  923. ath5k_setup_rate_idx(sc, sband);
  924. /* 5GHz band, A mode */
  925. if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
  926. sband = &sc->sbands[IEEE80211_BAND_5GHZ];
  927. sband->band = IEEE80211_BAND_5GHZ;
  928. sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
  929. memcpy(sband->bitrates, &ath5k_rates[4],
  930. sizeof(struct ieee80211_rate) * 8);
  931. sband->n_bitrates = 8;
  932. sband->channels = &sc->channels[count_c];
  933. sband->n_channels = ath5k_copy_channels(ah, sband->channels,
  934. AR5K_MODE_11A, max_c);
  935. hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
  936. }
  937. ath5k_setup_rate_idx(sc, sband);
  938. ath5k_debug_dump_bands(sc);
  939. return 0;
  940. }
  941. /*
  942. * Set/change channels. We always reset the chip.
  943. * To accomplish this we must first cleanup any pending DMA,
  944. * then restart stuff after a la ath5k_init.
  945. *
  946. * Called with sc->lock.
  947. */
  948. static int
  949. ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
  950. {
  951. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
  952. sc->curchan->center_freq, chan->center_freq);
  953. /*
  954. * To switch channels clear any pending DMA operations;
  955. * wait long enough for the RX fifo to drain, reset the
  956. * hardware at the new frequency, and then re-enable
  957. * the relevant bits of the h/w.
  958. */
  959. return ath5k_reset(sc, chan);
  960. }
  961. static void
  962. ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
  963. {
  964. sc->curmode = mode;
  965. if (mode == AR5K_MODE_11A) {
  966. sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
  967. } else {
  968. sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
  969. }
  970. }
  971. static void
  972. ath5k_mode_setup(struct ath5k_softc *sc)
  973. {
  974. struct ath5k_hw *ah = sc->ah;
  975. u32 rfilt;
  976. ah->ah_op_mode = sc->opmode;
  977. /* configure rx filter */
  978. rfilt = sc->filter_flags;
  979. ath5k_hw_set_rx_filter(ah, rfilt);
  980. if (ath5k_hw_hasbssidmask(ah))
  981. ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
  982. /* configure operational mode */
  983. ath5k_hw_set_opmode(ah);
  984. ath5k_hw_set_mcast_filter(ah, 0, 0);
  985. ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
  986. }
  987. static inline int
  988. ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
  989. {
  990. int rix;
  991. /* return base rate on errors */
  992. if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
  993. "hw_rix out of bounds: %x\n", hw_rix))
  994. return 0;
  995. rix = sc->rate_idx[sc->curband->band][hw_rix];
  996. if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
  997. rix = 0;
  998. return rix;
  999. }
  1000. /***************\
  1001. * Buffers setup *
  1002. \***************/
  1003. static
  1004. struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
  1005. {
  1006. struct ath_common *common = ath5k_hw_common(sc->ah);
  1007. struct sk_buff *skb;
  1008. /*
  1009. * Allocate buffer with headroom_needed space for the
  1010. * fake physical layer header at the start.
  1011. */
  1012. skb = ath_rxbuf_alloc(common,
  1013. sc->rxbufsize + common->cachelsz - 1,
  1014. GFP_ATOMIC);
  1015. if (!skb) {
  1016. ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
  1017. sc->rxbufsize + common->cachelsz - 1);
  1018. return NULL;
  1019. }
  1020. *skb_addr = pci_map_single(sc->pdev,
  1021. skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
  1022. if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
  1023. ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
  1024. dev_kfree_skb(skb);
  1025. return NULL;
  1026. }
  1027. return skb;
  1028. }
  1029. static int
  1030. ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
  1031. {
  1032. struct ath5k_hw *ah = sc->ah;
  1033. struct sk_buff *skb = bf->skb;
  1034. struct ath5k_desc *ds;
  1035. if (!skb) {
  1036. skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
  1037. if (!skb)
  1038. return -ENOMEM;
  1039. bf->skb = skb;
  1040. }
  1041. /*
  1042. * Setup descriptors. For receive we always terminate
  1043. * the descriptor list with a self-linked entry so we'll
  1044. * not get overrun under high load (as can happen with a
  1045. * 5212 when ANI processing enables PHY error frames).
  1046. *
  1047. * To insure the last descriptor is self-linked we create
  1048. * each descriptor as self-linked and add it to the end. As
  1049. * each additional descriptor is added the previous self-linked
  1050. * entry is ``fixed'' naturally. This should be safe even
  1051. * if DMA is happening. When processing RX interrupts we
  1052. * never remove/process the last, self-linked, entry on the
  1053. * descriptor list. This insures the hardware always has
  1054. * someplace to write a new frame.
  1055. */
  1056. ds = bf->desc;
  1057. ds->ds_link = bf->daddr; /* link to self */
  1058. ds->ds_data = bf->skbaddr;
  1059. ah->ah_setup_rx_desc(ah, ds,
  1060. skb_tailroom(skb), /* buffer size */
  1061. 0);
  1062. if (sc->rxlink != NULL)
  1063. *sc->rxlink = bf->daddr;
  1064. sc->rxlink = &ds->ds_link;
  1065. return 0;
  1066. }
  1067. static int
  1068. ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
  1069. struct ath5k_txq *txq)
  1070. {
  1071. struct ath5k_hw *ah = sc->ah;
  1072. struct ath5k_desc *ds = bf->desc;
  1073. struct sk_buff *skb = bf->skb;
  1074. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1075. unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
  1076. struct ieee80211_rate *rate;
  1077. unsigned int mrr_rate[3], mrr_tries[3];
  1078. int i, ret;
  1079. u16 hw_rate;
  1080. u16 cts_rate = 0;
  1081. u16 duration = 0;
  1082. u8 rc_flags;
  1083. flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
  1084. /* XXX endianness */
  1085. bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
  1086. PCI_DMA_TODEVICE);
  1087. rate = ieee80211_get_tx_rate(sc->hw, info);
  1088. if (info->flags & IEEE80211_TX_CTL_NO_ACK)
  1089. flags |= AR5K_TXDESC_NOACK;
  1090. rc_flags = info->control.rates[0].flags;
  1091. hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
  1092. rate->hw_value_short : rate->hw_value;
  1093. pktlen = skb->len;
  1094. /* FIXME: If we are in g mode and rate is a CCK rate
  1095. * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
  1096. * from tx power (value is in dB units already) */
  1097. if (info->control.hw_key) {
  1098. keyidx = info->control.hw_key->hw_key_idx;
  1099. pktlen += info->control.hw_key->icv_len;
  1100. }
  1101. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  1102. flags |= AR5K_TXDESC_RTSENA;
  1103. cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
  1104. duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
  1105. sc->vif, pktlen, info));
  1106. }
  1107. if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  1108. flags |= AR5K_TXDESC_CTSENA;
  1109. cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
  1110. duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
  1111. sc->vif, pktlen, info));
  1112. }
  1113. ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
  1114. ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
  1115. (sc->power_level * 2),
  1116. hw_rate,
  1117. info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
  1118. cts_rate, duration);
  1119. if (ret)
  1120. goto err_unmap;
  1121. memset(mrr_rate, 0, sizeof(mrr_rate));
  1122. memset(mrr_tries, 0, sizeof(mrr_tries));
  1123. for (i = 0; i < 3; i++) {
  1124. rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
  1125. if (!rate)
  1126. break;
  1127. mrr_rate[i] = rate->hw_value;
  1128. mrr_tries[i] = info->control.rates[i + 1].count;
  1129. }
  1130. ah->ah_setup_mrr_tx_desc(ah, ds,
  1131. mrr_rate[0], mrr_tries[0],
  1132. mrr_rate[1], mrr_tries[1],
  1133. mrr_rate[2], mrr_tries[2]);
  1134. ds->ds_link = 0;
  1135. ds->ds_data = bf->skbaddr;
  1136. spin_lock_bh(&txq->lock);
  1137. list_add_tail(&bf->list, &txq->q);
  1138. sc->tx_stats[txq->qnum].len++;
  1139. if (txq->link == NULL) /* is this first packet? */
  1140. ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
  1141. else /* no, so only link it */
  1142. *txq->link = bf->daddr;
  1143. txq->link = &ds->ds_link;
  1144. ath5k_hw_start_tx_dma(ah, txq->qnum);
  1145. mmiowb();
  1146. spin_unlock_bh(&txq->lock);
  1147. return 0;
  1148. err_unmap:
  1149. pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
  1150. return ret;
  1151. }
  1152. /*******************\
  1153. * Descriptors setup *
  1154. \*******************/
  1155. static int
  1156. ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
  1157. {
  1158. struct ath5k_desc *ds;
  1159. struct ath5k_buf *bf;
  1160. dma_addr_t da;
  1161. unsigned int i;
  1162. int ret;
  1163. /* allocate descriptors */
  1164. sc->desc_len = sizeof(struct ath5k_desc) *
  1165. (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
  1166. sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
  1167. if (sc->desc == NULL) {
  1168. ATH5K_ERR(sc, "can't allocate descriptors\n");
  1169. ret = -ENOMEM;
  1170. goto err;
  1171. }
  1172. ds = sc->desc;
  1173. da = sc->desc_daddr;
  1174. ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
  1175. ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
  1176. bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
  1177. sizeof(struct ath5k_buf), GFP_KERNEL);
  1178. if (bf == NULL) {
  1179. ATH5K_ERR(sc, "can't allocate bufptr\n");
  1180. ret = -ENOMEM;
  1181. goto err_free;
  1182. }
  1183. sc->bufptr = bf;
  1184. INIT_LIST_HEAD(&sc->rxbuf);
  1185. for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
  1186. bf->desc = ds;
  1187. bf->daddr = da;
  1188. list_add_tail(&bf->list, &sc->rxbuf);
  1189. }
  1190. INIT_LIST_HEAD(&sc->txbuf);
  1191. sc->txbuf_len = ATH_TXBUF;
  1192. for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
  1193. da += sizeof(*ds)) {
  1194. bf->desc = ds;
  1195. bf->daddr = da;
  1196. list_add_tail(&bf->list, &sc->txbuf);
  1197. }
  1198. /* beacon buffer */
  1199. bf->desc = ds;
  1200. bf->daddr = da;
  1201. sc->bbuf = bf;
  1202. return 0;
  1203. err_free:
  1204. pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
  1205. err:
  1206. sc->desc = NULL;
  1207. return ret;
  1208. }
  1209. static void
  1210. ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
  1211. {
  1212. struct ath5k_buf *bf;
  1213. ath5k_txbuf_free(sc, sc->bbuf);
  1214. list_for_each_entry(bf, &sc->txbuf, list)
  1215. ath5k_txbuf_free(sc, bf);
  1216. list_for_each_entry(bf, &sc->rxbuf, list)
  1217. ath5k_rxbuf_free(sc, bf);
  1218. /* Free memory associated with all descriptors */
  1219. pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
  1220. kfree(sc->bufptr);
  1221. sc->bufptr = NULL;
  1222. }
  1223. /**************\
  1224. * Queues setup *
  1225. \**************/
  1226. static struct ath5k_txq *
  1227. ath5k_txq_setup(struct ath5k_softc *sc,
  1228. int qtype, int subtype)
  1229. {
  1230. struct ath5k_hw *ah = sc->ah;
  1231. struct ath5k_txq *txq;
  1232. struct ath5k_txq_info qi = {
  1233. .tqi_subtype = subtype,
  1234. .tqi_aifs = AR5K_TXQ_USEDEFAULT,
  1235. .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
  1236. .tqi_cw_max = AR5K_TXQ_USEDEFAULT
  1237. };
  1238. int qnum;
  1239. /*
  1240. * Enable interrupts only for EOL and DESC conditions.
  1241. * We mark tx descriptors to receive a DESC interrupt
  1242. * when a tx queue gets deep; otherwise waiting for the
  1243. * EOL to reap descriptors. Note that this is done to
  1244. * reduce interrupt load and this only defers reaping
  1245. * descriptors, never transmitting frames. Aside from
  1246. * reducing interrupts this also permits more concurrency.
  1247. * The only potential downside is if the tx queue backs
  1248. * up in which case the top half of the kernel may backup
  1249. * due to a lack of tx descriptors.
  1250. */
  1251. qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
  1252. AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
  1253. qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
  1254. if (qnum < 0) {
  1255. /*
  1256. * NB: don't print a message, this happens
  1257. * normally on parts with too few tx queues
  1258. */
  1259. return ERR_PTR(qnum);
  1260. }
  1261. if (qnum >= ARRAY_SIZE(sc->txqs)) {
  1262. ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
  1263. qnum, ARRAY_SIZE(sc->txqs));
  1264. ath5k_hw_release_tx_queue(ah, qnum);
  1265. return ERR_PTR(-EINVAL);
  1266. }
  1267. txq = &sc->txqs[qnum];
  1268. if (!txq->setup) {
  1269. txq->qnum = qnum;
  1270. txq->link = NULL;
  1271. INIT_LIST_HEAD(&txq->q);
  1272. spin_lock_init(&txq->lock);
  1273. txq->setup = true;
  1274. }
  1275. return &sc->txqs[qnum];
  1276. }
  1277. static int
  1278. ath5k_beaconq_setup(struct ath5k_hw *ah)
  1279. {
  1280. struct ath5k_txq_info qi = {
  1281. .tqi_aifs = AR5K_TXQ_USEDEFAULT,
  1282. .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
  1283. .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
  1284. /* NB: for dynamic turbo, don't enable any other interrupts */
  1285. .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
  1286. };
  1287. return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
  1288. }
  1289. static int
  1290. ath5k_beaconq_config(struct ath5k_softc *sc)
  1291. {
  1292. struct ath5k_hw *ah = sc->ah;
  1293. struct ath5k_txq_info qi;
  1294. int ret;
  1295. ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
  1296. if (ret)
  1297. return ret;
  1298. if (sc->opmode == NL80211_IFTYPE_AP ||
  1299. sc->opmode == NL80211_IFTYPE_MESH_POINT) {
  1300. /*
  1301. * Always burst out beacon and CAB traffic
  1302. * (aifs = cwmin = cwmax = 0)
  1303. */
  1304. qi.tqi_aifs = 0;
  1305. qi.tqi_cw_min = 0;
  1306. qi.tqi_cw_max = 0;
  1307. } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
  1308. /*
  1309. * Adhoc mode; backoff between 0 and (2 * cw_min).
  1310. */
  1311. qi.tqi_aifs = 0;
  1312. qi.tqi_cw_min = 0;
  1313. qi.tqi_cw_max = 2 * ah->ah_cw_min;
  1314. }
  1315. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  1316. "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
  1317. qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
  1318. ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
  1319. if (ret) {
  1320. ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
  1321. "hardware queue!\n", __func__);
  1322. return ret;
  1323. }
  1324. return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
  1325. }
  1326. static void
  1327. ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
  1328. {
  1329. struct ath5k_buf *bf, *bf0;
  1330. /*
  1331. * NB: this assumes output has been stopped and
  1332. * we do not need to block ath5k_tx_tasklet
  1333. */
  1334. spin_lock_bh(&txq->lock);
  1335. list_for_each_entry_safe(bf, bf0, &txq->q, list) {
  1336. ath5k_debug_printtxbuf(sc, bf);
  1337. ath5k_txbuf_free(sc, bf);
  1338. spin_lock_bh(&sc->txbuflock);
  1339. sc->tx_stats[txq->qnum].len--;
  1340. list_move_tail(&bf->list, &sc->txbuf);
  1341. sc->txbuf_len++;
  1342. spin_unlock_bh(&sc->txbuflock);
  1343. }
  1344. txq->link = NULL;
  1345. spin_unlock_bh(&txq->lock);
  1346. }
  1347. /*
  1348. * Drain the transmit queues and reclaim resources.
  1349. */
  1350. static void
  1351. ath5k_txq_cleanup(struct ath5k_softc *sc)
  1352. {
  1353. struct ath5k_hw *ah = sc->ah;
  1354. unsigned int i;
  1355. /* XXX return value */
  1356. if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
  1357. /* don't touch the hardware if marked invalid */
  1358. ath5k_hw_stop_tx_dma(ah, sc->bhalq);
  1359. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
  1360. ath5k_hw_get_txdp(ah, sc->bhalq));
  1361. for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
  1362. if (sc->txqs[i].setup) {
  1363. ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
  1364. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
  1365. "link %p\n",
  1366. sc->txqs[i].qnum,
  1367. ath5k_hw_get_txdp(ah,
  1368. sc->txqs[i].qnum),
  1369. sc->txqs[i].link);
  1370. }
  1371. }
  1372. ieee80211_wake_queues(sc->hw); /* XXX move to callers */
  1373. for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
  1374. if (sc->txqs[i].setup)
  1375. ath5k_txq_drainq(sc, &sc->txqs[i]);
  1376. }
  1377. static void
  1378. ath5k_txq_release(struct ath5k_softc *sc)
  1379. {
  1380. struct ath5k_txq *txq = sc->txqs;
  1381. unsigned int i;
  1382. for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
  1383. if (txq->setup) {
  1384. ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
  1385. txq->setup = false;
  1386. }
  1387. }
  1388. /*************\
  1389. * RX Handling *
  1390. \*************/
  1391. /*
  1392. * Enable the receive h/w following a reset.
  1393. */
  1394. static int
  1395. ath5k_rx_start(struct ath5k_softc *sc)
  1396. {
  1397. struct ath5k_hw *ah = sc->ah;
  1398. struct ath_common *common = ath5k_hw_common(ah);
  1399. struct ath5k_buf *bf;
  1400. int ret;
  1401. sc->rxbufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
  1402. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
  1403. common->cachelsz, sc->rxbufsize);
  1404. spin_lock_bh(&sc->rxbuflock);
  1405. sc->rxlink = NULL;
  1406. list_for_each_entry(bf, &sc->rxbuf, list) {
  1407. ret = ath5k_rxbuf_setup(sc, bf);
  1408. if (ret != 0) {
  1409. spin_unlock_bh(&sc->rxbuflock);
  1410. goto err;
  1411. }
  1412. }
  1413. bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
  1414. ath5k_hw_set_rxdp(ah, bf->daddr);
  1415. spin_unlock_bh(&sc->rxbuflock);
  1416. ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
  1417. ath5k_mode_setup(sc); /* set filters, etc. */
  1418. ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
  1419. return 0;
  1420. err:
  1421. return ret;
  1422. }
  1423. /*
  1424. * Disable the receive h/w in preparation for a reset.
  1425. */
  1426. static void
  1427. ath5k_rx_stop(struct ath5k_softc *sc)
  1428. {
  1429. struct ath5k_hw *ah = sc->ah;
  1430. ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
  1431. ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
  1432. ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
  1433. ath5k_debug_printrxbuffs(sc, ah);
  1434. sc->rxlink = NULL; /* just in case */
  1435. }
  1436. static unsigned int
  1437. ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
  1438. struct sk_buff *skb, struct ath5k_rx_status *rs)
  1439. {
  1440. struct ieee80211_hdr *hdr = (void *)skb->data;
  1441. unsigned int keyix, hlen;
  1442. if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
  1443. rs->rs_keyix != AR5K_RXKEYIX_INVALID)
  1444. return RX_FLAG_DECRYPTED;
  1445. /* Apparently when a default key is used to decrypt the packet
  1446. the hw does not set the index used to decrypt. In such cases
  1447. get the index from the packet. */
  1448. hlen = ieee80211_hdrlen(hdr->frame_control);
  1449. if (ieee80211_has_protected(hdr->frame_control) &&
  1450. !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
  1451. skb->len >= hlen + 4) {
  1452. keyix = skb->data[hlen + 3] >> 6;
  1453. if (test_bit(keyix, sc->keymap))
  1454. return RX_FLAG_DECRYPTED;
  1455. }
  1456. return 0;
  1457. }
  1458. static void
  1459. ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
  1460. struct ieee80211_rx_status *rxs)
  1461. {
  1462. struct ath_common *common = ath5k_hw_common(sc->ah);
  1463. u64 tsf, bc_tstamp;
  1464. u32 hw_tu;
  1465. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
  1466. if (ieee80211_is_beacon(mgmt->frame_control) &&
  1467. le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
  1468. memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
  1469. /*
  1470. * Received an IBSS beacon with the same BSSID. Hardware *must*
  1471. * have updated the local TSF. We have to work around various
  1472. * hardware bugs, though...
  1473. */
  1474. tsf = ath5k_hw_get_tsf64(sc->ah);
  1475. bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
  1476. hw_tu = TSF_TO_TU(tsf);
  1477. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  1478. "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
  1479. (unsigned long long)bc_tstamp,
  1480. (unsigned long long)rxs->mactime,
  1481. (unsigned long long)(rxs->mactime - bc_tstamp),
  1482. (unsigned long long)tsf);
  1483. /*
  1484. * Sometimes the HW will give us a wrong tstamp in the rx
  1485. * status, causing the timestamp extension to go wrong.
  1486. * (This seems to happen especially with beacon frames bigger
  1487. * than 78 byte (incl. FCS))
  1488. * But we know that the receive timestamp must be later than the
  1489. * timestamp of the beacon since HW must have synced to that.
  1490. *
  1491. * NOTE: here we assume mactime to be after the frame was
  1492. * received, not like mac80211 which defines it at the start.
  1493. */
  1494. if (bc_tstamp > rxs->mactime) {
  1495. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  1496. "fixing mactime from %llx to %llx\n",
  1497. (unsigned long long)rxs->mactime,
  1498. (unsigned long long)tsf);
  1499. rxs->mactime = tsf;
  1500. }
  1501. /*
  1502. * Local TSF might have moved higher than our beacon timers,
  1503. * in that case we have to update them to continue sending
  1504. * beacons. This also takes care of synchronizing beacon sending
  1505. * times with other stations.
  1506. */
  1507. if (hw_tu >= sc->nexttbtt)
  1508. ath5k_beacon_update_timers(sc, bc_tstamp);
  1509. }
  1510. }
  1511. static void
  1512. ath5k_tasklet_rx(unsigned long data)
  1513. {
  1514. struct ieee80211_rx_status *rxs;
  1515. struct ath5k_rx_status rs = {};
  1516. struct sk_buff *skb, *next_skb;
  1517. dma_addr_t next_skb_addr;
  1518. struct ath5k_softc *sc = (void *)data;
  1519. struct ath5k_buf *bf;
  1520. struct ath5k_desc *ds;
  1521. int ret;
  1522. int hdrlen;
  1523. int padsize;
  1524. int rx_flag;
  1525. spin_lock(&sc->rxbuflock);
  1526. if (list_empty(&sc->rxbuf)) {
  1527. ATH5K_WARN(sc, "empty rx buf pool\n");
  1528. goto unlock;
  1529. }
  1530. do {
  1531. rx_flag = 0;
  1532. bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
  1533. BUG_ON(bf->skb == NULL);
  1534. skb = bf->skb;
  1535. ds = bf->desc;
  1536. /* bail if HW is still using self-linked descriptor */
  1537. if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
  1538. break;
  1539. ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
  1540. if (unlikely(ret == -EINPROGRESS))
  1541. break;
  1542. else if (unlikely(ret)) {
  1543. ATH5K_ERR(sc, "error in processing rx descriptor\n");
  1544. spin_unlock(&sc->rxbuflock);
  1545. return;
  1546. }
  1547. if (unlikely(rs.rs_more)) {
  1548. ATH5K_WARN(sc, "unsupported jumbo\n");
  1549. goto next;
  1550. }
  1551. if (unlikely(rs.rs_status)) {
  1552. if (rs.rs_status & AR5K_RXERR_PHY)
  1553. goto next;
  1554. if (rs.rs_status & AR5K_RXERR_DECRYPT) {
  1555. /*
  1556. * Decrypt error. If the error occurred
  1557. * because there was no hardware key, then
  1558. * let the frame through so the upper layers
  1559. * can process it. This is necessary for 5210
  1560. * parts which have no way to setup a ``clear''
  1561. * key cache entry.
  1562. *
  1563. * XXX do key cache faulting
  1564. */
  1565. if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
  1566. !(rs.rs_status & AR5K_RXERR_CRC))
  1567. goto accept;
  1568. }
  1569. if (rs.rs_status & AR5K_RXERR_MIC) {
  1570. rx_flag |= RX_FLAG_MMIC_ERROR;
  1571. goto accept;
  1572. }
  1573. /* let crypto-error packets fall through in MNTR */
  1574. if ((rs.rs_status &
  1575. ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
  1576. sc->opmode != NL80211_IFTYPE_MONITOR)
  1577. goto next;
  1578. }
  1579. accept:
  1580. next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
  1581. /*
  1582. * If we can't replace bf->skb with a new skb under memory
  1583. * pressure, just skip this packet
  1584. */
  1585. if (!next_skb)
  1586. goto next;
  1587. pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
  1588. PCI_DMA_FROMDEVICE);
  1589. skb_put(skb, rs.rs_datalen);
  1590. /* The MAC header is padded to have 32-bit boundary if the
  1591. * packet payload is non-zero. The general calculation for
  1592. * padsize would take into account odd header lengths:
  1593. * padsize = (4 - hdrlen % 4) % 4; However, since only
  1594. * even-length headers are used, padding can only be 0 or 2
  1595. * bytes and we can optimize this a bit. In addition, we must
  1596. * not try to remove padding from short control frames that do
  1597. * not have payload. */
  1598. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  1599. padsize = ath5k_pad_size(hdrlen);
  1600. if (padsize) {
  1601. memmove(skb->data + padsize, skb->data, hdrlen);
  1602. skb_pull(skb, padsize);
  1603. }
  1604. rxs = IEEE80211_SKB_RXCB(skb);
  1605. /*
  1606. * always extend the mac timestamp, since this information is
  1607. * also needed for proper IBSS merging.
  1608. *
  1609. * XXX: it might be too late to do it here, since rs_tstamp is
  1610. * 15bit only. that means TSF extension has to be done within
  1611. * 32768usec (about 32ms). it might be necessary to move this to
  1612. * the interrupt handler, like it is done in madwifi.
  1613. *
  1614. * Unfortunately we don't know when the hardware takes the rx
  1615. * timestamp (beginning of phy frame, data frame, end of rx?).
  1616. * The only thing we know is that it is hardware specific...
  1617. * On AR5213 it seems the rx timestamp is at the end of the
  1618. * frame, but i'm not sure.
  1619. *
  1620. * NOTE: mac80211 defines mactime at the beginning of the first
  1621. * data symbol. Since we don't have any time references it's
  1622. * impossible to comply to that. This affects IBSS merge only
  1623. * right now, so it's not too bad...
  1624. */
  1625. rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
  1626. rxs->flag = rx_flag | RX_FLAG_TSFT;
  1627. rxs->freq = sc->curchan->center_freq;
  1628. rxs->band = sc->curband->band;
  1629. rxs->noise = sc->ah->ah_noise_floor;
  1630. rxs->signal = rxs->noise + rs.rs_rssi;
  1631. /* An rssi of 35 indicates you should be able use
  1632. * 54 Mbps reliably. A more elaborate scheme can be used
  1633. * here but it requires a map of SNR/throughput for each
  1634. * possible mode used */
  1635. rxs->qual = rs.rs_rssi * 100 / 35;
  1636. /* rssi can be more than 35 though, anything above that
  1637. * should be considered at 100% */
  1638. if (rxs->qual > 100)
  1639. rxs->qual = 100;
  1640. rxs->antenna = rs.rs_antenna;
  1641. rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
  1642. rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
  1643. if (rxs->rate_idx >= 0 && rs.rs_rate ==
  1644. sc->curband->bitrates[rxs->rate_idx].hw_value_short)
  1645. rxs->flag |= RX_FLAG_SHORTPRE;
  1646. ath5k_debug_dump_skb(sc, skb, "RX ", 0);
  1647. /* check beacons in IBSS mode */
  1648. if (sc->opmode == NL80211_IFTYPE_ADHOC)
  1649. ath5k_check_ibss_tsf(sc, skb, rxs);
  1650. ieee80211_rx(sc->hw, skb);
  1651. bf->skb = next_skb;
  1652. bf->skbaddr = next_skb_addr;
  1653. next:
  1654. list_move_tail(&bf->list, &sc->rxbuf);
  1655. } while (ath5k_rxbuf_setup(sc, bf) == 0);
  1656. unlock:
  1657. spin_unlock(&sc->rxbuflock);
  1658. }
  1659. /*************\
  1660. * TX Handling *
  1661. \*************/
  1662. static void
  1663. ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
  1664. {
  1665. struct ath5k_tx_status ts = {};
  1666. struct ath5k_buf *bf, *bf0;
  1667. struct ath5k_desc *ds;
  1668. struct sk_buff *skb;
  1669. struct ieee80211_tx_info *info;
  1670. int i, ret;
  1671. spin_lock(&txq->lock);
  1672. list_for_each_entry_safe(bf, bf0, &txq->q, list) {
  1673. ds = bf->desc;
  1674. ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
  1675. if (unlikely(ret == -EINPROGRESS))
  1676. break;
  1677. else if (unlikely(ret)) {
  1678. ATH5K_ERR(sc, "error %d while processing queue %u\n",
  1679. ret, txq->qnum);
  1680. break;
  1681. }
  1682. skb = bf->skb;
  1683. info = IEEE80211_SKB_CB(skb);
  1684. bf->skb = NULL;
  1685. pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
  1686. PCI_DMA_TODEVICE);
  1687. ieee80211_tx_info_clear_status(info);
  1688. for (i = 0; i < 4; i++) {
  1689. struct ieee80211_tx_rate *r =
  1690. &info->status.rates[i];
  1691. if (ts.ts_rate[i]) {
  1692. r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
  1693. r->count = ts.ts_retry[i];
  1694. } else {
  1695. r->idx = -1;
  1696. r->count = 0;
  1697. }
  1698. }
  1699. /* count the successful attempt as well */
  1700. info->status.rates[ts.ts_final_idx].count++;
  1701. if (unlikely(ts.ts_status)) {
  1702. sc->ll_stats.dot11ACKFailureCount++;
  1703. if (ts.ts_status & AR5K_TXERR_FILT)
  1704. info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
  1705. } else {
  1706. info->flags |= IEEE80211_TX_STAT_ACK;
  1707. info->status.ack_signal = ts.ts_rssi;
  1708. }
  1709. ieee80211_tx_status(sc->hw, skb);
  1710. sc->tx_stats[txq->qnum].count++;
  1711. spin_lock(&sc->txbuflock);
  1712. sc->tx_stats[txq->qnum].len--;
  1713. list_move_tail(&bf->list, &sc->txbuf);
  1714. sc->txbuf_len++;
  1715. spin_unlock(&sc->txbuflock);
  1716. }
  1717. if (likely(list_empty(&txq->q)))
  1718. txq->link = NULL;
  1719. spin_unlock(&txq->lock);
  1720. if (sc->txbuf_len > ATH_TXBUF / 5)
  1721. ieee80211_wake_queues(sc->hw);
  1722. }
  1723. static void
  1724. ath5k_tasklet_tx(unsigned long data)
  1725. {
  1726. int i;
  1727. struct ath5k_softc *sc = (void *)data;
  1728. for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
  1729. if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
  1730. ath5k_tx_processq(sc, &sc->txqs[i]);
  1731. }
  1732. /*****************\
  1733. * Beacon handling *
  1734. \*****************/
  1735. /*
  1736. * Setup the beacon frame for transmit.
  1737. */
  1738. static int
  1739. ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
  1740. {
  1741. struct sk_buff *skb = bf->skb;
  1742. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1743. struct ath5k_hw *ah = sc->ah;
  1744. struct ath5k_desc *ds;
  1745. int ret = 0;
  1746. u8 antenna;
  1747. u32 flags;
  1748. bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
  1749. PCI_DMA_TODEVICE);
  1750. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
  1751. "skbaddr %llx\n", skb, skb->data, skb->len,
  1752. (unsigned long long)bf->skbaddr);
  1753. if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
  1754. ATH5K_ERR(sc, "beacon DMA mapping failed\n");
  1755. return -EIO;
  1756. }
  1757. ds = bf->desc;
  1758. antenna = ah->ah_tx_ant;
  1759. flags = AR5K_TXDESC_NOACK;
  1760. if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
  1761. ds->ds_link = bf->daddr; /* self-linked */
  1762. flags |= AR5K_TXDESC_VEOL;
  1763. } else
  1764. ds->ds_link = 0;
  1765. /*
  1766. * If we use multiple antennas on AP and use
  1767. * the Sectored AP scenario, switch antenna every
  1768. * 4 beacons to make sure everybody hears our AP.
  1769. * When a client tries to associate, hw will keep
  1770. * track of the tx antenna to be used for this client
  1771. * automaticaly, based on ACKed packets.
  1772. *
  1773. * Note: AP still listens and transmits RTS on the
  1774. * default antenna which is supposed to be an omni.
  1775. *
  1776. * Note2: On sectored scenarios it's possible to have
  1777. * multiple antennas (1omni -the default- and 14 sectors)
  1778. * so if we choose to actually support this mode we need
  1779. * to allow user to set how many antennas we have and tweak
  1780. * the code below to send beacons on all of them.
  1781. */
  1782. if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
  1783. antenna = sc->bsent & 4 ? 2 : 1;
  1784. /* FIXME: If we are in g mode and rate is a CCK rate
  1785. * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
  1786. * from tx power (value is in dB units already) */
  1787. ds->ds_data = bf->skbaddr;
  1788. ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
  1789. ieee80211_get_hdrlen_from_skb(skb),
  1790. AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
  1791. ieee80211_get_tx_rate(sc->hw, info)->hw_value,
  1792. 1, AR5K_TXKEYIX_INVALID,
  1793. antenna, flags, 0, 0);
  1794. if (ret)
  1795. goto err_unmap;
  1796. return 0;
  1797. err_unmap:
  1798. pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
  1799. return ret;
  1800. }
  1801. /*
  1802. * Transmit a beacon frame at SWBA. Dynamic updates to the
  1803. * frame contents are done as needed and the slot time is
  1804. * also adjusted based on current state.
  1805. *
  1806. * This is called from software irq context (beacontq or restq
  1807. * tasklets) or user context from ath5k_beacon_config.
  1808. */
  1809. static void
  1810. ath5k_beacon_send(struct ath5k_softc *sc)
  1811. {
  1812. struct ath5k_buf *bf = sc->bbuf;
  1813. struct ath5k_hw *ah = sc->ah;
  1814. struct sk_buff *skb;
  1815. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
  1816. if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
  1817. sc->opmode == NL80211_IFTYPE_MONITOR)) {
  1818. ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
  1819. return;
  1820. }
  1821. /*
  1822. * Check if the previous beacon has gone out. If
  1823. * not don't don't try to post another, skip this
  1824. * period and wait for the next. Missed beacons
  1825. * indicate a problem and should not occur. If we
  1826. * miss too many consecutive beacons reset the device.
  1827. */
  1828. if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
  1829. sc->bmisscount++;
  1830. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  1831. "missed %u consecutive beacons\n", sc->bmisscount);
  1832. if (sc->bmisscount > 10) { /* NB: 10 is a guess */
  1833. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  1834. "stuck beacon time (%u missed)\n",
  1835. sc->bmisscount);
  1836. tasklet_schedule(&sc->restq);
  1837. }
  1838. return;
  1839. }
  1840. if (unlikely(sc->bmisscount != 0)) {
  1841. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  1842. "resume beacon xmit after %u misses\n",
  1843. sc->bmisscount);
  1844. sc->bmisscount = 0;
  1845. }
  1846. /*
  1847. * Stop any current dma and put the new frame on the queue.
  1848. * This should never fail since we check above that no frames
  1849. * are still pending on the queue.
  1850. */
  1851. if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
  1852. ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
  1853. /* NB: hw still stops DMA, so proceed */
  1854. }
  1855. /* refresh the beacon for AP mode */
  1856. if (sc->opmode == NL80211_IFTYPE_AP)
  1857. ath5k_beacon_update(sc->hw, sc->vif);
  1858. ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
  1859. ath5k_hw_start_tx_dma(ah, sc->bhalq);
  1860. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
  1861. sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
  1862. skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
  1863. while (skb) {
  1864. ath5k_tx_queue(sc->hw, skb, sc->cabq);
  1865. skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
  1866. }
  1867. sc->bsent++;
  1868. }
  1869. /**
  1870. * ath5k_beacon_update_timers - update beacon timers
  1871. *
  1872. * @sc: struct ath5k_softc pointer we are operating on
  1873. * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
  1874. * beacon timer update based on the current HW TSF.
  1875. *
  1876. * Calculate the next target beacon transmit time (TBTT) based on the timestamp
  1877. * of a received beacon or the current local hardware TSF and write it to the
  1878. * beacon timer registers.
  1879. *
  1880. * This is called in a variety of situations, e.g. when a beacon is received,
  1881. * when a TSF update has been detected, but also when an new IBSS is created or
  1882. * when we otherwise know we have to update the timers, but we keep it in this
  1883. * function to have it all together in one place.
  1884. */
  1885. static void
  1886. ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
  1887. {
  1888. struct ath5k_hw *ah = sc->ah;
  1889. u32 nexttbtt, intval, hw_tu, bc_tu;
  1890. u64 hw_tsf;
  1891. intval = sc->bintval & AR5K_BEACON_PERIOD;
  1892. if (WARN_ON(!intval))
  1893. return;
  1894. /* beacon TSF converted to TU */
  1895. bc_tu = TSF_TO_TU(bc_tsf);
  1896. /* current TSF converted to TU */
  1897. hw_tsf = ath5k_hw_get_tsf64(ah);
  1898. hw_tu = TSF_TO_TU(hw_tsf);
  1899. #define FUDGE 3
  1900. /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
  1901. if (bc_tsf == -1) {
  1902. /*
  1903. * no beacons received, called internally.
  1904. * just need to refresh timers based on HW TSF.
  1905. */
  1906. nexttbtt = roundup(hw_tu + FUDGE, intval);
  1907. } else if (bc_tsf == 0) {
  1908. /*
  1909. * no beacon received, probably called by ath5k_reset_tsf().
  1910. * reset TSF to start with 0.
  1911. */
  1912. nexttbtt = intval;
  1913. intval |= AR5K_BEACON_RESET_TSF;
  1914. } else if (bc_tsf > hw_tsf) {
  1915. /*
  1916. * beacon received, SW merge happend but HW TSF not yet updated.
  1917. * not possible to reconfigure timers yet, but next time we
  1918. * receive a beacon with the same BSSID, the hardware will
  1919. * automatically update the TSF and then we need to reconfigure
  1920. * the timers.
  1921. */
  1922. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  1923. "need to wait for HW TSF sync\n");
  1924. return;
  1925. } else {
  1926. /*
  1927. * most important case for beacon synchronization between STA.
  1928. *
  1929. * beacon received and HW TSF has been already updated by HW.
  1930. * update next TBTT based on the TSF of the beacon, but make
  1931. * sure it is ahead of our local TSF timer.
  1932. */
  1933. nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
  1934. }
  1935. #undef FUDGE
  1936. sc->nexttbtt = nexttbtt;
  1937. intval |= AR5K_BEACON_ENA;
  1938. ath5k_hw_init_beacon(ah, nexttbtt, intval);
  1939. /*
  1940. * debugging output last in order to preserve the time critical aspect
  1941. * of this function
  1942. */
  1943. if (bc_tsf == -1)
  1944. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  1945. "reconfigured timers based on HW TSF\n");
  1946. else if (bc_tsf == 0)
  1947. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  1948. "reset HW TSF and timers\n");
  1949. else
  1950. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  1951. "updated timers based on beacon TSF\n");
  1952. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
  1953. "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
  1954. (unsigned long long) bc_tsf,
  1955. (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
  1956. ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
  1957. intval & AR5K_BEACON_PERIOD,
  1958. intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
  1959. intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
  1960. }
  1961. /**
  1962. * ath5k_beacon_config - Configure the beacon queues and interrupts
  1963. *
  1964. * @sc: struct ath5k_softc pointer we are operating on
  1965. *
  1966. * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
  1967. * interrupts to detect TSF updates only.
  1968. */
  1969. static void
  1970. ath5k_beacon_config(struct ath5k_softc *sc)
  1971. {
  1972. struct ath5k_hw *ah = sc->ah;
  1973. unsigned long flags;
  1974. spin_lock_irqsave(&sc->block, flags);
  1975. sc->bmisscount = 0;
  1976. sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
  1977. if (sc->enable_beacon) {
  1978. /*
  1979. * In IBSS mode we use a self-linked tx descriptor and let the
  1980. * hardware send the beacons automatically. We have to load it
  1981. * only once here.
  1982. * We use the SWBA interrupt only to keep track of the beacon
  1983. * timers in order to detect automatic TSF updates.
  1984. */
  1985. ath5k_beaconq_config(sc);
  1986. sc->imask |= AR5K_INT_SWBA;
  1987. if (sc->opmode == NL80211_IFTYPE_ADHOC) {
  1988. if (ath5k_hw_hasveol(ah))
  1989. ath5k_beacon_send(sc);
  1990. } else
  1991. ath5k_beacon_update_timers(sc, -1);
  1992. } else {
  1993. ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
  1994. }
  1995. ath5k_hw_set_imr(ah, sc->imask);
  1996. mmiowb();
  1997. spin_unlock_irqrestore(&sc->block, flags);
  1998. }
  1999. static void ath5k_tasklet_beacon(unsigned long data)
  2000. {
  2001. struct ath5k_softc *sc = (struct ath5k_softc *) data;
  2002. /*
  2003. * Software beacon alert--time to send a beacon.
  2004. *
  2005. * In IBSS mode we use this interrupt just to
  2006. * keep track of the next TBTT (target beacon
  2007. * transmission time) in order to detect wether
  2008. * automatic TSF updates happened.
  2009. */
  2010. if (sc->opmode == NL80211_IFTYPE_ADHOC) {
  2011. /* XXX: only if VEOL suppported */
  2012. u64 tsf = ath5k_hw_get_tsf64(sc->ah);
  2013. sc->nexttbtt += sc->bintval;
  2014. ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
  2015. "SWBA nexttbtt: %x hw_tu: %x "
  2016. "TSF: %llx\n",
  2017. sc->nexttbtt,
  2018. TSF_TO_TU(tsf),
  2019. (unsigned long long) tsf);
  2020. } else {
  2021. spin_lock(&sc->block);
  2022. ath5k_beacon_send(sc);
  2023. spin_unlock(&sc->block);
  2024. }
  2025. }
  2026. /********************\
  2027. * Interrupt handling *
  2028. \********************/
  2029. static int
  2030. ath5k_init(struct ath5k_softc *sc)
  2031. {
  2032. struct ath5k_hw *ah = sc->ah;
  2033. int ret, i;
  2034. mutex_lock(&sc->lock);
  2035. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
  2036. /*
  2037. * Stop anything previously setup. This is safe
  2038. * no matter this is the first time through or not.
  2039. */
  2040. ath5k_stop_locked(sc);
  2041. /*
  2042. * The basic interface to setting the hardware in a good
  2043. * state is ``reset''. On return the hardware is known to
  2044. * be powered up and with interrupts disabled. This must
  2045. * be followed by initialization of the appropriate bits
  2046. * and then setup of the interrupt mask.
  2047. */
  2048. sc->curchan = sc->hw->conf.channel;
  2049. sc->curband = &sc->sbands[sc->curchan->band];
  2050. sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
  2051. AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
  2052. AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
  2053. ret = ath5k_reset(sc, NULL);
  2054. if (ret)
  2055. goto done;
  2056. ath5k_rfkill_hw_start(ah);
  2057. /*
  2058. * Reset the key cache since some parts do not reset the
  2059. * contents on initial power up or resume from suspend.
  2060. */
  2061. for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
  2062. ath5k_hw_reset_key(ah, i);
  2063. /* Set ack to be sent at low bit-rates */
  2064. ath5k_hw_set_ack_bitrate_high(ah, false);
  2065. /* Set PHY calibration inteval */
  2066. ah->ah_cal_intval = ath5k_calinterval;
  2067. ret = 0;
  2068. done:
  2069. mmiowb();
  2070. mutex_unlock(&sc->lock);
  2071. return ret;
  2072. }
  2073. static int
  2074. ath5k_stop_locked(struct ath5k_softc *sc)
  2075. {
  2076. struct ath5k_hw *ah = sc->ah;
  2077. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
  2078. test_bit(ATH_STAT_INVALID, sc->status));
  2079. /*
  2080. * Shutdown the hardware and driver:
  2081. * stop output from above
  2082. * disable interrupts
  2083. * turn off timers
  2084. * turn off the radio
  2085. * clear transmit machinery
  2086. * clear receive machinery
  2087. * drain and release tx queues
  2088. * reclaim beacon resources
  2089. * power down hardware
  2090. *
  2091. * Note that some of this work is not possible if the
  2092. * hardware is gone (invalid).
  2093. */
  2094. ieee80211_stop_queues(sc->hw);
  2095. if (!test_bit(ATH_STAT_INVALID, sc->status)) {
  2096. ath5k_led_off(sc);
  2097. ath5k_hw_set_imr(ah, 0);
  2098. synchronize_irq(sc->pdev->irq);
  2099. }
  2100. ath5k_txq_cleanup(sc);
  2101. if (!test_bit(ATH_STAT_INVALID, sc->status)) {
  2102. ath5k_rx_stop(sc);
  2103. ath5k_hw_phy_disable(ah);
  2104. } else
  2105. sc->rxlink = NULL;
  2106. return 0;
  2107. }
  2108. /*
  2109. * Stop the device, grabbing the top-level lock to protect
  2110. * against concurrent entry through ath5k_init (which can happen
  2111. * if another thread does a system call and the thread doing the
  2112. * stop is preempted).
  2113. */
  2114. static int
  2115. ath5k_stop_hw(struct ath5k_softc *sc)
  2116. {
  2117. int ret;
  2118. mutex_lock(&sc->lock);
  2119. ret = ath5k_stop_locked(sc);
  2120. if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
  2121. /*
  2122. * Don't set the card in full sleep mode!
  2123. *
  2124. * a) When the device is in this state it must be carefully
  2125. * woken up or references to registers in the PCI clock
  2126. * domain may freeze the bus (and system). This varies
  2127. * by chip and is mostly an issue with newer parts
  2128. * (madwifi sources mentioned srev >= 0x78) that go to
  2129. * sleep more quickly.
  2130. *
  2131. * b) On older chips full sleep results a weird behaviour
  2132. * during wakeup. I tested various cards with srev < 0x78
  2133. * and they don't wake up after module reload, a second
  2134. * module reload is needed to bring the card up again.
  2135. *
  2136. * Until we figure out what's going on don't enable
  2137. * full chip reset on any chip (this is what Legacy HAL
  2138. * and Sam's HAL do anyway). Instead Perform a full reset
  2139. * on the device (same as initial state after attach) and
  2140. * leave it idle (keep MAC/BB on warm reset) */
  2141. ret = ath5k_hw_on_hold(sc->ah);
  2142. ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
  2143. "putting device to sleep\n");
  2144. }
  2145. ath5k_txbuf_free(sc, sc->bbuf);
  2146. mmiowb();
  2147. mutex_unlock(&sc->lock);
  2148. tasklet_kill(&sc->rxtq);
  2149. tasklet_kill(&sc->txtq);
  2150. tasklet_kill(&sc->restq);
  2151. tasklet_kill(&sc->calib);
  2152. tasklet_kill(&sc->beacontq);
  2153. ath5k_rfkill_hw_stop(sc->ah);
  2154. return ret;
  2155. }
  2156. static irqreturn_t
  2157. ath5k_intr(int irq, void *dev_id)
  2158. {
  2159. struct ath5k_softc *sc = dev_id;
  2160. struct ath5k_hw *ah = sc->ah;
  2161. enum ath5k_int status;
  2162. unsigned int counter = 1000;
  2163. if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
  2164. !ath5k_hw_is_intr_pending(ah)))
  2165. return IRQ_NONE;
  2166. do {
  2167. ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
  2168. ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
  2169. status, sc->imask);
  2170. if (unlikely(status & AR5K_INT_FATAL)) {
  2171. /*
  2172. * Fatal errors are unrecoverable.
  2173. * Typically these are caused by DMA errors.
  2174. */
  2175. tasklet_schedule(&sc->restq);
  2176. } else if (unlikely(status & AR5K_INT_RXORN)) {
  2177. tasklet_schedule(&sc->restq);
  2178. } else {
  2179. if (status & AR5K_INT_SWBA) {
  2180. tasklet_hi_schedule(&sc->beacontq);
  2181. }
  2182. if (status & AR5K_INT_RXEOL) {
  2183. /*
  2184. * NB: the hardware should re-read the link when
  2185. * RXE bit is written, but it doesn't work at
  2186. * least on older hardware revs.
  2187. */
  2188. sc->rxlink = NULL;
  2189. }
  2190. if (status & AR5K_INT_TXURN) {
  2191. /* bump tx trigger level */
  2192. ath5k_hw_update_tx_triglevel(ah, true);
  2193. }
  2194. if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
  2195. tasklet_schedule(&sc->rxtq);
  2196. if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
  2197. | AR5K_INT_TXERR | AR5K_INT_TXEOL))
  2198. tasklet_schedule(&sc->txtq);
  2199. if (status & AR5K_INT_BMISS) {
  2200. /* TODO */
  2201. }
  2202. if (status & AR5K_INT_SWI) {
  2203. tasklet_schedule(&sc->calib);
  2204. }
  2205. if (status & AR5K_INT_MIB) {
  2206. /*
  2207. * These stats are also used for ANI i think
  2208. * so how about updating them more often ?
  2209. */
  2210. ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
  2211. }
  2212. if (status & AR5K_INT_GPIO)
  2213. tasklet_schedule(&sc->rf_kill.toggleq);
  2214. }
  2215. } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
  2216. if (unlikely(!counter))
  2217. ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
  2218. ath5k_hw_calibration_poll(ah);
  2219. return IRQ_HANDLED;
  2220. }
  2221. static void
  2222. ath5k_tasklet_reset(unsigned long data)
  2223. {
  2224. struct ath5k_softc *sc = (void *)data;
  2225. ath5k_reset_wake(sc);
  2226. }
  2227. /*
  2228. * Periodically recalibrate the PHY to account
  2229. * for temperature/environment changes.
  2230. */
  2231. static void
  2232. ath5k_tasklet_calibrate(unsigned long data)
  2233. {
  2234. struct ath5k_softc *sc = (void *)data;
  2235. struct ath5k_hw *ah = sc->ah;
  2236. /* Only full calibration for now */
  2237. if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
  2238. return;
  2239. /* Stop queues so that calibration
  2240. * doesn't interfere with tx */
  2241. ieee80211_stop_queues(sc->hw);
  2242. ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
  2243. ieee80211_frequency_to_channel(sc->curchan->center_freq),
  2244. sc->curchan->hw_value);
  2245. if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
  2246. /*
  2247. * Rfgain is out of bounds, reset the chip
  2248. * to load new gain values.
  2249. */
  2250. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
  2251. ath5k_reset_wake(sc);
  2252. }
  2253. if (ath5k_hw_phy_calibrate(ah, sc->curchan))
  2254. ATH5K_ERR(sc, "calibration of channel %u failed\n",
  2255. ieee80211_frequency_to_channel(
  2256. sc->curchan->center_freq));
  2257. ah->ah_swi_mask = 0;
  2258. /* Wake queues */
  2259. ieee80211_wake_queues(sc->hw);
  2260. }
  2261. /********************\
  2262. * Mac80211 functions *
  2263. \********************/
  2264. static int
  2265. ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2266. {
  2267. struct ath5k_softc *sc = hw->priv;
  2268. return ath5k_tx_queue(hw, skb, sc->txq);
  2269. }
  2270. static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
  2271. struct ath5k_txq *txq)
  2272. {
  2273. struct ath5k_softc *sc = hw->priv;
  2274. struct ath5k_buf *bf;
  2275. unsigned long flags;
  2276. int hdrlen;
  2277. int padsize;
  2278. ath5k_debug_dump_skb(sc, skb, "TX ", 1);
  2279. if (sc->opmode == NL80211_IFTYPE_MONITOR)
  2280. ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
  2281. /*
  2282. * the hardware expects the header padded to 4 byte boundaries
  2283. * if this is not the case we add the padding after the header
  2284. */
  2285. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  2286. padsize = ath5k_pad_size(hdrlen);
  2287. if (padsize) {
  2288. if (skb_headroom(skb) < padsize) {
  2289. ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
  2290. " headroom to pad %d\n", hdrlen, padsize);
  2291. goto drop_packet;
  2292. }
  2293. skb_push(skb, padsize);
  2294. memmove(skb->data, skb->data+padsize, hdrlen);
  2295. }
  2296. spin_lock_irqsave(&sc->txbuflock, flags);
  2297. if (list_empty(&sc->txbuf)) {
  2298. ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
  2299. spin_unlock_irqrestore(&sc->txbuflock, flags);
  2300. ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
  2301. goto drop_packet;
  2302. }
  2303. bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
  2304. list_del(&bf->list);
  2305. sc->txbuf_len--;
  2306. if (list_empty(&sc->txbuf))
  2307. ieee80211_stop_queues(hw);
  2308. spin_unlock_irqrestore(&sc->txbuflock, flags);
  2309. bf->skb = skb;
  2310. if (ath5k_txbuf_setup(sc, bf, txq)) {
  2311. bf->skb = NULL;
  2312. spin_lock_irqsave(&sc->txbuflock, flags);
  2313. list_add_tail(&bf->list, &sc->txbuf);
  2314. sc->txbuf_len++;
  2315. spin_unlock_irqrestore(&sc->txbuflock, flags);
  2316. goto drop_packet;
  2317. }
  2318. return NETDEV_TX_OK;
  2319. drop_packet:
  2320. dev_kfree_skb_any(skb);
  2321. return NETDEV_TX_OK;
  2322. }
  2323. /*
  2324. * Reset the hardware. If chan is not NULL, then also pause rx/tx
  2325. * and change to the given channel.
  2326. */
  2327. static int
  2328. ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
  2329. {
  2330. struct ath5k_hw *ah = sc->ah;
  2331. int ret;
  2332. ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
  2333. if (chan) {
  2334. ath5k_hw_set_imr(ah, 0);
  2335. ath5k_txq_cleanup(sc);
  2336. ath5k_rx_stop(sc);
  2337. sc->curchan = chan;
  2338. sc->curband = &sc->sbands[chan->band];
  2339. }
  2340. ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
  2341. if (ret) {
  2342. ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
  2343. goto err;
  2344. }
  2345. ret = ath5k_rx_start(sc);
  2346. if (ret) {
  2347. ATH5K_ERR(sc, "can't start recv logic\n");
  2348. goto err;
  2349. }
  2350. /*
  2351. * Change channels and update the h/w rate map if we're switching;
  2352. * e.g. 11a to 11b/g.
  2353. *
  2354. * We may be doing a reset in response to an ioctl that changes the
  2355. * channel so update any state that might change as a result.
  2356. *
  2357. * XXX needed?
  2358. */
  2359. /* ath5k_chan_change(sc, c); */
  2360. ath5k_beacon_config(sc);
  2361. /* intrs are enabled by ath5k_beacon_config */
  2362. return 0;
  2363. err:
  2364. return ret;
  2365. }
  2366. static int
  2367. ath5k_reset_wake(struct ath5k_softc *sc)
  2368. {
  2369. int ret;
  2370. ret = ath5k_reset(sc, sc->curchan);
  2371. if (!ret)
  2372. ieee80211_wake_queues(sc->hw);
  2373. return ret;
  2374. }
  2375. static int ath5k_start(struct ieee80211_hw *hw)
  2376. {
  2377. return ath5k_init(hw->priv);
  2378. }
  2379. static void ath5k_stop(struct ieee80211_hw *hw)
  2380. {
  2381. ath5k_stop_hw(hw->priv);
  2382. }
  2383. static int ath5k_add_interface(struct ieee80211_hw *hw,
  2384. struct ieee80211_if_init_conf *conf)
  2385. {
  2386. struct ath5k_softc *sc = hw->priv;
  2387. int ret;
  2388. mutex_lock(&sc->lock);
  2389. if (sc->vif) {
  2390. ret = 0;
  2391. goto end;
  2392. }
  2393. sc->vif = conf->vif;
  2394. switch (conf->type) {
  2395. case NL80211_IFTYPE_AP:
  2396. case NL80211_IFTYPE_STATION:
  2397. case NL80211_IFTYPE_ADHOC:
  2398. case NL80211_IFTYPE_MESH_POINT:
  2399. case NL80211_IFTYPE_MONITOR:
  2400. sc->opmode = conf->type;
  2401. break;
  2402. default:
  2403. ret = -EOPNOTSUPP;
  2404. goto end;
  2405. }
  2406. ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
  2407. ath5k_mode_setup(sc);
  2408. ret = 0;
  2409. end:
  2410. mutex_unlock(&sc->lock);
  2411. return ret;
  2412. }
  2413. static void
  2414. ath5k_remove_interface(struct ieee80211_hw *hw,
  2415. struct ieee80211_if_init_conf *conf)
  2416. {
  2417. struct ath5k_softc *sc = hw->priv;
  2418. u8 mac[ETH_ALEN] = {};
  2419. mutex_lock(&sc->lock);
  2420. if (sc->vif != conf->vif)
  2421. goto end;
  2422. ath5k_hw_set_lladdr(sc->ah, mac);
  2423. sc->vif = NULL;
  2424. end:
  2425. mutex_unlock(&sc->lock);
  2426. }
  2427. /*
  2428. * TODO: Phy disable/diversity etc
  2429. */
  2430. static int
  2431. ath5k_config(struct ieee80211_hw *hw, u32 changed)
  2432. {
  2433. struct ath5k_softc *sc = hw->priv;
  2434. struct ath5k_hw *ah = sc->ah;
  2435. struct ieee80211_conf *conf = &hw->conf;
  2436. int ret = 0;
  2437. mutex_lock(&sc->lock);
  2438. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  2439. ret = ath5k_chan_set(sc, conf->channel);
  2440. if (ret < 0)
  2441. goto unlock;
  2442. }
  2443. if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
  2444. (sc->power_level != conf->power_level)) {
  2445. sc->power_level = conf->power_level;
  2446. /* Half dB steps */
  2447. ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
  2448. }
  2449. /* TODO:
  2450. * 1) Move this on config_interface and handle each case
  2451. * separately eg. when we have only one STA vif, use
  2452. * AR5K_ANTMODE_SINGLE_AP
  2453. *
  2454. * 2) Allow the user to change antenna mode eg. when only
  2455. * one antenna is present
  2456. *
  2457. * 3) Allow the user to set default/tx antenna when possible
  2458. *
  2459. * 4) Default mode should handle 90% of the cases, together
  2460. * with fixed a/b and single AP modes we should be able to
  2461. * handle 99%. Sectored modes are extreme cases and i still
  2462. * haven't found a usage for them. If we decide to support them,
  2463. * then we must allow the user to set how many tx antennas we
  2464. * have available
  2465. */
  2466. ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
  2467. unlock:
  2468. mutex_unlock(&sc->lock);
  2469. return ret;
  2470. }
  2471. static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
  2472. int mc_count, struct dev_addr_list *mclist)
  2473. {
  2474. u32 mfilt[2], val;
  2475. int i;
  2476. u8 pos;
  2477. mfilt[0] = 0;
  2478. mfilt[1] = 1;
  2479. for (i = 0; i < mc_count; i++) {
  2480. if (!mclist)
  2481. break;
  2482. /* calculate XOR of eight 6-bit values */
  2483. val = get_unaligned_le32(mclist->dmi_addr + 0);
  2484. pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
  2485. val = get_unaligned_le32(mclist->dmi_addr + 3);
  2486. pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
  2487. pos &= 0x3f;
  2488. mfilt[pos / 32] |= (1 << (pos % 32));
  2489. /* XXX: we might be able to just do this instead,
  2490. * but not sure, needs testing, if we do use this we'd
  2491. * neet to inform below to not reset the mcast */
  2492. /* ath5k_hw_set_mcast_filterindex(ah,
  2493. * mclist->dmi_addr[5]); */
  2494. mclist = mclist->next;
  2495. }
  2496. return ((u64)(mfilt[1]) << 32) | mfilt[0];
  2497. }
  2498. #define SUPPORTED_FIF_FLAGS \
  2499. FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
  2500. FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
  2501. FIF_BCN_PRBRESP_PROMISC
  2502. /*
  2503. * o always accept unicast, broadcast, and multicast traffic
  2504. * o multicast traffic for all BSSIDs will be enabled if mac80211
  2505. * says it should be
  2506. * o maintain current state of phy ofdm or phy cck error reception.
  2507. * If the hardware detects any of these type of errors then
  2508. * ath5k_hw_get_rx_filter() will pass to us the respective
  2509. * hardware filters to be able to receive these type of frames.
  2510. * o probe request frames are accepted only when operating in
  2511. * hostap, adhoc, or monitor modes
  2512. * o enable promiscuous mode according to the interface state
  2513. * o accept beacons:
  2514. * - when operating in adhoc mode so the 802.11 layer creates
  2515. * node table entries for peers,
  2516. * - when operating in station mode for collecting rssi data when
  2517. * the station is otherwise quiet, or
  2518. * - when scanning
  2519. */
  2520. static void ath5k_configure_filter(struct ieee80211_hw *hw,
  2521. unsigned int changed_flags,
  2522. unsigned int *new_flags,
  2523. u64 multicast)
  2524. {
  2525. struct ath5k_softc *sc = hw->priv;
  2526. struct ath5k_hw *ah = sc->ah;
  2527. u32 mfilt[2], rfilt;
  2528. mutex_lock(&sc->lock);
  2529. mfilt[0] = multicast;
  2530. mfilt[1] = multicast >> 32;
  2531. /* Only deal with supported flags */
  2532. changed_flags &= SUPPORTED_FIF_FLAGS;
  2533. *new_flags &= SUPPORTED_FIF_FLAGS;
  2534. /* If HW detects any phy or radar errors, leave those filters on.
  2535. * Also, always enable Unicast, Broadcasts and Multicast
  2536. * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
  2537. rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
  2538. (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
  2539. AR5K_RX_FILTER_MCAST);
  2540. if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
  2541. if (*new_flags & FIF_PROMISC_IN_BSS) {
  2542. rfilt |= AR5K_RX_FILTER_PROM;
  2543. __set_bit(ATH_STAT_PROMISC, sc->status);
  2544. } else {
  2545. __clear_bit(ATH_STAT_PROMISC, sc->status);
  2546. }
  2547. }
  2548. /* Note, AR5K_RX_FILTER_MCAST is already enabled */
  2549. if (*new_flags & FIF_ALLMULTI) {
  2550. mfilt[0] = ~0;
  2551. mfilt[1] = ~0;
  2552. }
  2553. /* This is the best we can do */
  2554. if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
  2555. rfilt |= AR5K_RX_FILTER_PHYERR;
  2556. /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
  2557. * and probes for any BSSID, this needs testing */
  2558. if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
  2559. rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
  2560. /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
  2561. * set we should only pass on control frames for this
  2562. * station. This needs testing. I believe right now this
  2563. * enables *all* control frames, which is OK.. but
  2564. * but we should see if we can improve on granularity */
  2565. if (*new_flags & FIF_CONTROL)
  2566. rfilt |= AR5K_RX_FILTER_CONTROL;
  2567. /* Additional settings per mode -- this is per ath5k */
  2568. /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
  2569. switch (sc->opmode) {
  2570. case NL80211_IFTYPE_MESH_POINT:
  2571. case NL80211_IFTYPE_MONITOR:
  2572. rfilt |= AR5K_RX_FILTER_CONTROL |
  2573. AR5K_RX_FILTER_BEACON |
  2574. AR5K_RX_FILTER_PROBEREQ |
  2575. AR5K_RX_FILTER_PROM;
  2576. break;
  2577. case NL80211_IFTYPE_AP:
  2578. case NL80211_IFTYPE_ADHOC:
  2579. rfilt |= AR5K_RX_FILTER_PROBEREQ |
  2580. AR5K_RX_FILTER_BEACON;
  2581. break;
  2582. case NL80211_IFTYPE_STATION:
  2583. if (sc->assoc)
  2584. rfilt |= AR5K_RX_FILTER_BEACON;
  2585. default:
  2586. break;
  2587. }
  2588. /* Set filters */
  2589. ath5k_hw_set_rx_filter(ah, rfilt);
  2590. /* Set multicast bits */
  2591. ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
  2592. /* Set the cached hw filter flags, this will alter actually
  2593. * be set in HW */
  2594. sc->filter_flags = rfilt;
  2595. mutex_unlock(&sc->lock);
  2596. }
  2597. static int
  2598. ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2599. struct ieee80211_vif *vif, struct ieee80211_sta *sta,
  2600. struct ieee80211_key_conf *key)
  2601. {
  2602. struct ath5k_softc *sc = hw->priv;
  2603. int ret = 0;
  2604. if (modparam_nohwcrypt)
  2605. return -EOPNOTSUPP;
  2606. if (sc->opmode == NL80211_IFTYPE_AP)
  2607. return -EOPNOTSUPP;
  2608. switch (key->alg) {
  2609. case ALG_WEP:
  2610. case ALG_TKIP:
  2611. break;
  2612. case ALG_CCMP:
  2613. if (sc->ah->ah_aes_support)
  2614. break;
  2615. return -EOPNOTSUPP;
  2616. default:
  2617. WARN_ON(1);
  2618. return -EINVAL;
  2619. }
  2620. mutex_lock(&sc->lock);
  2621. switch (cmd) {
  2622. case SET_KEY:
  2623. ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
  2624. sta ? sta->addr : NULL);
  2625. if (ret) {
  2626. ATH5K_ERR(sc, "can't set the key\n");
  2627. goto unlock;
  2628. }
  2629. __set_bit(key->keyidx, sc->keymap);
  2630. key->hw_key_idx = key->keyidx;
  2631. key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
  2632. IEEE80211_KEY_FLAG_GENERATE_MMIC);
  2633. break;
  2634. case DISABLE_KEY:
  2635. ath5k_hw_reset_key(sc->ah, key->keyidx);
  2636. __clear_bit(key->keyidx, sc->keymap);
  2637. break;
  2638. default:
  2639. ret = -EINVAL;
  2640. goto unlock;
  2641. }
  2642. unlock:
  2643. mmiowb();
  2644. mutex_unlock(&sc->lock);
  2645. return ret;
  2646. }
  2647. static int
  2648. ath5k_get_stats(struct ieee80211_hw *hw,
  2649. struct ieee80211_low_level_stats *stats)
  2650. {
  2651. struct ath5k_softc *sc = hw->priv;
  2652. struct ath5k_hw *ah = sc->ah;
  2653. /* Force update */
  2654. ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
  2655. memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
  2656. return 0;
  2657. }
  2658. static int
  2659. ath5k_get_tx_stats(struct ieee80211_hw *hw,
  2660. struct ieee80211_tx_queue_stats *stats)
  2661. {
  2662. struct ath5k_softc *sc = hw->priv;
  2663. memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
  2664. return 0;
  2665. }
  2666. static u64
  2667. ath5k_get_tsf(struct ieee80211_hw *hw)
  2668. {
  2669. struct ath5k_softc *sc = hw->priv;
  2670. return ath5k_hw_get_tsf64(sc->ah);
  2671. }
  2672. static void
  2673. ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  2674. {
  2675. struct ath5k_softc *sc = hw->priv;
  2676. ath5k_hw_set_tsf64(sc->ah, tsf);
  2677. }
  2678. static void
  2679. ath5k_reset_tsf(struct ieee80211_hw *hw)
  2680. {
  2681. struct ath5k_softc *sc = hw->priv;
  2682. /*
  2683. * in IBSS mode we need to update the beacon timers too.
  2684. * this will also reset the TSF if we call it with 0
  2685. */
  2686. if (sc->opmode == NL80211_IFTYPE_ADHOC)
  2687. ath5k_beacon_update_timers(sc, 0);
  2688. else
  2689. ath5k_hw_reset_tsf(sc->ah);
  2690. }
  2691. /*
  2692. * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
  2693. * this is called only once at config_bss time, for AP we do it every
  2694. * SWBA interrupt so that the TIM will reflect buffered frames.
  2695. *
  2696. * Called with the beacon lock.
  2697. */
  2698. static int
  2699. ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  2700. {
  2701. int ret;
  2702. struct ath5k_softc *sc = hw->priv;
  2703. struct sk_buff *skb;
  2704. if (WARN_ON(!vif)) {
  2705. ret = -EINVAL;
  2706. goto out;
  2707. }
  2708. skb = ieee80211_beacon_get(hw, vif);
  2709. if (!skb) {
  2710. ret = -ENOMEM;
  2711. goto out;
  2712. }
  2713. ath5k_debug_dump_skb(sc, skb, "BC ", 1);
  2714. ath5k_txbuf_free(sc, sc->bbuf);
  2715. sc->bbuf->skb = skb;
  2716. ret = ath5k_beacon_setup(sc, sc->bbuf);
  2717. if (ret)
  2718. sc->bbuf->skb = NULL;
  2719. out:
  2720. return ret;
  2721. }
  2722. static void
  2723. set_beacon_filter(struct ieee80211_hw *hw, bool enable)
  2724. {
  2725. struct ath5k_softc *sc = hw->priv;
  2726. struct ath5k_hw *ah = sc->ah;
  2727. u32 rfilt;
  2728. rfilt = ath5k_hw_get_rx_filter(ah);
  2729. if (enable)
  2730. rfilt |= AR5K_RX_FILTER_BEACON;
  2731. else
  2732. rfilt &= ~AR5K_RX_FILTER_BEACON;
  2733. ath5k_hw_set_rx_filter(ah, rfilt);
  2734. sc->filter_flags = rfilt;
  2735. }
  2736. static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
  2737. struct ieee80211_vif *vif,
  2738. struct ieee80211_bss_conf *bss_conf,
  2739. u32 changes)
  2740. {
  2741. struct ath5k_softc *sc = hw->priv;
  2742. struct ath5k_hw *ah = sc->ah;
  2743. struct ath_common *common = ath5k_hw_common(ah);
  2744. unsigned long flags;
  2745. mutex_lock(&sc->lock);
  2746. if (WARN_ON(sc->vif != vif))
  2747. goto unlock;
  2748. if (changes & BSS_CHANGED_BSSID) {
  2749. /* Cache for later use during resets */
  2750. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  2751. /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
  2752. * a clean way of letting us retrieve this yet. */
  2753. ath5k_hw_set_associd(ah, common->curbssid, 0);
  2754. mmiowb();
  2755. }
  2756. if (changes & BSS_CHANGED_BEACON_INT)
  2757. sc->bintval = bss_conf->beacon_int;
  2758. if (changes & BSS_CHANGED_ASSOC) {
  2759. sc->assoc = bss_conf->assoc;
  2760. if (sc->opmode == NL80211_IFTYPE_STATION)
  2761. set_beacon_filter(hw, sc->assoc);
  2762. ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
  2763. AR5K_LED_ASSOC : AR5K_LED_INIT);
  2764. }
  2765. if (changes & BSS_CHANGED_BEACON) {
  2766. spin_lock_irqsave(&sc->block, flags);
  2767. ath5k_beacon_update(hw, vif);
  2768. spin_unlock_irqrestore(&sc->block, flags);
  2769. }
  2770. if (changes & BSS_CHANGED_BEACON_ENABLED)
  2771. sc->enable_beacon = bss_conf->enable_beacon;
  2772. if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
  2773. BSS_CHANGED_BEACON_INT))
  2774. ath5k_beacon_config(sc);
  2775. unlock:
  2776. mutex_unlock(&sc->lock);
  2777. }
  2778. static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
  2779. {
  2780. struct ath5k_softc *sc = hw->priv;
  2781. if (!sc->assoc)
  2782. ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
  2783. }
  2784. static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
  2785. {
  2786. struct ath5k_softc *sc = hw->priv;
  2787. ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
  2788. AR5K_LED_ASSOC : AR5K_LED_INIT);
  2789. }