mach-mx28evk.c 4.8 KB

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  1. /*
  2. * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; either version 2 of the License, or
  7. * (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/gpio.h>
  17. #include <linux/irq.h>
  18. #include <linux/clk.h>
  19. #include <asm/mach-types.h>
  20. #include <asm/mach/arch.h>
  21. #include <asm/mach/time.h>
  22. #include <mach/common.h>
  23. #include <mach/iomux-mx28.h>
  24. #include "devices-mx28.h"
  25. #include "gpio.h"
  26. #define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15)
  27. #define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
  28. static const iomux_cfg_t mx28evk_pads[] __initconst = {
  29. /* duart */
  30. MX28_PAD_PWM0__DUART_RX | MXS_PAD_CTRL,
  31. MX28_PAD_PWM1__DUART_TX | MXS_PAD_CTRL,
  32. /* auart0 */
  33. MX28_PAD_AUART0_RX__AUART0_RX | MXS_PAD_CTRL,
  34. MX28_PAD_AUART0_TX__AUART0_TX | MXS_PAD_CTRL,
  35. MX28_PAD_AUART0_CTS__AUART0_CTS | MXS_PAD_CTRL,
  36. MX28_PAD_AUART0_RTS__AUART0_RTS | MXS_PAD_CTRL,
  37. /* auart3 */
  38. MX28_PAD_AUART3_RX__AUART3_RX | MXS_PAD_CTRL,
  39. MX28_PAD_AUART3_TX__AUART3_TX | MXS_PAD_CTRL,
  40. MX28_PAD_AUART3_CTS__AUART3_CTS | MXS_PAD_CTRL,
  41. MX28_PAD_AUART3_RTS__AUART3_RTS | MXS_PAD_CTRL,
  42. #define MXS_PAD_FEC (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP)
  43. /* fec0 */
  44. MX28_PAD_ENET0_MDC__ENET0_MDC | MXS_PAD_FEC,
  45. MX28_PAD_ENET0_MDIO__ENET0_MDIO | MXS_PAD_FEC,
  46. MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MXS_PAD_FEC,
  47. MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MXS_PAD_FEC,
  48. MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MXS_PAD_FEC,
  49. MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MXS_PAD_FEC,
  50. MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MXS_PAD_FEC,
  51. MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MXS_PAD_FEC,
  52. MX28_PAD_ENET_CLK__CLKCTRL_ENET | MXS_PAD_FEC,
  53. /* fec1 */
  54. MX28_PAD_ENET0_CRS__ENET1_RX_EN | MXS_PAD_FEC,
  55. MX28_PAD_ENET0_RXD2__ENET1_RXD0 | MXS_PAD_FEC,
  56. MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MXS_PAD_FEC,
  57. MX28_PAD_ENET0_COL__ENET1_TX_EN | MXS_PAD_FEC,
  58. MX28_PAD_ENET0_TXD2__ENET1_TXD0 | MXS_PAD_FEC,
  59. MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MXS_PAD_FEC,
  60. /* phy power line */
  61. MX28_PAD_SSP1_DATA3__GPIO_2_15 | MXS_PAD_CTRL,
  62. /* phy reset line */
  63. MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MXS_PAD_CTRL,
  64. };
  65. /* fec */
  66. static void __init mx28evk_fec_reset(void)
  67. {
  68. int ret;
  69. struct clk *clk;
  70. /* Enable fec phy clock */
  71. clk = clk_get_sys("pll2", NULL);
  72. if (!IS_ERR(clk))
  73. clk_enable(clk);
  74. /* Power up fec phy */
  75. ret = gpio_request(MX28EVK_FEC_PHY_POWER, "fec-phy-power");
  76. if (ret) {
  77. pr_err("Failed to request gpio fec-phy-%s: %d\n", "power", ret);
  78. return;
  79. }
  80. ret = gpio_direction_output(MX28EVK_FEC_PHY_POWER, 0);
  81. if (ret) {
  82. pr_err("Failed to drive gpio fec-phy-%s: %d\n", "power", ret);
  83. return;
  84. }
  85. /* Reset fec phy */
  86. ret = gpio_request(MX28EVK_FEC_PHY_RESET, "fec-phy-reset");
  87. if (ret) {
  88. pr_err("Failed to request gpio fec-phy-%s: %d\n", "reset", ret);
  89. return;
  90. }
  91. gpio_direction_output(MX28EVK_FEC_PHY_RESET, 0);
  92. if (ret) {
  93. pr_err("Failed to drive gpio fec-phy-%s: %d\n", "reset", ret);
  94. return;
  95. }
  96. mdelay(1);
  97. gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
  98. }
  99. static struct fec_platform_data mx28_fec_pdata[] __initdata = {
  100. {
  101. /* fec0 */
  102. .phy = PHY_INTERFACE_MODE_RMII,
  103. }, {
  104. /* fec1 */
  105. .phy = PHY_INTERFACE_MODE_RMII,
  106. },
  107. };
  108. static int __init mx28evk_fec_get_mac(void)
  109. {
  110. int i;
  111. u32 val;
  112. const u32 *ocotp = mxs_get_ocotp();
  113. if (!ocotp)
  114. goto error;
  115. /*
  116. * OCOTP only stores the last 4 octets for each mac address,
  117. * so hard-code Freescale OUI (00:04:9f) here.
  118. */
  119. for (i = 0; i < 2; i++) {
  120. val = ocotp[i * 4];
  121. mx28_fec_pdata[i].mac[0] = 0x00;
  122. mx28_fec_pdata[i].mac[1] = 0x04;
  123. mx28_fec_pdata[i].mac[2] = 0x9f;
  124. mx28_fec_pdata[i].mac[3] = (val >> 16) & 0xff;
  125. mx28_fec_pdata[i].mac[4] = (val >> 8) & 0xff;
  126. mx28_fec_pdata[i].mac[5] = (val >> 0) & 0xff;
  127. }
  128. return 0;
  129. error:
  130. pr_err("%s: timeout when reading fec mac from OCOTP\n", __func__);
  131. return -ETIMEDOUT;
  132. }
  133. static void __init mx28evk_init(void)
  134. {
  135. mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
  136. mx28_add_duart();
  137. mx28_add_auart0();
  138. mx28_add_auart3();
  139. if (mx28evk_fec_get_mac())
  140. pr_warn("%s: failed on fec mac setup\n", __func__);
  141. mx28evk_fec_reset();
  142. mx28_add_fec(0, &mx28_fec_pdata[0]);
  143. mx28_add_fec(1, &mx28_fec_pdata[1]);
  144. }
  145. static void __init mx28evk_timer_init(void)
  146. {
  147. mx28_clocks_init();
  148. }
  149. static struct sys_timer mx28evk_timer = {
  150. .init = mx28evk_timer_init,
  151. };
  152. MACHINE_START(MX28EVK, "Freescale MX28 EVK")
  153. /* Maintainer: Freescale Semiconductor, Inc. */
  154. .map_io = mx28_map_io,
  155. .init_irq = mx28_init_irq,
  156. .init_machine = mx28evk_init,
  157. .timer = &mx28evk_timer,
  158. MACHINE_END