at91sam9263.dtsi 11 KB

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  1. /*
  2. * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
  3. *
  4. * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  5. *
  6. * Licensed under GPLv2 only.
  7. */
  8. /include/ "skeleton.dtsi"
  9. / {
  10. model = "Atmel AT91SAM9263 family SoC";
  11. compatible = "atmel,at91sam9263";
  12. interrupt-parent = <&aic>;
  13. aliases {
  14. serial0 = &dbgu;
  15. serial1 = &usart0;
  16. serial2 = &usart1;
  17. serial3 = &usart2;
  18. gpio0 = &pioA;
  19. gpio1 = &pioB;
  20. gpio2 = &pioC;
  21. gpio3 = &pioD;
  22. gpio4 = &pioE;
  23. tcb0 = &tcb0;
  24. i2c0 = &i2c0;
  25. };
  26. cpus {
  27. cpu@0 {
  28. compatible = "arm,arm926ejs";
  29. };
  30. };
  31. memory {
  32. reg = <0x20000000 0x08000000>;
  33. };
  34. ahb {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. ranges;
  39. apb {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. ranges;
  44. aic: interrupt-controller@fffff000 {
  45. #interrupt-cells = <3>;
  46. compatible = "atmel,at91rm9200-aic";
  47. interrupt-controller;
  48. reg = <0xfffff000 0x200>;
  49. atmel,external-irqs = <30 31>;
  50. };
  51. pmc: pmc@fffffc00 {
  52. compatible = "atmel,at91rm9200-pmc";
  53. reg = <0xfffffc00 0x100>;
  54. };
  55. ramc: ramc@ffffe200 {
  56. compatible = "atmel,at91sam9260-sdramc";
  57. reg = <0xffffe200 0x200
  58. 0xffffe800 0x200>;
  59. };
  60. pit: timer@fffffd30 {
  61. compatible = "atmel,at91sam9260-pit";
  62. reg = <0xfffffd30 0xf>;
  63. interrupts = <1 4 7>;
  64. };
  65. tcb0: timer@fff7c000 {
  66. compatible = "atmel,at91rm9200-tcb";
  67. reg = <0xfff7c000 0x100>;
  68. interrupts = <19 4 0>;
  69. };
  70. rstc@fffffd00 {
  71. compatible = "atmel,at91sam9260-rstc";
  72. reg = <0xfffffd00 0x10>;
  73. };
  74. shdwc@fffffd10 {
  75. compatible = "atmel,at91sam9260-shdwc";
  76. reg = <0xfffffd10 0x10>;
  77. };
  78. pinctrl@fffff200 {
  79. #address-cells = <1>;
  80. #size-cells = <1>;
  81. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  82. ranges = <0xfffff200 0xfffff200 0xa00>;
  83. atmel,mux-mask = <
  84. /* A B */
  85. 0xfffffffb 0xffffe07f /* pioA */
  86. 0x0007ffff 0x39072fff /* pioB */
  87. 0xffffffff 0x3ffffff8 /* pioC */
  88. 0xfffffbff 0xffffffff /* pioD */
  89. 0xffe00fff 0xfbfcff00 /* pioE */
  90. >;
  91. /* shared pinctrl settings */
  92. dbgu {
  93. pinctrl_dbgu: dbgu-0 {
  94. atmel,pins =
  95. <2 30 0x1 0x0 /* PC30 periph A */
  96. 2 31 0x1 0x1>; /* PC31 periph with pullup */
  97. };
  98. };
  99. usart0 {
  100. pinctrl_usart0: usart0-0 {
  101. atmel,pins =
  102. <0 26 0x1 0x1 /* PA26 periph A with pullup */
  103. 0 27 0x1 0x0>; /* PA27 periph A */
  104. };
  105. pinctrl_usart0_rts: usart0_rts-0 {
  106. atmel,pins =
  107. <0 28 0x1 0x0>; /* PA28 periph A */
  108. };
  109. pinctrl_usart0_cts: usart0_cts-0 {
  110. atmel,pins =
  111. <0 29 0x1 0x0>; /* PA29 periph A */
  112. };
  113. };
  114. usart1 {
  115. pinctrl_usart1: usart1-0 {
  116. atmel,pins =
  117. <3 0 0x1 0x1 /* PD0 periph A with pullup */
  118. 3 1 0x1 0x0>; /* PD1 periph A */
  119. };
  120. pinctrl_usart1_rts: usart1_rts-0 {
  121. atmel,pins =
  122. <3 7 0x2 0x0>; /* PD7 periph B */
  123. };
  124. pinctrl_usart1_cts: usart1_cts-0 {
  125. atmel,pins =
  126. <3 8 0x2 0x0>; /* PD8 periph B */
  127. };
  128. };
  129. usart2 {
  130. pinctrl_usart2: usart2-0 {
  131. atmel,pins =
  132. <3 2 0x1 0x1 /* PD2 periph A with pullup */
  133. 3 3 0x1 0x0>; /* PD3 periph A */
  134. };
  135. pinctrl_usart2_rts: usart2_rts-0 {
  136. atmel,pins =
  137. <3 5 0x2 0x0>; /* PD5 periph B */
  138. };
  139. pinctrl_usart2_cts: usart2_cts-0 {
  140. atmel,pins =
  141. <4 6 0x2 0x0>; /* PD6 periph B */
  142. };
  143. };
  144. nand {
  145. pinctrl_nand: nand-0 {
  146. atmel,pins =
  147. <0 22 0x0 0x1 /* PA22 gpio RDY pin pull_up*/
  148. 3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
  149. };
  150. };
  151. macb {
  152. pinctrl_macb_rmii: macb_rmii-0 {
  153. atmel,pins =
  154. <2 25 0x2 0x0 /* PC25 periph B */
  155. 4 21 0x1 0x0 /* PE21 periph A */
  156. 4 23 0x1 0x0 /* PE23 periph A */
  157. 4 24 0x1 0x0 /* PE24 periph A */
  158. 4 25 0x1 0x0 /* PE25 periph A */
  159. 4 26 0x1 0x0 /* PE26 periph A */
  160. 4 27 0x1 0x0 /* PE27 periph A */
  161. 4 28 0x1 0x0 /* PE28 periph A */
  162. 4 29 0x1 0x0 /* PE29 periph A */
  163. 4 30 0x1 0x0>; /* PE30 periph A */
  164. };
  165. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  166. atmel,pins =
  167. <2 20 0x2 0x0 /* PC20 periph B */
  168. 2 21 0x2 0x0 /* PC21 periph B */
  169. 2 22 0x2 0x0 /* PC22 periph B */
  170. 2 23 0x2 0x0 /* PC23 periph B */
  171. 2 24 0x2 0x0 /* PC24 periph B */
  172. 2 25 0x2 0x0 /* PC25 periph B */
  173. 2 27 0x2 0x0 /* PC27 periph B */
  174. 4 22 0x2 0x0>; /* PE22 periph B */
  175. };
  176. };
  177. mmc0 {
  178. pinctrl_mmc0_clk: mmc0_clk-0 {
  179. atmel,pins =
  180. <0 12 0x1 0x0>; /* PA12 periph A */
  181. };
  182. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  183. atmel,pins =
  184. <0 1 0x1 0x1 /* PA1 periph A with pullup */
  185. 0 0 0x1 0x1>; /* PA0 periph A with pullup */
  186. };
  187. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  188. atmel,pins =
  189. <0 3 0x1 0x1 /* PA3 periph A with pullup */
  190. 0 4 0x1 0x1 /* PA4 periph A with pullup */
  191. 0 5 0x1 0x1>; /* PA5 periph A with pullup */
  192. };
  193. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  194. atmel,pins =
  195. <0 16 0x1 0x1 /* PA16 periph A with pullup */
  196. 0 17 0x1 0x1>; /* PA17 periph A with pullup */
  197. };
  198. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  199. atmel,pins =
  200. <0 18 0x1 0x1 /* PA18 periph A with pullup */
  201. 0 19 0x1 0x1 /* PA19 periph A with pullup */
  202. 0 20 0x1 0x1>; /* PA20 periph A with pullup */
  203. };
  204. };
  205. mmc1 {
  206. pinctrl_mmc1_clk: mmc1_clk-0 {
  207. atmel,pins =
  208. <0 6 0x1 0x0>; /* PA6 periph A */
  209. };
  210. pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
  211. atmel,pins =
  212. <0 7 0x1 0x1 /* PA7 periph A with pullup */
  213. 0 8 0x1 0x1>; /* PA8 periph A with pullup */
  214. };
  215. pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
  216. atmel,pins =
  217. <0 9 0x1 0x1 /* PA9 periph A with pullup */
  218. 0 10 0x1 0x1 /* PA10 periph A with pullup */
  219. 0 11 0x1 0x1>; /* PA11 periph A with pullup */
  220. };
  221. pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
  222. atmel,pins =
  223. <0 21 0x1 0x1 /* PA21 periph A with pullup */
  224. 0 22 0x1 0x1>; /* PA22 periph A with pullup */
  225. };
  226. pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
  227. atmel,pins =
  228. <0 23 0x1 0x1 /* PA23 periph A with pullup */
  229. 0 24 0x1 0x1 /* PA24 periph A with pullup */
  230. 0 25 0x1 0x1>; /* PA25 periph A with pullup */
  231. };
  232. };
  233. pioA: gpio@fffff200 {
  234. compatible = "atmel,at91rm9200-gpio";
  235. reg = <0xfffff200 0x200>;
  236. interrupts = <2 4 1>;
  237. #gpio-cells = <2>;
  238. gpio-controller;
  239. interrupt-controller;
  240. #interrupt-cells = <2>;
  241. };
  242. pioB: gpio@fffff400 {
  243. compatible = "atmel,at91rm9200-gpio";
  244. reg = <0xfffff400 0x200>;
  245. interrupts = <3 4 1>;
  246. #gpio-cells = <2>;
  247. gpio-controller;
  248. interrupt-controller;
  249. #interrupt-cells = <2>;
  250. };
  251. pioC: gpio@fffff600 {
  252. compatible = "atmel,at91rm9200-gpio";
  253. reg = <0xfffff600 0x200>;
  254. interrupts = <4 4 1>;
  255. #gpio-cells = <2>;
  256. gpio-controller;
  257. interrupt-controller;
  258. #interrupt-cells = <2>;
  259. };
  260. pioD: gpio@fffff800 {
  261. compatible = "atmel,at91rm9200-gpio";
  262. reg = <0xfffff800 0x200>;
  263. interrupts = <4 4 1>;
  264. #gpio-cells = <2>;
  265. gpio-controller;
  266. interrupt-controller;
  267. #interrupt-cells = <2>;
  268. };
  269. pioE: gpio@fffffa00 {
  270. compatible = "atmel,at91rm9200-gpio";
  271. reg = <0xfffffa00 0x200>;
  272. interrupts = <4 4 1>;
  273. #gpio-cells = <2>;
  274. gpio-controller;
  275. interrupt-controller;
  276. #interrupt-cells = <2>;
  277. };
  278. };
  279. dbgu: serial@ffffee00 {
  280. compatible = "atmel,at91sam9260-usart";
  281. reg = <0xffffee00 0x200>;
  282. interrupts = <1 4 7>;
  283. pinctrl-names = "default";
  284. pinctrl-0 = <&pinctrl_dbgu>;
  285. status = "disabled";
  286. };
  287. usart0: serial@fff8c000 {
  288. compatible = "atmel,at91sam9260-usart";
  289. reg = <0xfff8c000 0x200>;
  290. interrupts = <7 4 5>;
  291. atmel,use-dma-rx;
  292. atmel,use-dma-tx;
  293. pinctrl-names = "default";
  294. pinctrl-0 = <&pinctrl_usart0>;
  295. status = "disabled";
  296. };
  297. usart1: serial@fff90000 {
  298. compatible = "atmel,at91sam9260-usart";
  299. reg = <0xfff90000 0x200>;
  300. interrupts = <8 4 5>;
  301. atmel,use-dma-rx;
  302. atmel,use-dma-tx;
  303. pinctrl-names = "default";
  304. pinctrl-0 = <&pinctrl_usart1>;
  305. status = "disabled";
  306. };
  307. usart2: serial@fff94000 {
  308. compatible = "atmel,at91sam9260-usart";
  309. reg = <0xfff94000 0x200>;
  310. interrupts = <9 4 5>;
  311. atmel,use-dma-rx;
  312. atmel,use-dma-tx;
  313. pinctrl-names = "default";
  314. pinctrl-0 = <&pinctrl_usart2>;
  315. status = "disabled";
  316. };
  317. macb0: ethernet@fffbc000 {
  318. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  319. reg = <0xfffbc000 0x100>;
  320. interrupts = <21 4 3>;
  321. pinctrl-names = "default";
  322. pinctrl-0 = <&pinctrl_macb_rmii>;
  323. status = "disabled";
  324. };
  325. usb1: gadget@fff78000 {
  326. compatible = "atmel,at91rm9200-udc";
  327. reg = <0xfff78000 0x4000>;
  328. interrupts = <24 4 2>;
  329. status = "disabled";
  330. };
  331. i2c0: i2c@fff88000 {
  332. compatible = "atmel,at91sam9263-i2c";
  333. reg = <0xfff88000 0x100>;
  334. interrupts = <13 4 6>;
  335. #address-cells = <1>;
  336. #size-cells = <0>;
  337. status = "disabled";
  338. };
  339. mmc0: mmc@fff80000 {
  340. compatible = "atmel,hsmci";
  341. reg = <0xfff80000 0x600>;
  342. interrupts = <10 4 0>;
  343. #address-cells = <1>;
  344. #size-cells = <0>;
  345. status = "disabled";
  346. };
  347. mmc1: mmc@fff84000 {
  348. compatible = "atmel,hsmci";
  349. reg = <0xfff84000 0x600>;
  350. interrupts = <11 4 0>;
  351. #address-cells = <1>;
  352. #size-cells = <0>;
  353. status = "disabled";
  354. };
  355. watchdog@fffffd40 {
  356. compatible = "atmel,at91sam9260-wdt";
  357. reg = <0xfffffd40 0x10>;
  358. status = "disabled";
  359. };
  360. };
  361. nand0: nand@40000000 {
  362. compatible = "atmel,at91rm9200-nand";
  363. #address-cells = <1>;
  364. #size-cells = <1>;
  365. reg = <0x40000000 0x10000000
  366. 0xffffe000 0x200
  367. >;
  368. atmel,nand-addr-offset = <21>;
  369. atmel,nand-cmd-offset = <22>;
  370. pinctrl-names = "default";
  371. pinctrl-0 = <&pinctrl_nand>;
  372. gpios = <&pioA 22 0
  373. &pioD 15 0
  374. 0
  375. >;
  376. status = "disabled";
  377. };
  378. usb0: ohci@00a00000 {
  379. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  380. reg = <0x00a00000 0x100000>;
  381. interrupts = <29 4 2>;
  382. status = "disabled";
  383. };
  384. };
  385. i2c@0 {
  386. compatible = "i2c-gpio";
  387. gpios = <&pioB 4 0 /* sda */
  388. &pioB 5 0 /* scl */
  389. >;
  390. i2c-gpio,sda-open-drain;
  391. i2c-gpio,scl-open-drain;
  392. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  393. #address-cells = <1>;
  394. #size-cells = <0>;
  395. status = "disabled";
  396. };
  397. };