at91sam9260.dtsi 12 KB

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  1. /*
  2. * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
  3. *
  4. * Copyright (C) 2011 Atmel,
  5. * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
  6. * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  7. *
  8. * Licensed under GPLv2 or later.
  9. */
  10. /include/ "skeleton.dtsi"
  11. / {
  12. model = "Atmel AT91SAM9260 family SoC";
  13. compatible = "atmel,at91sam9260";
  14. interrupt-parent = <&aic>;
  15. aliases {
  16. serial0 = &dbgu;
  17. serial1 = &usart0;
  18. serial2 = &usart1;
  19. serial3 = &usart2;
  20. serial4 = &usart3;
  21. serial5 = &uart0;
  22. serial6 = &uart1;
  23. gpio0 = &pioA;
  24. gpio1 = &pioB;
  25. gpio2 = &pioC;
  26. tcb0 = &tcb0;
  27. tcb1 = &tcb1;
  28. i2c0 = &i2c0;
  29. };
  30. cpus {
  31. cpu@0 {
  32. compatible = "arm,arm926ejs";
  33. };
  34. };
  35. memory {
  36. reg = <0x20000000 0x04000000>;
  37. };
  38. ahb {
  39. compatible = "simple-bus";
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. ranges;
  43. apb {
  44. compatible = "simple-bus";
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. ranges;
  48. aic: interrupt-controller@fffff000 {
  49. #interrupt-cells = <3>;
  50. compatible = "atmel,at91rm9200-aic";
  51. interrupt-controller;
  52. reg = <0xfffff000 0x200>;
  53. atmel,external-irqs = <29 30 31>;
  54. };
  55. ramc0: ramc@ffffea00 {
  56. compatible = "atmel,at91sam9260-sdramc";
  57. reg = <0xffffea00 0x200>;
  58. };
  59. pmc: pmc@fffffc00 {
  60. compatible = "atmel,at91rm9200-pmc";
  61. reg = <0xfffffc00 0x100>;
  62. };
  63. rstc@fffffd00 {
  64. compatible = "atmel,at91sam9260-rstc";
  65. reg = <0xfffffd00 0x10>;
  66. };
  67. shdwc@fffffd10 {
  68. compatible = "atmel,at91sam9260-shdwc";
  69. reg = <0xfffffd10 0x10>;
  70. };
  71. pit: timer@fffffd30 {
  72. compatible = "atmel,at91sam9260-pit";
  73. reg = <0xfffffd30 0xf>;
  74. interrupts = <1 4 7>;
  75. };
  76. tcb0: timer@fffa0000 {
  77. compatible = "atmel,at91rm9200-tcb";
  78. reg = <0xfffa0000 0x100>;
  79. interrupts = <17 4 0 18 4 0 19 4 0>;
  80. };
  81. tcb1: timer@fffdc000 {
  82. compatible = "atmel,at91rm9200-tcb";
  83. reg = <0xfffdc000 0x100>;
  84. interrupts = <26 4 0 27 4 0 28 4 0>;
  85. };
  86. pinctrl@fffff400 {
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
  90. ranges = <0xfffff400 0xfffff400 0x600>;
  91. atmel,mux-mask = <
  92. /* A B */
  93. 0xffffffff 0xffc00c3b /* pioA */
  94. 0xffffffff 0x7fff3ccf /* pioB */
  95. 0xffffffff 0x007fffff /* pioC */
  96. >;
  97. /* shared pinctrl settings */
  98. dbgu {
  99. pinctrl_dbgu: dbgu-0 {
  100. atmel,pins =
  101. <1 14 0x1 0x0 /* PB14 periph A */
  102. 1 15 0x1 0x1>; /* PB15 periph with pullup */
  103. };
  104. };
  105. usart0 {
  106. pinctrl_usart0: usart0-0 {
  107. atmel,pins =
  108. <1 4 0x1 0x0 /* PB4 periph A */
  109. 1 5 0x1 0x0>; /* PB5 periph A */
  110. };
  111. pinctrl_usart0_rts: usart0_rts-0 {
  112. atmel,pins =
  113. <1 26 0x1 0x0>; /* PB26 periph A */
  114. };
  115. pinctrl_usart0_cts: usart0_cts-0 {
  116. atmel,pins =
  117. <1 27 0x1 0x0>; /* PB27 periph A */
  118. };
  119. pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
  120. atmel,pins =
  121. <1 24 0x1 0x0 /* PB24 periph A */
  122. 1 22 0x1 0x0>; /* PB22 periph A */
  123. };
  124. pinctrl_usart0_dcd: usart0_dcd-0 {
  125. atmel,pins =
  126. <1 23 0x1 0x0>; /* PB23 periph A */
  127. };
  128. pinctrl_usart0_ri: usart0_ri-0 {
  129. atmel,pins =
  130. <1 25 0x1 0x0>; /* PB25 periph A */
  131. };
  132. };
  133. usart1 {
  134. pinctrl_usart1: usart1-0 {
  135. atmel,pins =
  136. <2 6 0x1 0x1 /* PB6 periph A with pullup */
  137. 2 7 0x1 0x0>; /* PB7 periph A */
  138. };
  139. pinctrl_usart1_rts: usart1_rts-0 {
  140. atmel,pins =
  141. <1 28 0x1 0x0>; /* PB28 periph A */
  142. };
  143. pinctrl_usart1_cts: usart1_cts-0 {
  144. atmel,pins =
  145. <1 29 0x1 0x0>; /* PB29 periph A */
  146. };
  147. };
  148. usart2 {
  149. pinctrl_usart2: usart2-0 {
  150. atmel,pins =
  151. <1 8 0x1 0x1 /* PB8 periph A with pullup */
  152. 1 9 0x1 0x0>; /* PB9 periph A */
  153. };
  154. pinctrl_usart2_rts: usart2_rts-0 {
  155. atmel,pins =
  156. <0 4 0x1 0x0>; /* PA4 periph A */
  157. };
  158. pinctrl_usart2_cts: usart2_cts-0 {
  159. atmel,pins =
  160. <0 5 0x1 0x0>; /* PA5 periph A */
  161. };
  162. };
  163. usart3 {
  164. pinctrl_usart3: usart3-0 {
  165. atmel,pins =
  166. <2 10 0x1 0x1 /* PB10 periph A with pullup */
  167. 2 11 0x1 0x0>; /* PB11 periph A */
  168. };
  169. pinctrl_usart3_rts: usart3_rts-0 {
  170. atmel,pins =
  171. <3 8 0x2 0x0>; /* PB8 periph B */
  172. };
  173. pinctrl_usart3_cts: usart3_cts-0 {
  174. atmel,pins =
  175. <3 10 0x2 0x0>; /* PB10 periph B */
  176. };
  177. };
  178. uart0 {
  179. pinctrl_uart0: uart0-0 {
  180. atmel,pins =
  181. <0 31 0x2 0x1 /* PA31 periph B with pullup */
  182. 0 30 0x2 0x0>; /* PA30 periph B */
  183. };
  184. };
  185. uart1 {
  186. pinctrl_uart1: uart1-0 {
  187. atmel,pins =
  188. <2 12 0x1 0x1 /* PB12 periph A with pullup */
  189. 2 13 0x1 0x0>; /* PB13 periph A */
  190. };
  191. };
  192. nand {
  193. pinctrl_nand: nand-0 {
  194. atmel,pins =
  195. <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
  196. 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
  197. };
  198. };
  199. macb {
  200. pinctrl_macb_rmii: macb_rmii-0 {
  201. atmel,pins =
  202. <0 12 0x1 0x0 /* PA12 periph A */
  203. 0 13 0x1 0x0 /* PA13 periph A */
  204. 0 14 0x1 0x0 /* PA14 periph A */
  205. 0 15 0x1 0x0 /* PA15 periph A */
  206. 0 16 0x1 0x0 /* PA16 periph A */
  207. 0 17 0x1 0x0 /* PA17 periph A */
  208. 0 18 0x1 0x0 /* PA18 periph A */
  209. 0 19 0x1 0x0 /* PA19 periph A */
  210. 0 20 0x1 0x0 /* PA20 periph A */
  211. 0 21 0x1 0x0>; /* PA21 periph A */
  212. };
  213. pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
  214. atmel,pins =
  215. <0 22 0x2 0x0 /* PA22 periph B */
  216. 0 23 0x2 0x0 /* PA23 periph B */
  217. 0 24 0x2 0x0 /* PA24 periph B */
  218. 0 25 0x2 0x0 /* PA25 periph B */
  219. 0 26 0x2 0x0 /* PA26 periph B */
  220. 0 27 0x2 0x0 /* PA27 periph B */
  221. 0 28 0x2 0x0 /* PA28 periph B */
  222. 0 29 0x2 0x0>; /* PA29 periph B */
  223. };
  224. pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
  225. atmel,pins =
  226. <0 10 0x2 0x0 /* PA10 periph B */
  227. 0 11 0x2 0x0 /* PA11 periph B */
  228. 0 24 0x2 0x0 /* PA24 periph B */
  229. 0 25 0x2 0x0 /* PA25 periph B */
  230. 0 26 0x2 0x0 /* PA26 periph B */
  231. 0 27 0x2 0x0 /* PA27 periph B */
  232. 0 28 0x2 0x0 /* PA28 periph B */
  233. 0 29 0x2 0x0>; /* PA29 periph B */
  234. };
  235. };
  236. mmc0 {
  237. pinctrl_mmc0_clk: mmc0_clk-0 {
  238. atmel,pins =
  239. <0 8 0x1 0x0>; /* PA8 periph A */
  240. };
  241. pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
  242. atmel,pins =
  243. <0 7 0x1 0x1 /* PA7 periph A with pullup */
  244. 0 6 0x1 0x1>; /* PA6 periph A with pullup */
  245. };
  246. pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
  247. atmel,pins =
  248. <0 9 0x1 0x1 /* PA9 periph A with pullup */
  249. 0 10 0x1 0x1 /* PA10 periph A with pullup */
  250. 0 11 0x1 0x1>; /* PA11 periph A with pullup */
  251. };
  252. pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
  253. atmel,pins =
  254. <0 1 0x2 0x1 /* PA1 periph B with pullup */
  255. 0 0 0x2 0x1>; /* PA0 periph B with pullup */
  256. };
  257. pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
  258. atmel,pins =
  259. <0 5 0x2 0x1 /* PA5 periph B with pullup */
  260. 0 4 0x2 0x1 /* PA4 periph B with pullup */
  261. 0 3 0x2 0x1>; /* PA3 periph B with pullup */
  262. };
  263. };
  264. pioA: gpio@fffff400 {
  265. compatible = "atmel,at91rm9200-gpio";
  266. reg = <0xfffff400 0x200>;
  267. interrupts = <2 4 1>;
  268. #gpio-cells = <2>;
  269. gpio-controller;
  270. interrupt-controller;
  271. #interrupt-cells = <2>;
  272. };
  273. pioB: gpio@fffff600 {
  274. compatible = "atmel,at91rm9200-gpio";
  275. reg = <0xfffff600 0x200>;
  276. interrupts = <3 4 1>;
  277. #gpio-cells = <2>;
  278. gpio-controller;
  279. interrupt-controller;
  280. #interrupt-cells = <2>;
  281. };
  282. pioC: gpio@fffff800 {
  283. compatible = "atmel,at91rm9200-gpio";
  284. reg = <0xfffff800 0x200>;
  285. interrupts = <4 4 1>;
  286. #gpio-cells = <2>;
  287. gpio-controller;
  288. interrupt-controller;
  289. #interrupt-cells = <2>;
  290. };
  291. };
  292. dbgu: serial@fffff200 {
  293. compatible = "atmel,at91sam9260-usart";
  294. reg = <0xfffff200 0x200>;
  295. interrupts = <1 4 7>;
  296. pinctrl-names = "default";
  297. pinctrl-0 = <&pinctrl_dbgu>;
  298. status = "disabled";
  299. };
  300. usart0: serial@fffb0000 {
  301. compatible = "atmel,at91sam9260-usart";
  302. reg = <0xfffb0000 0x200>;
  303. interrupts = <6 4 5>;
  304. atmel,use-dma-rx;
  305. atmel,use-dma-tx;
  306. pinctrl-names = "default";
  307. pinctrl-0 = <&pinctrl_usart0>;
  308. status = "disabled";
  309. };
  310. usart1: serial@fffb4000 {
  311. compatible = "atmel,at91sam9260-usart";
  312. reg = <0xfffb4000 0x200>;
  313. interrupts = <7 4 5>;
  314. atmel,use-dma-rx;
  315. atmel,use-dma-tx;
  316. pinctrl-names = "default";
  317. pinctrl-0 = <&pinctrl_usart1>;
  318. status = "disabled";
  319. };
  320. usart2: serial@fffb8000 {
  321. compatible = "atmel,at91sam9260-usart";
  322. reg = <0xfffb8000 0x200>;
  323. interrupts = <8 4 5>;
  324. atmel,use-dma-rx;
  325. atmel,use-dma-tx;
  326. pinctrl-names = "default";
  327. pinctrl-0 = <&pinctrl_usart2>;
  328. status = "disabled";
  329. };
  330. usart3: serial@fffd0000 {
  331. compatible = "atmel,at91sam9260-usart";
  332. reg = <0xfffd0000 0x200>;
  333. interrupts = <23 4 5>;
  334. atmel,use-dma-rx;
  335. atmel,use-dma-tx;
  336. pinctrl-names = "default";
  337. pinctrl-0 = <&pinctrl_usart3>;
  338. status = "disabled";
  339. };
  340. uart0: serial@fffd4000 {
  341. compatible = "atmel,at91sam9260-usart";
  342. reg = <0xfffd4000 0x200>;
  343. interrupts = <24 4 5>;
  344. atmel,use-dma-rx;
  345. atmel,use-dma-tx;
  346. pinctrl-names = "default";
  347. pinctrl-0 = <&pinctrl_uart0>;
  348. status = "disabled";
  349. };
  350. uart1: serial@fffd8000 {
  351. compatible = "atmel,at91sam9260-usart";
  352. reg = <0xfffd8000 0x200>;
  353. interrupts = <25 4 5>;
  354. atmel,use-dma-rx;
  355. atmel,use-dma-tx;
  356. pinctrl-names = "default";
  357. pinctrl-0 = <&pinctrl_uart1>;
  358. status = "disabled";
  359. };
  360. macb0: ethernet@fffc4000 {
  361. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  362. reg = <0xfffc4000 0x100>;
  363. interrupts = <21 4 3>;
  364. pinctrl-names = "default";
  365. pinctrl-0 = <&pinctrl_macb_rmii>;
  366. status = "disabled";
  367. };
  368. usb1: gadget@fffa4000 {
  369. compatible = "atmel,at91rm9200-udc";
  370. reg = <0xfffa4000 0x4000>;
  371. interrupts = <10 4 2>;
  372. status = "disabled";
  373. };
  374. i2c0: i2c@fffac000 {
  375. compatible = "atmel,at91sam9260-i2c";
  376. reg = <0xfffac000 0x100>;
  377. interrupts = <11 4 6>;
  378. #address-cells = <1>;
  379. #size-cells = <0>;
  380. status = "disabled";
  381. };
  382. mmc0: mmc@fffa8000 {
  383. compatible = "atmel,hsmci";
  384. reg = <0xfffa8000 0x600>;
  385. interrupts = <9 4 0>;
  386. #address-cells = <1>;
  387. #size-cells = <0>;
  388. status = "disabled";
  389. };
  390. adc0: adc@fffe0000 {
  391. compatible = "atmel,at91sam9260-adc";
  392. reg = <0xfffe0000 0x100>;
  393. interrupts = <5 4 0>;
  394. atmel,adc-use-external-triggers;
  395. atmel,adc-channels-used = <0xf>;
  396. atmel,adc-vref = <3300>;
  397. atmel,adc-num-channels = <4>;
  398. atmel,adc-startup-time = <15>;
  399. atmel,adc-channel-base = <0x30>;
  400. atmel,adc-drdy-mask = <0x10000>;
  401. atmel,adc-status-register = <0x1c>;
  402. atmel,adc-trigger-register = <0x04>;
  403. trigger@0 {
  404. trigger-name = "timer-counter-0";
  405. trigger-value = <0x1>;
  406. };
  407. trigger@1 {
  408. trigger-name = "timer-counter-1";
  409. trigger-value = <0x3>;
  410. };
  411. trigger@2 {
  412. trigger-name = "timer-counter-2";
  413. trigger-value = <0x5>;
  414. };
  415. trigger@3 {
  416. trigger-name = "external";
  417. trigger-value = <0x13>;
  418. trigger-external;
  419. };
  420. };
  421. watchdog@fffffd40 {
  422. compatible = "atmel,at91sam9260-wdt";
  423. reg = <0xfffffd40 0x10>;
  424. status = "disabled";
  425. };
  426. };
  427. nand0: nand@40000000 {
  428. compatible = "atmel,at91rm9200-nand";
  429. #address-cells = <1>;
  430. #size-cells = <1>;
  431. reg = <0x40000000 0x10000000
  432. 0xffffe800 0x200
  433. >;
  434. atmel,nand-addr-offset = <21>;
  435. atmel,nand-cmd-offset = <22>;
  436. pinctrl-names = "default";
  437. pinctrl-0 = <&pinctrl_nand>;
  438. gpios = <&pioC 13 0
  439. &pioC 14 0
  440. 0
  441. >;
  442. status = "disabled";
  443. };
  444. usb0: ohci@00500000 {
  445. compatible = "atmel,at91rm9200-ohci", "usb-ohci";
  446. reg = <0x00500000 0x100000>;
  447. interrupts = <20 4 2>;
  448. status = "disabled";
  449. };
  450. };
  451. i2c@0 {
  452. compatible = "i2c-gpio";
  453. gpios = <&pioA 23 0 /* sda */
  454. &pioA 24 0 /* scl */
  455. >;
  456. i2c-gpio,sda-open-drain;
  457. i2c-gpio,scl-open-drain;
  458. i2c-gpio,delay-us = <2>; /* ~100 kHz */
  459. #address-cells = <1>;
  460. #size-cells = <0>;
  461. status = "disabled";
  462. };
  463. };