netxen_nic_init.c 39 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587
  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. struct crb_addr_pair {
  35. u32 addr;
  36. u32 data;
  37. };
  38. #define NETXEN_MAX_CRB_XFORM 60
  39. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  40. #define NETXEN_ADDR_ERROR (0xffffffff)
  41. #define crb_addr_transform(name) \
  42. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  43. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  44. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  45. static void
  46. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  47. struct nx_host_rds_ring *rds_ring);
  48. static void crb_addr_transform_setup(void)
  49. {
  50. crb_addr_transform(XDMA);
  51. crb_addr_transform(TIMR);
  52. crb_addr_transform(SRE);
  53. crb_addr_transform(SQN3);
  54. crb_addr_transform(SQN2);
  55. crb_addr_transform(SQN1);
  56. crb_addr_transform(SQN0);
  57. crb_addr_transform(SQS3);
  58. crb_addr_transform(SQS2);
  59. crb_addr_transform(SQS1);
  60. crb_addr_transform(SQS0);
  61. crb_addr_transform(RPMX7);
  62. crb_addr_transform(RPMX6);
  63. crb_addr_transform(RPMX5);
  64. crb_addr_transform(RPMX4);
  65. crb_addr_transform(RPMX3);
  66. crb_addr_transform(RPMX2);
  67. crb_addr_transform(RPMX1);
  68. crb_addr_transform(RPMX0);
  69. crb_addr_transform(ROMUSB);
  70. crb_addr_transform(SN);
  71. crb_addr_transform(QMN);
  72. crb_addr_transform(QMS);
  73. crb_addr_transform(PGNI);
  74. crb_addr_transform(PGND);
  75. crb_addr_transform(PGN3);
  76. crb_addr_transform(PGN2);
  77. crb_addr_transform(PGN1);
  78. crb_addr_transform(PGN0);
  79. crb_addr_transform(PGSI);
  80. crb_addr_transform(PGSD);
  81. crb_addr_transform(PGS3);
  82. crb_addr_transform(PGS2);
  83. crb_addr_transform(PGS1);
  84. crb_addr_transform(PGS0);
  85. crb_addr_transform(PS);
  86. crb_addr_transform(PH);
  87. crb_addr_transform(NIU);
  88. crb_addr_transform(I2Q);
  89. crb_addr_transform(EG);
  90. crb_addr_transform(MN);
  91. crb_addr_transform(MS);
  92. crb_addr_transform(CAS2);
  93. crb_addr_transform(CAS1);
  94. crb_addr_transform(CAS0);
  95. crb_addr_transform(CAM);
  96. crb_addr_transform(C2C1);
  97. crb_addr_transform(C2C0);
  98. crb_addr_transform(SMB);
  99. crb_addr_transform(OCM0);
  100. crb_addr_transform(I2C0);
  101. }
  102. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  103. {
  104. struct netxen_recv_context *recv_ctx;
  105. struct nx_host_rds_ring *rds_ring;
  106. struct netxen_rx_buffer *rx_buf;
  107. int i, ring;
  108. recv_ctx = &adapter->recv_ctx;
  109. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  110. rds_ring = &recv_ctx->rds_rings[ring];
  111. for (i = 0; i < rds_ring->num_desc; ++i) {
  112. rx_buf = &(rds_ring->rx_buf_arr[i]);
  113. if (rx_buf->state == NETXEN_BUFFER_FREE)
  114. continue;
  115. pci_unmap_single(adapter->pdev,
  116. rx_buf->dma,
  117. rds_ring->dma_size,
  118. PCI_DMA_FROMDEVICE);
  119. if (rx_buf->skb != NULL)
  120. dev_kfree_skb_any(rx_buf->skb);
  121. }
  122. }
  123. }
  124. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  125. {
  126. struct netxen_cmd_buffer *cmd_buf;
  127. struct netxen_skb_frag *buffrag;
  128. int i, j;
  129. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  130. cmd_buf = tx_ring->cmd_buf_arr;
  131. for (i = 0; i < tx_ring->num_desc; i++) {
  132. buffrag = cmd_buf->frag_array;
  133. if (buffrag->dma) {
  134. pci_unmap_single(adapter->pdev, buffrag->dma,
  135. buffrag->length, PCI_DMA_TODEVICE);
  136. buffrag->dma = 0ULL;
  137. }
  138. for (j = 0; j < cmd_buf->frag_count; j++) {
  139. buffrag++;
  140. if (buffrag->dma) {
  141. pci_unmap_page(adapter->pdev, buffrag->dma,
  142. buffrag->length,
  143. PCI_DMA_TODEVICE);
  144. buffrag->dma = 0ULL;
  145. }
  146. }
  147. if (cmd_buf->skb) {
  148. dev_kfree_skb_any(cmd_buf->skb);
  149. cmd_buf->skb = NULL;
  150. }
  151. cmd_buf++;
  152. }
  153. }
  154. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  155. {
  156. struct netxen_recv_context *recv_ctx;
  157. struct nx_host_rds_ring *rds_ring;
  158. struct nx_host_tx_ring *tx_ring;
  159. int ring;
  160. recv_ctx = &adapter->recv_ctx;
  161. if (recv_ctx->rds_rings == NULL)
  162. goto skip_rds;
  163. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  164. rds_ring = &recv_ctx->rds_rings[ring];
  165. vfree(rds_ring->rx_buf_arr);
  166. rds_ring->rx_buf_arr = NULL;
  167. }
  168. kfree(recv_ctx->rds_rings);
  169. skip_rds:
  170. if (adapter->tx_ring == NULL)
  171. return;
  172. tx_ring = adapter->tx_ring;
  173. vfree(tx_ring->cmd_buf_arr);
  174. }
  175. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  176. {
  177. struct netxen_recv_context *recv_ctx;
  178. struct nx_host_rds_ring *rds_ring;
  179. struct nx_host_sds_ring *sds_ring;
  180. struct nx_host_tx_ring *tx_ring;
  181. struct netxen_rx_buffer *rx_buf;
  182. int ring, i, size;
  183. struct netxen_cmd_buffer *cmd_buf_arr;
  184. struct net_device *netdev = adapter->netdev;
  185. struct pci_dev *pdev = adapter->pdev;
  186. size = sizeof(struct nx_host_tx_ring);
  187. tx_ring = kzalloc(size, GFP_KERNEL);
  188. if (tx_ring == NULL) {
  189. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  190. netdev->name);
  191. return -ENOMEM;
  192. }
  193. adapter->tx_ring = tx_ring;
  194. tx_ring->num_desc = adapter->num_txd;
  195. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  196. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  197. if (cmd_buf_arr == NULL) {
  198. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  199. netdev->name);
  200. return -ENOMEM;
  201. }
  202. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  203. tx_ring->cmd_buf_arr = cmd_buf_arr;
  204. recv_ctx = &adapter->recv_ctx;
  205. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  206. rds_ring = kzalloc(size, GFP_KERNEL);
  207. if (rds_ring == NULL) {
  208. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  209. netdev->name);
  210. return -ENOMEM;
  211. }
  212. recv_ctx->rds_rings = rds_ring;
  213. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  214. rds_ring = &recv_ctx->rds_rings[ring];
  215. switch (ring) {
  216. case RCV_RING_NORMAL:
  217. rds_ring->num_desc = adapter->num_rxd;
  218. if (adapter->ahw.cut_through) {
  219. rds_ring->dma_size =
  220. NX_CT_DEFAULT_RX_BUF_LEN;
  221. rds_ring->skb_size =
  222. NX_CT_DEFAULT_RX_BUF_LEN;
  223. } else {
  224. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  225. rds_ring->dma_size =
  226. NX_P3_RX_BUF_MAX_LEN;
  227. else
  228. rds_ring->dma_size =
  229. NX_P2_RX_BUF_MAX_LEN;
  230. rds_ring->skb_size =
  231. rds_ring->dma_size + NET_IP_ALIGN;
  232. }
  233. break;
  234. case RCV_RING_JUMBO:
  235. rds_ring->num_desc = adapter->num_jumbo_rxd;
  236. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  237. rds_ring->dma_size =
  238. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  239. else
  240. rds_ring->dma_size =
  241. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  242. if (adapter->capabilities & NX_CAP0_HW_LRO)
  243. rds_ring->dma_size += NX_LRO_BUFFER_EXTRA;
  244. rds_ring->skb_size =
  245. rds_ring->dma_size + NET_IP_ALIGN;
  246. break;
  247. case RCV_RING_LRO:
  248. rds_ring->num_desc = adapter->num_lro_rxd;
  249. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  250. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  251. break;
  252. }
  253. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  254. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  255. if (rds_ring->rx_buf_arr == NULL) {
  256. printk(KERN_ERR "%s: Failed to allocate "
  257. "rx buffer ring %d\n",
  258. netdev->name, ring);
  259. /* free whatever was already allocated */
  260. goto err_out;
  261. }
  262. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  263. INIT_LIST_HEAD(&rds_ring->free_list);
  264. /*
  265. * Now go through all of them, set reference handles
  266. * and put them in the queues.
  267. */
  268. rx_buf = rds_ring->rx_buf_arr;
  269. for (i = 0; i < rds_ring->num_desc; i++) {
  270. list_add_tail(&rx_buf->list,
  271. &rds_ring->free_list);
  272. rx_buf->ref_handle = i;
  273. rx_buf->state = NETXEN_BUFFER_FREE;
  274. rx_buf++;
  275. }
  276. spin_lock_init(&rds_ring->lock);
  277. }
  278. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  279. sds_ring = &recv_ctx->sds_rings[ring];
  280. sds_ring->irq = adapter->msix_entries[ring].vector;
  281. sds_ring->adapter = adapter;
  282. sds_ring->num_desc = adapter->num_rxd;
  283. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  284. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  285. }
  286. return 0;
  287. err_out:
  288. netxen_free_sw_resources(adapter);
  289. return -ENOMEM;
  290. }
  291. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  292. {
  293. adapter->init_port = netxen_niu_xg_init_port;
  294. adapter->stop_port = netxen_niu_disable_xg_port;
  295. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  296. adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
  297. adapter->set_multi = netxen_p2_nic_set_multi;
  298. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  299. adapter->set_promisc = netxen_p2_nic_set_promisc;
  300. } else {
  301. adapter->set_mtu = nx_fw_cmd_set_mtu;
  302. adapter->set_promisc = netxen_p3_nic_set_promisc;
  303. adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
  304. adapter->set_multi = netxen_p3_nic_set_multi;
  305. if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
  306. adapter->phy_read = nx_fw_cmd_query_phy;
  307. adapter->phy_write = nx_fw_cmd_set_phy;
  308. }
  309. }
  310. }
  311. /*
  312. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  313. * address to external PCI CRB address.
  314. */
  315. static u32 netxen_decode_crb_addr(u32 addr)
  316. {
  317. int i;
  318. u32 base_addr, offset, pci_base;
  319. crb_addr_transform_setup();
  320. pci_base = NETXEN_ADDR_ERROR;
  321. base_addr = addr & 0xfff00000;
  322. offset = addr & 0x000fffff;
  323. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  324. if (crb_addr_xform[i] == base_addr) {
  325. pci_base = i << 20;
  326. break;
  327. }
  328. }
  329. if (pci_base == NETXEN_ADDR_ERROR)
  330. return pci_base;
  331. else
  332. return (pci_base + offset);
  333. }
  334. #define NETXEN_MAX_ROM_WAIT_USEC 100
  335. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  336. {
  337. long timeout = 0;
  338. long done = 0;
  339. cond_resched();
  340. while (done == 0) {
  341. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  342. done &= 2;
  343. if (++timeout >= NETXEN_MAX_ROM_WAIT_USEC) {
  344. dev_err(&adapter->pdev->dev,
  345. "Timeout reached waiting for rom done");
  346. return -EIO;
  347. }
  348. udelay(1);
  349. }
  350. return 0;
  351. }
  352. static int do_rom_fast_read(struct netxen_adapter *adapter,
  353. int addr, int *valp)
  354. {
  355. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  356. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  357. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  358. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  359. if (netxen_wait_rom_done(adapter)) {
  360. printk("Error waiting for rom done\n");
  361. return -EIO;
  362. }
  363. /* reset abyte_cnt and dummy_byte_cnt */
  364. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  365. udelay(10);
  366. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  367. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  368. return 0;
  369. }
  370. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  371. u8 *bytes, size_t size)
  372. {
  373. int addridx;
  374. int ret = 0;
  375. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  376. int v;
  377. ret = do_rom_fast_read(adapter, addridx, &v);
  378. if (ret != 0)
  379. break;
  380. *(__le32 *)bytes = cpu_to_le32(v);
  381. bytes += 4;
  382. }
  383. return ret;
  384. }
  385. int
  386. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  387. u8 *bytes, size_t size)
  388. {
  389. int ret;
  390. ret = netxen_rom_lock(adapter);
  391. if (ret < 0)
  392. return ret;
  393. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  394. netxen_rom_unlock(adapter);
  395. return ret;
  396. }
  397. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  398. {
  399. int ret;
  400. if (netxen_rom_lock(adapter) != 0)
  401. return -EIO;
  402. ret = do_rom_fast_read(adapter, addr, valp);
  403. netxen_rom_unlock(adapter);
  404. return ret;
  405. }
  406. #define NETXEN_BOARDTYPE 0x4008
  407. #define NETXEN_BOARDNUM 0x400c
  408. #define NETXEN_CHIPNUM 0x4010
  409. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  410. {
  411. int addr, val;
  412. int i, n, init_delay = 0;
  413. struct crb_addr_pair *buf;
  414. unsigned offset;
  415. u32 off;
  416. /* resetall */
  417. netxen_rom_lock(adapter);
  418. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  419. netxen_rom_unlock(adapter);
  420. if (verbose) {
  421. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  422. printk("P2 ROM board type: 0x%08x\n", val);
  423. else
  424. printk("Could not read board type\n");
  425. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  426. printk("P2 ROM board num: 0x%08x\n", val);
  427. else
  428. printk("Could not read board number\n");
  429. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  430. printk("P2 ROM chip num: 0x%08x\n", val);
  431. else
  432. printk("Could not read chip number\n");
  433. }
  434. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  435. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  436. (n != 0xcafecafe) ||
  437. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  438. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  439. "n: %08x\n", netxen_nic_driver_name, n);
  440. return -EIO;
  441. }
  442. offset = n & 0xffffU;
  443. n = (n >> 16) & 0xffffU;
  444. } else {
  445. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  446. !(n & 0x80000000)) {
  447. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  448. "n: %08x\n", netxen_nic_driver_name, n);
  449. return -EIO;
  450. }
  451. offset = 1;
  452. n &= ~0x80000000;
  453. }
  454. if (n < 1024) {
  455. if (verbose)
  456. printk(KERN_DEBUG "%s: %d CRB init values found"
  457. " in ROM.\n", netxen_nic_driver_name, n);
  458. } else {
  459. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  460. " initialized.\n", __func__, n);
  461. return -EIO;
  462. }
  463. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  464. if (buf == NULL) {
  465. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  466. netxen_nic_driver_name);
  467. return -ENOMEM;
  468. }
  469. for (i = 0; i < n; i++) {
  470. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  471. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  472. kfree(buf);
  473. return -EIO;
  474. }
  475. buf[i].addr = addr;
  476. buf[i].data = val;
  477. if (verbose)
  478. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  479. netxen_nic_driver_name,
  480. (u32)netxen_decode_crb_addr(addr), val);
  481. }
  482. for (i = 0; i < n; i++) {
  483. off = netxen_decode_crb_addr(buf[i].addr);
  484. if (off == NETXEN_ADDR_ERROR) {
  485. printk(KERN_ERR"CRB init value out of range %x\n",
  486. buf[i].addr);
  487. continue;
  488. }
  489. off += NETXEN_PCI_CRBSPACE;
  490. /* skipping cold reboot MAGIC */
  491. if (off == NETXEN_CAM_RAM(0x1fc))
  492. continue;
  493. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  494. /* do not reset PCI */
  495. if (off == (ROMUSB_GLB + 0xbc))
  496. continue;
  497. if (off == (ROMUSB_GLB + 0xa8))
  498. continue;
  499. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  500. continue;
  501. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  502. continue;
  503. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  504. continue;
  505. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  506. buf[i].data = 0x1020;
  507. /* skip the function enable register */
  508. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  509. continue;
  510. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  511. continue;
  512. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  513. continue;
  514. }
  515. if (off == NETXEN_ADDR_ERROR) {
  516. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  517. netxen_nic_driver_name, buf[i].addr);
  518. continue;
  519. }
  520. init_delay = 1;
  521. /* After writing this register, HW needs time for CRB */
  522. /* to quiet down (else crb_window returns 0xffffffff) */
  523. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  524. init_delay = 1000;
  525. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  526. /* hold xdma in reset also */
  527. buf[i].data = NETXEN_NIC_XDMA_RESET;
  528. buf[i].data = 0x8000ff;
  529. }
  530. }
  531. NXWR32(adapter, off, buf[i].data);
  532. msleep(init_delay);
  533. }
  534. kfree(buf);
  535. /* disable_peg_cache_all */
  536. /* unreset_net_cache */
  537. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  538. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  539. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  540. }
  541. /* p2dn replyCount */
  542. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  543. /* disable_peg_cache 0 */
  544. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  545. /* disable_peg_cache 1 */
  546. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  547. /* peg_clr_all */
  548. /* peg_clr 0 */
  549. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  550. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  551. /* peg_clr 1 */
  552. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  553. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  554. /* peg_clr 2 */
  555. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  556. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  557. /* peg_clr 3 */
  558. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  559. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  560. return 0;
  561. }
  562. int
  563. netxen_need_fw_reset(struct netxen_adapter *adapter)
  564. {
  565. u32 count, old_count;
  566. u32 val, version, major, minor, build;
  567. int i, timeout;
  568. u8 fw_type;
  569. /* NX2031 firmware doesn't support heartbit */
  570. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  571. return 1;
  572. /* last attempt had failed */
  573. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  574. return 1;
  575. old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  576. for (i = 0; i < 10; i++) {
  577. timeout = msleep_interruptible(200);
  578. if (timeout) {
  579. NXWR32(adapter, CRB_CMDPEG_STATE,
  580. PHAN_INITIALIZE_FAILED);
  581. return -EINTR;
  582. }
  583. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  584. if (count != old_count)
  585. break;
  586. }
  587. /* firmware is dead */
  588. if (count == old_count)
  589. return 1;
  590. /* check if we have got newer or different file firmware */
  591. if (adapter->fw) {
  592. const struct firmware *fw = adapter->fw;
  593. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  594. version = NETXEN_DECODE_VERSION(val);
  595. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  596. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  597. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  598. if (version > NETXEN_VERSION_CODE(major, minor, build))
  599. return 1;
  600. if (version == NETXEN_VERSION_CODE(major, minor, build)) {
  601. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  602. fw_type = (val & 0x4) ?
  603. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  604. if (adapter->fw_type != fw_type)
  605. return 1;
  606. }
  607. }
  608. return 0;
  609. }
  610. static char *fw_name[] = {
  611. "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
  612. };
  613. int
  614. netxen_load_firmware(struct netxen_adapter *adapter)
  615. {
  616. u64 *ptr64;
  617. u32 i, flashaddr, size;
  618. const struct firmware *fw = adapter->fw;
  619. struct pci_dev *pdev = adapter->pdev;
  620. dev_info(&pdev->dev, "loading firmware from %s\n",
  621. fw_name[adapter->fw_type]);
  622. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  623. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  624. if (fw) {
  625. __le64 data;
  626. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  627. ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
  628. flashaddr = NETXEN_BOOTLD_START;
  629. for (i = 0; i < size; i++) {
  630. data = cpu_to_le64(ptr64[i]);
  631. adapter->pci_mem_write(adapter, flashaddr, &data, 8);
  632. flashaddr += 8;
  633. }
  634. size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
  635. size = (__force u32)cpu_to_le32(size) / 8;
  636. ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
  637. flashaddr = NETXEN_IMAGE_START;
  638. for (i = 0; i < size; i++) {
  639. data = cpu_to_le64(ptr64[i]);
  640. if (adapter->pci_mem_write(adapter,
  641. flashaddr, &data, 8))
  642. return -EIO;
  643. flashaddr += 8;
  644. }
  645. } else {
  646. u32 data;
  647. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
  648. flashaddr = NETXEN_BOOTLD_START;
  649. for (i = 0; i < size; i++) {
  650. if (netxen_rom_fast_read(adapter,
  651. flashaddr, (int *)&data) != 0)
  652. return -EIO;
  653. if (adapter->pci_mem_write(adapter,
  654. flashaddr, &data, 4))
  655. return -EIO;
  656. flashaddr += 4;
  657. }
  658. }
  659. msleep(1);
  660. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  661. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  662. else {
  663. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  664. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  665. }
  666. return 0;
  667. }
  668. static int
  669. netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
  670. {
  671. __le32 val;
  672. u32 ver, min_ver, bios;
  673. struct pci_dev *pdev = adapter->pdev;
  674. const struct firmware *fw = adapter->fw;
  675. if (fw->size < NX_FW_MIN_SIZE)
  676. return -EINVAL;
  677. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  678. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  679. return -EINVAL;
  680. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  681. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  682. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  683. else
  684. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  685. ver = NETXEN_DECODE_VERSION(val);
  686. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  687. dev_err(&pdev->dev,
  688. "%s: firmware version %d.%d.%d unsupported\n",
  689. fwname, _major(ver), _minor(ver), _build(ver));
  690. return -EINVAL;
  691. }
  692. val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  693. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  694. if ((__force u32)val != bios) {
  695. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  696. fwname);
  697. return -EINVAL;
  698. }
  699. /* check if flashed firmware is newer */
  700. if (netxen_rom_fast_read(adapter,
  701. NX_FW_VERSION_OFFSET, (int *)&val))
  702. return -EIO;
  703. val = NETXEN_DECODE_VERSION(val);
  704. if (val > ver) {
  705. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  706. fwname);
  707. return -EINVAL;
  708. }
  709. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  710. return 0;
  711. }
  712. static int
  713. netxen_p3_has_mn(struct netxen_adapter *adapter)
  714. {
  715. u32 capability, flashed_ver;
  716. capability = 0;
  717. netxen_rom_fast_read(adapter,
  718. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  719. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  720. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  721. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  722. if (capability & NX_PEG_TUNE_MN_PRESENT)
  723. return 1;
  724. }
  725. return 0;
  726. }
  727. void netxen_request_firmware(struct netxen_adapter *adapter)
  728. {
  729. u8 fw_type;
  730. struct pci_dev *pdev = adapter->pdev;
  731. int rc = 0;
  732. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  733. fw_type = NX_P2_MN_ROMIMAGE;
  734. goto request_fw;
  735. }
  736. fw_type = netxen_p3_has_mn(adapter) ?
  737. NX_P3_MN_ROMIMAGE : NX_P3_CT_ROMIMAGE;
  738. request_fw:
  739. rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
  740. if (rc != 0) {
  741. if (fw_type == NX_P3_MN_ROMIMAGE) {
  742. msleep(1);
  743. fw_type = NX_P3_CT_ROMIMAGE;
  744. goto request_fw;
  745. }
  746. fw_type = NX_FLASH_ROMIMAGE;
  747. adapter->fw = NULL;
  748. goto done;
  749. }
  750. rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
  751. if (rc != 0) {
  752. release_firmware(adapter->fw);
  753. if (fw_type == NX_P3_MN_ROMIMAGE) {
  754. msleep(1);
  755. fw_type = NX_P3_CT_ROMIMAGE;
  756. goto request_fw;
  757. }
  758. fw_type = NX_FLASH_ROMIMAGE;
  759. adapter->fw = NULL;
  760. goto done;
  761. }
  762. done:
  763. adapter->fw_type = fw_type;
  764. }
  765. void
  766. netxen_release_firmware(struct netxen_adapter *adapter)
  767. {
  768. if (adapter->fw)
  769. release_firmware(adapter->fw);
  770. adapter->fw = NULL;
  771. }
  772. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  773. {
  774. u64 addr;
  775. u32 hi, lo;
  776. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  777. return 0;
  778. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  779. NETXEN_HOST_DUMMY_DMA_SIZE,
  780. &adapter->dummy_dma.phys_addr);
  781. if (adapter->dummy_dma.addr == NULL) {
  782. dev_err(&adapter->pdev->dev,
  783. "ERROR: Could not allocate dummy DMA memory\n");
  784. return -ENOMEM;
  785. }
  786. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  787. hi = (addr >> 32) & 0xffffffff;
  788. lo = addr & 0xffffffff;
  789. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  790. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  791. return 0;
  792. }
  793. /*
  794. * NetXen DMA watchdog control:
  795. *
  796. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  797. * Bit 1 : disable_request => 1 req disable dma watchdog
  798. * Bit 2 : enable_request => 1 req enable dma watchdog
  799. * Bit 3-31 : unused
  800. */
  801. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  802. {
  803. int i = 100;
  804. u32 ctrl;
  805. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  806. return;
  807. if (!adapter->dummy_dma.addr)
  808. return;
  809. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  810. if ((ctrl & 0x1) != 0) {
  811. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  812. while ((ctrl & 0x1) != 0) {
  813. msleep(50);
  814. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  815. if (--i == 0)
  816. break;
  817. };
  818. }
  819. if (i) {
  820. pci_free_consistent(adapter->pdev,
  821. NETXEN_HOST_DUMMY_DMA_SIZE,
  822. adapter->dummy_dma.addr,
  823. adapter->dummy_dma.phys_addr);
  824. adapter->dummy_dma.addr = NULL;
  825. } else
  826. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  827. }
  828. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  829. {
  830. u32 val = 0;
  831. int retries = 60;
  832. if (pegtune_val)
  833. return 0;
  834. do {
  835. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  836. switch (val) {
  837. case PHAN_INITIALIZE_COMPLETE:
  838. case PHAN_INITIALIZE_ACK:
  839. return 0;
  840. case PHAN_INITIALIZE_FAILED:
  841. goto out_err;
  842. default:
  843. break;
  844. }
  845. msleep(500);
  846. } while (--retries);
  847. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  848. out_err:
  849. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  850. return -EIO;
  851. }
  852. static int
  853. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  854. {
  855. u32 val = 0;
  856. int retries = 2000;
  857. do {
  858. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  859. if (val == PHAN_PEG_RCV_INITIALIZED)
  860. return 0;
  861. msleep(10);
  862. } while (--retries);
  863. if (!retries) {
  864. printk(KERN_ERR "Receive Peg initialization not "
  865. "complete, state: 0x%x.\n", val);
  866. return -EIO;
  867. }
  868. return 0;
  869. }
  870. int netxen_init_firmware(struct netxen_adapter *adapter)
  871. {
  872. int err;
  873. err = netxen_receive_peg_ready(adapter);
  874. if (err)
  875. return err;
  876. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  877. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  878. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  879. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  880. return err;
  881. }
  882. static void
  883. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  884. {
  885. u32 cable_OUI;
  886. u16 cable_len;
  887. u16 link_speed;
  888. u8 link_status, module, duplex, autoneg;
  889. struct net_device *netdev = adapter->netdev;
  890. adapter->has_link_events = 1;
  891. cable_OUI = msg->body[1] & 0xffffffff;
  892. cable_len = (msg->body[1] >> 32) & 0xffff;
  893. link_speed = (msg->body[1] >> 48) & 0xffff;
  894. link_status = msg->body[2] & 0xff;
  895. duplex = (msg->body[2] >> 16) & 0xff;
  896. autoneg = (msg->body[2] >> 24) & 0xff;
  897. module = (msg->body[2] >> 8) & 0xff;
  898. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  899. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  900. netdev->name, cable_OUI, cable_len);
  901. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  902. printk(KERN_INFO "%s: unsupported cable length %d\n",
  903. netdev->name, cable_len);
  904. }
  905. netxen_advert_link_change(adapter, link_status);
  906. /* update link parameters */
  907. if (duplex == LINKEVENT_FULL_DUPLEX)
  908. adapter->link_duplex = DUPLEX_FULL;
  909. else
  910. adapter->link_duplex = DUPLEX_HALF;
  911. adapter->module_type = module;
  912. adapter->link_autoneg = autoneg;
  913. adapter->link_speed = link_speed;
  914. }
  915. static void
  916. netxen_handle_fw_message(int desc_cnt, int index,
  917. struct nx_host_sds_ring *sds_ring)
  918. {
  919. nx_fw_msg_t msg;
  920. struct status_desc *desc;
  921. int i = 0, opcode;
  922. while (desc_cnt > 0 && i < 8) {
  923. desc = &sds_ring->desc_head[index];
  924. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  925. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  926. index = get_next_index(index, sds_ring->num_desc);
  927. desc_cnt--;
  928. }
  929. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  930. switch (opcode) {
  931. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  932. netxen_handle_linkevent(sds_ring->adapter, &msg);
  933. break;
  934. default:
  935. break;
  936. }
  937. }
  938. static int
  939. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  940. struct nx_host_rds_ring *rds_ring,
  941. struct netxen_rx_buffer *buffer)
  942. {
  943. struct sk_buff *skb;
  944. dma_addr_t dma;
  945. struct pci_dev *pdev = adapter->pdev;
  946. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  947. if (!buffer->skb)
  948. return 1;
  949. skb = buffer->skb;
  950. if (!adapter->ahw.cut_through)
  951. skb_reserve(skb, 2);
  952. dma = pci_map_single(pdev, skb->data,
  953. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  954. if (pci_dma_mapping_error(pdev, dma)) {
  955. dev_kfree_skb_any(skb);
  956. buffer->skb = NULL;
  957. return 1;
  958. }
  959. buffer->skb = skb;
  960. buffer->dma = dma;
  961. buffer->state = NETXEN_BUFFER_BUSY;
  962. return 0;
  963. }
  964. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  965. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  966. {
  967. struct netxen_rx_buffer *buffer;
  968. struct sk_buff *skb;
  969. buffer = &rds_ring->rx_buf_arr[index];
  970. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  971. PCI_DMA_FROMDEVICE);
  972. skb = buffer->skb;
  973. if (!skb)
  974. goto no_skb;
  975. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  976. adapter->stats.csummed++;
  977. skb->ip_summed = CHECKSUM_UNNECESSARY;
  978. } else
  979. skb->ip_summed = CHECKSUM_NONE;
  980. skb->dev = adapter->netdev;
  981. buffer->skb = NULL;
  982. no_skb:
  983. buffer->state = NETXEN_BUFFER_FREE;
  984. return skb;
  985. }
  986. static struct netxen_rx_buffer *
  987. netxen_process_rcv(struct netxen_adapter *adapter,
  988. struct nx_host_sds_ring *sds_ring,
  989. int ring, u64 sts_data0)
  990. {
  991. struct net_device *netdev = adapter->netdev;
  992. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  993. struct netxen_rx_buffer *buffer;
  994. struct sk_buff *skb;
  995. struct nx_host_rds_ring *rds_ring;
  996. int index, length, cksum, pkt_offset;
  997. if (unlikely(ring >= adapter->max_rds_rings))
  998. return NULL;
  999. rds_ring = &recv_ctx->rds_rings[ring];
  1000. index = netxen_get_sts_refhandle(sts_data0);
  1001. if (unlikely(index >= rds_ring->num_desc))
  1002. return NULL;
  1003. buffer = &rds_ring->rx_buf_arr[index];
  1004. length = netxen_get_sts_totallength(sts_data0);
  1005. cksum = netxen_get_sts_status(sts_data0);
  1006. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1007. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1008. if (!skb)
  1009. return buffer;
  1010. if (length > rds_ring->skb_size)
  1011. skb_put(skb, rds_ring->skb_size);
  1012. else
  1013. skb_put(skb, length);
  1014. if (pkt_offset)
  1015. skb_pull(skb, pkt_offset);
  1016. skb->truesize = skb->len + sizeof(struct sk_buff);
  1017. skb->protocol = eth_type_trans(skb, netdev);
  1018. napi_gro_receive(&sds_ring->napi, skb);
  1019. adapter->stats.rx_pkts++;
  1020. adapter->stats.rxbytes += length;
  1021. return buffer;
  1022. }
  1023. #define TCP_HDR_SIZE 20
  1024. #define TCP_TS_OPTION_SIZE 12
  1025. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1026. static struct netxen_rx_buffer *
  1027. netxen_process_lro(struct netxen_adapter *adapter,
  1028. struct nx_host_sds_ring *sds_ring,
  1029. int ring, u64 sts_data0, u64 sts_data1)
  1030. {
  1031. struct net_device *netdev = adapter->netdev;
  1032. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1033. struct netxen_rx_buffer *buffer;
  1034. struct sk_buff *skb;
  1035. struct nx_host_rds_ring *rds_ring;
  1036. struct iphdr *iph;
  1037. struct tcphdr *th;
  1038. bool push, timestamp;
  1039. int l2_hdr_offset, l4_hdr_offset;
  1040. int index;
  1041. u16 lro_length, length, data_offset;
  1042. u32 seq_number;
  1043. if (unlikely(ring > adapter->max_rds_rings))
  1044. return NULL;
  1045. rds_ring = &recv_ctx->rds_rings[ring];
  1046. index = netxen_get_lro_sts_refhandle(sts_data0);
  1047. if (unlikely(index > rds_ring->num_desc))
  1048. return NULL;
  1049. buffer = &rds_ring->rx_buf_arr[index];
  1050. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1051. lro_length = netxen_get_lro_sts_length(sts_data0);
  1052. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1053. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1054. push = netxen_get_lro_sts_push_flag(sts_data0);
  1055. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1056. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1057. if (!skb)
  1058. return buffer;
  1059. if (timestamp)
  1060. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1061. else
  1062. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1063. skb_put(skb, lro_length + data_offset);
  1064. skb->truesize = skb->len + sizeof(struct sk_buff) + skb_headroom(skb);
  1065. skb_pull(skb, l2_hdr_offset);
  1066. skb->protocol = eth_type_trans(skb, netdev);
  1067. iph = (struct iphdr *)skb->data;
  1068. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1069. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1070. iph->tot_len = htons(length);
  1071. iph->check = 0;
  1072. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1073. th->psh = push;
  1074. th->seq = htonl(seq_number);
  1075. length = skb->len;
  1076. netif_receive_skb(skb);
  1077. adapter->stats.lro_pkts++;
  1078. adapter->stats.rxbytes += length;
  1079. return buffer;
  1080. }
  1081. #define netxen_merge_rx_buffers(list, head) \
  1082. do { list_splice_tail_init(list, head); } while (0);
  1083. int
  1084. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1085. {
  1086. struct netxen_adapter *adapter = sds_ring->adapter;
  1087. struct list_head *cur;
  1088. struct status_desc *desc;
  1089. struct netxen_rx_buffer *rxbuf;
  1090. u32 consumer = sds_ring->consumer;
  1091. int count = 0;
  1092. u64 sts_data0, sts_data1;
  1093. int opcode, ring = 0, desc_cnt;
  1094. while (count < max) {
  1095. desc = &sds_ring->desc_head[consumer];
  1096. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1097. if (!(sts_data0 & STATUS_OWNER_HOST))
  1098. break;
  1099. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1100. opcode = netxen_get_sts_opcode(sts_data0);
  1101. switch (opcode) {
  1102. case NETXEN_NIC_RXPKT_DESC:
  1103. case NETXEN_OLD_RXPKT_DESC:
  1104. case NETXEN_NIC_SYN_OFFLOAD:
  1105. ring = netxen_get_sts_type(sts_data0);
  1106. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1107. ring, sts_data0);
  1108. break;
  1109. case NETXEN_NIC_LRO_DESC:
  1110. ring = netxen_get_lro_sts_type(sts_data0);
  1111. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1112. rxbuf = netxen_process_lro(adapter, sds_ring,
  1113. ring, sts_data0, sts_data1);
  1114. break;
  1115. case NETXEN_NIC_RESPONSE_DESC:
  1116. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1117. default:
  1118. goto skip;
  1119. }
  1120. WARN_ON(desc_cnt > 1);
  1121. if (rxbuf)
  1122. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1123. skip:
  1124. for (; desc_cnt > 0; desc_cnt--) {
  1125. desc = &sds_ring->desc_head[consumer];
  1126. desc->status_desc_data[0] =
  1127. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1128. consumer = get_next_index(consumer, sds_ring->num_desc);
  1129. }
  1130. count++;
  1131. }
  1132. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1133. struct nx_host_rds_ring *rds_ring =
  1134. &adapter->recv_ctx.rds_rings[ring];
  1135. if (!list_empty(&sds_ring->free_list[ring])) {
  1136. list_for_each(cur, &sds_ring->free_list[ring]) {
  1137. rxbuf = list_entry(cur,
  1138. struct netxen_rx_buffer, list);
  1139. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1140. }
  1141. spin_lock(&rds_ring->lock);
  1142. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1143. &rds_ring->free_list);
  1144. spin_unlock(&rds_ring->lock);
  1145. }
  1146. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1147. }
  1148. if (count) {
  1149. sds_ring->consumer = consumer;
  1150. NXWR32(adapter, sds_ring->crb_sts_consumer, consumer);
  1151. }
  1152. return count;
  1153. }
  1154. /* Process Command status ring */
  1155. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1156. {
  1157. u32 sw_consumer, hw_consumer;
  1158. int count = 0, i;
  1159. struct netxen_cmd_buffer *buffer;
  1160. struct pci_dev *pdev = adapter->pdev;
  1161. struct net_device *netdev = adapter->netdev;
  1162. struct netxen_skb_frag *frag;
  1163. int done = 0;
  1164. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1165. if (!spin_trylock(&adapter->tx_clean_lock))
  1166. return 1;
  1167. sw_consumer = tx_ring->sw_consumer;
  1168. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1169. while (sw_consumer != hw_consumer) {
  1170. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1171. if (buffer->skb) {
  1172. frag = &buffer->frag_array[0];
  1173. pci_unmap_single(pdev, frag->dma, frag->length,
  1174. PCI_DMA_TODEVICE);
  1175. frag->dma = 0ULL;
  1176. for (i = 1; i < buffer->frag_count; i++) {
  1177. frag++; /* Get the next frag */
  1178. pci_unmap_page(pdev, frag->dma, frag->length,
  1179. PCI_DMA_TODEVICE);
  1180. frag->dma = 0ULL;
  1181. }
  1182. adapter->stats.xmitfinished++;
  1183. dev_kfree_skb_any(buffer->skb);
  1184. buffer->skb = NULL;
  1185. }
  1186. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1187. if (++count >= MAX_STATUS_HANDLE)
  1188. break;
  1189. }
  1190. if (count && netif_running(netdev)) {
  1191. tx_ring->sw_consumer = sw_consumer;
  1192. smp_mb();
  1193. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1194. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1195. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1196. netif_wake_queue(netdev);
  1197. __netif_tx_unlock(tx_ring->txq);
  1198. }
  1199. }
  1200. /*
  1201. * If everything is freed up to consumer then check if the ring is full
  1202. * If the ring is full then check if more needs to be freed and
  1203. * schedule the call back again.
  1204. *
  1205. * This happens when there are 2 CPUs. One could be freeing and the
  1206. * other filling it. If the ring is full when we get out of here and
  1207. * the card has already interrupted the host then the host can miss the
  1208. * interrupt.
  1209. *
  1210. * There is still a possible race condition and the host could miss an
  1211. * interrupt. The card has to take care of this.
  1212. */
  1213. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1214. done = (sw_consumer == hw_consumer);
  1215. spin_unlock(&adapter->tx_clean_lock);
  1216. return (done);
  1217. }
  1218. void
  1219. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1220. struct nx_host_rds_ring *rds_ring)
  1221. {
  1222. struct rcv_desc *pdesc;
  1223. struct netxen_rx_buffer *buffer;
  1224. int producer, count = 0;
  1225. netxen_ctx_msg msg = 0;
  1226. struct list_head *head;
  1227. producer = rds_ring->producer;
  1228. spin_lock(&rds_ring->lock);
  1229. head = &rds_ring->free_list;
  1230. while (!list_empty(head)) {
  1231. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1232. if (!buffer->skb) {
  1233. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1234. break;
  1235. }
  1236. count++;
  1237. list_del(&buffer->list);
  1238. /* make a rcv descriptor */
  1239. pdesc = &rds_ring->desc_head[producer];
  1240. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1241. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1242. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1243. producer = get_next_index(producer, rds_ring->num_desc);
  1244. }
  1245. spin_unlock(&rds_ring->lock);
  1246. if (count) {
  1247. rds_ring->producer = producer;
  1248. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1249. (producer-1) & (rds_ring->num_desc-1));
  1250. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1251. /*
  1252. * Write a doorbell msg to tell phanmon of change in
  1253. * receive ring producer
  1254. * Only for firmware version < 4.0.0
  1255. */
  1256. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1257. netxen_set_msg_privid(msg);
  1258. netxen_set_msg_count(msg,
  1259. ((producer - 1) &
  1260. (rds_ring->num_desc - 1)));
  1261. netxen_set_msg_ctxid(msg, adapter->portnum);
  1262. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1263. writel(msg,
  1264. DB_NORMALIZE(adapter,
  1265. NETXEN_RCV_PRODUCER_OFFSET));
  1266. }
  1267. }
  1268. }
  1269. static void
  1270. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1271. struct nx_host_rds_ring *rds_ring)
  1272. {
  1273. struct rcv_desc *pdesc;
  1274. struct netxen_rx_buffer *buffer;
  1275. int producer, count = 0;
  1276. struct list_head *head;
  1277. producer = rds_ring->producer;
  1278. if (!spin_trylock(&rds_ring->lock))
  1279. return;
  1280. head = &rds_ring->free_list;
  1281. while (!list_empty(head)) {
  1282. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1283. if (!buffer->skb) {
  1284. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1285. break;
  1286. }
  1287. count++;
  1288. list_del(&buffer->list);
  1289. /* make a rcv descriptor */
  1290. pdesc = &rds_ring->desc_head[producer];
  1291. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1292. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1293. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1294. producer = get_next_index(producer, rds_ring->num_desc);
  1295. }
  1296. if (count) {
  1297. rds_ring->producer = producer;
  1298. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1299. (producer - 1) & (rds_ring->num_desc - 1));
  1300. }
  1301. spin_unlock(&rds_ring->lock);
  1302. }
  1303. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1304. {
  1305. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1306. return;
  1307. }