twl4030.c 37 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294
  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /*
  117. * read twl4030 register cache
  118. */
  119. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  120. unsigned int reg)
  121. {
  122. u8 *cache = codec->reg_cache;
  123. if (reg >= TWL4030_CACHEREGNUM)
  124. return -EIO;
  125. return cache[reg];
  126. }
  127. /*
  128. * write twl4030 register cache
  129. */
  130. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  131. u8 reg, u8 value)
  132. {
  133. u8 *cache = codec->reg_cache;
  134. if (reg >= TWL4030_CACHEREGNUM)
  135. return;
  136. cache[reg] = value;
  137. }
  138. /*
  139. * write to the twl4030 register space
  140. */
  141. static int twl4030_write(struct snd_soc_codec *codec,
  142. unsigned int reg, unsigned int value)
  143. {
  144. twl4030_write_reg_cache(codec, reg, value);
  145. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  146. }
  147. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  148. {
  149. u8 mode;
  150. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  151. if (enable)
  152. mode |= TWL4030_CODECPDZ;
  153. else
  154. mode &= ~TWL4030_CODECPDZ;
  155. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  156. /* REVISIT: this delay is present in TI sample drivers */
  157. /* but there seems to be no TRM requirement for it */
  158. udelay(10);
  159. }
  160. static void twl4030_init_chip(struct snd_soc_codec *codec)
  161. {
  162. int i;
  163. /* clear CODECPDZ prior to setting register defaults */
  164. twl4030_codec_enable(codec, 0);
  165. /* set all audio section registers to reasonable defaults */
  166. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  167. twl4030_write(codec, i, twl4030_reg[i]);
  168. }
  169. /* Earpiece */
  170. static const char *twl4030_earpiece_texts[] =
  171. {"Off", "DACL1", "DACL2", "DACR1"};
  172. static const unsigned int twl4030_earpiece_values[] =
  173. {0x0, 0x1, 0x2, 0x4};
  174. static const struct soc_enum twl4030_earpiece_enum =
  175. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
  176. ARRAY_SIZE(twl4030_earpiece_texts),
  177. twl4030_earpiece_texts,
  178. twl4030_earpiece_values);
  179. static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
  180. SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
  181. /* PreDrive Left */
  182. static const char *twl4030_predrivel_texts[] =
  183. {"Off", "DACL1", "DACL2", "DACR2"};
  184. static const unsigned int twl4030_predrivel_values[] =
  185. {0x0, 0x1, 0x2, 0x4};
  186. static const struct soc_enum twl4030_predrivel_enum =
  187. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
  188. ARRAY_SIZE(twl4030_predrivel_texts),
  189. twl4030_predrivel_texts,
  190. twl4030_predrivel_values);
  191. static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
  192. SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
  193. /* PreDrive Right */
  194. static const char *twl4030_predriver_texts[] =
  195. {"Off", "DACR1", "DACR2", "DACL2"};
  196. static const unsigned int twl4030_predriver_values[] =
  197. {0x0, 0x1, 0x2, 0x4};
  198. static const struct soc_enum twl4030_predriver_enum =
  199. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
  200. ARRAY_SIZE(twl4030_predriver_texts),
  201. twl4030_predriver_texts,
  202. twl4030_predriver_values);
  203. static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
  204. SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
  205. /* Headset Left */
  206. static const char *twl4030_hsol_texts[] =
  207. {"Off", "DACL1", "DACL2"};
  208. static const struct soc_enum twl4030_hsol_enum =
  209. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
  210. ARRAY_SIZE(twl4030_hsol_texts),
  211. twl4030_hsol_texts);
  212. static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
  213. SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
  214. /* Headset Right */
  215. static const char *twl4030_hsor_texts[] =
  216. {"Off", "DACR1", "DACR2"};
  217. static const struct soc_enum twl4030_hsor_enum =
  218. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
  219. ARRAY_SIZE(twl4030_hsor_texts),
  220. twl4030_hsor_texts);
  221. static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
  222. SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
  223. /* Carkit Left */
  224. static const char *twl4030_carkitl_texts[] =
  225. {"Off", "DACL1", "DACL2"};
  226. static const struct soc_enum twl4030_carkitl_enum =
  227. SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
  228. ARRAY_SIZE(twl4030_carkitl_texts),
  229. twl4030_carkitl_texts);
  230. static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
  231. SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
  232. /* Carkit Right */
  233. static const char *twl4030_carkitr_texts[] =
  234. {"Off", "DACR1", "DACR2"};
  235. static const struct soc_enum twl4030_carkitr_enum =
  236. SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
  237. ARRAY_SIZE(twl4030_carkitr_texts),
  238. twl4030_carkitr_texts);
  239. static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
  240. SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
  241. /* Handsfree Left */
  242. static const char *twl4030_handsfreel_texts[] =
  243. {"Voice", "DACL1", "DACL2", "DACR2"};
  244. static const struct soc_enum twl4030_handsfreel_enum =
  245. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  246. ARRAY_SIZE(twl4030_handsfreel_texts),
  247. twl4030_handsfreel_texts);
  248. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  249. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  250. /* Handsfree Right */
  251. static const char *twl4030_handsfreer_texts[] =
  252. {"Voice", "DACR1", "DACR2", "DACL2"};
  253. static const struct soc_enum twl4030_handsfreer_enum =
  254. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  255. ARRAY_SIZE(twl4030_handsfreer_texts),
  256. twl4030_handsfreer_texts);
  257. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  258. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  259. /* Left analog microphone selection */
  260. static const char *twl4030_analoglmic_texts[] =
  261. {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
  262. static const unsigned int twl4030_analoglmic_values[] =
  263. {0x0, 0x1, 0x2, 0x4, 0x8};
  264. static const struct soc_enum twl4030_analoglmic_enum =
  265. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
  266. ARRAY_SIZE(twl4030_analoglmic_texts),
  267. twl4030_analoglmic_texts,
  268. twl4030_analoglmic_values);
  269. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
  270. SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
  271. /* Right analog microphone selection */
  272. static const char *twl4030_analogrmic_texts[] =
  273. {"Off", "Sub mic", "AUXR"};
  274. static const unsigned int twl4030_analogrmic_values[] =
  275. {0x0, 0x1, 0x4};
  276. static const struct soc_enum twl4030_analogrmic_enum =
  277. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
  278. ARRAY_SIZE(twl4030_analogrmic_texts),
  279. twl4030_analogrmic_texts,
  280. twl4030_analogrmic_values);
  281. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
  282. SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
  283. /* TX1 L/R Analog/Digital microphone selection */
  284. static const char *twl4030_micpathtx1_texts[] =
  285. {"Analog", "Digimic0"};
  286. static const struct soc_enum twl4030_micpathtx1_enum =
  287. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  288. ARRAY_SIZE(twl4030_micpathtx1_texts),
  289. twl4030_micpathtx1_texts);
  290. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  291. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  292. /* TX2 L/R Analog/Digital microphone selection */
  293. static const char *twl4030_micpathtx2_texts[] =
  294. {"Analog", "Digimic1"};
  295. static const struct soc_enum twl4030_micpathtx2_enum =
  296. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  297. ARRAY_SIZE(twl4030_micpathtx2_texts),
  298. twl4030_micpathtx2_texts);
  299. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  300. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  301. static int micpath_event(struct snd_soc_dapm_widget *w,
  302. struct snd_kcontrol *kcontrol, int event)
  303. {
  304. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  305. unsigned char adcmicsel, micbias_ctl;
  306. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  307. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  308. /* Prepare the bits for the given TX path:
  309. * shift_l == 0: TX1 microphone path
  310. * shift_l == 2: TX2 microphone path */
  311. if (e->shift_l) {
  312. /* TX2 microphone path */
  313. if (adcmicsel & TWL4030_TX2IN_SEL)
  314. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  315. else
  316. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  317. } else {
  318. /* TX1 microphone path */
  319. if (adcmicsel & TWL4030_TX1IN_SEL)
  320. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  321. else
  322. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  323. }
  324. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  325. return 0;
  326. }
  327. static int handsfree_event(struct snd_soc_dapm_widget *w,
  328. struct snd_kcontrol *kcontrol, int event)
  329. {
  330. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  331. unsigned char hs_ctl;
  332. hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
  333. if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
  334. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  335. twl4030_write(w->codec, e->reg, hs_ctl);
  336. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  337. twl4030_write(w->codec, e->reg, hs_ctl);
  338. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  339. twl4030_write(w->codec, e->reg, hs_ctl);
  340. } else {
  341. hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
  342. | TWL4030_HF_CTL_HB_EN);
  343. twl4030_write(w->codec, e->reg, hs_ctl);
  344. }
  345. return 0;
  346. }
  347. /*
  348. * Some of the gain controls in TWL (mostly those which are associated with
  349. * the outputs) are implemented in an interesting way:
  350. * 0x0 : Power down (mute)
  351. * 0x1 : 6dB
  352. * 0x2 : 0 dB
  353. * 0x3 : -6 dB
  354. * Inverting not going to help with these.
  355. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  356. */
  357. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  358. xinvert, tlv_array) \
  359. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  360. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  361. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  362. .tlv.p = (tlv_array), \
  363. .info = snd_soc_info_volsw, \
  364. .get = snd_soc_get_volsw_twl4030, \
  365. .put = snd_soc_put_volsw_twl4030, \
  366. .private_value = (unsigned long)&(struct soc_mixer_control) \
  367. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  368. .max = xmax, .invert = xinvert} }
  369. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  370. xinvert, tlv_array) \
  371. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  372. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  373. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  374. .tlv.p = (tlv_array), \
  375. .info = snd_soc_info_volsw_2r, \
  376. .get = snd_soc_get_volsw_r2_twl4030,\
  377. .put = snd_soc_put_volsw_r2_twl4030, \
  378. .private_value = (unsigned long)&(struct soc_mixer_control) \
  379. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  380. .rshift = xshift, .max = xmax, .invert = xinvert} }
  381. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  382. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  383. xinvert, tlv_array)
  384. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  385. struct snd_ctl_elem_value *ucontrol)
  386. {
  387. struct soc_mixer_control *mc =
  388. (struct soc_mixer_control *)kcontrol->private_value;
  389. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  390. unsigned int reg = mc->reg;
  391. unsigned int shift = mc->shift;
  392. unsigned int rshift = mc->rshift;
  393. int max = mc->max;
  394. int mask = (1 << fls(max)) - 1;
  395. ucontrol->value.integer.value[0] =
  396. (snd_soc_read(codec, reg) >> shift) & mask;
  397. if (ucontrol->value.integer.value[0])
  398. ucontrol->value.integer.value[0] =
  399. max + 1 - ucontrol->value.integer.value[0];
  400. if (shift != rshift) {
  401. ucontrol->value.integer.value[1] =
  402. (snd_soc_read(codec, reg) >> rshift) & mask;
  403. if (ucontrol->value.integer.value[1])
  404. ucontrol->value.integer.value[1] =
  405. max + 1 - ucontrol->value.integer.value[1];
  406. }
  407. return 0;
  408. }
  409. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  410. struct snd_ctl_elem_value *ucontrol)
  411. {
  412. struct soc_mixer_control *mc =
  413. (struct soc_mixer_control *)kcontrol->private_value;
  414. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  415. unsigned int reg = mc->reg;
  416. unsigned int shift = mc->shift;
  417. unsigned int rshift = mc->rshift;
  418. int max = mc->max;
  419. int mask = (1 << fls(max)) - 1;
  420. unsigned short val, val2, val_mask;
  421. val = (ucontrol->value.integer.value[0] & mask);
  422. val_mask = mask << shift;
  423. if (val)
  424. val = max + 1 - val;
  425. val = val << shift;
  426. if (shift != rshift) {
  427. val2 = (ucontrol->value.integer.value[1] & mask);
  428. val_mask |= mask << rshift;
  429. if (val2)
  430. val2 = max + 1 - val2;
  431. val |= val2 << rshift;
  432. }
  433. return snd_soc_update_bits(codec, reg, val_mask, val);
  434. }
  435. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  436. struct snd_ctl_elem_value *ucontrol)
  437. {
  438. struct soc_mixer_control *mc =
  439. (struct soc_mixer_control *)kcontrol->private_value;
  440. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  441. unsigned int reg = mc->reg;
  442. unsigned int reg2 = mc->rreg;
  443. unsigned int shift = mc->shift;
  444. int max = mc->max;
  445. int mask = (1<<fls(max))-1;
  446. ucontrol->value.integer.value[0] =
  447. (snd_soc_read(codec, reg) >> shift) & mask;
  448. ucontrol->value.integer.value[1] =
  449. (snd_soc_read(codec, reg2) >> shift) & mask;
  450. if (ucontrol->value.integer.value[0])
  451. ucontrol->value.integer.value[0] =
  452. max + 1 - ucontrol->value.integer.value[0];
  453. if (ucontrol->value.integer.value[1])
  454. ucontrol->value.integer.value[1] =
  455. max + 1 - ucontrol->value.integer.value[1];
  456. return 0;
  457. }
  458. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  459. struct snd_ctl_elem_value *ucontrol)
  460. {
  461. struct soc_mixer_control *mc =
  462. (struct soc_mixer_control *)kcontrol->private_value;
  463. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  464. unsigned int reg = mc->reg;
  465. unsigned int reg2 = mc->rreg;
  466. unsigned int shift = mc->shift;
  467. int max = mc->max;
  468. int mask = (1 << fls(max)) - 1;
  469. int err;
  470. unsigned short val, val2, val_mask;
  471. val_mask = mask << shift;
  472. val = (ucontrol->value.integer.value[0] & mask);
  473. val2 = (ucontrol->value.integer.value[1] & mask);
  474. if (val)
  475. val = max + 1 - val;
  476. if (val2)
  477. val2 = max + 1 - val2;
  478. val = val << shift;
  479. val2 = val2 << shift;
  480. err = snd_soc_update_bits(codec, reg, val_mask, val);
  481. if (err < 0)
  482. return err;
  483. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  484. return err;
  485. }
  486. /*
  487. * FGAIN volume control:
  488. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  489. */
  490. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  491. /*
  492. * CGAIN volume control:
  493. * 0 dB to 12 dB in 6 dB steps
  494. * value 2 and 3 means 12 dB
  495. */
  496. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  497. /*
  498. * Analog playback gain
  499. * -24 dB to 12 dB in 2 dB steps
  500. */
  501. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  502. /*
  503. * Gain controls tied to outputs
  504. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  505. */
  506. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  507. /*
  508. * Capture gain after the ADCs
  509. * from 0 dB to 31 dB in 1 dB steps
  510. */
  511. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  512. /*
  513. * Gain control for input amplifiers
  514. * 0 dB to 30 dB in 6 dB steps
  515. */
  516. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  517. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  518. /* Common playback gain controls */
  519. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  520. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  521. 0, 0x3f, 0, digital_fine_tlv),
  522. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  523. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  524. 0, 0x3f, 0, digital_fine_tlv),
  525. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  526. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  527. 6, 0x2, 0, digital_coarse_tlv),
  528. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  529. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  530. 6, 0x2, 0, digital_coarse_tlv),
  531. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  532. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  533. 3, 0x12, 1, analog_tlv),
  534. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  535. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  536. 3, 0x12, 1, analog_tlv),
  537. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  538. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  539. 1, 1, 0),
  540. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  541. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  542. 1, 1, 0),
  543. /* Separate output gain controls */
  544. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  545. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  546. 4, 3, 0, output_tvl),
  547. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  548. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  549. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  550. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  551. 4, 3, 0, output_tvl),
  552. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  553. TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
  554. /* Common capture gain controls */
  555. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  556. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  557. 0, 0x1f, 0, digital_capture_tlv),
  558. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  559. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  560. 0, 0x1f, 0, digital_capture_tlv),
  561. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  562. 0, 3, 5, 0, input_gain_tlv),
  563. };
  564. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  565. /* Left channel inputs */
  566. SND_SOC_DAPM_INPUT("MAINMIC"),
  567. SND_SOC_DAPM_INPUT("HSMIC"),
  568. SND_SOC_DAPM_INPUT("AUXL"),
  569. SND_SOC_DAPM_INPUT("CARKITMIC"),
  570. /* Right channel inputs */
  571. SND_SOC_DAPM_INPUT("SUBMIC"),
  572. SND_SOC_DAPM_INPUT("AUXR"),
  573. /* Digital microphones (Stereo) */
  574. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  575. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  576. /* Outputs */
  577. SND_SOC_DAPM_OUTPUT("OUTL"),
  578. SND_SOC_DAPM_OUTPUT("OUTR"),
  579. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  580. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  581. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  582. SND_SOC_DAPM_OUTPUT("HSOL"),
  583. SND_SOC_DAPM_OUTPUT("HSOR"),
  584. SND_SOC_DAPM_OUTPUT("CARKITL"),
  585. SND_SOC_DAPM_OUTPUT("CARKITR"),
  586. SND_SOC_DAPM_OUTPUT("HFL"),
  587. SND_SOC_DAPM_OUTPUT("HFR"),
  588. /* DACs */
  589. SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
  590. TWL4030_REG_AVDAC_CTL, 0, 0),
  591. SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
  592. TWL4030_REG_AVDAC_CTL, 1, 0),
  593. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
  594. TWL4030_REG_AVDAC_CTL, 2, 0),
  595. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
  596. TWL4030_REG_AVDAC_CTL, 3, 0),
  597. /* Analog PGAs */
  598. SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
  599. 0, 0, NULL, 0),
  600. SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
  601. 0, 0, NULL, 0),
  602. SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
  603. 0, 0, NULL, 0),
  604. SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
  605. 0, 0, NULL, 0),
  606. /* Output MUX controls */
  607. /* Earpiece */
  608. SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
  609. &twl4030_dapm_earpiece_control),
  610. /* PreDrivL/R */
  611. SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
  612. &twl4030_dapm_predrivel_control),
  613. SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
  614. &twl4030_dapm_predriver_control),
  615. /* HeadsetL/R */
  616. SND_SOC_DAPM_MUX("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
  617. &twl4030_dapm_hsol_control),
  618. SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
  619. &twl4030_dapm_hsor_control),
  620. /* CarkitL/R */
  621. SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
  622. &twl4030_dapm_carkitl_control),
  623. SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
  624. &twl4030_dapm_carkitr_control),
  625. /* HandsfreeL/R */
  626. SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
  627. &twl4030_dapm_handsfreel_control, handsfree_event,
  628. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  629. SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
  630. &twl4030_dapm_handsfreer_control, handsfree_event,
  631. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  632. /* Introducing four virtual ADC, since TWL4030 have four channel for
  633. capture */
  634. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  635. SND_SOC_NOPM, 0, 0),
  636. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  637. SND_SOC_NOPM, 0, 0),
  638. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  639. SND_SOC_NOPM, 0, 0),
  640. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  641. SND_SOC_NOPM, 0, 0),
  642. /* Analog/Digital mic path selection.
  643. TX1 Left/Right: either analog Left/Right or Digimic0
  644. TX2 Left/Right: either analog Left/Right or Digimic1 */
  645. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  646. &twl4030_dapm_micpathtx1_control, micpath_event,
  647. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  648. SND_SOC_DAPM_POST_REG),
  649. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  650. &twl4030_dapm_micpathtx2_control, micpath_event,
  651. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  652. SND_SOC_DAPM_POST_REG),
  653. /* Analog input muxes with power switch for the physical ADCL/R */
  654. SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
  655. TWL4030_REG_AVADC_CTL, 3, 0, &twl4030_dapm_analoglmic_control),
  656. SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
  657. TWL4030_REG_AVADC_CTL, 1, 0, &twl4030_dapm_analogrmic_control),
  658. SND_SOC_DAPM_PGA("Analog Left Amplifier",
  659. TWL4030_REG_ANAMICL, 4, 0, NULL, 0),
  660. SND_SOC_DAPM_PGA("Analog Right Amplifier",
  661. TWL4030_REG_ANAMICR, 4, 0, NULL, 0),
  662. SND_SOC_DAPM_PGA("Digimic0 Enable",
  663. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  664. SND_SOC_DAPM_PGA("Digimic1 Enable",
  665. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  666. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  667. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  668. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  669. };
  670. static const struct snd_soc_dapm_route intercon[] = {
  671. {"ARXL1_APGA", NULL, "DAC Left1"},
  672. {"ARXR1_APGA", NULL, "DAC Right1"},
  673. {"ARXL2_APGA", NULL, "DAC Left2"},
  674. {"ARXR2_APGA", NULL, "DAC Right2"},
  675. /* Internal playback routings */
  676. /* Earpiece */
  677. {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
  678. {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
  679. {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
  680. /* PreDrivL */
  681. {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
  682. {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
  683. {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
  684. /* PreDrivR */
  685. {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
  686. {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
  687. {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
  688. /* HeadsetL */
  689. {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
  690. {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
  691. /* HeadsetR */
  692. {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
  693. {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
  694. /* CarkitL */
  695. {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
  696. {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
  697. /* CarkitR */
  698. {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
  699. {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
  700. /* HandsfreeL */
  701. {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
  702. {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
  703. {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
  704. /* HandsfreeR */
  705. {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
  706. {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
  707. {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
  708. /* outputs */
  709. {"OUTL", NULL, "ARXL2_APGA"},
  710. {"OUTR", NULL, "ARXR2_APGA"},
  711. {"EARPIECE", NULL, "Earpiece Mux"},
  712. {"PREDRIVEL", NULL, "PredriveL Mux"},
  713. {"PREDRIVER", NULL, "PredriveR Mux"},
  714. {"HSOL", NULL, "HeadsetL Mux"},
  715. {"HSOR", NULL, "HeadsetR Mux"},
  716. {"CARKITL", NULL, "CarkitL Mux"},
  717. {"CARKITR", NULL, "CarkitR Mux"},
  718. {"HFL", NULL, "HandsfreeL Mux"},
  719. {"HFR", NULL, "HandsfreeR Mux"},
  720. /* Capture path */
  721. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  722. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  723. {"Analog Left Capture Route", "AUXL", "AUXL"},
  724. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  725. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  726. {"Analog Right Capture Route", "AUXR", "AUXR"},
  727. {"Analog Left Amplifier", NULL, "Analog Left Capture Route"},
  728. {"Analog Right Amplifier", NULL, "Analog Right Capture Route"},
  729. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  730. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  731. /* TX1 Left capture path */
  732. {"TX1 Capture Route", "Analog", "Analog Left Amplifier"},
  733. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  734. /* TX1 Right capture path */
  735. {"TX1 Capture Route", "Analog", "Analog Right Amplifier"},
  736. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  737. /* TX2 Left capture path */
  738. {"TX2 Capture Route", "Analog", "Analog Left Amplifier"},
  739. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  740. /* TX2 Right capture path */
  741. {"TX2 Capture Route", "Analog", "Analog Right Amplifier"},
  742. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  743. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  744. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  745. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  746. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  747. };
  748. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  749. {
  750. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  751. ARRAY_SIZE(twl4030_dapm_widgets));
  752. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  753. snd_soc_dapm_new_widgets(codec);
  754. return 0;
  755. }
  756. static void twl4030_power_up(struct snd_soc_codec *codec)
  757. {
  758. u8 anamicl, regmisc1, byte, popn;
  759. int i = 0;
  760. /* set CODECPDZ to turn on codec */
  761. twl4030_codec_enable(codec, 1);
  762. /* initiate offset cancellation */
  763. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  764. twl4030_write(codec, TWL4030_REG_ANAMICL,
  765. anamicl | TWL4030_CNCL_OFFSET_START);
  766. /* wait for offset cancellation to complete */
  767. do {
  768. /* this takes a little while, so don't slam i2c */
  769. udelay(2000);
  770. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  771. TWL4030_REG_ANAMICL);
  772. } while ((i++ < 100) &&
  773. ((byte & TWL4030_CNCL_OFFSET_START) ==
  774. TWL4030_CNCL_OFFSET_START));
  775. /* Make sure that the reg_cache has the same value as the HW */
  776. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  777. /* anti-pop when changing analog gain */
  778. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  779. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  780. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  781. /* toggle CODECPDZ as per TRM */
  782. twl4030_codec_enable(codec, 0);
  783. twl4030_codec_enable(codec, 1);
  784. /* program anti-pop with bias ramp delay */
  785. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  786. popn &= TWL4030_RAMP_DELAY;
  787. popn |= TWL4030_RAMP_DELAY_645MS;
  788. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  789. popn |= TWL4030_VMID_EN;
  790. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  791. /* enable anti-pop ramp */
  792. popn |= TWL4030_RAMP_EN;
  793. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  794. }
  795. static void twl4030_power_down(struct snd_soc_codec *codec)
  796. {
  797. u8 popn;
  798. /* disable anti-pop ramp */
  799. popn = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
  800. popn &= ~TWL4030_RAMP_EN;
  801. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  802. /* disable bias out */
  803. popn &= ~TWL4030_VMID_EN;
  804. twl4030_write(codec, TWL4030_REG_HS_POPN_SET, popn);
  805. /* power down */
  806. twl4030_codec_enable(codec, 0);
  807. }
  808. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  809. enum snd_soc_bias_level level)
  810. {
  811. switch (level) {
  812. case SND_SOC_BIAS_ON:
  813. twl4030_power_up(codec);
  814. break;
  815. case SND_SOC_BIAS_PREPARE:
  816. /* TODO: develop a twl4030_prepare function */
  817. break;
  818. case SND_SOC_BIAS_STANDBY:
  819. /* TODO: develop a twl4030_standby function */
  820. twl4030_power_down(codec);
  821. break;
  822. case SND_SOC_BIAS_OFF:
  823. twl4030_power_down(codec);
  824. break;
  825. }
  826. codec->bias_level = level;
  827. return 0;
  828. }
  829. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  830. struct snd_pcm_hw_params *params,
  831. struct snd_soc_dai *dai)
  832. {
  833. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  834. struct snd_soc_device *socdev = rtd->socdev;
  835. struct snd_soc_codec *codec = socdev->card->codec;
  836. u8 mode, old_mode, format, old_format;
  837. /* bit rate */
  838. old_mode = twl4030_read_reg_cache(codec,
  839. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  840. mode = old_mode & ~TWL4030_APLL_RATE;
  841. switch (params_rate(params)) {
  842. case 8000:
  843. mode |= TWL4030_APLL_RATE_8000;
  844. break;
  845. case 11025:
  846. mode |= TWL4030_APLL_RATE_11025;
  847. break;
  848. case 12000:
  849. mode |= TWL4030_APLL_RATE_12000;
  850. break;
  851. case 16000:
  852. mode |= TWL4030_APLL_RATE_16000;
  853. break;
  854. case 22050:
  855. mode |= TWL4030_APLL_RATE_22050;
  856. break;
  857. case 24000:
  858. mode |= TWL4030_APLL_RATE_24000;
  859. break;
  860. case 32000:
  861. mode |= TWL4030_APLL_RATE_32000;
  862. break;
  863. case 44100:
  864. mode |= TWL4030_APLL_RATE_44100;
  865. break;
  866. case 48000:
  867. mode |= TWL4030_APLL_RATE_48000;
  868. break;
  869. default:
  870. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  871. params_rate(params));
  872. return -EINVAL;
  873. }
  874. if (mode != old_mode) {
  875. /* change rate and set CODECPDZ */
  876. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  877. twl4030_codec_enable(codec, 1);
  878. }
  879. /* sample size */
  880. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  881. format = old_format;
  882. format &= ~TWL4030_DATA_WIDTH;
  883. switch (params_format(params)) {
  884. case SNDRV_PCM_FORMAT_S16_LE:
  885. format |= TWL4030_DATA_WIDTH_16S_16W;
  886. break;
  887. case SNDRV_PCM_FORMAT_S24_LE:
  888. format |= TWL4030_DATA_WIDTH_32S_24W;
  889. break;
  890. default:
  891. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  892. params_format(params));
  893. return -EINVAL;
  894. }
  895. if (format != old_format) {
  896. /* clear CODECPDZ before changing format (codec requirement) */
  897. twl4030_codec_enable(codec, 0);
  898. /* change format */
  899. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  900. /* set CODECPDZ afterwards */
  901. twl4030_codec_enable(codec, 1);
  902. }
  903. return 0;
  904. }
  905. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  906. int clk_id, unsigned int freq, int dir)
  907. {
  908. struct snd_soc_codec *codec = codec_dai->codec;
  909. u8 infreq;
  910. switch (freq) {
  911. case 19200000:
  912. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  913. break;
  914. case 26000000:
  915. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  916. break;
  917. case 38400000:
  918. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  919. break;
  920. default:
  921. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  922. freq);
  923. return -EINVAL;
  924. }
  925. infreq |= TWL4030_APLL_EN;
  926. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  927. return 0;
  928. }
  929. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  930. unsigned int fmt)
  931. {
  932. struct snd_soc_codec *codec = codec_dai->codec;
  933. u8 old_format, format;
  934. /* get format */
  935. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  936. format = old_format;
  937. /* set master/slave audio interface */
  938. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  939. case SND_SOC_DAIFMT_CBM_CFM:
  940. format &= ~(TWL4030_AIF_SLAVE_EN);
  941. format &= ~(TWL4030_CLK256FS_EN);
  942. break;
  943. case SND_SOC_DAIFMT_CBS_CFS:
  944. format |= TWL4030_AIF_SLAVE_EN;
  945. format |= TWL4030_CLK256FS_EN;
  946. break;
  947. default:
  948. return -EINVAL;
  949. }
  950. /* interface format */
  951. format &= ~TWL4030_AIF_FORMAT;
  952. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  953. case SND_SOC_DAIFMT_I2S:
  954. format |= TWL4030_AIF_FORMAT_CODEC;
  955. break;
  956. default:
  957. return -EINVAL;
  958. }
  959. if (format != old_format) {
  960. /* clear CODECPDZ before changing format (codec requirement) */
  961. twl4030_codec_enable(codec, 0);
  962. /* change format */
  963. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  964. /* set CODECPDZ afterwards */
  965. twl4030_codec_enable(codec, 1);
  966. }
  967. return 0;
  968. }
  969. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  970. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  971. struct snd_soc_dai twl4030_dai = {
  972. .name = "twl4030",
  973. .playback = {
  974. .stream_name = "Playback",
  975. .channels_min = 2,
  976. .channels_max = 2,
  977. .rates = TWL4030_RATES,
  978. .formats = TWL4030_FORMATS,},
  979. .capture = {
  980. .stream_name = "Capture",
  981. .channels_min = 2,
  982. .channels_max = 2,
  983. .rates = TWL4030_RATES,
  984. .formats = TWL4030_FORMATS,},
  985. .ops = {
  986. .hw_params = twl4030_hw_params,
  987. .set_sysclk = twl4030_set_dai_sysclk,
  988. .set_fmt = twl4030_set_dai_fmt,
  989. }
  990. };
  991. EXPORT_SYMBOL_GPL(twl4030_dai);
  992. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  993. {
  994. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  995. struct snd_soc_codec *codec = socdev->card->codec;
  996. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  997. return 0;
  998. }
  999. static int twl4030_resume(struct platform_device *pdev)
  1000. {
  1001. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1002. struct snd_soc_codec *codec = socdev->card->codec;
  1003. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1004. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1005. return 0;
  1006. }
  1007. /*
  1008. * initialize the driver
  1009. * register the mixer and dsp interfaces with the kernel
  1010. */
  1011. static int twl4030_init(struct snd_soc_device *socdev)
  1012. {
  1013. struct snd_soc_codec *codec = socdev->card->codec;
  1014. int ret = 0;
  1015. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1016. codec->name = "twl4030";
  1017. codec->owner = THIS_MODULE;
  1018. codec->read = twl4030_read_reg_cache;
  1019. codec->write = twl4030_write;
  1020. codec->set_bias_level = twl4030_set_bias_level;
  1021. codec->dai = &twl4030_dai;
  1022. codec->num_dai = 1;
  1023. codec->reg_cache_size = sizeof(twl4030_reg);
  1024. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1025. GFP_KERNEL);
  1026. if (codec->reg_cache == NULL)
  1027. return -ENOMEM;
  1028. /* register pcms */
  1029. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1030. if (ret < 0) {
  1031. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1032. goto pcm_err;
  1033. }
  1034. twl4030_init_chip(codec);
  1035. /* power on device */
  1036. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1037. snd_soc_add_controls(codec, twl4030_snd_controls,
  1038. ARRAY_SIZE(twl4030_snd_controls));
  1039. twl4030_add_widgets(codec);
  1040. ret = snd_soc_init_card(socdev);
  1041. if (ret < 0) {
  1042. printk(KERN_ERR "twl4030: failed to register card\n");
  1043. goto card_err;
  1044. }
  1045. return ret;
  1046. card_err:
  1047. snd_soc_free_pcms(socdev);
  1048. snd_soc_dapm_free(socdev);
  1049. pcm_err:
  1050. kfree(codec->reg_cache);
  1051. return ret;
  1052. }
  1053. static struct snd_soc_device *twl4030_socdev;
  1054. static int twl4030_probe(struct platform_device *pdev)
  1055. {
  1056. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1057. struct snd_soc_codec *codec;
  1058. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1059. if (codec == NULL)
  1060. return -ENOMEM;
  1061. socdev->card->codec = codec;
  1062. mutex_init(&codec->mutex);
  1063. INIT_LIST_HEAD(&codec->dapm_widgets);
  1064. INIT_LIST_HEAD(&codec->dapm_paths);
  1065. twl4030_socdev = socdev;
  1066. twl4030_init(socdev);
  1067. return 0;
  1068. }
  1069. static int twl4030_remove(struct platform_device *pdev)
  1070. {
  1071. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1072. struct snd_soc_codec *codec = socdev->card->codec;
  1073. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1074. snd_soc_free_pcms(socdev);
  1075. snd_soc_dapm_free(socdev);
  1076. kfree(codec);
  1077. return 0;
  1078. }
  1079. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1080. .probe = twl4030_probe,
  1081. .remove = twl4030_remove,
  1082. .suspend = twl4030_suspend,
  1083. .resume = twl4030_resume,
  1084. };
  1085. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1086. static int __init twl4030_modinit(void)
  1087. {
  1088. return snd_soc_register_dai(&twl4030_dai);
  1089. }
  1090. module_init(twl4030_modinit);
  1091. static void __exit twl4030_exit(void)
  1092. {
  1093. snd_soc_unregister_dai(&twl4030_dai);
  1094. }
  1095. module_exit(twl4030_exit);
  1096. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1097. MODULE_AUTHOR("Steve Sakoman");
  1098. MODULE_LICENSE("GPL");