cx23885-dvb.c 34 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/init.h>
  23. #include <linux/device.h>
  24. #include <linux/fs.h>
  25. #include <linux/kthread.h>
  26. #include <linux/file.h>
  27. #include <linux/suspend.h>
  28. #include "cx23885.h"
  29. #include <media/v4l2-common.h>
  30. #include "dvb_ca_en50221.h"
  31. #include "s5h1409.h"
  32. #include "s5h1411.h"
  33. #include "mt2131.h"
  34. #include "tda8290.h"
  35. #include "tda18271.h"
  36. #include "lgdt330x.h"
  37. #include "xc5000.h"
  38. #include "max2165.h"
  39. #include "tda10048.h"
  40. #include "tuner-xc2028.h"
  41. #include "tuner-simple.h"
  42. #include "dib7000p.h"
  43. #include "dibx000_common.h"
  44. #include "zl10353.h"
  45. #include "stv0900.h"
  46. #include "stv0900_reg.h"
  47. #include "stv6110.h"
  48. #include "lnbh24.h"
  49. #include "cx24116.h"
  50. #include "cimax2.h"
  51. #include "lgs8gxx.h"
  52. #include "netup-eeprom.h"
  53. #include "netup-init.h"
  54. #include "lgdt3305.h"
  55. #include "atbm8830.h"
  56. #include "ds3000.h"
  57. #include "cx23885-f300.h"
  58. #include "altera-ci.h"
  59. #include "stv0367.h"
  60. static unsigned int debug;
  61. #define dprintk(level, fmt, arg...)\
  62. do { if (debug >= level)\
  63. printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
  64. } while (0)
  65. /* ------------------------------------------------------------------ */
  66. static unsigned int alt_tuner;
  67. module_param(alt_tuner, int, 0644);
  68. MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
  69. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  70. /* ------------------------------------------------------------------ */
  71. static int dvb_buf_setup(struct videobuf_queue *q,
  72. unsigned int *count, unsigned int *size)
  73. {
  74. struct cx23885_tsport *port = q->priv_data;
  75. port->ts_packet_size = 188 * 4;
  76. port->ts_packet_count = 32;
  77. *size = port->ts_packet_size * port->ts_packet_count;
  78. *count = 32;
  79. return 0;
  80. }
  81. static int dvb_buf_prepare(struct videobuf_queue *q,
  82. struct videobuf_buffer *vb, enum v4l2_field field)
  83. {
  84. struct cx23885_tsport *port = q->priv_data;
  85. return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
  86. }
  87. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  88. {
  89. struct cx23885_tsport *port = q->priv_data;
  90. cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
  91. }
  92. static void dvb_buf_release(struct videobuf_queue *q,
  93. struct videobuf_buffer *vb)
  94. {
  95. cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
  96. }
  97. static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
  98. {
  99. struct videobuf_dvb_frontends *f;
  100. struct videobuf_dvb_frontend *fe;
  101. f = &port->frontends;
  102. if (f->gate <= 1) /* undefined or fe0 */
  103. fe = videobuf_dvb_get_frontend(f, 1);
  104. else
  105. fe = videobuf_dvb_get_frontend(f, f->gate);
  106. if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
  107. fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
  108. }
  109. static struct videobuf_queue_ops dvb_qops = {
  110. .buf_setup = dvb_buf_setup,
  111. .buf_prepare = dvb_buf_prepare,
  112. .buf_queue = dvb_buf_queue,
  113. .buf_release = dvb_buf_release,
  114. };
  115. static struct s5h1409_config hauppauge_generic_config = {
  116. .demod_address = 0x32 >> 1,
  117. .output_mode = S5H1409_SERIAL_OUTPUT,
  118. .gpio = S5H1409_GPIO_ON,
  119. .qam_if = 44000,
  120. .inversion = S5H1409_INVERSION_OFF,
  121. .status_mode = S5H1409_DEMODLOCKING,
  122. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  123. };
  124. static struct tda10048_config hauppauge_hvr1200_config = {
  125. .demod_address = 0x10 >> 1,
  126. .output_mode = TDA10048_SERIAL_OUTPUT,
  127. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  128. .inversion = TDA10048_INVERSION_ON,
  129. .dtv6_if_freq_khz = TDA10048_IF_3300,
  130. .dtv7_if_freq_khz = TDA10048_IF_3800,
  131. .dtv8_if_freq_khz = TDA10048_IF_4300,
  132. .clk_freq_khz = TDA10048_CLK_16000,
  133. };
  134. static struct tda10048_config hauppauge_hvr1210_config = {
  135. .demod_address = 0x10 >> 1,
  136. .output_mode = TDA10048_SERIAL_OUTPUT,
  137. .fwbulkwritelen = TDA10048_BULKWRITE_200,
  138. .inversion = TDA10048_INVERSION_ON,
  139. .dtv6_if_freq_khz = TDA10048_IF_3300,
  140. .dtv7_if_freq_khz = TDA10048_IF_3500,
  141. .dtv8_if_freq_khz = TDA10048_IF_4000,
  142. .clk_freq_khz = TDA10048_CLK_16000,
  143. };
  144. static struct s5h1409_config hauppauge_ezqam_config = {
  145. .demod_address = 0x32 >> 1,
  146. .output_mode = S5H1409_SERIAL_OUTPUT,
  147. .gpio = S5H1409_GPIO_OFF,
  148. .qam_if = 4000,
  149. .inversion = S5H1409_INVERSION_ON,
  150. .status_mode = S5H1409_DEMODLOCKING,
  151. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  152. };
  153. static struct s5h1409_config hauppauge_hvr1800lp_config = {
  154. .demod_address = 0x32 >> 1,
  155. .output_mode = S5H1409_SERIAL_OUTPUT,
  156. .gpio = S5H1409_GPIO_OFF,
  157. .qam_if = 44000,
  158. .inversion = S5H1409_INVERSION_OFF,
  159. .status_mode = S5H1409_DEMODLOCKING,
  160. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  161. };
  162. static struct s5h1409_config hauppauge_hvr1500_config = {
  163. .demod_address = 0x32 >> 1,
  164. .output_mode = S5H1409_SERIAL_OUTPUT,
  165. .gpio = S5H1409_GPIO_OFF,
  166. .inversion = S5H1409_INVERSION_OFF,
  167. .status_mode = S5H1409_DEMODLOCKING,
  168. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  169. };
  170. static struct mt2131_config hauppauge_generic_tunerconfig = {
  171. 0x61
  172. };
  173. static struct lgdt330x_config fusionhdtv_5_express = {
  174. .demod_address = 0x0e,
  175. .demod_chip = LGDT3303,
  176. .serial_mpeg = 0x40,
  177. };
  178. static struct s5h1409_config hauppauge_hvr1500q_config = {
  179. .demod_address = 0x32 >> 1,
  180. .output_mode = S5H1409_SERIAL_OUTPUT,
  181. .gpio = S5H1409_GPIO_ON,
  182. .qam_if = 44000,
  183. .inversion = S5H1409_INVERSION_OFF,
  184. .status_mode = S5H1409_DEMODLOCKING,
  185. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  186. };
  187. static struct s5h1409_config dvico_s5h1409_config = {
  188. .demod_address = 0x32 >> 1,
  189. .output_mode = S5H1409_SERIAL_OUTPUT,
  190. .gpio = S5H1409_GPIO_ON,
  191. .qam_if = 44000,
  192. .inversion = S5H1409_INVERSION_OFF,
  193. .status_mode = S5H1409_DEMODLOCKING,
  194. .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  195. };
  196. static struct s5h1411_config dvico_s5h1411_config = {
  197. .output_mode = S5H1411_SERIAL_OUTPUT,
  198. .gpio = S5H1411_GPIO_ON,
  199. .qam_if = S5H1411_IF_44000,
  200. .vsb_if = S5H1411_IF_44000,
  201. .inversion = S5H1411_INVERSION_OFF,
  202. .status_mode = S5H1411_DEMODLOCKING,
  203. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  204. };
  205. static struct s5h1411_config hcw_s5h1411_config = {
  206. .output_mode = S5H1411_SERIAL_OUTPUT,
  207. .gpio = S5H1411_GPIO_OFF,
  208. .vsb_if = S5H1411_IF_44000,
  209. .qam_if = S5H1411_IF_4000,
  210. .inversion = S5H1411_INVERSION_ON,
  211. .status_mode = S5H1411_DEMODLOCKING,
  212. .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
  213. };
  214. static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
  215. .i2c_address = 0x61,
  216. .if_khz = 5380,
  217. };
  218. static struct xc5000_config dvico_xc5000_tunerconfig = {
  219. .i2c_address = 0x64,
  220. .if_khz = 5380,
  221. };
  222. static struct tda829x_config tda829x_no_probe = {
  223. .probe_tuner = TDA829X_DONT_PROBE,
  224. };
  225. static struct tda18271_std_map hauppauge_tda18271_std_map = {
  226. .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
  227. .if_lvl = 6, .rfagc_top = 0x37 },
  228. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
  229. .if_lvl = 6, .rfagc_top = 0x37 },
  230. };
  231. static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
  232. .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
  233. .if_lvl = 1, .rfagc_top = 0x37, },
  234. .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
  235. .if_lvl = 1, .rfagc_top = 0x37, },
  236. .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
  237. .if_lvl = 1, .rfagc_top = 0x37, },
  238. };
  239. static struct tda18271_config hauppauge_tda18271_config = {
  240. .std_map = &hauppauge_tda18271_std_map,
  241. .gate = TDA18271_GATE_ANALOG,
  242. .output_opt = TDA18271_OUTPUT_LT_OFF,
  243. };
  244. static struct tda18271_config hauppauge_hvr1200_tuner_config = {
  245. .std_map = &hauppauge_hvr1200_tda18271_std_map,
  246. .gate = TDA18271_GATE_ANALOG,
  247. .output_opt = TDA18271_OUTPUT_LT_OFF,
  248. };
  249. static struct tda18271_config hauppauge_hvr1210_tuner_config = {
  250. .gate = TDA18271_GATE_DIGITAL,
  251. .output_opt = TDA18271_OUTPUT_LT_OFF,
  252. };
  253. static struct tda18271_std_map hauppauge_hvr127x_std_map = {
  254. .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
  255. .if_lvl = 1, .rfagc_top = 0x58 },
  256. .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
  257. .if_lvl = 1, .rfagc_top = 0x58 },
  258. };
  259. static struct tda18271_config hauppauge_hvr127x_config = {
  260. .std_map = &hauppauge_hvr127x_std_map,
  261. .output_opt = TDA18271_OUTPUT_LT_OFF,
  262. };
  263. static struct lgdt3305_config hauppauge_lgdt3305_config = {
  264. .i2c_addr = 0x0e,
  265. .mpeg_mode = LGDT3305_MPEG_SERIAL,
  266. .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
  267. .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
  268. .deny_i2c_rptr = 1,
  269. .spectral_inversion = 1,
  270. .qam_if_khz = 4000,
  271. .vsb_if_khz = 3250,
  272. };
  273. static struct dibx000_agc_config xc3028_agc_config = {
  274. BAND_VHF | BAND_UHF, /* band_caps */
  275. /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
  276. * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
  277. * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
  278. * P_agc_nb_est=2, P_agc_write=0
  279. */
  280. (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
  281. (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
  282. 712, /* inv_gain */
  283. 21, /* time_stabiliz */
  284. 0, /* alpha_level */
  285. 118, /* thlock */
  286. 0, /* wbd_inv */
  287. 2867, /* wbd_ref */
  288. 0, /* wbd_sel */
  289. 2, /* wbd_alpha */
  290. 0, /* agc1_max */
  291. 0, /* agc1_min */
  292. 39718, /* agc2_max */
  293. 9930, /* agc2_min */
  294. 0, /* agc1_pt1 */
  295. 0, /* agc1_pt2 */
  296. 0, /* agc1_pt3 */
  297. 0, /* agc1_slope1 */
  298. 0, /* agc1_slope2 */
  299. 0, /* agc2_pt1 */
  300. 128, /* agc2_pt2 */
  301. 29, /* agc2_slope1 */
  302. 29, /* agc2_slope2 */
  303. 17, /* alpha_mant */
  304. 27, /* alpha_exp */
  305. 23, /* beta_mant */
  306. 51, /* beta_exp */
  307. 1, /* perform_agc_softsplit */
  308. };
  309. /* PLL Configuration for COFDM BW_MHz = 8.000000
  310. * With external clock = 30.000000 */
  311. static struct dibx000_bandwidth_config xc3028_bw_config = {
  312. 60000, /* internal */
  313. 30000, /* sampling */
  314. 1, /* pll_cfg: prediv */
  315. 8, /* pll_cfg: ratio */
  316. 3, /* pll_cfg: range */
  317. 1, /* pll_cfg: reset */
  318. 0, /* pll_cfg: bypass */
  319. 0, /* misc: refdiv */
  320. 0, /* misc: bypclk_div */
  321. 1, /* misc: IO_CLK_en_core */
  322. 1, /* misc: ADClkSrc */
  323. 0, /* misc: modulo */
  324. (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
  325. (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
  326. 20452225, /* timf */
  327. 30000000 /* xtal_hz */
  328. };
  329. static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
  330. .output_mpeg2_in_188_bytes = 1,
  331. .hostbus_diversity = 1,
  332. .tuner_is_baseband = 0,
  333. .update_lna = NULL,
  334. .agc_config_count = 1,
  335. .agc = &xc3028_agc_config,
  336. .bw = &xc3028_bw_config,
  337. .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
  338. .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
  339. .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
  340. .pwm_freq_div = 0,
  341. .agc_control = NULL,
  342. .spur_protect = 0,
  343. .output_mode = OUTMODE_MPEG2_SERIAL,
  344. };
  345. static struct zl10353_config dvico_fusionhdtv_xc3028 = {
  346. .demod_address = 0x0f,
  347. .if2 = 45600,
  348. .no_tuner = 1,
  349. .disable_i2c_gate_ctrl = 1,
  350. };
  351. static struct stv0900_reg stv0900_ts_regs[] = {
  352. { R0900_TSGENERAL, 0x00 },
  353. { R0900_P1_TSSPEED, 0x40 },
  354. { R0900_P2_TSSPEED, 0x40 },
  355. { R0900_P1_TSCFGM, 0xc0 },
  356. { R0900_P2_TSCFGM, 0xc0 },
  357. { R0900_P1_TSCFGH, 0xe0 },
  358. { R0900_P2_TSCFGH, 0xe0 },
  359. { R0900_P1_TSCFGL, 0x20 },
  360. { R0900_P2_TSCFGL, 0x20 },
  361. { 0xffff, 0xff }, /* terminate */
  362. };
  363. static struct stv0900_config netup_stv0900_config = {
  364. .demod_address = 0x68,
  365. .demod_mode = 1, /* dual */
  366. .xtal = 8000000,
  367. .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
  368. .diseqc_mode = 2,/* 2/3 PWM */
  369. .ts_config_regs = stv0900_ts_regs,
  370. .tun1_maddress = 0,/* 0x60 */
  371. .tun2_maddress = 3,/* 0x63 */
  372. .tun1_adc = 1,/* 1 Vpp */
  373. .tun2_adc = 1,/* 1 Vpp */
  374. };
  375. static struct stv6110_config netup_stv6110_tunerconfig_a = {
  376. .i2c_address = 0x60,
  377. .mclk = 16000000,
  378. .clk_div = 1,
  379. .gain = 8, /* +16 dB - maximum gain */
  380. };
  381. static struct stv6110_config netup_stv6110_tunerconfig_b = {
  382. .i2c_address = 0x63,
  383. .mclk = 16000000,
  384. .clk_div = 1,
  385. .gain = 8, /* +16 dB - maximum gain */
  386. };
  387. static struct cx24116_config tbs_cx24116_config = {
  388. .demod_address = 0x55,
  389. };
  390. static struct ds3000_config tevii_ds3000_config = {
  391. .demod_address = 0x68,
  392. };
  393. static struct cx24116_config dvbworld_cx24116_config = {
  394. .demod_address = 0x05,
  395. };
  396. static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
  397. .prod = LGS8GXX_PROD_LGS8GL5,
  398. .demod_address = 0x19,
  399. .serial_ts = 0,
  400. .ts_clk_pol = 1,
  401. .ts_clk_gated = 1,
  402. .if_clk_freq = 30400, /* 30.4 MHz */
  403. .if_freq = 5380, /* 5.38 MHz */
  404. .if_neg_center = 1,
  405. .ext_adc = 0,
  406. .adc_signed = 0,
  407. .if_neg_edge = 0,
  408. };
  409. static struct xc5000_config mygica_x8506_xc5000_config = {
  410. .i2c_address = 0x61,
  411. .if_khz = 5380,
  412. };
  413. static int cx23885_dvb_set_frontend(struct dvb_frontend *fe,
  414. struct dvb_frontend_parameters *param)
  415. {
  416. struct cx23885_tsport *port = fe->dvb->priv;
  417. struct cx23885_dev *dev = port->dev;
  418. switch (dev->board) {
  419. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  420. switch (param->u.vsb.modulation) {
  421. case VSB_8:
  422. cx23885_gpio_clear(dev, GPIO_5);
  423. break;
  424. case QAM_64:
  425. case QAM_256:
  426. default:
  427. cx23885_gpio_set(dev, GPIO_5);
  428. break;
  429. }
  430. break;
  431. case CX23885_BOARD_MYGICA_X8506:
  432. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  433. /* Select Digital TV */
  434. cx23885_gpio_set(dev, GPIO_0);
  435. break;
  436. }
  437. return 0;
  438. }
  439. static int cx23885_dvb_fe_ioctl_override(struct dvb_frontend *fe,
  440. unsigned int cmd, void *parg,
  441. unsigned int stage)
  442. {
  443. int err = 0;
  444. switch (stage) {
  445. case DVB_FE_IOCTL_PRE:
  446. switch (cmd) {
  447. case FE_SET_FRONTEND:
  448. err = cx23885_dvb_set_frontend(fe,
  449. (struct dvb_frontend_parameters *) parg);
  450. break;
  451. }
  452. break;
  453. case DVB_FE_IOCTL_POST:
  454. /* no post-ioctl handling required */
  455. break;
  456. }
  457. return err;
  458. };
  459. static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
  460. .prod = LGS8GXX_PROD_LGS8G75,
  461. .demod_address = 0x19,
  462. .serial_ts = 0,
  463. .ts_clk_pol = 1,
  464. .ts_clk_gated = 1,
  465. .if_clk_freq = 30400, /* 30.4 MHz */
  466. .if_freq = 6500, /* 6.50 MHz */
  467. .if_neg_center = 1,
  468. .ext_adc = 0,
  469. .adc_signed = 1,
  470. .adc_vpp = 2, /* 1.6 Vpp */
  471. .if_neg_edge = 1,
  472. };
  473. static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
  474. .i2c_address = 0x61,
  475. .if_khz = 6500,
  476. };
  477. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
  478. .prod = ATBM8830_PROD_8830,
  479. .demod_address = 0x44,
  480. .serial_ts = 0,
  481. .ts_sampling_edge = 1,
  482. .ts_clk_gated = 0,
  483. .osc_clk_freq = 30400, /* in kHz */
  484. .if_freq = 0, /* zero IF */
  485. .zif_swap_iq = 1,
  486. .agc_min = 0x2E,
  487. .agc_max = 0xFF,
  488. .agc_hold_loop = 0,
  489. };
  490. static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
  491. .i2c_address = 0x60,
  492. .osc_clk = 20
  493. };
  494. static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
  495. .prod = ATBM8830_PROD_8830,
  496. .demod_address = 0x44,
  497. .serial_ts = 1,
  498. .ts_sampling_edge = 1,
  499. .ts_clk_gated = 0,
  500. .osc_clk_freq = 30400, /* in kHz */
  501. .if_freq = 0, /* zero IF */
  502. .zif_swap_iq = 1,
  503. .agc_min = 0x2E,
  504. .agc_max = 0xFF,
  505. .agc_hold_loop = 0,
  506. };
  507. static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
  508. .i2c_address = 0x60,
  509. .osc_clk = 20
  510. };
  511. static struct stv0367_config netup_stv0367_config[] = {
  512. {
  513. .demod_address = 0x1c,
  514. .xtal = 27000000,
  515. .if_khz = 4500,
  516. .if_iq_mode = 0,
  517. .ts_mode = 1,
  518. .clk_pol = 0,
  519. }, {
  520. .demod_address = 0x1d,
  521. .xtal = 27000000,
  522. .if_khz = 4500,
  523. .if_iq_mode = 0,
  524. .ts_mode = 1,
  525. .clk_pol = 0,
  526. },
  527. };
  528. static struct xc5000_config netup_xc5000_config[] = {
  529. {
  530. .i2c_address = 0x61,
  531. .if_khz = 4500,
  532. }, {
  533. .i2c_address = 0x64,
  534. .if_khz = 4500,
  535. },
  536. };
  537. int netup_altera_fpga_rw(void *device, int flag, int data, int read)
  538. {
  539. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  540. unsigned long timeout = jiffies + msecs_to_jiffies(1);
  541. uint32_t mem = 0;
  542. mem = cx_read(MC417_RWD);
  543. if (read)
  544. cx_set(MC417_OEN, ALT_DATA);
  545. else {
  546. cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
  547. mem &= ~ALT_DATA;
  548. mem |= (data & ALT_DATA);
  549. }
  550. if (flag)
  551. mem |= ALT_AD_RG;
  552. else
  553. mem &= ~ALT_AD_RG;
  554. mem &= ~ALT_CS;
  555. if (read)
  556. mem = (mem & ~ALT_RD) | ALT_WR;
  557. else
  558. mem = (mem & ~ALT_WR) | ALT_RD;
  559. cx_write(MC417_RWD, mem); /* start RW cycle */
  560. for (;;) {
  561. mem = cx_read(MC417_RWD);
  562. if ((mem & ALT_RDY) == 0)
  563. break;
  564. if (time_after(jiffies, timeout))
  565. break;
  566. udelay(1);
  567. }
  568. cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
  569. if (read)
  570. return mem & ALT_DATA;
  571. return 0;
  572. };
  573. static int dvb_register(struct cx23885_tsport *port)
  574. {
  575. struct cx23885_dev *dev = port->dev;
  576. struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
  577. struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
  578. int mfe_shared = 0; /* bus not shared by default */
  579. int ret;
  580. /* Get the first frontend */
  581. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  582. if (!fe0)
  583. return -EINVAL;
  584. /* init struct videobuf_dvb */
  585. fe0->dvb.name = dev->name;
  586. /* multi-frontend gate control is undefined or defaults to fe0 */
  587. port->frontends.gate = 0;
  588. /* Sets the gate control callback to be used by i2c command calls */
  589. port->gate_ctrl = cx23885_dvb_gate_ctrl;
  590. /* init frontend */
  591. switch (dev->board) {
  592. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  593. i2c_bus = &dev->i2c_bus[0];
  594. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  595. &hauppauge_generic_config,
  596. &i2c_bus->i2c_adap);
  597. if (fe0->dvb.frontend != NULL) {
  598. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  599. &i2c_bus->i2c_adap,
  600. &hauppauge_generic_tunerconfig, 0);
  601. }
  602. break;
  603. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  604. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  605. i2c_bus = &dev->i2c_bus[0];
  606. fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
  607. &hauppauge_lgdt3305_config,
  608. &i2c_bus->i2c_adap);
  609. if (fe0->dvb.frontend != NULL) {
  610. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  611. 0x60, &dev->i2c_bus[1].i2c_adap,
  612. &hauppauge_hvr127x_config);
  613. }
  614. break;
  615. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  616. i2c_bus = &dev->i2c_bus[0];
  617. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  618. &hcw_s5h1411_config,
  619. &i2c_bus->i2c_adap);
  620. if (fe0->dvb.frontend != NULL) {
  621. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  622. 0x60, &dev->i2c_bus[1].i2c_adap,
  623. &hauppauge_tda18271_config);
  624. }
  625. break;
  626. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  627. i2c_bus = &dev->i2c_bus[0];
  628. switch (alt_tuner) {
  629. case 1:
  630. fe0->dvb.frontend =
  631. dvb_attach(s5h1409_attach,
  632. &hauppauge_ezqam_config,
  633. &i2c_bus->i2c_adap);
  634. if (fe0->dvb.frontend != NULL) {
  635. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  636. &dev->i2c_bus[1].i2c_adap, 0x42,
  637. &tda829x_no_probe);
  638. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  639. 0x60, &dev->i2c_bus[1].i2c_adap,
  640. &hauppauge_tda18271_config);
  641. }
  642. break;
  643. case 0:
  644. default:
  645. fe0->dvb.frontend =
  646. dvb_attach(s5h1409_attach,
  647. &hauppauge_generic_config,
  648. &i2c_bus->i2c_adap);
  649. if (fe0->dvb.frontend != NULL)
  650. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  651. &i2c_bus->i2c_adap,
  652. &hauppauge_generic_tunerconfig, 0);
  653. break;
  654. }
  655. break;
  656. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  657. i2c_bus = &dev->i2c_bus[0];
  658. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  659. &hauppauge_hvr1800lp_config,
  660. &i2c_bus->i2c_adap);
  661. if (fe0->dvb.frontend != NULL) {
  662. dvb_attach(mt2131_attach, fe0->dvb.frontend,
  663. &i2c_bus->i2c_adap,
  664. &hauppauge_generic_tunerconfig, 0);
  665. }
  666. break;
  667. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  668. i2c_bus = &dev->i2c_bus[0];
  669. fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
  670. &fusionhdtv_5_express,
  671. &i2c_bus->i2c_adap);
  672. if (fe0->dvb.frontend != NULL) {
  673. dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
  674. &i2c_bus->i2c_adap, 0x61,
  675. TUNER_LG_TDVS_H06XF);
  676. }
  677. break;
  678. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  679. i2c_bus = &dev->i2c_bus[1];
  680. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  681. &hauppauge_hvr1500q_config,
  682. &dev->i2c_bus[0].i2c_adap);
  683. if (fe0->dvb.frontend != NULL)
  684. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  685. &i2c_bus->i2c_adap,
  686. &hauppauge_hvr1500q_tunerconfig);
  687. break;
  688. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  689. i2c_bus = &dev->i2c_bus[1];
  690. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  691. &hauppauge_hvr1500_config,
  692. &dev->i2c_bus[0].i2c_adap);
  693. if (fe0->dvb.frontend != NULL) {
  694. struct dvb_frontend *fe;
  695. struct xc2028_config cfg = {
  696. .i2c_adap = &i2c_bus->i2c_adap,
  697. .i2c_addr = 0x61,
  698. };
  699. static struct xc2028_ctrl ctl = {
  700. .fname = XC2028_DEFAULT_FIRMWARE,
  701. .max_len = 64,
  702. .demod = XC3028_FE_OREN538,
  703. };
  704. fe = dvb_attach(xc2028_attach,
  705. fe0->dvb.frontend, &cfg);
  706. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  707. fe->ops.tuner_ops.set_config(fe, &ctl);
  708. }
  709. break;
  710. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  711. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  712. i2c_bus = &dev->i2c_bus[0];
  713. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  714. &hauppauge_hvr1200_config,
  715. &i2c_bus->i2c_adap);
  716. if (fe0->dvb.frontend != NULL) {
  717. dvb_attach(tda829x_attach, fe0->dvb.frontend,
  718. &dev->i2c_bus[1].i2c_adap, 0x42,
  719. &tda829x_no_probe);
  720. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  721. 0x60, &dev->i2c_bus[1].i2c_adap,
  722. &hauppauge_hvr1200_tuner_config);
  723. }
  724. break;
  725. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  726. i2c_bus = &dev->i2c_bus[0];
  727. fe0->dvb.frontend = dvb_attach(tda10048_attach,
  728. &hauppauge_hvr1210_config,
  729. &i2c_bus->i2c_adap);
  730. if (fe0->dvb.frontend != NULL) {
  731. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  732. 0x60, &dev->i2c_bus[1].i2c_adap,
  733. &hauppauge_hvr1210_tuner_config);
  734. }
  735. break;
  736. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  737. i2c_bus = &dev->i2c_bus[0];
  738. fe0->dvb.frontend = dvb_attach(dib7000p_attach,
  739. &i2c_bus->i2c_adap,
  740. 0x12, &hauppauge_hvr1400_dib7000_config);
  741. if (fe0->dvb.frontend != NULL) {
  742. struct dvb_frontend *fe;
  743. struct xc2028_config cfg = {
  744. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  745. .i2c_addr = 0x64,
  746. };
  747. static struct xc2028_ctrl ctl = {
  748. .fname = XC3028L_DEFAULT_FIRMWARE,
  749. .max_len = 64,
  750. .demod = 5000,
  751. /* This is true for all demods with
  752. v36 firmware? */
  753. .type = XC2028_D2633,
  754. };
  755. fe = dvb_attach(xc2028_attach,
  756. fe0->dvb.frontend, &cfg);
  757. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  758. fe->ops.tuner_ops.set_config(fe, &ctl);
  759. }
  760. break;
  761. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  762. i2c_bus = &dev->i2c_bus[port->nr - 1];
  763. fe0->dvb.frontend = dvb_attach(s5h1409_attach,
  764. &dvico_s5h1409_config,
  765. &i2c_bus->i2c_adap);
  766. if (fe0->dvb.frontend == NULL)
  767. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  768. &dvico_s5h1411_config,
  769. &i2c_bus->i2c_adap);
  770. if (fe0->dvb.frontend != NULL)
  771. dvb_attach(xc5000_attach, fe0->dvb.frontend,
  772. &i2c_bus->i2c_adap,
  773. &dvico_xc5000_tunerconfig);
  774. break;
  775. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
  776. i2c_bus = &dev->i2c_bus[port->nr - 1];
  777. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  778. &dvico_fusionhdtv_xc3028,
  779. &i2c_bus->i2c_adap);
  780. if (fe0->dvb.frontend != NULL) {
  781. struct dvb_frontend *fe;
  782. struct xc2028_config cfg = {
  783. .i2c_adap = &i2c_bus->i2c_adap,
  784. .i2c_addr = 0x61,
  785. };
  786. static struct xc2028_ctrl ctl = {
  787. .fname = XC2028_DEFAULT_FIRMWARE,
  788. .max_len = 64,
  789. .demod = XC3028_FE_ZARLINK456,
  790. };
  791. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  792. &cfg);
  793. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  794. fe->ops.tuner_ops.set_config(fe, &ctl);
  795. }
  796. break;
  797. }
  798. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  799. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  800. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  801. i2c_bus = &dev->i2c_bus[0];
  802. fe0->dvb.frontend = dvb_attach(zl10353_attach,
  803. &dvico_fusionhdtv_xc3028,
  804. &i2c_bus->i2c_adap);
  805. if (fe0->dvb.frontend != NULL) {
  806. struct dvb_frontend *fe;
  807. struct xc2028_config cfg = {
  808. .i2c_adap = &dev->i2c_bus[1].i2c_adap,
  809. .i2c_addr = 0x61,
  810. };
  811. static struct xc2028_ctrl ctl = {
  812. .fname = XC2028_DEFAULT_FIRMWARE,
  813. .max_len = 64,
  814. .demod = XC3028_FE_ZARLINK456,
  815. };
  816. fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
  817. &cfg);
  818. if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
  819. fe->ops.tuner_ops.set_config(fe, &ctl);
  820. }
  821. break;
  822. case CX23885_BOARD_TBS_6920:
  823. i2c_bus = &dev->i2c_bus[1];
  824. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  825. &tbs_cx24116_config,
  826. &i2c_bus->i2c_adap);
  827. if (fe0->dvb.frontend != NULL)
  828. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  829. break;
  830. case CX23885_BOARD_TEVII_S470:
  831. i2c_bus = &dev->i2c_bus[1];
  832. fe0->dvb.frontend = dvb_attach(ds3000_attach,
  833. &tevii_ds3000_config,
  834. &i2c_bus->i2c_adap);
  835. if (fe0->dvb.frontend != NULL)
  836. fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
  837. break;
  838. case CX23885_BOARD_DVBWORLD_2005:
  839. i2c_bus = &dev->i2c_bus[1];
  840. fe0->dvb.frontend = dvb_attach(cx24116_attach,
  841. &dvbworld_cx24116_config,
  842. &i2c_bus->i2c_adap);
  843. break;
  844. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  845. i2c_bus = &dev->i2c_bus[0];
  846. switch (port->nr) {
  847. /* port B */
  848. case 1:
  849. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  850. &netup_stv0900_config,
  851. &i2c_bus->i2c_adap, 0);
  852. if (fe0->dvb.frontend != NULL) {
  853. if (dvb_attach(stv6110_attach,
  854. fe0->dvb.frontend,
  855. &netup_stv6110_tunerconfig_a,
  856. &i2c_bus->i2c_adap)) {
  857. if (!dvb_attach(lnbh24_attach,
  858. fe0->dvb.frontend,
  859. &i2c_bus->i2c_adap,
  860. LNBH24_PCL | LNBH24_TTX,
  861. LNBH24_TEN, 0x09))
  862. printk(KERN_ERR
  863. "No LNBH24 found!\n");
  864. }
  865. }
  866. break;
  867. /* port C */
  868. case 2:
  869. fe0->dvb.frontend = dvb_attach(stv0900_attach,
  870. &netup_stv0900_config,
  871. &i2c_bus->i2c_adap, 1);
  872. if (fe0->dvb.frontend != NULL) {
  873. if (dvb_attach(stv6110_attach,
  874. fe0->dvb.frontend,
  875. &netup_stv6110_tunerconfig_b,
  876. &i2c_bus->i2c_adap)) {
  877. if (!dvb_attach(lnbh24_attach,
  878. fe0->dvb.frontend,
  879. &i2c_bus->i2c_adap,
  880. LNBH24_PCL | LNBH24_TTX,
  881. LNBH24_TEN, 0x0a))
  882. printk(KERN_ERR
  883. "No LNBH24 found!\n");
  884. }
  885. }
  886. break;
  887. }
  888. break;
  889. case CX23885_BOARD_MYGICA_X8506:
  890. i2c_bus = &dev->i2c_bus[0];
  891. i2c_bus2 = &dev->i2c_bus[1];
  892. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  893. &mygica_x8506_lgs8gl5_config,
  894. &i2c_bus->i2c_adap);
  895. if (fe0->dvb.frontend != NULL) {
  896. dvb_attach(xc5000_attach,
  897. fe0->dvb.frontend,
  898. &i2c_bus2->i2c_adap,
  899. &mygica_x8506_xc5000_config);
  900. }
  901. break;
  902. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  903. i2c_bus = &dev->i2c_bus[0];
  904. i2c_bus2 = &dev->i2c_bus[1];
  905. fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
  906. &magicpro_prohdtve2_lgs8g75_config,
  907. &i2c_bus->i2c_adap);
  908. if (fe0->dvb.frontend != NULL) {
  909. dvb_attach(xc5000_attach,
  910. fe0->dvb.frontend,
  911. &i2c_bus2->i2c_adap,
  912. &magicpro_prohdtve2_xc5000_config);
  913. }
  914. break;
  915. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  916. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  917. i2c_bus = &dev->i2c_bus[0];
  918. fe0->dvb.frontend = dvb_attach(s5h1411_attach,
  919. &hcw_s5h1411_config,
  920. &i2c_bus->i2c_adap);
  921. if (fe0->dvb.frontend != NULL)
  922. dvb_attach(tda18271_attach, fe0->dvb.frontend,
  923. 0x60, &dev->i2c_bus[0].i2c_adap,
  924. &hauppauge_tda18271_config);
  925. break;
  926. case CX23885_BOARD_MYGICA_X8558PRO:
  927. switch (port->nr) {
  928. /* port B */
  929. case 1:
  930. i2c_bus = &dev->i2c_bus[0];
  931. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  932. &mygica_x8558pro_atbm8830_cfg1,
  933. &i2c_bus->i2c_adap);
  934. if (fe0->dvb.frontend != NULL) {
  935. dvb_attach(max2165_attach,
  936. fe0->dvb.frontend,
  937. &i2c_bus->i2c_adap,
  938. &mygic_x8558pro_max2165_cfg1);
  939. }
  940. break;
  941. /* port C */
  942. case 2:
  943. i2c_bus = &dev->i2c_bus[1];
  944. fe0->dvb.frontend = dvb_attach(atbm8830_attach,
  945. &mygica_x8558pro_atbm8830_cfg2,
  946. &i2c_bus->i2c_adap);
  947. if (fe0->dvb.frontend != NULL) {
  948. dvb_attach(max2165_attach,
  949. fe0->dvb.frontend,
  950. &i2c_bus->i2c_adap,
  951. &mygic_x8558pro_max2165_cfg2);
  952. }
  953. break;
  954. }
  955. break;
  956. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  957. i2c_bus = &dev->i2c_bus[0];
  958. mfe_shared = 1;/* MFE */
  959. port->frontends.gate = 0;/* not clear for me yet */
  960. /* ports B, C */
  961. /* MFE frontend 1 DVB-T */
  962. fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
  963. &netup_stv0367_config[port->nr - 1],
  964. &i2c_bus->i2c_adap);
  965. if (fe0->dvb.frontend != NULL) {
  966. if (NULL == dvb_attach(xc5000_attach,
  967. fe0->dvb.frontend,
  968. &i2c_bus->i2c_adap,
  969. &netup_xc5000_config[port->nr - 1]))
  970. goto frontend_detach;
  971. /* load xc5000 firmware */
  972. fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
  973. }
  974. /* MFE frontend 2 */
  975. fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
  976. if (fe1 == NULL)
  977. goto frontend_detach;
  978. /* DVB-C init */
  979. fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
  980. &netup_stv0367_config[port->nr - 1],
  981. &i2c_bus->i2c_adap);
  982. if (fe1->dvb.frontend != NULL) {
  983. fe1->dvb.frontend->id = 1;
  984. if (NULL == dvb_attach(xc5000_attach,
  985. fe1->dvb.frontend,
  986. &i2c_bus->i2c_adap,
  987. &netup_xc5000_config[port->nr - 1]))
  988. goto frontend_detach;
  989. }
  990. break;
  991. default:
  992. printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
  993. " isn't supported yet\n",
  994. dev->name);
  995. break;
  996. }
  997. if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
  998. printk(KERN_ERR "%s: frontend initialization failed\n",
  999. dev->name);
  1000. goto frontend_detach;
  1001. }
  1002. /* define general-purpose callback pointer */
  1003. fe0->dvb.frontend->callback = cx23885_tuner_callback;
  1004. if (fe1)
  1005. fe1->dvb.frontend->callback = cx23885_tuner_callback;
  1006. #if 0
  1007. /* Ensure all frontends negotiate bus access */
  1008. fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1009. if (fe1)
  1010. fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
  1011. #endif
  1012. /* Put the analog decoder in standby to keep it quiet */
  1013. call_all(dev, core, s_power, 0);
  1014. if (fe0->dvb.frontend->ops.analog_ops.standby)
  1015. fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
  1016. /* register everything */
  1017. ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
  1018. &dev->pci->dev, adapter_nr, mfe_shared,
  1019. cx23885_dvb_fe_ioctl_override);
  1020. if (ret)
  1021. goto frontend_detach;
  1022. /* init CI & MAC */
  1023. switch (dev->board) {
  1024. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
  1025. static struct netup_card_info cinfo;
  1026. netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
  1027. memcpy(port->frontends.adapter.proposed_mac,
  1028. cinfo.port[port->nr - 1].mac, 6);
  1029. printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
  1030. port->nr, port->frontends.adapter.proposed_mac);
  1031. netup_ci_init(port);
  1032. break;
  1033. }
  1034. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1035. struct altera_ci_config netup_ci_cfg = {
  1036. .dev = dev,/* magic number to identify*/
  1037. .adapter = &port->frontends.adapter,/* for CI */
  1038. .demux = &fe0->dvb.demux,/* for hw pid filter */
  1039. .fpga_rw = netup_altera_fpga_rw,
  1040. };
  1041. altera_ci_init(&netup_ci_cfg, port->nr);
  1042. break;
  1043. }
  1044. case CX23885_BOARD_TEVII_S470: {
  1045. u8 eeprom[256]; /* 24C02 i2c eeprom */
  1046. if (port->nr != 1)
  1047. break;
  1048. /* Read entire EEPROM */
  1049. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1050. tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
  1051. printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
  1052. memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
  1053. break;
  1054. }
  1055. }
  1056. return ret;
  1057. frontend_detach:
  1058. port->gate_ctrl = NULL;
  1059. videobuf_dvb_dealloc_frontends(&port->frontends);
  1060. return -EINVAL;
  1061. }
  1062. int cx23885_dvb_register(struct cx23885_tsport *port)
  1063. {
  1064. struct videobuf_dvb_frontend *fe0;
  1065. struct cx23885_dev *dev = port->dev;
  1066. int err, i;
  1067. /* Here we need to allocate the correct number of frontends,
  1068. * as reflected in the cards struct. The reality is that currently
  1069. * no cx23885 boards support this - yet. But, if we don't modify this
  1070. * code then the second frontend would never be allocated (later)
  1071. * and fail with error before the attach in dvb_register().
  1072. * Without these changes we risk an OOPS later. The changes here
  1073. * are for safety, and should provide a good foundation for the
  1074. * future addition of any multi-frontend cx23885 based boards.
  1075. */
  1076. printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
  1077. port->num_frontends);
  1078. for (i = 1; i <= port->num_frontends; i++) {
  1079. if (videobuf_dvb_alloc_frontend(
  1080. &port->frontends, i) == NULL) {
  1081. printk(KERN_ERR "%s() failed to alloc\n", __func__);
  1082. return -ENOMEM;
  1083. }
  1084. fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
  1085. if (!fe0)
  1086. err = -EINVAL;
  1087. dprintk(1, "%s\n", __func__);
  1088. dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
  1089. dev->board,
  1090. dev->name,
  1091. dev->pci_bus,
  1092. dev->pci_slot);
  1093. err = -ENODEV;
  1094. /* dvb stuff */
  1095. /* We have to init the queue for each frontend on a port. */
  1096. printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
  1097. videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
  1098. &dev->pci->dev, &port->slock,
  1099. V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
  1100. sizeof(struct cx23885_buffer), port, NULL);
  1101. }
  1102. err = dvb_register(port);
  1103. if (err != 0)
  1104. printk(KERN_ERR "%s() dvb_register failed err = %d\n",
  1105. __func__, err);
  1106. return err;
  1107. }
  1108. int cx23885_dvb_unregister(struct cx23885_tsport *port)
  1109. {
  1110. struct videobuf_dvb_frontend *fe0;
  1111. /* FIXME: in an error condition where the we have
  1112. * an expected number of frontends (attach problem)
  1113. * then this might not clean up correctly, if 1
  1114. * is invalid.
  1115. * This comment only applies to future boards IF they
  1116. * implement MFE support.
  1117. */
  1118. fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
  1119. if (fe0->dvb.frontend)
  1120. videobuf_dvb_unregister_bus(&port->frontends);
  1121. switch (port->dev->board) {
  1122. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1123. netup_ci_exit(port);
  1124. break;
  1125. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1126. altera_ci_release(port->dev, port->nr);
  1127. break;
  1128. }
  1129. port->gate_ctrl = NULL;
  1130. return 0;
  1131. }