cx23885-cards.c 40 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/delay.h>
  25. #include <media/cx25840.h>
  26. #include <linux/firmware.h>
  27. #include <staging/altera.h>
  28. #include "cx23885.h"
  29. #include "tuner-xc2028.h"
  30. #include "netup-init.h"
  31. #include "altera-ci.h"
  32. #include "xc5000.h"
  33. #include "cx23888-ir.h"
  34. static unsigned int enable_885_ir;
  35. module_param(enable_885_ir, int, 0644);
  36. MODULE_PARM_DESC(enable_885_ir,
  37. "Enable integrated IR controller for supported\n"
  38. "\t\t CX2388[57] boards that are wired for it:\n"
  39. "\t\t\tHVR-1250 (reported safe)\n"
  40. "\t\t\tTeVii S470 (reported unsafe)\n"
  41. "\t\t This can cause an interrupt storm with some cards.\n"
  42. "\t\t Default: 0 [Disabled]");
  43. /* ------------------------------------------------------------------ */
  44. /* board config info */
  45. struct cx23885_board cx23885_boards[] = {
  46. [CX23885_BOARD_UNKNOWN] = {
  47. .name = "UNKNOWN/GENERIC",
  48. /* Ensure safe default for unknown boards */
  49. .clk_freq = 0,
  50. .input = {{
  51. .type = CX23885_VMUX_COMPOSITE1,
  52. .vmux = 0,
  53. }, {
  54. .type = CX23885_VMUX_COMPOSITE2,
  55. .vmux = 1,
  56. }, {
  57. .type = CX23885_VMUX_COMPOSITE3,
  58. .vmux = 2,
  59. }, {
  60. .type = CX23885_VMUX_COMPOSITE4,
  61. .vmux = 3,
  62. } },
  63. },
  64. [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
  65. .name = "Hauppauge WinTV-HVR1800lp",
  66. .portc = CX23885_MPEG_DVB,
  67. .input = {{
  68. .type = CX23885_VMUX_TELEVISION,
  69. .vmux = 0,
  70. .gpio0 = 0xff00,
  71. }, {
  72. .type = CX23885_VMUX_DEBUG,
  73. .vmux = 0,
  74. .gpio0 = 0xff01,
  75. }, {
  76. .type = CX23885_VMUX_COMPOSITE1,
  77. .vmux = 1,
  78. .gpio0 = 0xff02,
  79. }, {
  80. .type = CX23885_VMUX_SVIDEO,
  81. .vmux = 2,
  82. .gpio0 = 0xff02,
  83. } },
  84. },
  85. [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
  86. .name = "Hauppauge WinTV-HVR1800",
  87. .porta = CX23885_ANALOG_VIDEO,
  88. .portb = CX23885_MPEG_ENCODER,
  89. .portc = CX23885_MPEG_DVB,
  90. .tuner_type = TUNER_PHILIPS_TDA8290,
  91. .tuner_addr = 0x42, /* 0x84 >> 1 */
  92. .tuner_bus = 1,
  93. .input = {{
  94. .type = CX23885_VMUX_TELEVISION,
  95. .vmux = CX25840_VIN7_CH3 |
  96. CX25840_VIN5_CH2 |
  97. CX25840_VIN2_CH1,
  98. .gpio0 = 0,
  99. }, {
  100. .type = CX23885_VMUX_COMPOSITE1,
  101. .vmux = CX25840_VIN7_CH3 |
  102. CX25840_VIN4_CH2 |
  103. CX25840_VIN6_CH1,
  104. .gpio0 = 0,
  105. }, {
  106. .type = CX23885_VMUX_SVIDEO,
  107. .vmux = CX25840_VIN7_CH3 |
  108. CX25840_VIN4_CH2 |
  109. CX25840_VIN8_CH1 |
  110. CX25840_SVIDEO_ON,
  111. .gpio0 = 0,
  112. } },
  113. },
  114. [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
  115. .name = "Hauppauge WinTV-HVR1250",
  116. .portc = CX23885_MPEG_DVB,
  117. .input = {{
  118. .type = CX23885_VMUX_TELEVISION,
  119. .vmux = 0,
  120. .gpio0 = 0xff00,
  121. }, {
  122. .type = CX23885_VMUX_DEBUG,
  123. .vmux = 0,
  124. .gpio0 = 0xff01,
  125. }, {
  126. .type = CX23885_VMUX_COMPOSITE1,
  127. .vmux = 1,
  128. .gpio0 = 0xff02,
  129. }, {
  130. .type = CX23885_VMUX_SVIDEO,
  131. .vmux = 2,
  132. .gpio0 = 0xff02,
  133. } },
  134. },
  135. [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
  136. .name = "DViCO FusionHDTV5 Express",
  137. .portb = CX23885_MPEG_DVB,
  138. },
  139. [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
  140. .name = "Hauppauge WinTV-HVR1500Q",
  141. .portc = CX23885_MPEG_DVB,
  142. },
  143. [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
  144. .name = "Hauppauge WinTV-HVR1500",
  145. .portc = CX23885_MPEG_DVB,
  146. },
  147. [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
  148. .name = "Hauppauge WinTV-HVR1200",
  149. .portc = CX23885_MPEG_DVB,
  150. },
  151. [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
  152. .name = "Hauppauge WinTV-HVR1700",
  153. .portc = CX23885_MPEG_DVB,
  154. },
  155. [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
  156. .name = "Hauppauge WinTV-HVR1400",
  157. .portc = CX23885_MPEG_DVB,
  158. },
  159. [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
  160. .name = "DViCO FusionHDTV7 Dual Express",
  161. .portb = CX23885_MPEG_DVB,
  162. .portc = CX23885_MPEG_DVB,
  163. },
  164. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
  165. .name = "DViCO FusionHDTV DVB-T Dual Express",
  166. .portb = CX23885_MPEG_DVB,
  167. .portc = CX23885_MPEG_DVB,
  168. },
  169. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
  170. .name = "Leadtek Winfast PxDVR3200 H",
  171. .portc = CX23885_MPEG_DVB,
  172. },
  173. [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
  174. .name = "Compro VideoMate E650F",
  175. .portc = CX23885_MPEG_DVB,
  176. },
  177. [CX23885_BOARD_TBS_6920] = {
  178. .name = "TurboSight TBS 6920",
  179. .portb = CX23885_MPEG_DVB,
  180. },
  181. [CX23885_BOARD_TEVII_S470] = {
  182. .name = "TeVii S470",
  183. .portb = CX23885_MPEG_DVB,
  184. },
  185. [CX23885_BOARD_DVBWORLD_2005] = {
  186. .name = "DVBWorld DVB-S2 2005",
  187. .portb = CX23885_MPEG_DVB,
  188. },
  189. [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
  190. .ci_type = 1,
  191. .name = "NetUP Dual DVB-S2 CI",
  192. .portb = CX23885_MPEG_DVB,
  193. .portc = CX23885_MPEG_DVB,
  194. },
  195. [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
  196. .name = "Hauppauge WinTV-HVR1270",
  197. .portc = CX23885_MPEG_DVB,
  198. },
  199. [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
  200. .name = "Hauppauge WinTV-HVR1275",
  201. .portc = CX23885_MPEG_DVB,
  202. },
  203. [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
  204. .name = "Hauppauge WinTV-HVR1255",
  205. .portc = CX23885_MPEG_DVB,
  206. },
  207. [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
  208. .name = "Hauppauge WinTV-HVR1210",
  209. .portc = CX23885_MPEG_DVB,
  210. },
  211. [CX23885_BOARD_MYGICA_X8506] = {
  212. .name = "Mygica X8506 DMB-TH",
  213. .tuner_type = TUNER_XC5000,
  214. .tuner_addr = 0x61,
  215. .tuner_bus = 1,
  216. .porta = CX23885_ANALOG_VIDEO,
  217. .portb = CX23885_MPEG_DVB,
  218. .input = {
  219. {
  220. .type = CX23885_VMUX_TELEVISION,
  221. .vmux = CX25840_COMPOSITE2,
  222. },
  223. {
  224. .type = CX23885_VMUX_COMPOSITE1,
  225. .vmux = CX25840_COMPOSITE8,
  226. },
  227. {
  228. .type = CX23885_VMUX_SVIDEO,
  229. .vmux = CX25840_SVIDEO_LUMA3 |
  230. CX25840_SVIDEO_CHROMA4,
  231. },
  232. {
  233. .type = CX23885_VMUX_COMPONENT,
  234. .vmux = CX25840_COMPONENT_ON |
  235. CX25840_VIN1_CH1 |
  236. CX25840_VIN6_CH2 |
  237. CX25840_VIN7_CH3,
  238. },
  239. },
  240. },
  241. [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
  242. .name = "Magic-Pro ProHDTV Extreme 2",
  243. .tuner_type = TUNER_XC5000,
  244. .tuner_addr = 0x61,
  245. .tuner_bus = 1,
  246. .porta = CX23885_ANALOG_VIDEO,
  247. .portb = CX23885_MPEG_DVB,
  248. .input = {
  249. {
  250. .type = CX23885_VMUX_TELEVISION,
  251. .vmux = CX25840_COMPOSITE2,
  252. },
  253. {
  254. .type = CX23885_VMUX_COMPOSITE1,
  255. .vmux = CX25840_COMPOSITE8,
  256. },
  257. {
  258. .type = CX23885_VMUX_SVIDEO,
  259. .vmux = CX25840_SVIDEO_LUMA3 |
  260. CX25840_SVIDEO_CHROMA4,
  261. },
  262. {
  263. .type = CX23885_VMUX_COMPONENT,
  264. .vmux = CX25840_COMPONENT_ON |
  265. CX25840_VIN1_CH1 |
  266. CX25840_VIN6_CH2 |
  267. CX25840_VIN7_CH3,
  268. },
  269. },
  270. },
  271. [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
  272. .name = "Hauppauge WinTV-HVR1850",
  273. .portb = CX23885_MPEG_ENCODER,
  274. .portc = CX23885_MPEG_DVB,
  275. },
  276. [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
  277. .name = "Compro VideoMate E800",
  278. .portc = CX23885_MPEG_DVB,
  279. },
  280. [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
  281. .name = "Hauppauge WinTV-HVR1290",
  282. .portc = CX23885_MPEG_DVB,
  283. },
  284. [CX23885_BOARD_MYGICA_X8558PRO] = {
  285. .name = "Mygica X8558 PRO DMB-TH",
  286. .portb = CX23885_MPEG_DVB,
  287. .portc = CX23885_MPEG_DVB,
  288. },
  289. [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
  290. .name = "LEADTEK WinFast PxTV1200",
  291. .porta = CX23885_ANALOG_VIDEO,
  292. .tuner_type = TUNER_XC2028,
  293. .tuner_addr = 0x61,
  294. .tuner_bus = 1,
  295. .input = {{
  296. .type = CX23885_VMUX_TELEVISION,
  297. .vmux = CX25840_VIN2_CH1 |
  298. CX25840_VIN5_CH2 |
  299. CX25840_NONE0_CH3,
  300. }, {
  301. .type = CX23885_VMUX_COMPOSITE1,
  302. .vmux = CX25840_COMPOSITE1,
  303. }, {
  304. .type = CX23885_VMUX_SVIDEO,
  305. .vmux = CX25840_SVIDEO_LUMA3 |
  306. CX25840_SVIDEO_CHROMA4,
  307. }, {
  308. .type = CX23885_VMUX_COMPONENT,
  309. .vmux = CX25840_VIN7_CH1 |
  310. CX25840_VIN6_CH2 |
  311. CX25840_VIN8_CH3 |
  312. CX25840_COMPONENT_ON,
  313. } },
  314. },
  315. [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
  316. .name = "GoTView X5 3D Hybrid",
  317. .tuner_type = TUNER_XC5000,
  318. .tuner_addr = 0x64,
  319. .tuner_bus = 1,
  320. .porta = CX23885_ANALOG_VIDEO,
  321. .portb = CX23885_MPEG_DVB,
  322. .input = {{
  323. .type = CX23885_VMUX_TELEVISION,
  324. .vmux = CX25840_VIN2_CH1 |
  325. CX25840_VIN5_CH2,
  326. .gpio0 = 0x02,
  327. }, {
  328. .type = CX23885_VMUX_COMPOSITE1,
  329. .vmux = CX23885_VMUX_COMPOSITE1,
  330. }, {
  331. .type = CX23885_VMUX_SVIDEO,
  332. .vmux = CX25840_SVIDEO_LUMA3 |
  333. CX25840_SVIDEO_CHROMA4,
  334. } },
  335. },
  336. [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
  337. .ci_type = 2,
  338. .name = "NetUP Dual DVB-T/C-CI RF",
  339. .porta = CX23885_ANALOG_VIDEO,
  340. .portb = CX23885_MPEG_DVB,
  341. .portc = CX23885_MPEG_DVB,
  342. .num_fds_portb = 2,
  343. .num_fds_portc = 2,
  344. .tuner_type = TUNER_XC5000,
  345. .tuner_addr = 0x64,
  346. .input = { {
  347. .type = CX23885_VMUX_TELEVISION,
  348. .vmux = CX25840_COMPOSITE1,
  349. } },
  350. },
  351. };
  352. const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
  353. /* ------------------------------------------------------------------ */
  354. /* PCI subsystem IDs */
  355. struct cx23885_subid cx23885_subids[] = {
  356. {
  357. .subvendor = 0x0070,
  358. .subdevice = 0x3400,
  359. .card = CX23885_BOARD_UNKNOWN,
  360. }, {
  361. .subvendor = 0x0070,
  362. .subdevice = 0x7600,
  363. .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
  364. }, {
  365. .subvendor = 0x0070,
  366. .subdevice = 0x7800,
  367. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  368. }, {
  369. .subvendor = 0x0070,
  370. .subdevice = 0x7801,
  371. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  372. }, {
  373. .subvendor = 0x0070,
  374. .subdevice = 0x7809,
  375. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  376. }, {
  377. .subvendor = 0x0070,
  378. .subdevice = 0x7911,
  379. .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
  380. }, {
  381. .subvendor = 0x18ac,
  382. .subdevice = 0xd500,
  383. .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
  384. }, {
  385. .subvendor = 0x0070,
  386. .subdevice = 0x7790,
  387. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  388. }, {
  389. .subvendor = 0x0070,
  390. .subdevice = 0x7797,
  391. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  392. }, {
  393. .subvendor = 0x0070,
  394. .subdevice = 0x7710,
  395. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  396. }, {
  397. .subvendor = 0x0070,
  398. .subdevice = 0x7717,
  399. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  400. }, {
  401. .subvendor = 0x0070,
  402. .subdevice = 0x71d1,
  403. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  404. }, {
  405. .subvendor = 0x0070,
  406. .subdevice = 0x71d3,
  407. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  408. }, {
  409. .subvendor = 0x0070,
  410. .subdevice = 0x8101,
  411. .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
  412. }, {
  413. .subvendor = 0x0070,
  414. .subdevice = 0x8010,
  415. .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
  416. }, {
  417. .subvendor = 0x18ac,
  418. .subdevice = 0xd618,
  419. .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
  420. }, {
  421. .subvendor = 0x18ac,
  422. .subdevice = 0xdb78,
  423. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
  424. }, {
  425. .subvendor = 0x107d,
  426. .subdevice = 0x6681,
  427. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
  428. }, {
  429. .subvendor = 0x185b,
  430. .subdevice = 0xe800,
  431. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
  432. }, {
  433. .subvendor = 0x6920,
  434. .subdevice = 0x8888,
  435. .card = CX23885_BOARD_TBS_6920,
  436. }, {
  437. .subvendor = 0xd470,
  438. .subdevice = 0x9022,
  439. .card = CX23885_BOARD_TEVII_S470,
  440. }, {
  441. .subvendor = 0x0001,
  442. .subdevice = 0x2005,
  443. .card = CX23885_BOARD_DVBWORLD_2005,
  444. }, {
  445. .subvendor = 0x1b55,
  446. .subdevice = 0x2a2c,
  447. .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
  448. }, {
  449. .subvendor = 0x0070,
  450. .subdevice = 0x2211,
  451. .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
  452. }, {
  453. .subvendor = 0x0070,
  454. .subdevice = 0x2215,
  455. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  456. }, {
  457. .subvendor = 0x0070,
  458. .subdevice = 0x221d,
  459. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  460. }, {
  461. .subvendor = 0x0070,
  462. .subdevice = 0x2251,
  463. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  464. }, {
  465. .subvendor = 0x0070,
  466. .subdevice = 0x2259,
  467. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  468. }, {
  469. .subvendor = 0x0070,
  470. .subdevice = 0x2291,
  471. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  472. }, {
  473. .subvendor = 0x0070,
  474. .subdevice = 0x2295,
  475. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  476. }, {
  477. .subvendor = 0x0070,
  478. .subdevice = 0x2299,
  479. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  480. }, {
  481. .subvendor = 0x0070,
  482. .subdevice = 0x229d,
  483. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  484. }, {
  485. .subvendor = 0x0070,
  486. .subdevice = 0x22f0,
  487. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  488. }, {
  489. .subvendor = 0x0070,
  490. .subdevice = 0x22f1,
  491. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  492. }, {
  493. .subvendor = 0x0070,
  494. .subdevice = 0x22f2,
  495. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  496. }, {
  497. .subvendor = 0x0070,
  498. .subdevice = 0x22f3,
  499. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  500. }, {
  501. .subvendor = 0x0070,
  502. .subdevice = 0x22f4,
  503. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  504. }, {
  505. .subvendor = 0x0070,
  506. .subdevice = 0x22f5,
  507. .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
  508. }, {
  509. .subvendor = 0x14f1,
  510. .subdevice = 0x8651,
  511. .card = CX23885_BOARD_MYGICA_X8506,
  512. }, {
  513. .subvendor = 0x14f1,
  514. .subdevice = 0x8657,
  515. .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
  516. }, {
  517. .subvendor = 0x0070,
  518. .subdevice = 0x8541,
  519. .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
  520. }, {
  521. .subvendor = 0x1858,
  522. .subdevice = 0xe800,
  523. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
  524. }, {
  525. .subvendor = 0x0070,
  526. .subdevice = 0x8551,
  527. .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
  528. }, {
  529. .subvendor = 0x14f1,
  530. .subdevice = 0x8578,
  531. .card = CX23885_BOARD_MYGICA_X8558PRO,
  532. }, {
  533. .subvendor = 0x107d,
  534. .subdevice = 0x6f22,
  535. .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
  536. }, {
  537. .subvendor = 0x5654,
  538. .subdevice = 0x2390,
  539. .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
  540. }, {
  541. .subvendor = 0x1b55,
  542. .subdevice = 0xe2e4,
  543. .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
  544. },
  545. };
  546. const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
  547. void cx23885_card_list(struct cx23885_dev *dev)
  548. {
  549. int i;
  550. if (0 == dev->pci->subsystem_vendor &&
  551. 0 == dev->pci->subsystem_device) {
  552. printk(KERN_INFO
  553. "%s: Board has no valid PCIe Subsystem ID and can't\n"
  554. "%s: be autodetected. Pass card=<n> insmod option\n"
  555. "%s: to workaround that. Redirect complaints to the\n"
  556. "%s: vendor of the TV card. Best regards,\n"
  557. "%s: -- tux\n",
  558. dev->name, dev->name, dev->name, dev->name, dev->name);
  559. } else {
  560. printk(KERN_INFO
  561. "%s: Your board isn't known (yet) to the driver.\n"
  562. "%s: Try to pick one of the existing card configs via\n"
  563. "%s: card=<n> insmod option. Updating to the latest\n"
  564. "%s: version might help as well.\n",
  565. dev->name, dev->name, dev->name, dev->name);
  566. }
  567. printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
  568. dev->name);
  569. for (i = 0; i < cx23885_bcount; i++)
  570. printk(KERN_INFO "%s: card=%d -> %s\n",
  571. dev->name, i, cx23885_boards[i].name);
  572. }
  573. static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  574. {
  575. struct tveeprom tv;
  576. tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
  577. eeprom_data);
  578. /* Make sure we support the board model */
  579. switch (tv.model) {
  580. case 22001:
  581. /* WinTV-HVR1270 (PCIe, Retail, half height)
  582. * ATSC/QAM and basic analog, IR Blast */
  583. case 22009:
  584. /* WinTV-HVR1210 (PCIe, Retail, half height)
  585. * DVB-T and basic analog, IR Blast */
  586. case 22011:
  587. /* WinTV-HVR1270 (PCIe, Retail, half height)
  588. * ATSC/QAM and basic analog, IR Recv */
  589. case 22019:
  590. /* WinTV-HVR1210 (PCIe, Retail, half height)
  591. * DVB-T and basic analog, IR Recv */
  592. case 22021:
  593. /* WinTV-HVR1275 (PCIe, Retail, half height)
  594. * ATSC/QAM and basic analog, IR Recv */
  595. case 22029:
  596. /* WinTV-HVR1210 (PCIe, Retail, half height)
  597. * DVB-T and basic analog, IR Recv */
  598. case 22101:
  599. /* WinTV-HVR1270 (PCIe, Retail, full height)
  600. * ATSC/QAM and basic analog, IR Blast */
  601. case 22109:
  602. /* WinTV-HVR1210 (PCIe, Retail, full height)
  603. * DVB-T and basic analog, IR Blast */
  604. case 22111:
  605. /* WinTV-HVR1270 (PCIe, Retail, full height)
  606. * ATSC/QAM and basic analog, IR Recv */
  607. case 22119:
  608. /* WinTV-HVR1210 (PCIe, Retail, full height)
  609. * DVB-T and basic analog, IR Recv */
  610. case 22121:
  611. /* WinTV-HVR1275 (PCIe, Retail, full height)
  612. * ATSC/QAM and basic analog, IR Recv */
  613. case 22129:
  614. /* WinTV-HVR1210 (PCIe, Retail, full height)
  615. * DVB-T and basic analog, IR Recv */
  616. case 71009:
  617. /* WinTV-HVR1200 (PCIe, Retail, full height)
  618. * DVB-T and basic analog */
  619. case 71359:
  620. /* WinTV-HVR1200 (PCIe, OEM, half height)
  621. * DVB-T and basic analog */
  622. case 71439:
  623. /* WinTV-HVR1200 (PCIe, OEM, half height)
  624. * DVB-T and basic analog */
  625. case 71449:
  626. /* WinTV-HVR1200 (PCIe, OEM, full height)
  627. * DVB-T and basic analog */
  628. case 71939:
  629. /* WinTV-HVR1200 (PCIe, OEM, half height)
  630. * DVB-T and basic analog */
  631. case 71949:
  632. /* WinTV-HVR1200 (PCIe, OEM, full height)
  633. * DVB-T and basic analog */
  634. case 71959:
  635. /* WinTV-HVR1200 (PCIe, OEM, full height)
  636. * DVB-T and basic analog */
  637. case 71979:
  638. /* WinTV-HVR1200 (PCIe, OEM, half height)
  639. * DVB-T and basic analog */
  640. case 71999:
  641. /* WinTV-HVR1200 (PCIe, OEM, full height)
  642. * DVB-T and basic analog */
  643. case 76601:
  644. /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
  645. channel ATSC and MPEG2 HW Encoder */
  646. case 77001:
  647. /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
  648. and Basic analog */
  649. case 77011:
  650. /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
  651. and Basic analog */
  652. case 77041:
  653. /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
  654. and Basic analog */
  655. case 77051:
  656. /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
  657. and Basic analog */
  658. case 78011:
  659. /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
  660. Dual channel ATSC and MPEG2 HW Encoder */
  661. case 78501:
  662. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  663. Dual channel ATSC and MPEG2 HW Encoder */
  664. case 78521:
  665. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  666. Dual channel ATSC and MPEG2 HW Encoder */
  667. case 78531:
  668. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
  669. Dual channel ATSC and MPEG2 HW Encoder */
  670. case 78631:
  671. /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
  672. Dual channel ATSC and MPEG2 HW Encoder */
  673. case 79001:
  674. /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
  675. ATSC and Basic analog */
  676. case 79101:
  677. /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
  678. ATSC and Basic analog */
  679. case 79501:
  680. /* WinTV-HVR1250 (PCIe, No IR, half height,
  681. ATSC [at least] and Basic analog) */
  682. case 79561:
  683. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  684. ATSC and Basic analog */
  685. case 79571:
  686. /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
  687. ATSC and Basic analog */
  688. case 79671:
  689. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  690. ATSC and Basic analog */
  691. case 80019:
  692. /* WinTV-HVR1400 (Express Card, Retail, IR,
  693. * DVB-T and Basic analog */
  694. case 81509:
  695. /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
  696. * DVB-T and MPEG2 HW Encoder */
  697. case 81519:
  698. /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
  699. * DVB-T and MPEG2 HW Encoder */
  700. break;
  701. case 85021:
  702. /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
  703. Dual channel ATSC and MPEG2 HW Encoder */
  704. break;
  705. case 85721:
  706. /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
  707. Dual channel ATSC and Basic analog */
  708. break;
  709. default:
  710. printk(KERN_WARNING "%s: warning: "
  711. "unknown hauppauge model #%d\n",
  712. dev->name, tv.model);
  713. break;
  714. }
  715. printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
  716. dev->name, tv.model);
  717. }
  718. int cx23885_tuner_callback(void *priv, int component, int command, int arg)
  719. {
  720. struct cx23885_tsport *port = priv;
  721. struct cx23885_dev *dev = port->dev;
  722. u32 bitmask = 0;
  723. if (command == XC2028_RESET_CLK)
  724. return 0;
  725. if (command != 0) {
  726. printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
  727. __func__, command);
  728. return -EINVAL;
  729. }
  730. switch (dev->board) {
  731. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  732. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  733. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  734. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  735. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  736. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  737. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  738. /* Tuner Reset Command */
  739. bitmask = 0x04;
  740. break;
  741. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  742. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  743. /* Two identical tuners on two different i2c buses,
  744. * we need to reset the correct gpio. */
  745. if (port->nr == 1)
  746. bitmask = 0x01;
  747. else if (port->nr == 2)
  748. bitmask = 0x04;
  749. break;
  750. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  751. /* Tuner Reset Command */
  752. bitmask = 0x02;
  753. break;
  754. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  755. altera_ci_tuner_reset(dev, port->nr);
  756. break;
  757. }
  758. if (bitmask) {
  759. /* Drive the tuner into reset and back out */
  760. cx_clear(GP0_IO, bitmask);
  761. mdelay(200);
  762. cx_set(GP0_IO, bitmask);
  763. }
  764. return 0;
  765. }
  766. void cx23885_gpio_setup(struct cx23885_dev *dev)
  767. {
  768. switch (dev->board) {
  769. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  770. /* GPIO-0 cx24227 demodulator reset */
  771. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  772. break;
  773. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  774. /* GPIO-0 cx24227 demodulator */
  775. /* GPIO-2 xc3028 tuner */
  776. /* Put the parts into reset */
  777. cx_set(GP0_IO, 0x00050000);
  778. cx_clear(GP0_IO, 0x00000005);
  779. msleep(5);
  780. /* Bring the parts out of reset */
  781. cx_set(GP0_IO, 0x00050005);
  782. break;
  783. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  784. /* GPIO-0 cx24227 demodulator reset */
  785. /* GPIO-2 xc5000 tuner reset */
  786. cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
  787. break;
  788. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  789. /* GPIO-0 656_CLK */
  790. /* GPIO-1 656_D0 */
  791. /* GPIO-2 8295A Reset */
  792. /* GPIO-3-10 cx23417 data0-7 */
  793. /* GPIO-11-14 cx23417 addr0-3 */
  794. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  795. /* GPIO-19 IR_RX */
  796. /* CX23417 GPIO's */
  797. /* EIO15 Zilog Reset */
  798. /* EIO14 S5H1409/CX24227 Reset */
  799. mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
  800. /* Put the demod into reset and protect the eeprom */
  801. mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
  802. mdelay(100);
  803. /* Bring the demod and blaster out of reset */
  804. mc417_gpio_set(dev, GPIO_15 | GPIO_14);
  805. mdelay(100);
  806. /* Force the TDA8295A into reset and back */
  807. cx23885_gpio_enable(dev, GPIO_2, 1);
  808. cx23885_gpio_set(dev, GPIO_2);
  809. mdelay(20);
  810. cx23885_gpio_clear(dev, GPIO_2);
  811. mdelay(20);
  812. cx23885_gpio_set(dev, GPIO_2);
  813. mdelay(20);
  814. break;
  815. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  816. /* GPIO-0 tda10048 demodulator reset */
  817. /* GPIO-2 tda18271 tuner reset */
  818. /* Put the parts into reset and back */
  819. cx_set(GP0_IO, 0x00050000);
  820. mdelay(20);
  821. cx_clear(GP0_IO, 0x00000005);
  822. mdelay(20);
  823. cx_set(GP0_IO, 0x00050005);
  824. break;
  825. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  826. /* GPIO-0 TDA10048 demodulator reset */
  827. /* GPIO-2 TDA8295A Reset */
  828. /* GPIO-3-10 cx23417 data0-7 */
  829. /* GPIO-11-14 cx23417 addr0-3 */
  830. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  831. /* The following GPIO's are on the interna AVCore (cx25840) */
  832. /* GPIO-19 IR_RX */
  833. /* GPIO-20 IR_TX 416/DVBT Select */
  834. /* GPIO-21 IIS DAT */
  835. /* GPIO-22 IIS WCLK */
  836. /* GPIO-23 IIS BCLK */
  837. /* Put the parts into reset and back */
  838. cx_set(GP0_IO, 0x00050000);
  839. mdelay(20);
  840. cx_clear(GP0_IO, 0x00000005);
  841. mdelay(20);
  842. cx_set(GP0_IO, 0x00050005);
  843. break;
  844. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  845. /* GPIO-0 Dibcom7000p demodulator reset */
  846. /* GPIO-2 xc3028L tuner reset */
  847. /* GPIO-13 LED */
  848. /* Put the parts into reset and back */
  849. cx_set(GP0_IO, 0x00050000);
  850. mdelay(20);
  851. cx_clear(GP0_IO, 0x00000005);
  852. mdelay(20);
  853. cx_set(GP0_IO, 0x00050005);
  854. break;
  855. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  856. /* GPIO-0 xc5000 tuner reset i2c bus 0 */
  857. /* GPIO-1 s5h1409 demod reset i2c bus 0 */
  858. /* GPIO-2 xc5000 tuner reset i2c bus 1 */
  859. /* GPIO-3 s5h1409 demod reset i2c bus 0 */
  860. /* Put the parts into reset and back */
  861. cx_set(GP0_IO, 0x000f0000);
  862. mdelay(20);
  863. cx_clear(GP0_IO, 0x0000000f);
  864. mdelay(20);
  865. cx_set(GP0_IO, 0x000f000f);
  866. break;
  867. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  868. /* GPIO-0 portb xc3028 reset */
  869. /* GPIO-1 portb zl10353 reset */
  870. /* GPIO-2 portc xc3028 reset */
  871. /* GPIO-3 portc zl10353 reset */
  872. /* Put the parts into reset and back */
  873. cx_set(GP0_IO, 0x000f0000);
  874. mdelay(20);
  875. cx_clear(GP0_IO, 0x0000000f);
  876. mdelay(20);
  877. cx_set(GP0_IO, 0x000f000f);
  878. break;
  879. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  880. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  881. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  882. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  883. /* GPIO-2 xc3028 tuner reset */
  884. /* The following GPIO's are on the internal AVCore (cx25840) */
  885. /* GPIO-? zl10353 demod reset */
  886. /* Put the parts into reset and back */
  887. cx_set(GP0_IO, 0x00040000);
  888. mdelay(20);
  889. cx_clear(GP0_IO, 0x00000004);
  890. mdelay(20);
  891. cx_set(GP0_IO, 0x00040004);
  892. break;
  893. case CX23885_BOARD_TBS_6920:
  894. cx_write(MC417_CTL, 0x00000036);
  895. cx_write(MC417_OEN, 0x00001000);
  896. cx_set(MC417_RWD, 0x00000002);
  897. mdelay(200);
  898. cx_clear(MC417_RWD, 0x00000800);
  899. mdelay(200);
  900. cx_set(MC417_RWD, 0x00000800);
  901. mdelay(200);
  902. break;
  903. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  904. /* GPIO-0 INTA from CiMax1
  905. GPIO-1 INTB from CiMax2
  906. GPIO-2 reset chips
  907. GPIO-3 to GPIO-10 data/addr for CA
  908. GPIO-11 ~CS0 to CiMax1
  909. GPIO-12 ~CS1 to CiMax2
  910. GPIO-13 ADL0 load LSB addr
  911. GPIO-14 ADL1 load MSB addr
  912. GPIO-15 ~RDY from CiMax
  913. GPIO-17 ~RD to CiMax
  914. GPIO-18 ~WR to CiMax
  915. */
  916. cx_set(GP0_IO, 0x00040000); /* GPIO as out */
  917. /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
  918. cx_clear(GP0_IO, 0x00030004);
  919. mdelay(100);/* reset delay */
  920. cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
  921. cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
  922. /* GPIO-15 IN as ~ACK, rest as OUT */
  923. cx_write(MC417_OEN, 0x00001000);
  924. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  925. cx_write(MC417_RWD, 0x0000c300);
  926. /* enable irq */
  927. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  928. break;
  929. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  930. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  931. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  932. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  933. /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
  934. /* GPIO-6 I2C Gate which can isolate the demod from the bus */
  935. /* GPIO-9 Demod reset */
  936. /* Put the parts into reset and back */
  937. cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
  938. cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
  939. cx23885_gpio_clear(dev, GPIO_9);
  940. mdelay(20);
  941. cx23885_gpio_set(dev, GPIO_9);
  942. break;
  943. case CX23885_BOARD_MYGICA_X8506:
  944. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  945. /* GPIO-0 (0)Analog / (1)Digital TV */
  946. /* GPIO-1 reset XC5000 */
  947. /* GPIO-2 reset LGS8GL5 / LGS8G75 */
  948. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
  949. cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
  950. mdelay(100);
  951. cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
  952. mdelay(100);
  953. break;
  954. case CX23885_BOARD_MYGICA_X8558PRO:
  955. /* GPIO-0 reset first ATBM8830 */
  956. /* GPIO-1 reset second ATBM8830 */
  957. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
  958. cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
  959. mdelay(100);
  960. cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
  961. mdelay(100);
  962. break;
  963. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  964. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  965. /* GPIO-0 656_CLK */
  966. /* GPIO-1 656_D0 */
  967. /* GPIO-2 Wake# */
  968. /* GPIO-3-10 cx23417 data0-7 */
  969. /* GPIO-11-14 cx23417 addr0-3 */
  970. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  971. /* GPIO-19 IR_RX */
  972. /* GPIO-20 C_IR_TX */
  973. /* GPIO-21 I2S DAT */
  974. /* GPIO-22 I2S WCLK */
  975. /* GPIO-23 I2S BCLK */
  976. /* ALT GPIO: EXP GPIO LATCH */
  977. /* CX23417 GPIO's */
  978. /* GPIO-14 S5H1411/CX24228 Reset */
  979. /* GPIO-13 EEPROM write protect */
  980. mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
  981. /* Put the demod into reset and protect the eeprom */
  982. mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
  983. mdelay(100);
  984. /* Bring the demod out of reset */
  985. mc417_gpio_set(dev, GPIO_14);
  986. mdelay(100);
  987. /* CX24228 GPIO */
  988. /* Connected to IF / Mux */
  989. break;
  990. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  991. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  992. break;
  993. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  994. /* GPIO-0 ~INT in
  995. GPIO-1 TMS out
  996. GPIO-2 ~reset chips out
  997. GPIO-3 to GPIO-10 data/addr for CA in/out
  998. GPIO-11 ~CS out
  999. GPIO-12 ADDR out
  1000. GPIO-13 ~WR out
  1001. GPIO-14 ~RD out
  1002. GPIO-15 ~RDY in
  1003. GPIO-16 TCK out
  1004. GPIO-17 TDO in
  1005. GPIO-18 TDI out
  1006. */
  1007. cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
  1008. /* GPIO-0 as INT, reset & TMS low */
  1009. cx_clear(GP0_IO, 0x00010006);
  1010. mdelay(100);/* reset delay */
  1011. cx_set(GP0_IO, 0x00000004); /* reset high */
  1012. cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
  1013. /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
  1014. cx_write(MC417_OEN, 0x00005000);
  1015. /* ~RD, ~WR high; ADDR low; ~CS high */
  1016. cx_write(MC417_RWD, 0x00000d00);
  1017. /* enable irq */
  1018. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  1019. break;
  1020. }
  1021. }
  1022. int cx23885_ir_init(struct cx23885_dev *dev)
  1023. {
  1024. static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
  1025. {
  1026. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1027. .pin = CX23885_PIN_IR_RX_GPIO19,
  1028. .function = CX23885_PAD_IR_RX,
  1029. .value = 0,
  1030. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1031. }, {
  1032. .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
  1033. .pin = CX23885_PIN_IR_TX_GPIO20,
  1034. .function = CX23885_PAD_IR_TX,
  1035. .value = 0,
  1036. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1037. }
  1038. };
  1039. const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
  1040. static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
  1041. {
  1042. .flags = V4L2_SUBDEV_IO_PIN_INPUT,
  1043. .pin = CX23885_PIN_IR_RX_GPIO19,
  1044. .function = CX23885_PAD_IR_RX,
  1045. .value = 0,
  1046. .strength = CX25840_PIN_DRIVE_MEDIUM,
  1047. }
  1048. };
  1049. const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
  1050. struct v4l2_subdev_ir_parameters params;
  1051. int ret = 0;
  1052. switch (dev->board) {
  1053. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1054. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1055. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1056. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1057. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1058. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1059. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1060. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1061. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1062. /* FIXME: Implement me */
  1063. break;
  1064. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1065. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1066. ret = cx23888_ir_probe(dev);
  1067. if (ret)
  1068. break;
  1069. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  1070. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1071. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1072. /*
  1073. * For these boards we need to invert the Tx output via the
  1074. * IR controller to have the LED off while idle
  1075. */
  1076. v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
  1077. params.enable = false;
  1078. params.shutdown = false;
  1079. params.invert_level = true;
  1080. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1081. params.shutdown = true;
  1082. v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
  1083. break;
  1084. case CX23885_BOARD_TEVII_S470:
  1085. if (!enable_885_ir)
  1086. break;
  1087. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1088. if (dev->sd_ir == NULL) {
  1089. ret = -ENODEV;
  1090. break;
  1091. }
  1092. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1093. ir_rx_pin_cfg_count, ir_rx_pin_cfg);
  1094. break;
  1095. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1096. if (!enable_885_ir)
  1097. break;
  1098. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
  1099. if (dev->sd_ir == NULL) {
  1100. ret = -ENODEV;
  1101. break;
  1102. }
  1103. v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
  1104. ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
  1105. break;
  1106. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1107. request_module("ir-kbd-i2c");
  1108. break;
  1109. }
  1110. return ret;
  1111. }
  1112. void cx23885_ir_fini(struct cx23885_dev *dev)
  1113. {
  1114. switch (dev->board) {
  1115. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1116. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1117. cx23885_irq_remove(dev, PCI_MSK_IR);
  1118. cx23888_ir_remove(dev);
  1119. dev->sd_ir = NULL;
  1120. break;
  1121. case CX23885_BOARD_TEVII_S470:
  1122. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1123. cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
  1124. /* sd_ir is a duplicate pointer to the AV Core, just clear it */
  1125. dev->sd_ir = NULL;
  1126. break;
  1127. }
  1128. }
  1129. int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
  1130. {
  1131. int data;
  1132. int tdo = 0;
  1133. struct cx23885_dev *dev = (struct cx23885_dev *)device;
  1134. /*TMS*/
  1135. data = ((cx_read(GP0_IO)) & (~0x00000002));
  1136. data |= (tms ? 0x00020002 : 0x00020000);
  1137. cx_write(GP0_IO, data);
  1138. /*TDI*/
  1139. data = ((cx_read(MC417_RWD)) & (~0x0000a000));
  1140. data |= (tdi ? 0x00008000 : 0);
  1141. cx_write(MC417_RWD, data);
  1142. if (read_tdo)
  1143. tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
  1144. cx_write(MC417_RWD, data | 0x00002000);
  1145. udelay(1);
  1146. /*TCK*/
  1147. cx_write(MC417_RWD, data);
  1148. return tdo;
  1149. }
  1150. void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
  1151. {
  1152. switch (dev->board) {
  1153. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1154. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1155. if (dev->sd_ir)
  1156. cx23885_irq_add_enable(dev, PCI_MSK_IR);
  1157. break;
  1158. case CX23885_BOARD_TEVII_S470:
  1159. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1160. if (dev->sd_ir)
  1161. cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
  1162. break;
  1163. }
  1164. }
  1165. void cx23885_card_setup(struct cx23885_dev *dev)
  1166. {
  1167. struct cx23885_tsport *ts1 = &dev->ts1;
  1168. struct cx23885_tsport *ts2 = &dev->ts2;
  1169. static u8 eeprom[256];
  1170. if (dev->i2c_bus[0].i2c_rc == 0) {
  1171. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  1172. tveeprom_read(&dev->i2c_bus[0].i2c_client,
  1173. eeprom, sizeof(eeprom));
  1174. }
  1175. switch (dev->board) {
  1176. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1177. if (dev->i2c_bus[0].i2c_rc == 0) {
  1178. if (eeprom[0x80] != 0x84)
  1179. hauppauge_eeprom(dev, eeprom+0xc0);
  1180. else
  1181. hauppauge_eeprom(dev, eeprom+0x80);
  1182. }
  1183. break;
  1184. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1185. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1186. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1187. if (dev->i2c_bus[0].i2c_rc == 0)
  1188. hauppauge_eeprom(dev, eeprom+0x80);
  1189. break;
  1190. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1191. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1192. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1193. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1194. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1195. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1196. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1197. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1198. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1199. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1200. if (dev->i2c_bus[0].i2c_rc == 0)
  1201. hauppauge_eeprom(dev, eeprom+0xc0);
  1202. break;
  1203. }
  1204. switch (dev->board) {
  1205. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  1206. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  1207. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1208. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1209. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1210. /* break omitted intentionally */
  1211. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  1212. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1213. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1214. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1215. break;
  1216. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1217. /* Defaults for VID B - Analog encoder */
  1218. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  1219. ts1->gen_ctrl_val = 0x10e;
  1220. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1221. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1222. /* APB_TSVALERR_POL (active low)*/
  1223. ts1->vld_misc_val = 0x2000;
  1224. ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
  1225. /* Defaults for VID C */
  1226. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1227. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1228. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1229. break;
  1230. case CX23885_BOARD_TBS_6920:
  1231. ts1->gen_ctrl_val = 0x4; /* Parallel */
  1232. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1233. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1234. break;
  1235. case CX23885_BOARD_TEVII_S470:
  1236. case CX23885_BOARD_DVBWORLD_2005:
  1237. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1238. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1239. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1240. break;
  1241. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1242. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1243. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1244. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1245. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1246. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1247. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1248. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1249. break;
  1250. case CX23885_BOARD_MYGICA_X8506:
  1251. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1252. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1253. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1254. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1255. break;
  1256. case CX23885_BOARD_MYGICA_X8558PRO:
  1257. ts1->gen_ctrl_val = 0x5; /* Parallel */
  1258. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1259. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1260. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1261. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1262. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1263. break;
  1264. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1265. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  1266. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  1267. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1268. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  1269. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1270. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  1271. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1272. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1273. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  1274. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  1275. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  1276. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  1277. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1278. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1279. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1280. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1281. default:
  1282. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  1283. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  1284. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  1285. }
  1286. /* Certain boards support analog, or require the avcore to be
  1287. * loaded, ensure this happens.
  1288. */
  1289. switch (dev->board) {
  1290. case CX23885_BOARD_TEVII_S470:
  1291. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  1292. /* Currently only enabled for the integrated IR controller */
  1293. if (!enable_885_ir)
  1294. break;
  1295. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  1296. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  1297. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  1298. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  1299. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  1300. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1301. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
  1302. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  1303. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  1304. case CX23885_BOARD_MYGICA_X8506:
  1305. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  1306. case CX23885_BOARD_HAUPPAUGE_HVR1290:
  1307. case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
  1308. case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
  1309. dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
  1310. &dev->i2c_bus[2].i2c_adap,
  1311. "cx25840", 0x88 >> 1, NULL);
  1312. if (dev->sd_cx25840) {
  1313. dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
  1314. v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
  1315. }
  1316. break;
  1317. }
  1318. /* AUX-PLL 27MHz CLK */
  1319. switch (dev->board) {
  1320. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  1321. netup_initialize(dev);
  1322. break;
  1323. case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
  1324. int ret;
  1325. const struct firmware *fw;
  1326. const char *filename = "dvb-netup-altera-01.fw";
  1327. char *action = "configure";
  1328. struct altera_config netup_config = {
  1329. .dev = dev,
  1330. .action = action,
  1331. .jtag_io = netup_jtag_io,
  1332. };
  1333. netup_initialize(dev);
  1334. ret = request_firmware(&fw, filename, &dev->pci->dev);
  1335. if (ret != 0)
  1336. printk(KERN_ERR "did not find the firmware file. (%s) "
  1337. "Please see linux/Documentation/dvb/ for more details "
  1338. "on firmware-problems.", filename);
  1339. else
  1340. altera_init(&netup_config, fw);
  1341. release_firmware(fw);
  1342. break;
  1343. }
  1344. }
  1345. }
  1346. /* ------------------------------------------------------------------ */