s1d13xxxfb.c 20 KB

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  1. /* drivers/video/s1d13xxxfb.c
  2. *
  3. * (c) 2004 Simtec Electronics
  4. * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
  5. *
  6. * Driver for Epson S1D13xxx series framebuffer chips
  7. *
  8. * Adapted from
  9. * linux/drivers/video/skeletonfb.c
  10. * linux/drivers/video/epson1355fb.c
  11. * linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson)
  12. *
  13. * Note, currently only tested on S1D13806 with 16bit CRT.
  14. * As such, this driver might still contain some hardcoded bits relating to
  15. * S1D13806.
  16. * Making it work on other S1D13XXX chips should merely be a matter of adding
  17. * a few switch()s, some missing glue here and there maybe, and split header
  18. * files.
  19. *
  20. * TODO: - handle dual screen display (CRT and LCD at the same time).
  21. * - check_var(), mode change, etc.
  22. * - PM untested.
  23. * - Accelerated interfaces.
  24. * - Probably not SMP safe :)
  25. *
  26. * This file is subject to the terms and conditions of the GNU General Public
  27. * License. See the file COPYING in the main directory of this archive for
  28. * more details.
  29. */
  30. #include <linux/config.h>
  31. #include <linux/module.h>
  32. #include <linux/device.h>
  33. #include <linux/delay.h>
  34. #include <linux/types.h>
  35. #include <linux/errno.h>
  36. #include <linux/mm.h>
  37. #include <linux/mman.h>
  38. #include <linux/fb.h>
  39. #include <asm/io.h>
  40. #include <video/s1d13xxxfb.h>
  41. #define PFX "s1d13xxxfb: "
  42. #if 0
  43. #define dbg(fmt, args...) do { printk(KERN_INFO fmt, ## args); } while(0)
  44. #else
  45. #define dbg(fmt, args...) do { } while (0)
  46. #endif
  47. /*
  48. * Here we define the default struct fb_fix_screeninfo
  49. */
  50. static struct fb_fix_screeninfo __devinitdata s1d13xxxfb_fix = {
  51. .id = S1D_FBID,
  52. .type = FB_TYPE_PACKED_PIXELS,
  53. .visual = FB_VISUAL_PSEUDOCOLOR,
  54. .xpanstep = 0,
  55. .ypanstep = 1,
  56. .ywrapstep = 0,
  57. .accel = FB_ACCEL_NONE,
  58. };
  59. static inline u8
  60. s1d13xxxfb_readreg(struct s1d13xxxfb_par *par, u16 regno)
  61. {
  62. #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
  63. regno=((regno & 1) ? (regno & ~1L) : (regno + 1));
  64. #endif
  65. return readb(par->regs + regno);
  66. }
  67. static inline void
  68. s1d13xxxfb_writereg(struct s1d13xxxfb_par *par, u16 regno, u8 value)
  69. {
  70. #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
  71. regno=((regno & 1) ? (regno & ~1L) : (regno + 1));
  72. #endif
  73. writeb(value, par->regs + regno);
  74. }
  75. static inline void
  76. s1d13xxxfb_runinit(struct s1d13xxxfb_par *par,
  77. const struct s1d13xxxfb_regval *initregs,
  78. const unsigned int size)
  79. {
  80. int i;
  81. for (i = 0; i < size; i++) {
  82. if ((initregs[i].addr == S1DREG_DELAYOFF) ||
  83. (initregs[i].addr == S1DREG_DELAYON))
  84. mdelay((int)initregs[i].value);
  85. else {
  86. s1d13xxxfb_writereg(par, initregs[i].addr, initregs[i].value);
  87. }
  88. }
  89. /* make sure the hardware can cope with us */
  90. mdelay(1);
  91. }
  92. static inline void
  93. lcd_enable(struct s1d13xxxfb_par *par, int enable)
  94. {
  95. u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
  96. if (enable)
  97. mode |= 0x01;
  98. else
  99. mode &= ~0x01;
  100. s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
  101. }
  102. static inline void
  103. crt_enable(struct s1d13xxxfb_par *par, int enable)
  104. {
  105. u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
  106. if (enable)
  107. mode |= 0x02;
  108. else
  109. mode &= ~0x02;
  110. s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
  111. }
  112. /* framebuffer control routines */
  113. static inline void
  114. s1d13xxxfb_setup_pseudocolour(struct fb_info *info)
  115. {
  116. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  117. info->var.red.length = 4;
  118. info->var.green.length = 4;
  119. info->var.blue.length = 4;
  120. }
  121. static inline void
  122. s1d13xxxfb_setup_truecolour(struct fb_info *info)
  123. {
  124. info->fix.visual = FB_VISUAL_TRUECOLOR;
  125. info->var.bits_per_pixel = 16;
  126. info->var.red.length = 5;
  127. info->var.red.offset = 11;
  128. info->var.green.length = 6;
  129. info->var.green.offset = 5;
  130. info->var.blue.length = 5;
  131. info->var.blue.offset = 0;
  132. }
  133. /**
  134. * s1d13xxxfb_set_par - Alters the hardware state.
  135. * @info: frame buffer structure
  136. *
  137. * Using the fb_var_screeninfo in fb_info we set the depth of the
  138. * framebuffer. This function alters the par AND the
  139. * fb_fix_screeninfo stored in fb_info. It doesn't not alter var in
  140. * fb_info since we are using that data. This means we depend on the
  141. * data in var inside fb_info to be supported by the hardware.
  142. * xxxfb_check_var is always called before xxxfb_set_par to ensure this.
  143. *
  144. * XXX TODO: write proper s1d13xxxfb_check_var(), without which that
  145. * function is quite useless.
  146. */
  147. static int
  148. s1d13xxxfb_set_par(struct fb_info *info)
  149. {
  150. struct s1d13xxxfb_par *s1dfb = info->par;
  151. unsigned int val;
  152. dbg("s1d13xxxfb_set_par: bpp=%d\n", info->var.bits_per_pixel);
  153. if ((s1dfb->display & 0x01)) /* LCD */
  154. val = s1d13xxxfb_readreg(s1dfb, S1DREG_LCD_DISP_MODE); /* read colour control */
  155. else /* CRT */
  156. val = s1d13xxxfb_readreg(s1dfb, S1DREG_CRT_DISP_MODE); /* read colour control */
  157. val &= ~0x07;
  158. switch (info->var.bits_per_pixel) {
  159. case 4:
  160. dbg("pseudo colour 4\n");
  161. s1d13xxxfb_setup_pseudocolour(info);
  162. val |= 2;
  163. break;
  164. case 8:
  165. dbg("pseudo colour 8\n");
  166. s1d13xxxfb_setup_pseudocolour(info);
  167. val |= 3;
  168. break;
  169. case 16:
  170. dbg("true colour\n");
  171. s1d13xxxfb_setup_truecolour(info);
  172. val |= 5;
  173. break;
  174. default:
  175. dbg("bpp not supported!\n");
  176. return -EINVAL;
  177. }
  178. dbg("writing %02x to display mode register\n", val);
  179. if ((s1dfb->display & 0x01)) /* LCD */
  180. s1d13xxxfb_writereg(s1dfb, S1DREG_LCD_DISP_MODE, val);
  181. else /* CRT */
  182. s1d13xxxfb_writereg(s1dfb, S1DREG_CRT_DISP_MODE, val);
  183. info->fix.line_length = info->var.xres * info->var.bits_per_pixel;
  184. info->fix.line_length /= 8;
  185. dbg("setting line_length to %d\n", info->fix.line_length);
  186. dbg("done setup\n");
  187. return 0;
  188. }
  189. /**
  190. * s1d13xxxfb_setcolreg - sets a color register.
  191. * @regno: Which register in the CLUT we are programming
  192. * @red: The red value which can be up to 16 bits wide
  193. * @green: The green value which can be up to 16 bits wide
  194. * @blue: The blue value which can be up to 16 bits wide.
  195. * @transp: If supported the alpha value which can be up to 16 bits wide.
  196. * @info: frame buffer info structure
  197. *
  198. * Returns negative errno on error, or zero on success.
  199. */
  200. static int
  201. s1d13xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  202. u_int transp, struct fb_info *info)
  203. {
  204. struct s1d13xxxfb_par *s1dfb = info->par;
  205. unsigned int pseudo_val;
  206. if (regno >= S1D_PALETTE_SIZE)
  207. return -EINVAL;
  208. dbg("s1d13xxxfb_setcolreg: %d: rgb=%d,%d,%d, tr=%d\n",
  209. regno, red, green, blue, transp);
  210. if (info->var.grayscale)
  211. red = green = blue = (19595*red + 38470*green + 7471*blue) >> 16;
  212. switch (info->fix.visual) {
  213. case FB_VISUAL_TRUECOLOR:
  214. if (regno >= 16)
  215. return -EINVAL;
  216. /* deal with creating pseudo-palette entries */
  217. pseudo_val = (red >> 11) << info->var.red.offset;
  218. pseudo_val |= (green >> 10) << info->var.green.offset;
  219. pseudo_val |= (blue >> 11) << info->var.blue.offset;
  220. dbg("s1d13xxxfb_setcolreg: pseudo %d, val %08x\n",
  221. regno, pseudo_val);
  222. #if defined(CONFIG_PLAT_MAPPI)
  223. ((u32 *)info->pseudo_palette)[regno] = cpu_to_le16(pseudo_val);
  224. #else
  225. ((u32 *)info->pseudo_palette)[regno] = pseudo_val;
  226. #endif
  227. break;
  228. case FB_VISUAL_PSEUDOCOLOR:
  229. s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_ADDR, regno);
  230. s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, red);
  231. s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, green);
  232. s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, blue);
  233. break;
  234. default:
  235. return -ENOSYS;
  236. }
  237. dbg("s1d13xxxfb_setcolreg: done\n");
  238. return 0;
  239. }
  240. /**
  241. * s1d13xxxfb_blank - blanks the display.
  242. * @blank_mode: the blank mode we want.
  243. * @info: frame buffer structure that represents a single frame buffer
  244. *
  245. * Blank the screen if blank_mode != 0, else unblank. Return 0 if
  246. * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
  247. * video mode which doesn't support it. Implements VESA suspend
  248. * and powerdown modes on hardware that supports disabling hsync/vsync:
  249. * blank_mode == 2: suspend vsync
  250. * blank_mode == 3: suspend hsync
  251. * blank_mode == 4: powerdown
  252. *
  253. * Returns negative errno on error, or zero on success.
  254. */
  255. static int
  256. s1d13xxxfb_blank(int blank_mode, struct fb_info *info)
  257. {
  258. struct s1d13xxxfb_par *par = info->par;
  259. dbg("s1d13xxxfb_blank: blank=%d, info=%p\n", blank_mode, info);
  260. switch (blank_mode) {
  261. case FB_BLANK_UNBLANK:
  262. case FB_BLANK_NORMAL:
  263. if ((par->display & 0x01) != 0)
  264. lcd_enable(par, 1);
  265. if ((par->display & 0x02) != 0)
  266. crt_enable(par, 1);
  267. break;
  268. case FB_BLANK_VSYNC_SUSPEND:
  269. case FB_BLANK_HSYNC_SUSPEND:
  270. break;
  271. case FB_BLANK_POWERDOWN:
  272. lcd_enable(par, 0);
  273. crt_enable(par, 0);
  274. break;
  275. default:
  276. return -EINVAL;
  277. }
  278. /* let fbcon do a soft blank for us */
  279. return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
  280. }
  281. /**
  282. * s1d13xxxfb_pan_display - Pans the display.
  283. * @var: frame buffer variable screen structure
  284. * @info: frame buffer structure that represents a single frame buffer
  285. *
  286. * Pan (or wrap, depending on the `vmode' field) the display using the
  287. * `yoffset' field of the `var' structure (`xoffset' not yet supported).
  288. * If the values don't fit, return -EINVAL.
  289. *
  290. * Returns negative errno on error, or zero on success.
  291. */
  292. static int
  293. s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
  294. {
  295. struct s1d13xxxfb_par *par = info->par;
  296. u32 start;
  297. if (var->xoffset != 0) /* not yet ... */
  298. return -EINVAL;
  299. if (var->yoffset + info->var.yres > info->var.yres_virtual)
  300. return -EINVAL;
  301. start = (info->fix.line_length >> 1) * var->yoffset;
  302. if ((par->display & 0x01)) {
  303. /* LCD */
  304. s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START0, (start & 0xff));
  305. s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START1, ((start >> 8) & 0xff));
  306. s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START2, ((start >> 16) & 0x0f));
  307. } else {
  308. /* CRT */
  309. s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START0, (start & 0xff));
  310. s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START1, ((start >> 8) & 0xff));
  311. s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START2, ((start >> 16) & 0x0f));
  312. }
  313. return 0;
  314. }
  315. /* framebuffer information structures */
  316. static struct fb_ops s1d13xxxfb_fbops = {
  317. .owner = THIS_MODULE,
  318. .fb_set_par = s1d13xxxfb_set_par,
  319. .fb_setcolreg = s1d13xxxfb_setcolreg,
  320. .fb_blank = s1d13xxxfb_blank,
  321. .fb_pan_display = s1d13xxxfb_pan_display,
  322. /* to be replaced by any acceleration we can */
  323. .fb_fillrect = cfb_fillrect,
  324. .fb_copyarea = cfb_copyarea,
  325. .fb_imageblit = cfb_imageblit,
  326. .fb_cursor = soft_cursor
  327. };
  328. static int s1d13xxxfb_width_tab[2][4] __devinitdata = {
  329. {4, 8, 16, -1},
  330. {9, 12, 18, -1},
  331. };
  332. /**
  333. * s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to
  334. * hardware setup.
  335. * @info: frame buffer structure
  336. *
  337. * We setup the framebuffer structures according to the current
  338. * hardware setup. On some machines, the BIOS will have filled
  339. * the chip registers with such info, on others, these values will
  340. * have been written in some init procedure. In any case, the
  341. * software values needs to match the hardware ones. This is what
  342. * this function ensures.
  343. *
  344. * Note: some of the hardcoded values here might need some love to
  345. * work on various chips, and might need to no longer be hardcoded.
  346. */
  347. static void __devinit
  348. s1d13xxxfb_fetch_hw_state(struct fb_info *info)
  349. {
  350. struct fb_var_screeninfo *var = &info->var;
  351. struct fb_fix_screeninfo *fix = &info->fix;
  352. struct s1d13xxxfb_par *par = info->par;
  353. u8 panel, display;
  354. u16 offset;
  355. u32 xres, yres;
  356. u32 xres_virtual, yres_virtual;
  357. int bpp, lcd_bpp;
  358. int is_color, is_dual, is_tft;
  359. int lcd_enabled, crt_enabled;
  360. fix->type = FB_TYPE_PACKED_PIXELS;
  361. /* general info */
  362. par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
  363. crt_enabled = (par->display & 0x02) != 0;
  364. lcd_enabled = (par->display & 0x01) != 0;
  365. if (lcd_enabled && crt_enabled)
  366. printk(KERN_WARNING PFX "Warning: LCD and CRT detected, using LCD\n");
  367. if (lcd_enabled)
  368. display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE);
  369. else /* CRT */
  370. display = s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_MODE);
  371. bpp = display & 0x07;
  372. switch (bpp) {
  373. case 2: /* 4 bpp */
  374. case 3: /* 8 bpp */
  375. var->bits_per_pixel = 8;
  376. var->red.offset = var->green.offset = var->blue.offset = 0;
  377. var->red.length = var->green.length = var->blue.length = 8;
  378. break;
  379. case 5: /* 16 bpp */
  380. s1d13xxxfb_setup_truecolour(info);
  381. break;
  382. default:
  383. dbg("bpp: %i\n", bpp);
  384. }
  385. fb_alloc_cmap(&info->cmap, 256, 0);
  386. /* LCD info */
  387. panel = s1d13xxxfb_readreg(par, S1DREG_PANEL_TYPE);
  388. is_color = (panel & 0x04) != 0;
  389. is_dual = (panel & 0x02) != 0;
  390. is_tft = (panel & 0x01) != 0;
  391. lcd_bpp = s1d13xxxfb_width_tab[is_tft][(panel >> 4) & 3];
  392. if (lcd_enabled) {
  393. xres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_HWIDTH) + 1) * 8;
  394. yres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT0) +
  395. ((s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT1) & 0x03) << 8) + 1);
  396. offset = (s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF0) +
  397. ((s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF1) & 0x7) << 8));
  398. } else { /* crt */
  399. xres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_HWIDTH) + 1) * 8;
  400. yres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT0) +
  401. ((s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT1) & 0x03) << 8) + 1);
  402. offset = (s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF0) +
  403. ((s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF1) & 0x7) << 8));
  404. }
  405. xres_virtual = offset * 16 / var->bits_per_pixel;
  406. yres_virtual = fix->smem_len / (offset * 2);
  407. var->xres = xres;
  408. var->yres = yres;
  409. var->xres_virtual = xres_virtual;
  410. var->yres_virtual = yres_virtual;
  411. var->xoffset = var->yoffset = 0;
  412. fix->line_length = offset * 2;
  413. var->grayscale = !is_color;
  414. var->activate = FB_ACTIVATE_NOW;
  415. dbg(PFX "bpp=%d, lcd_bpp=%d, "
  416. "crt_enabled=%d, lcd_enabled=%d\n",
  417. var->bits_per_pixel, lcd_bpp, crt_enabled, lcd_enabled);
  418. dbg(PFX "xres=%d, yres=%d, vxres=%d, vyres=%d "
  419. "is_color=%d, is_dual=%d, is_tft=%d\n",
  420. xres, yres, xres_virtual, yres_virtual, is_color, is_dual, is_tft);
  421. }
  422. static int
  423. s1d13xxxfb_remove(struct device *dev)
  424. {
  425. struct fb_info *info = dev_get_drvdata(dev);
  426. struct platform_device *pdev = to_platform_device(dev);
  427. struct s1d13xxxfb_par *par = NULL;
  428. if (info) {
  429. par = info->par;
  430. if (par && par->regs) {
  431. /* disable output & enable powersave */
  432. s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, 0x00);
  433. s1d13xxxfb_writereg(par, S1DREG_PS_CNF, 0x11);
  434. iounmap(par->regs);
  435. }
  436. fb_dealloc_cmap(&info->cmap);
  437. if (info->screen_base)
  438. iounmap(info->screen_base);
  439. framebuffer_release(info);
  440. }
  441. release_mem_region(pdev->resource[0].start,
  442. pdev->resource[0].end - pdev->resource[0].start +1);
  443. release_mem_region(pdev->resource[1].start,
  444. pdev->resource[1].end - pdev->resource[1].start +1);
  445. return 0;
  446. }
  447. static int __devinit
  448. s1d13xxxfb_probe(struct device *dev)
  449. {
  450. struct platform_device *pdev = to_platform_device(dev);
  451. struct s1d13xxxfb_par *default_par;
  452. struct fb_info *info;
  453. struct s1d13xxxfb_pdata *pdata = NULL;
  454. int ret = 0;
  455. u8 revision;
  456. dbg("probe called: device is %p\n", dev);
  457. printk(KERN_INFO "Epson S1D13XXX FB Driver\n");
  458. /* enable platform-dependent hardware glue, if any */
  459. if (dev->platform_data)
  460. pdata = dev->platform_data;
  461. if (pdata && pdata->platform_init_video)
  462. pdata->platform_init_video();
  463. if (pdev->num_resources != 2) {
  464. dev_err(&pdev->dev, "invalid num_resources: %i\n",
  465. pdev->num_resources);
  466. ret = -ENODEV;
  467. goto bail;
  468. }
  469. /* resource[0] is VRAM, resource[1] is registers */
  470. if (pdev->resource[0].flags != IORESOURCE_MEM
  471. || pdev->resource[1].flags != IORESOURCE_MEM) {
  472. dev_err(&pdev->dev, "invalid resource type\n");
  473. ret = -ENODEV;
  474. goto bail;
  475. }
  476. if (!request_mem_region(pdev->resource[0].start,
  477. pdev->resource[0].end - pdev->resource[0].start +1, "s1d13xxxfb mem")) {
  478. dev_dbg(dev, "request_mem_region failed\n");
  479. ret = -EBUSY;
  480. goto bail;
  481. }
  482. if (!request_mem_region(pdev->resource[1].start,
  483. pdev->resource[1].end - pdev->resource[1].start +1, "s1d13xxxfb regs")) {
  484. dev_dbg(dev, "request_mem_region failed\n");
  485. ret = -EBUSY;
  486. goto bail;
  487. }
  488. info = framebuffer_alloc(sizeof(struct s1d13xxxfb_par) + sizeof(u32) * 256, &pdev->dev);
  489. if (!info) {
  490. ret = -ENOMEM;
  491. goto bail;
  492. }
  493. default_par = info->par;
  494. default_par->regs = ioremap_nocache(pdev->resource[1].start,
  495. pdev->resource[1].end - pdev->resource[1].start +1);
  496. if (!default_par->regs) {
  497. printk(KERN_ERR PFX "unable to map registers\n");
  498. ret = -ENOMEM;
  499. goto bail;
  500. }
  501. info->pseudo_palette = default_par->pseudo_palette;
  502. info->screen_base = ioremap_nocache(pdev->resource[0].start,
  503. pdev->resource[0].end - pdev->resource[0].start +1);
  504. if (!info->screen_base) {
  505. printk(KERN_ERR PFX "unable to map framebuffer\n");
  506. ret = -ENOMEM;
  507. goto bail;
  508. }
  509. revision = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE);
  510. if ((revision >> 2) != S1D_CHIP_REV) {
  511. printk(KERN_INFO PFX "chip not found: %i\n", (revision >> 2));
  512. ret = -ENODEV;
  513. goto bail;
  514. }
  515. info->fix = s1d13xxxfb_fix;
  516. info->fix.mmio_start = pdev->resource[1].start;
  517. info->fix.mmio_len = pdev->resource[1].end - pdev->resource[1].start +1;
  518. info->fix.smem_start = pdev->resource[0].start;
  519. info->fix.smem_len = pdev->resource[0].end - pdev->resource[0].start +1;
  520. printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n",
  521. default_par->regs, info->fix.smem_len / 1024, info->screen_base);
  522. info->par = default_par;
  523. info->fbops = &s1d13xxxfb_fbops;
  524. info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  525. /* perform "manual" chip initialization, if needed */
  526. if (pdata && pdata->initregs)
  527. s1d13xxxfb_runinit(info->par, pdata->initregs, pdata->initregssize);
  528. s1d13xxxfb_fetch_hw_state(info);
  529. if (register_framebuffer(info) < 0) {
  530. ret = -EINVAL;
  531. goto bail;
  532. }
  533. dev_set_drvdata(&pdev->dev, info);
  534. printk(KERN_INFO "fb%d: %s frame buffer device\n",
  535. info->node, info->fix.id);
  536. return 0;
  537. bail:
  538. s1d13xxxfb_remove(dev);
  539. return ret;
  540. }
  541. #ifdef CONFIG_PM
  542. static int s1d13xxxfb_suspend(struct device *dev, pm_message_t state, u32 level)
  543. {
  544. struct fb_info *info = dev_get_drvdata(dev);
  545. struct s1d13xxxfb_par *s1dfb = info->par;
  546. struct s1d13xxxfb_pdata *pdata = NULL;
  547. /* disable display */
  548. lcd_enable(s1dfb, 0);
  549. crt_enable(s1dfb, 0);
  550. if (dev->platform_data)
  551. pdata = dev->platform_data;
  552. #if 0
  553. if (!s1dfb->disp_save)
  554. s1dfb->disp_save = kmalloc(info->fix.smem_len, GFP_KERNEL);
  555. if (!s1dfb->disp_save) {
  556. printk(KERN_ERR PFX "no memory to save screen");
  557. return -ENOMEM;
  558. }
  559. memcpy_fromio(s1dfb->disp_save, info->screen_base, info->fix.smem_len);
  560. #else
  561. s1dfb->disp_save = NULL;
  562. #endif
  563. if (!s1dfb->regs_save)
  564. s1dfb->regs_save = kmalloc(info->fix.mmio_len, GFP_KERNEL);
  565. if (!s1dfb->regs_save) {
  566. printk(KERN_ERR PFX "no memory to save registers");
  567. return -ENOMEM;
  568. }
  569. /* backup all registers */
  570. memcpy_fromio(s1dfb->regs_save, s1dfb->regs, info->fix.mmio_len);
  571. /* now activate power save mode */
  572. s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x11);
  573. if (pdata && pdata->platform_suspend_video)
  574. return pdata->platform_suspend_video();
  575. else
  576. return 0;
  577. }
  578. static int s1d13xxxfb_resume(struct device *dev, u32 level)
  579. {
  580. struct fb_info *info = dev_get_drvdata(dev);
  581. struct s1d13xxxfb_par *s1dfb = info->par;
  582. struct s1d13xxxfb_pdata *pdata = NULL;
  583. if (level != RESUME_ENABLE)
  584. return 0;
  585. /* awaken the chip */
  586. s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x10);
  587. /* do not let go until SDRAM "wakes up" */
  588. while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01))
  589. udelay(10);
  590. if (dev->platform_data)
  591. pdata = dev->platform_data;
  592. if (s1dfb->regs_save) {
  593. /* will write RO regs, *should* get away with it :) */
  594. memcpy_toio(s1dfb->regs, s1dfb->regs_save, info->fix.mmio_len);
  595. kfree(s1dfb->regs_save);
  596. }
  597. if (s1dfb->disp_save) {
  598. memcpy_toio(info->screen_base, s1dfb->disp_save,
  599. info->fix.smem_len);
  600. kfree(s1dfb->disp_save); /* XXX kmalloc()'d when? */
  601. }
  602. if ((s1dfb->display & 0x01) != 0)
  603. lcd_enable(s1dfb, 1);
  604. if ((s1dfb->display & 0x02) != 0)
  605. crt_enable(s1dfb, 1);
  606. if (pdata && pdata->platform_resume_video)
  607. return pdata->platform_resume_video();
  608. else
  609. return 0;
  610. }
  611. #endif /* CONFIG_PM */
  612. static struct device_driver s1d13xxxfb_driver = {
  613. .name = S1D_DEVICENAME,
  614. .bus = &platform_bus_type,
  615. .probe = s1d13xxxfb_probe,
  616. .remove = s1d13xxxfb_remove,
  617. #ifdef CONFIG_PM
  618. .suspend = s1d13xxxfb_suspend,
  619. .resume = s1d13xxxfb_resume
  620. #endif
  621. };
  622. static int __init
  623. s1d13xxxfb_init(void)
  624. {
  625. if (fb_get_options("s1d13xxxfb", NULL))
  626. return -ENODEV;
  627. return driver_register(&s1d13xxxfb_driver);
  628. }
  629. static void __exit
  630. s1d13xxxfb_exit(void)
  631. {
  632. driver_unregister(&s1d13xxxfb_driver);
  633. }
  634. module_init(s1d13xxxfb_init);
  635. module_exit(s1d13xxxfb_exit);
  636. MODULE_LICENSE("GPL");
  637. MODULE_DESCRIPTION("Framebuffer driver for S1D13xxx devices");
  638. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Thibaut VARENE <varenet@parisc-linux.org>");