ti113x.h 24 KB

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  1. /*
  2. * ti113x.h 1.16 1999/10/25 20:03:34
  3. *
  4. * The contents of this file are subject to the Mozilla Public License
  5. * Version 1.1 (the "License"); you may not use this file except in
  6. * compliance with the License. You may obtain a copy of the License
  7. * at http://www.mozilla.org/MPL/
  8. *
  9. * Software distributed under the License is distributed on an "AS IS"
  10. * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
  11. * the License for the specific language governing rights and
  12. * limitations under the License.
  13. *
  14. * The initial developer of the original code is David A. Hinds
  15. * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
  16. * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
  17. *
  18. * Alternatively, the contents of this file may be used under the
  19. * terms of the GNU General Public License version 2 (the "GPL"), in which
  20. * case the provisions of the GPL are applicable instead of the
  21. * above. If you wish to allow the use of your version of this file
  22. * only under the terms of the GPL and not to allow others to use
  23. * your version of this file under the MPL, indicate your decision by
  24. * deleting the provisions above and replace them with the notice and
  25. * other provisions required by the GPL. If you do not delete the
  26. * provisions above, a recipient may use your version of this file
  27. * under either the MPL or the GPL.
  28. */
  29. #ifndef _LINUX_TI113X_H
  30. #define _LINUX_TI113X_H
  31. #include <linux/config.h>
  32. /* Register definitions for TI 113X PCI-to-CardBus bridges */
  33. /* System Control Register */
  34. #define TI113X_SYSTEM_CONTROL 0x0080 /* 32 bit */
  35. #define TI113X_SCR_SMIROUTE 0x04000000
  36. #define TI113X_SCR_SMISTATUS 0x02000000
  37. #define TI113X_SCR_SMIENB 0x01000000
  38. #define TI113X_SCR_VCCPROT 0x00200000
  39. #define TI113X_SCR_REDUCEZV 0x00100000
  40. #define TI113X_SCR_CDREQEN 0x00080000
  41. #define TI113X_SCR_CDMACHAN 0x00070000
  42. #define TI113X_SCR_SOCACTIVE 0x00002000
  43. #define TI113X_SCR_PWRSTREAM 0x00000800
  44. #define TI113X_SCR_DELAYUP 0x00000400
  45. #define TI113X_SCR_DELAYDOWN 0x00000200
  46. #define TI113X_SCR_INTERROGATE 0x00000100
  47. #define TI113X_SCR_CLKRUN_SEL 0x00000080
  48. #define TI113X_SCR_PWRSAVINGS 0x00000040
  49. #define TI113X_SCR_SUBSYSRW 0x00000020
  50. #define TI113X_SCR_CB_DPAR 0x00000010
  51. #define TI113X_SCR_CDMA_EN 0x00000008
  52. #define TI113X_SCR_ASYNC_IRQ 0x00000004
  53. #define TI113X_SCR_KEEPCLK 0x00000002
  54. #define TI113X_SCR_CLKRUN_ENA 0x00000001
  55. #define TI122X_SCR_SER_STEP 0xc0000000
  56. #define TI122X_SCR_INTRTIE 0x20000000
  57. #define TI122X_SCR_CBRSVD 0x00400000
  58. #define TI122X_SCR_MRBURSTDN 0x00008000
  59. #define TI122X_SCR_MRBURSTUP 0x00004000
  60. #define TI122X_SCR_RIMUX 0x00000001
  61. /* Multimedia Control Register */
  62. #define TI1250_MULTIMEDIA_CTL 0x0084 /* 8 bit */
  63. #define TI1250_MMC_ZVOUTEN 0x80
  64. #define TI1250_MMC_PORTSEL 0x40
  65. #define TI1250_MMC_ZVEN1 0x02
  66. #define TI1250_MMC_ZVEN0 0x01
  67. #define TI1250_GENERAL_STATUS 0x0085 /* 8 bit */
  68. #define TI1250_GPIO0_CONTROL 0x0088 /* 8 bit */
  69. #define TI1250_GPIO1_CONTROL 0x0089 /* 8 bit */
  70. #define TI1250_GPIO2_CONTROL 0x008a /* 8 bit */
  71. #define TI1250_GPIO3_CONTROL 0x008b /* 8 bit */
  72. #define TI1250_GPIO_MODE_MASK 0xc0
  73. /* IRQMUX/MFUNC Register */
  74. #define TI122X_MFUNC 0x008c /* 32 bit */
  75. #define TI122X_MFUNC0_MASK 0x0000000f
  76. #define TI122X_MFUNC1_MASK 0x000000f0
  77. #define TI122X_MFUNC2_MASK 0x00000f00
  78. #define TI122X_MFUNC3_MASK 0x0000f000
  79. #define TI122X_MFUNC4_MASK 0x000f0000
  80. #define TI122X_MFUNC5_MASK 0x00f00000
  81. #define TI122X_MFUNC6_MASK 0x0f000000
  82. #define TI122X_MFUNC0_INTA 0x00000002
  83. #define TI125X_MFUNC0_INTB 0x00000001
  84. #define TI122X_MFUNC1_INTB 0x00000020
  85. #define TI122X_MFUNC3_IRQSER 0x00001000
  86. /* Retry Status Register */
  87. #define TI113X_RETRY_STATUS 0x0090 /* 8 bit */
  88. #define TI113X_RSR_PCIRETRY 0x80
  89. #define TI113X_RSR_CBRETRY 0x40
  90. #define TI113X_RSR_TEXP_CBB 0x20
  91. #define TI113X_RSR_MEXP_CBB 0x10
  92. #define TI113X_RSR_TEXP_CBA 0x08
  93. #define TI113X_RSR_MEXP_CBA 0x04
  94. #define TI113X_RSR_TEXP_PCI 0x02
  95. #define TI113X_RSR_MEXP_PCI 0x01
  96. /* Card Control Register */
  97. #define TI113X_CARD_CONTROL 0x0091 /* 8 bit */
  98. #define TI113X_CCR_RIENB 0x80
  99. #define TI113X_CCR_ZVENABLE 0x40
  100. #define TI113X_CCR_PCI_IRQ_ENA 0x20
  101. #define TI113X_CCR_PCI_IREQ 0x10
  102. #define TI113X_CCR_PCI_CSC 0x08
  103. #define TI113X_CCR_SPKROUTEN 0x02
  104. #define TI113X_CCR_IFG 0x01
  105. #define TI1220_CCR_PORT_SEL 0x20
  106. #define TI122X_CCR_AUD2MUX 0x04
  107. /* Device Control Register */
  108. #define TI113X_DEVICE_CONTROL 0x0092 /* 8 bit */
  109. #define TI113X_DCR_5V_FORCE 0x40
  110. #define TI113X_DCR_3V_FORCE 0x20
  111. #define TI113X_DCR_IMODE_MASK 0x06
  112. #define TI113X_DCR_IMODE_ISA 0x02
  113. #define TI113X_DCR_IMODE_SERIAL 0x04
  114. #define TI12XX_DCR_IMODE_PCI_ONLY 0x00
  115. #define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
  116. /* Buffer Control Register */
  117. #define TI113X_BUFFER_CONTROL 0x0093 /* 8 bit */
  118. #define TI113X_BCR_CB_READ_DEPTH 0x08
  119. #define TI113X_BCR_CB_WRITE_DEPTH 0x04
  120. #define TI113X_BCR_PCI_READ_DEPTH 0x02
  121. #define TI113X_BCR_PCI_WRITE_DEPTH 0x01
  122. /* Diagnostic Register */
  123. #define TI1250_DIAGNOSTIC 0x0093 /* 8 bit */
  124. #define TI1250_DIAG_TRUE_VALUE 0x80
  125. #define TI1250_DIAG_PCI_IREQ 0x40
  126. #define TI1250_DIAG_PCI_CSC 0x20
  127. #define TI1250_DIAG_ASYNC_CSC 0x01
  128. /* DMA Registers */
  129. #define TI113X_DMA_0 0x0094 /* 32 bit */
  130. #define TI113X_DMA_1 0x0098 /* 32 bit */
  131. /* ExCA IO offset registers */
  132. #define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
  133. /* EnE test register */
  134. #define ENE_TEST_C9 0xc9 /* 8bit */
  135. #define ENE_TEST_C9_TLTENABLE 0x02
  136. /*
  137. * Texas Instruments CardBus controller overrides.
  138. */
  139. #define ti_sysctl(socket) ((socket)->private[0])
  140. #define ti_cardctl(socket) ((socket)->private[1])
  141. #define ti_devctl(socket) ((socket)->private[2])
  142. #define ti_diag(socket) ((socket)->private[3])
  143. #define ti_mfunc(socket) ((socket)->private[4])
  144. #define ene_test_c9(socket) ((socket)->private[5])
  145. /*
  146. * These are the TI specific power management handlers.
  147. */
  148. static void ti_save_state(struct yenta_socket *socket)
  149. {
  150. ti_sysctl(socket) = config_readl(socket, TI113X_SYSTEM_CONTROL);
  151. ti_mfunc(socket) = config_readl(socket, TI122X_MFUNC);
  152. ti_cardctl(socket) = config_readb(socket, TI113X_CARD_CONTROL);
  153. ti_devctl(socket) = config_readb(socket, TI113X_DEVICE_CONTROL);
  154. ti_diag(socket) = config_readb(socket, TI1250_DIAGNOSTIC);
  155. if (socket->dev->vendor == PCI_VENDOR_ID_ENE)
  156. ene_test_c9(socket) = config_readb(socket, ENE_TEST_C9);
  157. }
  158. static void ti_restore_state(struct yenta_socket *socket)
  159. {
  160. config_writel(socket, TI113X_SYSTEM_CONTROL, ti_sysctl(socket));
  161. config_writel(socket, TI122X_MFUNC, ti_mfunc(socket));
  162. config_writeb(socket, TI113X_CARD_CONTROL, ti_cardctl(socket));
  163. config_writeb(socket, TI113X_DEVICE_CONTROL, ti_devctl(socket));
  164. config_writeb(socket, TI1250_DIAGNOSTIC, ti_diag(socket));
  165. if (socket->dev->vendor == PCI_VENDOR_ID_ENE)
  166. config_writeb(socket, ENE_TEST_C9, ene_test_c9(socket));
  167. }
  168. /*
  169. * Zoom video control for TI122x/113x chips
  170. */
  171. static void ti_zoom_video(struct pcmcia_socket *sock, int onoff)
  172. {
  173. u8 reg;
  174. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  175. /* If we don't have a Zoom Video switch this is harmless,
  176. we just tristate the unused (ZV) lines */
  177. reg = config_readb(socket, TI113X_CARD_CONTROL);
  178. if (onoff)
  179. /* Zoom zoom, we will all go together, zoom zoom, zoom zoom */
  180. reg |= TI113X_CCR_ZVENABLE;
  181. else
  182. reg &= ~TI113X_CCR_ZVENABLE;
  183. config_writeb(socket, TI113X_CARD_CONTROL, reg);
  184. }
  185. /*
  186. * The 145x series can also use this. They have an additional
  187. * ZV autodetect mode we don't use but don't actually need.
  188. * FIXME: manual says its in func0 and func1 but disagrees with
  189. * itself about this - do we need to force func0, if so we need
  190. * to know a lot more about socket pairings in pcmcia_socket than
  191. * we do now.. uggh.
  192. */
  193. static void ti1250_zoom_video(struct pcmcia_socket *sock, int onoff)
  194. {
  195. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  196. int shift = 0;
  197. u8 reg;
  198. ti_zoom_video(sock, onoff);
  199. reg = config_readb(socket, TI1250_MULTIMEDIA_CTL);
  200. reg |= TI1250_MMC_ZVOUTEN; /* ZV bus enable */
  201. if(PCI_FUNC(socket->dev->devfn)==1)
  202. shift = 1;
  203. if(onoff)
  204. {
  205. reg &= ~(1<<6); /* Clear select bit */
  206. reg |= shift<<6; /* Favour our socket */
  207. reg |= 1<<shift; /* Socket zoom video on */
  208. }
  209. else
  210. {
  211. reg &= ~(1<<6); /* Clear select bit */
  212. reg |= (1^shift)<<6; /* Favour other socket */
  213. reg &= ~(1<<shift); /* Socket zoon video off */
  214. }
  215. config_writeb(socket, TI1250_MULTIMEDIA_CTL, reg);
  216. }
  217. static void ti_set_zv(struct yenta_socket *socket)
  218. {
  219. if(socket->dev->vendor == PCI_VENDOR_ID_TI)
  220. {
  221. switch(socket->dev->device)
  222. {
  223. /* There may be more .. */
  224. case PCI_DEVICE_ID_TI_1220:
  225. case PCI_DEVICE_ID_TI_1221:
  226. case PCI_DEVICE_ID_TI_1225:
  227. case PCI_DEVICE_ID_TI_4510:
  228. socket->socket.zoom_video = ti_zoom_video;
  229. break;
  230. case PCI_DEVICE_ID_TI_1250:
  231. case PCI_DEVICE_ID_TI_1251A:
  232. case PCI_DEVICE_ID_TI_1251B:
  233. case PCI_DEVICE_ID_TI_1450:
  234. socket->socket.zoom_video = ti1250_zoom_video;
  235. }
  236. }
  237. }
  238. /*
  239. * Generic TI init - TI has an extension for the
  240. * INTCTL register that sets the PCI CSC interrupt.
  241. * Make sure we set it correctly at open and init
  242. * time
  243. * - override: disable the PCI CSC interrupt. This makes
  244. * it possible to use the CSC interrupt to probe the
  245. * ISA interrupts.
  246. * - init: set the interrupt to match our PCI state.
  247. * This makes us correctly get PCI CSC interrupt
  248. * events.
  249. */
  250. static int ti_init(struct yenta_socket *socket)
  251. {
  252. u8 new, reg = exca_readb(socket, I365_INTCTL);
  253. new = reg & ~I365_INTR_ENA;
  254. if (socket->cb_irq)
  255. new |= I365_INTR_ENA;
  256. if (new != reg)
  257. exca_writeb(socket, I365_INTCTL, new);
  258. return 0;
  259. }
  260. static int ti_override(struct yenta_socket *socket)
  261. {
  262. u8 new, reg = exca_readb(socket, I365_INTCTL);
  263. new = reg & ~I365_INTR_ENA;
  264. if (new != reg)
  265. exca_writeb(socket, I365_INTCTL, new);
  266. ti_set_zv(socket);
  267. return 0;
  268. }
  269. static int ti113x_override(struct yenta_socket *socket)
  270. {
  271. u8 cardctl;
  272. cardctl = config_readb(socket, TI113X_CARD_CONTROL);
  273. cardctl &= ~(TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_IREQ | TI113X_CCR_PCI_CSC);
  274. if (socket->cb_irq)
  275. cardctl |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_CSC | TI113X_CCR_PCI_IREQ;
  276. config_writeb(socket, TI113X_CARD_CONTROL, cardctl);
  277. return ti_override(socket);
  278. }
  279. /* irqrouting for func0, probes PCI interrupt and ISA interrupts */
  280. static void ti12xx_irqroute_func0(struct yenta_socket *socket)
  281. {
  282. u32 mfunc, mfunc_old, devctl;
  283. u8 gpio3, gpio3_old;
  284. int pci_irq_status;
  285. mfunc = mfunc_old = config_readl(socket, TI122X_MFUNC);
  286. devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
  287. printk(KERN_INFO "Yenta TI: socket %s, mfunc 0x%08x, devctl 0x%02x\n",
  288. pci_name(socket->dev), mfunc, devctl);
  289. /* make sure PCI interrupts are enabled before probing */
  290. ti_init(socket);
  291. /* test PCI interrupts first. only try fixing if return value is 0! */
  292. pci_irq_status = yenta_probe_cb_irq(socket);
  293. if (pci_irq_status)
  294. goto out;
  295. /*
  296. * We're here which means PCI interrupts are _not_ delivered. try to
  297. * find the right setting (all serial or parallel)
  298. */
  299. printk(KERN_INFO "Yenta TI: socket %s probing PCI interrupt failed, trying to fix\n",
  300. pci_name(socket->dev));
  301. /* for serial PCI make sure MFUNC3 is set to IRQSER */
  302. if ((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) {
  303. switch (socket->dev->device) {
  304. case PCI_DEVICE_ID_TI_1250:
  305. case PCI_DEVICE_ID_TI_1251A:
  306. case PCI_DEVICE_ID_TI_1251B:
  307. case PCI_DEVICE_ID_TI_1450:
  308. case PCI_DEVICE_ID_TI_1451A:
  309. case PCI_DEVICE_ID_TI_4450:
  310. case PCI_DEVICE_ID_TI_4451:
  311. /* these chips have no IRQSER setting in MFUNC3 */
  312. break;
  313. default:
  314. mfunc = (mfunc & ~TI122X_MFUNC3_MASK) | TI122X_MFUNC3_IRQSER;
  315. /* write down if changed, probe */
  316. if (mfunc != mfunc_old) {
  317. config_writel(socket, TI122X_MFUNC, mfunc);
  318. pci_irq_status = yenta_probe_cb_irq(socket);
  319. if (pci_irq_status == 1) {
  320. printk(KERN_INFO "Yenta TI: socket %s all-serial interrupts ok\n",
  321. pci_name(socket->dev));
  322. mfunc_old = mfunc;
  323. goto out;
  324. }
  325. /* not working, back to old value */
  326. mfunc = mfunc_old;
  327. config_writel(socket, TI122X_MFUNC, mfunc);
  328. if (pci_irq_status == -1)
  329. goto out;
  330. }
  331. }
  332. /* serial PCI interrupts not working fall back to parallel */
  333. printk(KERN_INFO "Yenta TI: socket %s falling back to parallel PCI interrupts\n",
  334. pci_name(socket->dev));
  335. devctl &= ~TI113X_DCR_IMODE_MASK;
  336. devctl |= TI113X_DCR_IMODE_SERIAL; /* serial ISA could be right */
  337. config_writeb(socket, TI113X_DEVICE_CONTROL, devctl);
  338. }
  339. /* parallel PCI interrupts: route INTA */
  340. switch (socket->dev->device) {
  341. case PCI_DEVICE_ID_TI_1250:
  342. case PCI_DEVICE_ID_TI_1251A:
  343. case PCI_DEVICE_ID_TI_1251B:
  344. case PCI_DEVICE_ID_TI_1450:
  345. /* make sure GPIO3 is set to INTA */
  346. gpio3 = gpio3_old = config_readb(socket, TI1250_GPIO3_CONTROL);
  347. gpio3 &= ~TI1250_GPIO_MODE_MASK;
  348. if (gpio3 != gpio3_old)
  349. config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3);
  350. break;
  351. default:
  352. gpio3 = gpio3_old = 0;
  353. mfunc = (mfunc & ~TI122X_MFUNC0_MASK) | TI122X_MFUNC0_INTA;
  354. if (mfunc != mfunc_old)
  355. config_writel(socket, TI122X_MFUNC, mfunc);
  356. }
  357. /* time to probe again */
  358. pci_irq_status = yenta_probe_cb_irq(socket);
  359. if (pci_irq_status == 1) {
  360. mfunc_old = mfunc;
  361. printk(KERN_INFO "Yenta TI: socket %s parallel PCI interrupts ok\n",
  362. pci_name(socket->dev));
  363. } else {
  364. /* not working, back to old value */
  365. mfunc = mfunc_old;
  366. config_writel(socket, TI122X_MFUNC, mfunc);
  367. if (gpio3 != gpio3_old)
  368. config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3_old);
  369. }
  370. out:
  371. if (pci_irq_status < 1) {
  372. socket->cb_irq = 0;
  373. printk(KERN_INFO "Yenta TI: socket %s no PCI interrupts. Fish. Please report.\n",
  374. pci_name(socket->dev));
  375. }
  376. }
  377. /* changes the irq of func1 to match that of func0 */
  378. static int ti12xx_align_irqs(struct yenta_socket *socket, int *old_irq)
  379. {
  380. struct pci_dev *func0;
  381. /* find func0 device */
  382. func0 = pci_get_slot(socket->dev->bus, socket->dev->devfn & ~0x07);
  383. if (!func0)
  384. return 0;
  385. if (old_irq)
  386. *old_irq = socket->cb_irq;
  387. socket->cb_irq = socket->dev->irq = func0->irq;
  388. pci_dev_put(func0);
  389. return 1;
  390. }
  391. /*
  392. * ties INTA and INTB together. also changes the devices irq to that of
  393. * the function 0 device. call from func1 only.
  394. * returns 1 if INTRTIE changed, 0 otherwise.
  395. */
  396. static int ti12xx_tie_interrupts(struct yenta_socket *socket, int *old_irq)
  397. {
  398. u32 sysctl;
  399. int ret;
  400. sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
  401. if (sysctl & TI122X_SCR_INTRTIE)
  402. return 0;
  403. /* align */
  404. ret = ti12xx_align_irqs(socket, old_irq);
  405. if (!ret)
  406. return 0;
  407. /* tie */
  408. sysctl |= TI122X_SCR_INTRTIE;
  409. config_writel(socket, TI113X_SYSTEM_CONTROL, sysctl);
  410. return 1;
  411. }
  412. /* undo what ti12xx_tie_interrupts() did */
  413. static void ti12xx_untie_interrupts(struct yenta_socket *socket, int old_irq)
  414. {
  415. u32 sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
  416. sysctl &= ~TI122X_SCR_INTRTIE;
  417. config_writel(socket, TI113X_SYSTEM_CONTROL, sysctl);
  418. socket->cb_irq = socket->dev->irq = old_irq;
  419. }
  420. /*
  421. * irqrouting for func1, plays with INTB routing
  422. * only touches MFUNC for INTB routing. all other bits are taken
  423. * care of in func0 already.
  424. */
  425. static void ti12xx_irqroute_func1(struct yenta_socket *socket)
  426. {
  427. u32 mfunc, mfunc_old, devctl, sysctl;
  428. int pci_irq_status;
  429. mfunc = mfunc_old = config_readl(socket, TI122X_MFUNC);
  430. devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
  431. printk(KERN_INFO "Yenta TI: socket %s, mfunc 0x%08x, devctl 0x%02x\n",
  432. pci_name(socket->dev), mfunc, devctl);
  433. /* if IRQs are configured as tied, align irq of func1 with func0 */
  434. sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
  435. if (sysctl & TI122X_SCR_INTRTIE)
  436. ti12xx_align_irqs(socket, NULL);
  437. /* make sure PCI interrupts are enabled before probing */
  438. ti_init(socket);
  439. /* test PCI interrupts first. only try fixing if return value is 0! */
  440. pci_irq_status = yenta_probe_cb_irq(socket);
  441. if (pci_irq_status)
  442. goto out;
  443. /*
  444. * We're here which means PCI interrupts are _not_ delivered. try to
  445. * find the right setting
  446. */
  447. printk(KERN_INFO "Yenta TI: socket %s probing PCI interrupt failed, trying to fix\n",
  448. pci_name(socket->dev));
  449. /* if all serial: set INTRTIE, probe again */
  450. if ((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) {
  451. int old_irq;
  452. if (ti12xx_tie_interrupts(socket, &old_irq)) {
  453. pci_irq_status = yenta_probe_cb_irq(socket);
  454. if (pci_irq_status == 1) {
  455. printk(KERN_INFO "Yenta TI: socket %s all-serial interrupts, tied ok\n",
  456. pci_name(socket->dev));
  457. goto out;
  458. }
  459. ti12xx_untie_interrupts(socket, old_irq);
  460. }
  461. }
  462. /* parallel PCI: route INTB, probe again */
  463. else {
  464. int old_irq;
  465. switch (socket->dev->device) {
  466. case PCI_DEVICE_ID_TI_1250:
  467. /* the 1250 has one pin for IRQSER/INTB depending on devctl */
  468. break;
  469. case PCI_DEVICE_ID_TI_1251A:
  470. case PCI_DEVICE_ID_TI_1251B:
  471. case PCI_DEVICE_ID_TI_1450:
  472. /*
  473. * those have a pin for IRQSER/INTB plus INTB in MFUNC0
  474. * we alread probed the shared pin, now go for MFUNC0
  475. */
  476. mfunc = (mfunc & ~TI122X_MFUNC0_MASK) | TI125X_MFUNC0_INTB;
  477. break;
  478. default:
  479. mfunc = (mfunc & ~TI122X_MFUNC1_MASK) | TI122X_MFUNC1_INTB;
  480. break;
  481. }
  482. /* write, probe */
  483. if (mfunc != mfunc_old) {
  484. config_writel(socket, TI122X_MFUNC, mfunc);
  485. pci_irq_status = yenta_probe_cb_irq(socket);
  486. if (pci_irq_status == 1) {
  487. printk(KERN_INFO "Yenta TI: socket %s parallel PCI interrupts ok\n",
  488. pci_name(socket->dev));
  489. goto out;
  490. }
  491. mfunc = mfunc_old;
  492. config_writel(socket, TI122X_MFUNC, mfunc);
  493. if (pci_irq_status == -1)
  494. goto out;
  495. }
  496. /* still nothing: set INTRTIE */
  497. if (ti12xx_tie_interrupts(socket, &old_irq)) {
  498. pci_irq_status = yenta_probe_cb_irq(socket);
  499. if (pci_irq_status == 1) {
  500. printk(KERN_INFO "Yenta TI: socket %s parallel PCI interrupts, tied ok\n",
  501. pci_name(socket->dev));
  502. goto out;
  503. }
  504. ti12xx_untie_interrupts(socket, old_irq);
  505. }
  506. }
  507. out:
  508. if (pci_irq_status < 1) {
  509. socket->cb_irq = 0;
  510. printk(KERN_INFO "Yenta TI: socket %s no PCI interrupts. Fish. Please report.\n",
  511. pci_name(socket->dev));
  512. }
  513. }
  514. /* Returns true value if the second slot of a two-slot controller is empty */
  515. static int ti12xx_2nd_slot_empty(struct yenta_socket *socket)
  516. {
  517. struct pci_dev *func;
  518. struct yenta_socket *slot2;
  519. int devfn;
  520. unsigned int state;
  521. int ret = 1;
  522. /* catch the two-slot controllers */
  523. switch (socket->dev->device) {
  524. case PCI_DEVICE_ID_TI_1220:
  525. case PCI_DEVICE_ID_TI_1221:
  526. case PCI_DEVICE_ID_TI_1225:
  527. case PCI_DEVICE_ID_TI_1251A:
  528. case PCI_DEVICE_ID_TI_1251B:
  529. case PCI_DEVICE_ID_TI_1420:
  530. case PCI_DEVICE_ID_TI_1450:
  531. case PCI_DEVICE_ID_TI_1451A:
  532. case PCI_DEVICE_ID_TI_1520:
  533. case PCI_DEVICE_ID_TI_1620:
  534. case PCI_DEVICE_ID_TI_4520:
  535. case PCI_DEVICE_ID_TI_4450:
  536. case PCI_DEVICE_ID_TI_4451:
  537. /*
  538. * there are way more, but they need to be added in yenta_socket.c
  539. * and pci_ids.h first anyway.
  540. */
  541. break;
  542. /* single-slot controllers have the 2nd slot empty always :) */
  543. default:
  544. return 1;
  545. }
  546. /* get other slot */
  547. devfn = socket->dev->devfn & ~0x07;
  548. func = pci_get_slot(socket->dev->bus,
  549. (socket->dev->devfn & 0x07) ? devfn : devfn | 0x01);
  550. if (!func)
  551. return 1;
  552. slot2 = pci_get_drvdata(func);
  553. if (!slot2)
  554. goto out;
  555. /* check state */
  556. yenta_get_status(&socket->socket, &state);
  557. if (state & SS_DETECT) {
  558. ret = 0;
  559. goto out;
  560. }
  561. out:
  562. pci_dev_put(func);
  563. return ret;
  564. }
  565. /*
  566. * TI specifiy parts for the power hook.
  567. *
  568. * some TI's with some CB's produces interrupt storm on power on. it has been
  569. * seen with atheros wlan cards on TI1225 and TI1410. solution is simply to
  570. * disable any CB interrupts during this time.
  571. */
  572. static int ti12xx_power_hook(struct pcmcia_socket *sock, int operation)
  573. {
  574. struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
  575. u32 mfunc, devctl, sysctl;
  576. u8 gpio3;
  577. /* only POWER_PRE and POWER_POST are interesting */
  578. if ((operation != HOOK_POWER_PRE) && (operation != HOOK_POWER_POST))
  579. return 0;
  580. devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
  581. sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
  582. mfunc = config_readl(socket, TI122X_MFUNC);
  583. /*
  584. * all serial/tied: only disable when modparm set. always doing it
  585. * would mean a regression for working setups 'cos it disables the
  586. * interrupts for both both slots on 2-slot controllers
  587. * (and users of single slot controllers where it's save have to
  588. * live with setting the modparm, most don't have to anyway)
  589. */
  590. if (((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) &&
  591. (pwr_irqs_off || ti12xx_2nd_slot_empty(socket))) {
  592. switch (socket->dev->device) {
  593. case PCI_DEVICE_ID_TI_1250:
  594. case PCI_DEVICE_ID_TI_1251A:
  595. case PCI_DEVICE_ID_TI_1251B:
  596. case PCI_DEVICE_ID_TI_1450:
  597. case PCI_DEVICE_ID_TI_1451A:
  598. case PCI_DEVICE_ID_TI_4450:
  599. case PCI_DEVICE_ID_TI_4451:
  600. /* these chips have no IRQSER setting in MFUNC3 */
  601. break;
  602. default:
  603. if (operation == HOOK_POWER_PRE)
  604. mfunc = (mfunc & ~TI122X_MFUNC3_MASK);
  605. else
  606. mfunc = (mfunc & ~TI122X_MFUNC3_MASK) | TI122X_MFUNC3_IRQSER;
  607. }
  608. return 0;
  609. }
  610. /* do the job differently for func0/1 */
  611. if ((PCI_FUNC(socket->dev->devfn) == 0) ||
  612. ((sysctl & TI122X_SCR_INTRTIE) &&
  613. (pwr_irqs_off || ti12xx_2nd_slot_empty(socket)))) {
  614. /* some bridges are different */
  615. switch (socket->dev->device) {
  616. case PCI_DEVICE_ID_TI_1250:
  617. case PCI_DEVICE_ID_TI_1251A:
  618. case PCI_DEVICE_ID_TI_1251B:
  619. case PCI_DEVICE_ID_TI_1450:
  620. /* those oldies use gpio3 for INTA */
  621. gpio3 = config_readb(socket, TI1250_GPIO3_CONTROL);
  622. if (operation == HOOK_POWER_PRE)
  623. gpio3 = (gpio3 & ~TI1250_GPIO_MODE_MASK) | 0x40;
  624. else
  625. gpio3 &= ~TI1250_GPIO_MODE_MASK;
  626. config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3);
  627. break;
  628. default:
  629. /* all new bridges are the same */
  630. if (operation == HOOK_POWER_PRE)
  631. mfunc &= ~TI122X_MFUNC0_MASK;
  632. else
  633. mfunc |= TI122X_MFUNC0_INTA;
  634. config_writel(socket, TI122X_MFUNC, mfunc);
  635. }
  636. } else {
  637. switch (socket->dev->device) {
  638. case PCI_DEVICE_ID_TI_1251A:
  639. case PCI_DEVICE_ID_TI_1251B:
  640. case PCI_DEVICE_ID_TI_1450:
  641. /* those have INTA elsewhere and INTB in MFUNC0 */
  642. if (operation == HOOK_POWER_PRE)
  643. mfunc &= ~TI122X_MFUNC0_MASK;
  644. else
  645. mfunc |= TI125X_MFUNC0_INTB;
  646. config_writel(socket, TI122X_MFUNC, mfunc);
  647. break;
  648. default:
  649. /* all new bridges are the same */
  650. if (operation == HOOK_POWER_PRE)
  651. mfunc &= ~TI122X_MFUNC1_MASK;
  652. else
  653. mfunc |= TI122X_MFUNC1_INTB;
  654. config_writel(socket, TI122X_MFUNC, mfunc);
  655. }
  656. }
  657. return 0;
  658. }
  659. static int ti12xx_override(struct yenta_socket *socket)
  660. {
  661. u32 val, val_orig;
  662. /* make sure that memory burst is active */
  663. val_orig = val = config_readl(socket, TI113X_SYSTEM_CONTROL);
  664. if (disable_clkrun && PCI_FUNC(socket->dev->devfn) == 0) {
  665. printk(KERN_INFO "Yenta: Disabling CLKRUN feature\n");
  666. val |= TI113X_SCR_KEEPCLK;
  667. }
  668. if (!(val & TI122X_SCR_MRBURSTUP)) {
  669. printk(KERN_INFO "Yenta: Enabling burst memory read transactions\n");
  670. val |= TI122X_SCR_MRBURSTUP;
  671. }
  672. if (val_orig != val)
  673. config_writel(socket, TI113X_SYSTEM_CONTROL, val);
  674. /*
  675. * for EnE bridges only: clear testbit TLTEnable. this makes the
  676. * RME Hammerfall DSP sound card working.
  677. */
  678. if (socket->dev->vendor == PCI_VENDOR_ID_ENE) {
  679. u8 test_c9 = config_readb(socket, ENE_TEST_C9);
  680. test_c9 &= ~ENE_TEST_C9_TLTENABLE;
  681. config_writeb(socket, ENE_TEST_C9, test_c9);
  682. }
  683. /*
  684. * Yenta expects controllers to use CSCINT to route
  685. * CSC interrupts to PCI rather than INTVAL.
  686. */
  687. val = config_readb(socket, TI1250_DIAGNOSTIC);
  688. printk(KERN_INFO "Yenta: Using %s to route CSC interrupts to PCI\n",
  689. (val & TI1250_DIAG_PCI_CSC) ? "CSCINT" : "INTVAL");
  690. printk(KERN_INFO "Yenta: Routing CardBus interrupts to %s\n",
  691. (val & TI1250_DIAG_PCI_IREQ) ? "PCI" : "ISA");
  692. /* do irqrouting, depending on function */
  693. if (PCI_FUNC(socket->dev->devfn) == 0)
  694. ti12xx_irqroute_func0(socket);
  695. else
  696. ti12xx_irqroute_func1(socket);
  697. /* install power hook */
  698. socket->socket.power_hook = ti12xx_power_hook;
  699. return ti_override(socket);
  700. }
  701. static int ti1250_override(struct yenta_socket *socket)
  702. {
  703. u8 old, diag;
  704. old = config_readb(socket, TI1250_DIAGNOSTIC);
  705. diag = old & ~(TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ);
  706. if (socket->cb_irq)
  707. diag |= TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ;
  708. if (diag != old) {
  709. printk(KERN_INFO "Yenta: adjusting diagnostic: %02x -> %02x\n",
  710. old, diag);
  711. config_writeb(socket, TI1250_DIAGNOSTIC, diag);
  712. }
  713. return ti12xx_override(socket);
  714. }
  715. #endif /* _LINUX_TI113X_H */