arv.c 22 KB

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  1. /*
  2. * Colour AR M64278(VGA) driver for Video4Linux
  3. *
  4. * Copyright (C) 2003 Takeo Takahashi <takahashi.takeo@renesas.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. * Some code is taken from AR driver sample program for M3T-M32700UT.
  12. *
  13. * AR driver sample (M32R SDK):
  14. * Copyright (c) 2003 RENESAS TECHNOROGY CORPORATION
  15. * AND RENESAS SOLUTIONS CORPORATION
  16. * All Rights Reserved.
  17. *
  18. * 2003-09-01: Support w3cam by Takeo Takahashi
  19. */
  20. #include <linux/config.h>
  21. #include <linux/init.h>
  22. #include <linux/devfs_fs_kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/version.h>
  25. #include <linux/delay.h>
  26. #include <linux/errno.h>
  27. #include <linux/fs.h>
  28. #include <linux/init.h>
  29. #include <linux/kernel.h>
  30. #include <linux/slab.h>
  31. #include <linux/mm.h>
  32. #include <linux/sched.h>
  33. #include <linux/videodev.h>
  34. #include <asm/semaphore.h>
  35. #include <asm/uaccess.h>
  36. #include <asm/m32r.h>
  37. #include <asm/io.h>
  38. #include <asm/dma.h>
  39. #include <asm/byteorder.h>
  40. #if 0
  41. #define DEBUG(n, args...) printk(args)
  42. #define CHECK_LOST 1
  43. #else
  44. #define DEBUG(n, args...)
  45. #define CHECK_LOST 0
  46. #endif
  47. /*
  48. * USE_INT is always 0, interrupt mode is not available
  49. * on linux due to lack of speed
  50. */
  51. #define USE_INT 0 /* Don't modify */
  52. #define VERSION "0.03"
  53. #define ar_inl(addr) inl((unsigned long)(addr))
  54. #define ar_outl(val, addr) outl((unsigned long)(val),(unsigned long)(addr))
  55. extern struct cpuinfo_m32r boot_cpu_data;
  56. /*
  57. * CCD pixel size
  58. * Note that M32700UT does not support CIF mode, but QVGA is
  59. * supported by M32700UT hardware using VGA mode of AR LSI.
  60. *
  61. * Supported: VGA (Normal mode, Interlace mode)
  62. * QVGA (Always Interlace mode of VGA)
  63. *
  64. */
  65. #define AR_WIDTH_VGA 640
  66. #define AR_HEIGHT_VGA 480
  67. #define AR_WIDTH_QVGA 320
  68. #define AR_HEIGHT_QVGA 240
  69. #define MIN_AR_WIDTH AR_WIDTH_QVGA
  70. #define MIN_AR_HEIGHT AR_HEIGHT_QVGA
  71. #define MAX_AR_WIDTH AR_WIDTH_VGA
  72. #define MAX_AR_HEIGHT AR_HEIGHT_VGA
  73. /* bits & bytes per pixel */
  74. #define AR_BITS_PER_PIXEL 16
  75. #define AR_BYTES_PER_PIXEL (AR_BITS_PER_PIXEL/8)
  76. /* line buffer size */
  77. #define AR_LINE_BYTES_VGA (AR_WIDTH_VGA * AR_BYTES_PER_PIXEL)
  78. #define AR_LINE_BYTES_QVGA (AR_WIDTH_QVGA * AR_BYTES_PER_PIXEL)
  79. #define MAX_AR_LINE_BYTES AR_LINE_BYTES_VGA
  80. /* frame size & type */
  81. #define AR_FRAME_BYTES_VGA \
  82. (AR_WIDTH_VGA * AR_HEIGHT_VGA * AR_BYTES_PER_PIXEL)
  83. #define AR_FRAME_BYTES_QVGA \
  84. (AR_WIDTH_QVGA * AR_HEIGHT_QVGA * AR_BYTES_PER_PIXEL)
  85. #define MAX_AR_FRAME_BYTES \
  86. (MAX_AR_WIDTH * MAX_AR_HEIGHT * AR_BYTES_PER_PIXEL)
  87. #define AR_MAX_FRAME 15
  88. /* capture size */
  89. #define AR_SIZE_VGA 0
  90. #define AR_SIZE_QVGA 1
  91. /* capture mode */
  92. #define AR_MODE_INTERLACE 0
  93. #define AR_MODE_NORMAL 1
  94. struct ar_device {
  95. struct video_device *vdev;
  96. unsigned int start_capture; /* duaring capture in INT. mode. */
  97. #if USE_INT
  98. unsigned char *line_buff; /* DMA line buffer */
  99. #endif
  100. unsigned char *frame[MAX_AR_HEIGHT]; /* frame data */
  101. short size; /* capture size */
  102. short mode; /* capture mode */
  103. int width, height;
  104. int frame_bytes, line_bytes;
  105. wait_queue_head_t wait;
  106. struct semaphore lock;
  107. };
  108. static int video_nr = -1; /* video device number (first free) */
  109. static unsigned char yuv[MAX_AR_FRAME_BYTES];
  110. /* module parameters */
  111. /* default frequency */
  112. #define DEFAULT_FREQ 50 /* 50 or 75 (MHz) is available as BCLK */
  113. static int freq = DEFAULT_FREQ; /* BCLK: available 50 or 70 (MHz) */
  114. static int vga = 0; /* default mode(0:QVGA mode, other:VGA mode) */
  115. static int vga_interlace = 0; /* 0 is normal mode for, else interlace mode */
  116. MODULE_PARM(freq, "i");
  117. MODULE_PARM(vga, "i");
  118. MODULE_PARM(vga_interlace, "i");
  119. static int ar_initialize(struct video_device *dev);
  120. static inline void wait_for_vsync(void)
  121. {
  122. while (ar_inl(ARVCR0) & ARVCR0_VDS) /* wait for VSYNC */
  123. cpu_relax();
  124. while (!(ar_inl(ARVCR0) & ARVCR0_VDS)) /* wait for VSYNC */
  125. cpu_relax();
  126. }
  127. static inline void wait_acknowledge(void)
  128. {
  129. int i;
  130. for (i = 0; i < 1000; i++)
  131. cpu_relax();
  132. while (ar_inl(PLDI2CSTS) & PLDI2CSTS_NOACK)
  133. cpu_relax();
  134. }
  135. /*******************************************************************
  136. * I2C functions
  137. *******************************************************************/
  138. void iic(int n, unsigned long addr, unsigned long data1, unsigned long data2,
  139. unsigned long data3)
  140. {
  141. int i;
  142. /* Slave Address */
  143. ar_outl(addr, PLDI2CDATA);
  144. wait_for_vsync();
  145. /* Start */
  146. ar_outl(1, PLDI2CCND);
  147. wait_acknowledge();
  148. /* Transfer data 1 */
  149. ar_outl(data1, PLDI2CDATA);
  150. wait_for_vsync();
  151. ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
  152. wait_acknowledge();
  153. /* Transfer data 2 */
  154. ar_outl(data2, PLDI2CDATA);
  155. wait_for_vsync();
  156. ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
  157. wait_acknowledge();
  158. if (n == 3) {
  159. /* Transfer data 3 */
  160. ar_outl(data3, PLDI2CDATA);
  161. wait_for_vsync();
  162. ar_outl(PLDI2CSTEN_STEN, PLDI2CSTEN);
  163. wait_acknowledge();
  164. }
  165. /* Stop */
  166. for (i = 0; i < 100; i++)
  167. cpu_relax();
  168. ar_outl(2, PLDI2CCND);
  169. ar_outl(2, PLDI2CCND);
  170. while (ar_inl(PLDI2CSTS) & PLDI2CSTS_BB)
  171. cpu_relax();
  172. }
  173. void init_iic(void)
  174. {
  175. DEBUG(1, "init_iic:\n");
  176. /*
  177. * ICU Setting (iic)
  178. */
  179. /* I2C Setting */
  180. ar_outl(0x0, PLDI2CCR); /* I2CCR Disable */
  181. ar_outl(0x0300, PLDI2CMOD); /* I2CMOD ACK/8b-data/7b-addr/auto */
  182. ar_outl(0x1, PLDI2CACK); /* I2CACK ACK */
  183. /* I2C CLK */
  184. /* 50MH-100k */
  185. if (freq == 75) {
  186. ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */
  187. } else if (freq == 50) {
  188. ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */
  189. } else {
  190. ar_outl(244, PLDI2CFREQ); /* default: BCLK = 50MHz */
  191. }
  192. ar_outl(0x1, PLDI2CCR); /* I2CCR Enable */
  193. }
  194. /**************************************************************************
  195. *
  196. * Video4Linux Interface functions
  197. *
  198. **************************************************************************/
  199. static inline void disable_dma(void)
  200. {
  201. ar_outl(0x8000, M32R_DMAEN_PORTL); /* disable DMA0 */
  202. }
  203. static inline void enable_dma(void)
  204. {
  205. ar_outl(0x8080, M32R_DMAEN_PORTL); /* enable DMA0 */
  206. }
  207. static inline void clear_dma_status(void)
  208. {
  209. ar_outl(0x8000, M32R_DMAEDET_PORTL); /* clear status */
  210. }
  211. static inline void wait_for_vertical_sync(int exp_line)
  212. {
  213. #if CHECK_LOST
  214. int tmout = 10000; /* FIXME */
  215. int l;
  216. /*
  217. * check HCOUNT because we cannot check vertical sync.
  218. */
  219. for (; tmout >= 0; tmout--) {
  220. l = ar_inl(ARVHCOUNT);
  221. if (l == exp_line)
  222. break;
  223. }
  224. if (tmout < 0)
  225. printk("arv: lost %d -> %d\n", exp_line, l);
  226. #else
  227. while (ar_inl(ARVHCOUNT) != exp_line)
  228. cpu_relax();
  229. #endif
  230. }
  231. static ssize_t ar_read(struct file *file, char *buf, size_t count, loff_t *ppos)
  232. {
  233. struct video_device *v = video_devdata(file);
  234. struct ar_device *ar = v->priv;
  235. long ret = ar->frame_bytes; /* return read bytes */
  236. unsigned long arvcr1 = 0;
  237. unsigned long flags;
  238. unsigned char *p;
  239. int h, w;
  240. unsigned char *py, *pu, *pv;
  241. #if ! USE_INT
  242. int l;
  243. #endif
  244. DEBUG(1, "ar_read()\n");
  245. if (ar->size == AR_SIZE_QVGA)
  246. arvcr1 |= ARVCR1_QVGA;
  247. if (ar->mode == AR_MODE_NORMAL)
  248. arvcr1 |= ARVCR1_NORMAL;
  249. down(&ar->lock);
  250. #if USE_INT
  251. local_irq_save(flags);
  252. disable_dma();
  253. ar_outl(0xa1871300, M32R_DMA0CR0_PORTL);
  254. ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
  255. /* set AR FIFO address as source(BSEL5) */
  256. ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
  257. ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
  258. ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* destination addr. */
  259. ar_outl(ar->line_buff, M32R_DMA0RDA_PORTL); /* reload address */
  260. ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL); /* byte count (bytes) */
  261. ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL); /* reload count (bytes) */
  262. /*
  263. * Okey , kicks AR LSI to invoke an interrupt
  264. */
  265. ar->start_capture = 0;
  266. ar_outl(arvcr1 | ARVCR1_HIEN, ARVCR1);
  267. local_irq_restore(flags);
  268. /* .... AR interrupts .... */
  269. interruptible_sleep_on(&ar->wait);
  270. if (signal_pending(current)) {
  271. printk("arv: interrupted while get frame data.\n");
  272. ret = -EINTR;
  273. goto out_up;
  274. }
  275. #else /* ! USE_INT */
  276. /* polling */
  277. ar_outl(arvcr1, ARVCR1);
  278. disable_dma();
  279. ar_outl(0x8000, M32R_DMAEDET_PORTL);
  280. ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
  281. ar_outl(0x01000000, M32R_DMA0CR1_PORTL);
  282. ar_outl(ARDATA32, M32R_DMA0CSA_PORTL);
  283. ar_outl(ARDATA32, M32R_DMA0RSA_PORTL);
  284. ar_outl(ar->line_bytes, M32R_DMA0CBCUT_PORTL);
  285. ar_outl(ar->line_bytes, M32R_DMA0RBCUT_PORTL);
  286. local_irq_save(flags);
  287. while (ar_inl(ARVHCOUNT) != 0) /* wait for 0 */
  288. cpu_relax();
  289. if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) {
  290. for (h = 0; h < ar->height; h++) {
  291. wait_for_vertical_sync(h);
  292. if (h < (AR_HEIGHT_VGA/2))
  293. l = h << 1;
  294. else
  295. l = (((h - (AR_HEIGHT_VGA/2)) << 1) + 1);
  296. ar_outl(virt_to_phys(ar->frame[l]), M32R_DMA0CDA_PORTL);
  297. enable_dma();
  298. while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000))
  299. cpu_relax();
  300. disable_dma();
  301. clear_dma_status();
  302. ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
  303. }
  304. } else {
  305. for (h = 0; h < ar->height; h++) {
  306. wait_for_vertical_sync(h);
  307. ar_outl(virt_to_phys(ar->frame[h]), M32R_DMA0CDA_PORTL);
  308. enable_dma();
  309. while (!(ar_inl(M32R_DMAEDET_PORTL) & 0x8000))
  310. cpu_relax();
  311. disable_dma();
  312. clear_dma_status();
  313. ar_outl(0xa0861300, M32R_DMA0CR0_PORTL);
  314. }
  315. }
  316. local_irq_restore(flags);
  317. #endif /* ! USE_INT */
  318. /*
  319. * convert YUV422 to YUV422P
  320. * +--------------------+
  321. * | Y0,Y1,... |
  322. * | ..............Yn |
  323. * +--------------------+
  324. * | U0,U1,........Un |
  325. * +--------------------+
  326. * | V0,V1,........Vn |
  327. * +--------------------+
  328. */
  329. py = yuv;
  330. pu = py + (ar->frame_bytes / 2);
  331. pv = pu + (ar->frame_bytes / 4);
  332. for (h = 0; h < ar->height; h++) {
  333. p = ar->frame[h];
  334. for (w = 0; w < ar->line_bytes; w += 4) {
  335. *py++ = *p++;
  336. *pu++ = *p++;
  337. *py++ = *p++;
  338. *pv++ = *p++;
  339. }
  340. }
  341. if (copy_to_user(buf, yuv, ar->frame_bytes)) {
  342. printk("arv: failed while copy_to_user yuv.\n");
  343. ret = -EFAULT;
  344. goto out_up;
  345. }
  346. DEBUG(1, "ret = %d\n", ret);
  347. out_up:
  348. up(&ar->lock);
  349. return ret;
  350. }
  351. static int ar_do_ioctl(struct inode *inode, struct file *file,
  352. unsigned int cmd, void *arg)
  353. {
  354. struct video_device *dev = video_devdata(file);
  355. struct ar_device *ar = dev->priv;
  356. DEBUG(1, "ar_ioctl()\n");
  357. switch(cmd) {
  358. case VIDIOCGCAP:
  359. {
  360. struct video_capability *b = arg;
  361. DEBUG(1, "VIDIOCGCAP:\n");
  362. strcpy(b->name, ar->vdev->name);
  363. b->type = VID_TYPE_CAPTURE;
  364. b->channels = 0;
  365. b->audios = 0;
  366. b->maxwidth = MAX_AR_WIDTH;
  367. b->maxheight = MAX_AR_HEIGHT;
  368. b->minwidth = MIN_AR_WIDTH;
  369. b->minheight = MIN_AR_HEIGHT;
  370. return 0;
  371. }
  372. case VIDIOCGCHAN:
  373. DEBUG(1, "VIDIOCGCHAN:\n");
  374. return 0;
  375. case VIDIOCSCHAN:
  376. DEBUG(1, "VIDIOCSCHAN:\n");
  377. return 0;
  378. case VIDIOCGTUNER:
  379. DEBUG(1, "VIDIOCGTUNER:\n");
  380. return 0;
  381. case VIDIOCSTUNER:
  382. DEBUG(1, "VIDIOCSTUNER:\n");
  383. return 0;
  384. case VIDIOCGPICT:
  385. DEBUG(1, "VIDIOCGPICT:\n");
  386. return 0;
  387. case VIDIOCSPICT:
  388. DEBUG(1, "VIDIOCSPICT:\n");
  389. return 0;
  390. case VIDIOCCAPTURE:
  391. DEBUG(1, "VIDIOCCAPTURE:\n");
  392. return -EINVAL;
  393. case VIDIOCGWIN:
  394. {
  395. struct video_window *w = arg;
  396. DEBUG(1, "VIDIOCGWIN:\n");
  397. memset(w, 0, sizeof(w));
  398. w->width = ar->width;
  399. w->height = ar->height;
  400. return 0;
  401. }
  402. case VIDIOCSWIN:
  403. {
  404. struct video_window *w = arg;
  405. DEBUG(1, "VIDIOCSWIN:\n");
  406. if ((w->width != AR_WIDTH_VGA || w->height != AR_HEIGHT_VGA) &&
  407. (w->width != AR_WIDTH_QVGA || w->height != AR_HEIGHT_QVGA))
  408. return -EINVAL;
  409. down(&ar->lock);
  410. ar->width = w->width;
  411. ar->height = w->height;
  412. if (ar->width == AR_WIDTH_VGA) {
  413. ar->size = AR_SIZE_VGA;
  414. ar->frame_bytes = AR_FRAME_BYTES_VGA;
  415. ar->line_bytes = AR_LINE_BYTES_VGA;
  416. if (vga_interlace)
  417. ar->mode = AR_MODE_INTERLACE;
  418. else
  419. ar->mode = AR_MODE_NORMAL;
  420. } else {
  421. ar->size = AR_SIZE_QVGA;
  422. ar->frame_bytes = AR_FRAME_BYTES_QVGA;
  423. ar->line_bytes = AR_LINE_BYTES_QVGA;
  424. ar->mode = AR_MODE_INTERLACE;
  425. }
  426. up(&ar->lock);
  427. return 0;
  428. }
  429. case VIDIOCGFBUF:
  430. DEBUG(1, "VIDIOCGFBUF:\n");
  431. return -EINVAL;
  432. case VIDIOCSFBUF:
  433. DEBUG(1, "VIDIOCSFBUF:\n");
  434. return -EINVAL;
  435. case VIDIOCKEY:
  436. DEBUG(1, "VIDIOCKEY:\n");
  437. return 0;
  438. case VIDIOCGFREQ:
  439. DEBUG(1, "VIDIOCGFREQ:\n");
  440. return -EINVAL;
  441. case VIDIOCSFREQ:
  442. DEBUG(1, "VIDIOCSFREQ:\n");
  443. return -EINVAL;
  444. case VIDIOCGAUDIO:
  445. DEBUG(1, "VIDIOCGAUDIO:\n");
  446. return -EINVAL;
  447. case VIDIOCSAUDIO:
  448. DEBUG(1, "VIDIOCSAUDIO:\n");
  449. return -EINVAL;
  450. case VIDIOCSYNC:
  451. DEBUG(1, "VIDIOCSYNC:\n");
  452. return -EINVAL;
  453. case VIDIOCMCAPTURE:
  454. DEBUG(1, "VIDIOCMCAPTURE:\n");
  455. return -EINVAL;
  456. case VIDIOCGMBUF:
  457. DEBUG(1, "VIDIOCGMBUF:\n");
  458. return -EINVAL;
  459. case VIDIOCGUNIT:
  460. DEBUG(1, "VIDIOCGUNIT:\n");
  461. return -EINVAL;
  462. case VIDIOCGCAPTURE:
  463. DEBUG(1, "VIDIOCGCAPTURE:\n");
  464. return -EINVAL;
  465. case VIDIOCSCAPTURE:
  466. DEBUG(1, "VIDIOCSCAPTURE:\n");
  467. return -EINVAL;
  468. case VIDIOCSPLAYMODE:
  469. DEBUG(1, "VIDIOCSPLAYMODE:\n");
  470. return -EINVAL;
  471. case VIDIOCSWRITEMODE:
  472. DEBUG(1, "VIDIOCSWRITEMODE:\n");
  473. return -EINVAL;
  474. case VIDIOCGPLAYINFO:
  475. DEBUG(1, "VIDIOCGPLAYINFO:\n");
  476. return -EINVAL;
  477. case VIDIOCSMICROCODE:
  478. DEBUG(1, "VIDIOCSMICROCODE:\n");
  479. return -EINVAL;
  480. case VIDIOCGVBIFMT:
  481. DEBUG(1, "VIDIOCGVBIFMT:\n");
  482. return -EINVAL;
  483. case VIDIOCSVBIFMT:
  484. DEBUG(1, "VIDIOCSVBIFMT:\n");
  485. return -EINVAL;
  486. default:
  487. DEBUG(1, "Unknown ioctl(0x%08x)\n", cmd);
  488. return -ENOIOCTLCMD;
  489. }
  490. return 0;
  491. }
  492. static int ar_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
  493. unsigned long arg)
  494. {
  495. return video_usercopy(inode, file, cmd, arg, ar_do_ioctl);
  496. }
  497. #if USE_INT
  498. /*
  499. * Interrupt handler
  500. */
  501. static void ar_interrupt(int irq, void *dev, struct pt_regs *regs)
  502. {
  503. struct ar_device *ar = dev;
  504. unsigned int line_count;
  505. unsigned int line_number;
  506. unsigned int arvcr1;
  507. line_count = ar_inl(ARVHCOUNT); /* line number */
  508. if (ar->mode == AR_MODE_INTERLACE && ar->size == AR_SIZE_VGA) {
  509. /* operations for interlace mode */
  510. if ( line_count < (AR_HEIGHT_VGA/2) ) /* even line */
  511. line_number = (line_count << 1);
  512. else /* odd line */
  513. line_number =
  514. (((line_count - (AR_HEIGHT_VGA/2)) << 1) + 1);
  515. } else {
  516. line_number = line_count;
  517. }
  518. if (line_number == 0) {
  519. /*
  520. * It is an interrupt for line 0.
  521. * we have to start capture.
  522. */
  523. disable_dma();
  524. #if 0
  525. ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL); /* needless? */
  526. #endif
  527. memcpy(ar->frame[0], ar->line_buff, ar->line_bytes);
  528. #if 0
  529. ar_outl(0xa1861300, M32R_DMA0CR0_PORTL);
  530. #endif
  531. enable_dma();
  532. ar->start_capture = 1; /* during capture */
  533. return;
  534. }
  535. if (ar->start_capture == 1 && line_number <= (ar->height - 1)) {
  536. disable_dma();
  537. memcpy(ar->frame[line_number], ar->line_buff, ar->line_bytes);
  538. /*
  539. * if captured all line of a frame, disable AR interrupt
  540. * and wake a process up.
  541. */
  542. if (line_number == (ar->height - 1)) { /* end of line */
  543. ar->start_capture = 0;
  544. /* disable AR interrupt request */
  545. arvcr1 = ar_inl(ARVCR1);
  546. arvcr1 &= ~ARVCR1_HIEN; /* clear int. flag */
  547. ar_outl(arvcr1, ARVCR1); /* disable */
  548. wake_up_interruptible(&ar->wait);
  549. } else {
  550. #if 0
  551. ar_outl(ar->line_buff, M32R_DMA0CDA_PORTL);
  552. ar_outl(0xa1861300, M32R_DMA0CR0_PORTL);
  553. #endif
  554. enable_dma();
  555. }
  556. }
  557. }
  558. #endif
  559. /*
  560. * ar_initialize()
  561. * ar_initialize() is called by video_register_device() and
  562. * initializes AR LSI and peripherals.
  563. *
  564. * -1 is returned in all failures.
  565. * 0 is returned in success.
  566. *
  567. */
  568. static int ar_initialize(struct video_device *dev)
  569. {
  570. struct ar_device *ar = dev->priv;
  571. unsigned long cr = 0;
  572. int i,found=0;
  573. DEBUG(1, "ar_initialize:\n");
  574. /*
  575. * initialize AR LSI
  576. */
  577. ar_outl(0, ARVCR0); /* assert reset of AR LSI */
  578. for (i = 0; i < 0x18; i++) /* wait for over 10 cycles @ 27MHz */
  579. cpu_relax();
  580. ar_outl(ARVCR0_RST, ARVCR0); /* negate reset of AR LSI (enable) */
  581. for (i = 0; i < 0x40d; i++) /* wait for over 420 cycles @ 27MHz */
  582. cpu_relax();
  583. /* AR uses INT3 of CPU as interrupt pin. */
  584. ar_outl(ARINTSEL_INT3, ARINTSEL);
  585. if (ar->size == AR_SIZE_QVGA)
  586. cr |= ARVCR1_QVGA;
  587. if (ar->mode == AR_MODE_NORMAL)
  588. cr |= ARVCR1_NORMAL;
  589. ar_outl(cr, ARVCR1);
  590. /*
  591. * Initialize IIC so that CPU can communicate with AR LSI,
  592. * and send boot commands to AR LSI.
  593. */
  594. init_iic();
  595. for (i = 0; i < 0x100000; i++) { /* > 0xa1d10, 56ms */
  596. if ((ar_inl(ARVCR0) & ARVCR0_VDS)) { /* VSYNC */
  597. found = 1;
  598. break;
  599. }
  600. }
  601. if (found == 0)
  602. return -ENODEV;
  603. printk("arv: Initializing ");
  604. iic(2,0x78,0x11,0x01,0x00); /* start */
  605. iic(3,0x78,0x12,0x00,0x06);
  606. iic(3,0x78,0x12,0x12,0x30);
  607. iic(3,0x78,0x12,0x15,0x58);
  608. iic(3,0x78,0x12,0x17,0x30);
  609. printk(".");
  610. iic(3,0x78,0x12,0x1a,0x97);
  611. iic(3,0x78,0x12,0x1b,0xff);
  612. iic(3,0x78,0x12,0x1c,0xff);
  613. iic(3,0x78,0x12,0x26,0x10);
  614. iic(3,0x78,0x12,0x27,0x00);
  615. printk(".");
  616. iic(2,0x78,0x34,0x02,0x00);
  617. iic(2,0x78,0x7a,0x10,0x00);
  618. iic(2,0x78,0x80,0x39,0x00);
  619. iic(2,0x78,0x81,0xe6,0x00);
  620. iic(2,0x78,0x8d,0x00,0x00);
  621. printk(".");
  622. iic(2,0x78,0x8e,0x0c,0x00);
  623. iic(2,0x78,0x8f,0x00,0x00);
  624. #if 0
  625. iic(2,0x78,0x90,0x00,0x00); /* AWB on=1 off=0 */
  626. #endif
  627. iic(2,0x78,0x93,0x01,0x00);
  628. iic(2,0x78,0x94,0xcd,0x00);
  629. iic(2,0x78,0x95,0x00,0x00);
  630. printk(".");
  631. iic(2,0x78,0x96,0xa0,0x00);
  632. iic(2,0x78,0x97,0x00,0x00);
  633. iic(2,0x78,0x98,0x60,0x00);
  634. iic(2,0x78,0x99,0x01,0x00);
  635. iic(2,0x78,0x9a,0x19,0x00);
  636. printk(".");
  637. iic(2,0x78,0x9b,0x02,0x00);
  638. iic(2,0x78,0x9c,0xe8,0x00);
  639. iic(2,0x78,0x9d,0x02,0x00);
  640. iic(2,0x78,0x9e,0x2e,0x00);
  641. iic(2,0x78,0xb8,0x78,0x00);
  642. iic(2,0x78,0xba,0x05,0x00);
  643. #if 0
  644. iic(2,0x78,0x83,0x8c,0x00); /* brightness */
  645. #endif
  646. printk(".");
  647. /* color correction */
  648. iic(3,0x78,0x49,0x00,0x95); /* a */
  649. iic(3,0x78,0x49,0x01,0x96); /* b */
  650. iic(3,0x78,0x49,0x03,0x85); /* c */
  651. iic(3,0x78,0x49,0x04,0x97); /* d */
  652. iic(3,0x78,0x49,0x02,0x7e); /* e(Lo) */
  653. iic(3,0x78,0x49,0x05,0xa4); /* f(Lo) */
  654. iic(3,0x78,0x49,0x06,0x04); /* e(Hi) */
  655. iic(3,0x78,0x49,0x07,0x04); /* e(Hi) */
  656. iic(2,0x78,0x48,0x01,0x00); /* on=1 off=0 */
  657. printk(".");
  658. iic(2,0x78,0x11,0x00,0x00); /* end */
  659. printk(" done\n");
  660. return 0;
  661. }
  662. void ar_release(struct video_device *vfd)
  663. {
  664. struct ar_device *ar = vfd->priv;
  665. down(&ar->lock);
  666. video_device_release(vfd);
  667. }
  668. /****************************************************************************
  669. *
  670. * Video4Linux Module functions
  671. *
  672. ****************************************************************************/
  673. static struct file_operations ar_fops = {
  674. .owner = THIS_MODULE,
  675. .open = video_exclusive_open,
  676. .release = video_exclusive_release,
  677. .read = ar_read,
  678. .ioctl = ar_ioctl,
  679. .llseek = no_llseek,
  680. };
  681. static struct video_device ar_template = {
  682. .owner = THIS_MODULE,
  683. .name = "Colour AR VGA",
  684. .type = VID_TYPE_CAPTURE,
  685. .hardware = VID_HARDWARE_ARV,
  686. .fops = &ar_fops,
  687. .release = ar_release,
  688. .minor = -1,
  689. };
  690. #define ALIGN4(x) ((((int)(x)) & 0x3) == 0)
  691. static struct ar_device ardev;
  692. static int __init ar_init(void)
  693. {
  694. struct ar_device *ar;
  695. int ret;
  696. int i;
  697. DEBUG(1, "ar_init:\n");
  698. ret = -EIO;
  699. printk(KERN_INFO "arv: Colour AR VGA driver %s\n", VERSION);
  700. ar = &ardev;
  701. memset(ar, 0, sizeof(struct ar_device));
  702. #if USE_INT
  703. /* allocate a DMA buffer for 1 line. */
  704. ar->line_buff = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL | GFP_DMA);
  705. if (ar->line_buff == NULL || ! ALIGN4(ar->line_buff)) {
  706. printk("arv: buffer allocation failed for DMA.\n");
  707. ret = -ENOMEM;
  708. goto out_end;
  709. }
  710. #endif
  711. /* allocate buffers for a frame */
  712. for (i = 0; i < MAX_AR_HEIGHT; i++) {
  713. ar->frame[i] = kmalloc(MAX_AR_LINE_BYTES, GFP_KERNEL);
  714. if (ar->frame[i] == NULL || ! ALIGN4(ar->frame[i])) {
  715. printk("arv: buffer allocation failed for frame.\n");
  716. ret = -ENOMEM;
  717. goto out_line_buff;
  718. }
  719. }
  720. ar->vdev = video_device_alloc();
  721. if (!ar->vdev) {
  722. printk(KERN_ERR "arv: video_device_alloc() failed\n");
  723. return -ENOMEM;
  724. }
  725. memcpy(ar->vdev, &ar_template, sizeof(ar_template));
  726. ar->vdev->priv = ar;
  727. if (vga) {
  728. ar->width = AR_WIDTH_VGA;
  729. ar->height = AR_HEIGHT_VGA;
  730. ar->size = AR_SIZE_VGA;
  731. ar->frame_bytes = AR_FRAME_BYTES_VGA;
  732. ar->line_bytes = AR_LINE_BYTES_VGA;
  733. if (vga_interlace)
  734. ar->mode = AR_MODE_INTERLACE;
  735. else
  736. ar->mode = AR_MODE_NORMAL;
  737. } else {
  738. ar->width = AR_WIDTH_QVGA;
  739. ar->height = AR_HEIGHT_QVGA;
  740. ar->size = AR_SIZE_QVGA;
  741. ar->frame_bytes = AR_FRAME_BYTES_QVGA;
  742. ar->line_bytes = AR_LINE_BYTES_QVGA;
  743. ar->mode = AR_MODE_INTERLACE;
  744. }
  745. init_MUTEX(&ar->lock);
  746. init_waitqueue_head(&ar->wait);
  747. #if USE_INT
  748. if (request_irq(M32R_IRQ_INT3, ar_interrupt, 0, "arv", ar)) {
  749. printk("arv: request_irq(%d) failed.\n", M32R_IRQ_INT3);
  750. ret = -EIO;
  751. goto out_irq;
  752. }
  753. #endif
  754. if (ar_initialize(ar->vdev) != 0) {
  755. printk("arv: M64278 not found.\n");
  756. ret = -ENODEV;
  757. goto out_dev;
  758. }
  759. /*
  760. * ok, we can initialize h/w according to parameters,
  761. * so register video device as a frame grabber type.
  762. * device is named "video[0-64]".
  763. * video_register_device() initializes h/w using ar_initialize().
  764. */
  765. if (video_register_device(ar->vdev, VFL_TYPE_GRABBER, video_nr) != 0) {
  766. /* return -1, -ENFILE(full) or others */
  767. printk("arv: register video (Colour AR) failed.\n");
  768. ret = -ENODEV;
  769. goto out_dev;
  770. }
  771. printk("video%d: Found M64278 VGA (IRQ %d, Freq %dMHz).\n",
  772. ar->vdev->minor, M32R_IRQ_INT3, freq);
  773. return 0;
  774. out_dev:
  775. #if USE_INT
  776. free_irq(M32R_IRQ_INT3, ar);
  777. out_irq:
  778. #endif
  779. for (i = 0; i < MAX_AR_HEIGHT; i++) {
  780. if (ar->frame[i])
  781. kfree(ar->frame[i]);
  782. }
  783. out_line_buff:
  784. #if USE_INT
  785. kfree(ar->line_buff);
  786. out_end:
  787. #endif
  788. return ret;
  789. }
  790. static int __init ar_init_module(void)
  791. {
  792. freq = (boot_cpu_data.bus_clock / 1000000);
  793. printk("arv: Bus clock %d\n", freq);
  794. if (freq != 50 && freq != 75)
  795. freq = DEFAULT_FREQ;
  796. return ar_init();
  797. }
  798. static void __exit ar_cleanup_module(void)
  799. {
  800. struct ar_device *ar;
  801. int i;
  802. ar = &ardev;
  803. video_unregister_device(ar->vdev);
  804. #if USE_INT
  805. free_irq(M32R_IRQ_INT3, ar);
  806. #endif
  807. for (i = 0; i < MAX_AR_HEIGHT; i++) {
  808. if (ar->frame[i])
  809. kfree(ar->frame[i]);
  810. }
  811. #if USE_INT
  812. kfree(ar->line_buff);
  813. #endif
  814. }
  815. module_init(ar_init_module);
  816. module_exit(ar_cleanup_module);
  817. MODULE_AUTHOR("Takeo Takahashi <takahashi.takeo@renesas.com>");
  818. MODULE_DESCRIPTION("Colour AR M64278(VGA) for Video4Linux");
  819. MODULE_LICENSE("GPL");