cciss.h 6.1 KB

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  1. #ifndef CCISS_H
  2. #define CCISS_H
  3. #include <linux/genhd.h>
  4. #include "cciss_cmd.h"
  5. #define NWD 16
  6. #define NWD_SHIFT 4
  7. #define MAX_PART (1 << NWD_SHIFT)
  8. #define IO_OK 0
  9. #define IO_ERROR 1
  10. #define MAJOR_NR COMPAQ_CISS_MAJOR
  11. struct ctlr_info;
  12. typedef struct ctlr_info ctlr_info_t;
  13. struct access_method {
  14. void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
  15. void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
  16. unsigned long (*fifo_full)(ctlr_info_t *h);
  17. unsigned long (*intr_pending)(ctlr_info_t *h);
  18. unsigned long (*command_completed)(ctlr_info_t *h);
  19. };
  20. typedef struct _drive_info_struct
  21. {
  22. __u32 LunID;
  23. int usage_count;
  24. struct request_queue *queue;
  25. sector_t nr_blocks;
  26. int block_size;
  27. int heads;
  28. int sectors;
  29. int cylinders;
  30. int raid_level;
  31. } drive_info_struct;
  32. struct ctlr_info
  33. {
  34. int ctlr;
  35. char devname[8];
  36. char *product_name;
  37. char firm_ver[4]; // Firmware version
  38. struct pci_dev *pdev;
  39. __u32 board_id;
  40. void __iomem *vaddr;
  41. unsigned long paddr;
  42. unsigned long io_mem_addr;
  43. unsigned long io_mem_length;
  44. CfgTable_struct __iomem *cfgtable;
  45. unsigned int intr;
  46. int interrupts_enabled;
  47. int major;
  48. int max_commands;
  49. int commands_outstanding;
  50. int max_outstanding; /* Debug */
  51. int num_luns;
  52. int highest_lun;
  53. int usage_count; /* number of opens all all minor devices */
  54. // information about each logical volume
  55. drive_info_struct drv[CISS_MAX_LUN];
  56. struct access_method access;
  57. /* queue and queue Info */
  58. CommandList_struct *reqQ;
  59. CommandList_struct *cmpQ;
  60. unsigned int Qdepth;
  61. unsigned int maxQsinceinit;
  62. unsigned int maxSG;
  63. spinlock_t lock;
  64. //* pointers to command and error info pool */
  65. CommandList_struct *cmd_pool;
  66. dma_addr_t cmd_pool_dhandle;
  67. ErrorInfo_struct *errinfo_pool;
  68. dma_addr_t errinfo_pool_dhandle;
  69. unsigned long *cmd_pool_bits;
  70. int nr_allocs;
  71. int nr_frees;
  72. int busy_configuring;
  73. /* This element holds the zero based queue number of the last
  74. * queue to be started. It is used for fairness.
  75. */
  76. int next_to_run;
  77. // Disk structures we need to pass back
  78. struct gendisk *gendisk[NWD];
  79. #ifdef CONFIG_CISS_SCSI_TAPE
  80. void *scsi_ctlr; /* ptr to structure containing scsi related stuff */
  81. #endif
  82. };
  83. /* Defining the diffent access_menthods */
  84. /*
  85. * Memory mapped FIFO interface (SMART 53xx cards)
  86. */
  87. #define SA5_DOORBELL 0x20
  88. #define SA5_REQUEST_PORT_OFFSET 0x40
  89. #define SA5_REPLY_INTR_MASK_OFFSET 0x34
  90. #define SA5_REPLY_PORT_OFFSET 0x44
  91. #define SA5_INTR_STATUS 0x30
  92. #define SA5_SCRATCHPAD_OFFSET 0xB0
  93. #define SA5_CTCFG_OFFSET 0xB4
  94. #define SA5_CTMEM_OFFSET 0xB8
  95. #define SA5_INTR_OFF 0x08
  96. #define SA5B_INTR_OFF 0x04
  97. #define SA5_INTR_PENDING 0x08
  98. #define SA5B_INTR_PENDING 0x04
  99. #define FIFO_EMPTY 0xffffffff
  100. #define CCISS_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
  101. #define CISS_ERROR_BIT 0x02
  102. #define CCISS_INTR_ON 1
  103. #define CCISS_INTR_OFF 0
  104. /*
  105. Send the command to the hardware
  106. */
  107. static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
  108. {
  109. #ifdef CCISS_DEBUG
  110. printk("Sending %x - down to controller\n", c->busaddr );
  111. #endif /* CCISS_DEBUG */
  112. writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
  113. h->commands_outstanding++;
  114. if ( h->commands_outstanding > h->max_outstanding)
  115. h->max_outstanding = h->commands_outstanding;
  116. }
  117. /*
  118. * This card is the opposite of the other cards.
  119. * 0 turns interrupts on...
  120. * 0x08 turns them off...
  121. */
  122. static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
  123. {
  124. if (val)
  125. { /* Turn interrupts on */
  126. h->interrupts_enabled = 1;
  127. writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  128. } else /* Turn them off */
  129. {
  130. h->interrupts_enabled = 0;
  131. writel( SA5_INTR_OFF,
  132. h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  133. }
  134. }
  135. /*
  136. * This card is the opposite of the other cards.
  137. * 0 turns interrupts on...
  138. * 0x04 turns them off...
  139. */
  140. static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
  141. {
  142. if (val)
  143. { /* Turn interrupts on */
  144. h->interrupts_enabled = 1;
  145. writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  146. } else /* Turn them off */
  147. {
  148. h->interrupts_enabled = 0;
  149. writel( SA5B_INTR_OFF,
  150. h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  151. }
  152. }
  153. /*
  154. * Returns true if fifo is full.
  155. *
  156. */
  157. static unsigned long SA5_fifo_full(ctlr_info_t *h)
  158. {
  159. if( h->commands_outstanding >= h->max_commands)
  160. return(1);
  161. else
  162. return(0);
  163. }
  164. /*
  165. * returns value read from hardware.
  166. * returns FIFO_EMPTY if there is nothing to read
  167. */
  168. static unsigned long SA5_completed(ctlr_info_t *h)
  169. {
  170. unsigned long register_value
  171. = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
  172. if(register_value != FIFO_EMPTY)
  173. {
  174. h->commands_outstanding--;
  175. #ifdef CCISS_DEBUG
  176. printk("cciss: Read %lx back from board\n", register_value);
  177. #endif /* CCISS_DEBUG */
  178. }
  179. #ifdef CCISS_DEBUG
  180. else
  181. {
  182. printk("cciss: FIFO Empty read\n");
  183. }
  184. #endif
  185. return ( register_value);
  186. }
  187. /*
  188. * Returns true if an interrupt is pending..
  189. */
  190. static unsigned long SA5_intr_pending(ctlr_info_t *h)
  191. {
  192. unsigned long register_value =
  193. readl(h->vaddr + SA5_INTR_STATUS);
  194. #ifdef CCISS_DEBUG
  195. printk("cciss: intr_pending %lx\n", register_value);
  196. #endif /* CCISS_DEBUG */
  197. if( register_value & SA5_INTR_PENDING)
  198. return 1;
  199. return 0 ;
  200. }
  201. /*
  202. * Returns true if an interrupt is pending..
  203. */
  204. static unsigned long SA5B_intr_pending(ctlr_info_t *h)
  205. {
  206. unsigned long register_value =
  207. readl(h->vaddr + SA5_INTR_STATUS);
  208. #ifdef CCISS_DEBUG
  209. printk("cciss: intr_pending %lx\n", register_value);
  210. #endif /* CCISS_DEBUG */
  211. if( register_value & SA5B_INTR_PENDING)
  212. return 1;
  213. return 0 ;
  214. }
  215. static struct access_method SA5_access = {
  216. SA5_submit_command,
  217. SA5_intr_mask,
  218. SA5_fifo_full,
  219. SA5_intr_pending,
  220. SA5_completed,
  221. };
  222. static struct access_method SA5B_access = {
  223. SA5_submit_command,
  224. SA5B_intr_mask,
  225. SA5_fifo_full,
  226. SA5B_intr_pending,
  227. SA5_completed,
  228. };
  229. struct board_type {
  230. __u32 board_id;
  231. char *product_name;
  232. struct access_method *access;
  233. };
  234. #define CCISS_LOCK(i) (&hba[i]->lock)
  235. #endif /* CCISS_H */