gbus_int.c 7.4 KB

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  1. /*
  2. * arch/v850/kernel/gbus_int.c -- Midas labs GBUS interrupt support
  3. *
  4. * Copyright (C) 2001,02,03 NEC Electronics Corporation
  5. * Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
  6. *
  7. * This file is subject to the terms and conditions of the GNU General
  8. * Public License. See the file COPYING in the main directory of this
  9. * archive for more details.
  10. *
  11. * Written by Miles Bader <miles@gnu.org>
  12. */
  13. #include <linux/types.h>
  14. #include <linux/init.h>
  15. #include <linux/irq.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/signal.h>
  18. #include <asm/machdep.h>
  19. /* The number of shared GINT interrupts. */
  20. #define NUM_GINTS 4
  21. /* For each GINT interrupt, how many GBUS interrupts are using it. */
  22. static unsigned gint_num_active_irqs[NUM_GINTS] = { 0 };
  23. /* A table of GINTn interrupts we actually use.
  24. Note that we don't use GINT0 because all the boards we support treat it
  25. specially. */
  26. struct used_gint {
  27. unsigned gint;
  28. unsigned priority;
  29. } used_gint[] = {
  30. { 1, GBUS_INT_PRIORITY_HIGH },
  31. { 3, GBUS_INT_PRIORITY_LOW }
  32. };
  33. #define NUM_USED_GINTS (sizeof used_gint / sizeof used_gint[0])
  34. /* A table of which GINT is used by each GBUS interrupts (they are
  35. assigned based on priority). */
  36. static unsigned char gbus_int_gint[IRQ_GBUS_INT_NUM];
  37. /* Interrupt enabling/disabling. */
  38. /* Enable interrupt handling for interrupt IRQ. */
  39. void gbus_int_enable_irq (unsigned irq)
  40. {
  41. unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
  42. GBUS_INT_ENABLE (GBUS_INT_IRQ_WORD(irq), gint)
  43. |= GBUS_INT_IRQ_MASK (irq);
  44. }
  45. /* Disable interrupt handling for interrupt IRQ. Note that any
  46. interrupts received while disabled will be delivered once the
  47. interrupt is enabled again, unless they are explicitly cleared using
  48. `gbus_int_clear_pending_irq'. */
  49. void gbus_int_disable_irq (unsigned irq)
  50. {
  51. unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
  52. GBUS_INT_ENABLE (GBUS_INT_IRQ_WORD(irq), gint)
  53. &= ~GBUS_INT_IRQ_MASK (irq);
  54. }
  55. /* Return true if interrupt handling for interrupt IRQ is enabled. */
  56. int gbus_int_irq_enabled (unsigned irq)
  57. {
  58. unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
  59. return (GBUS_INT_ENABLE (GBUS_INT_IRQ_WORD(irq), gint)
  60. & GBUS_INT_IRQ_MASK(irq));
  61. }
  62. /* Disable all GBUS irqs. */
  63. void gbus_int_disable_irqs ()
  64. {
  65. unsigned w, n;
  66. for (w = 0; w < GBUS_INT_NUM_WORDS; w++)
  67. for (n = 0; n < IRQ_GINT_NUM; n++)
  68. GBUS_INT_ENABLE (w, n) = 0;
  69. }
  70. /* Clear any pending interrupts for IRQ. */
  71. void gbus_int_clear_pending_irq (unsigned irq)
  72. {
  73. GBUS_INT_CLEAR (GBUS_INT_IRQ_WORD(irq)) = GBUS_INT_IRQ_MASK (irq);
  74. }
  75. /* Return true if interrupt IRQ is pending (but disabled). */
  76. int gbus_int_irq_pending (unsigned irq)
  77. {
  78. return (GBUS_INT_STATUS (GBUS_INT_IRQ_WORD(irq))
  79. & GBUS_INT_IRQ_MASK(irq));
  80. }
  81. /* Delegating interrupts. */
  82. /* Handle a shared GINT interrupt by passing to the appropriate GBUS
  83. interrupt handler. */
  84. static irqreturn_t gbus_int_handle_irq (int irq, void *dev_id,
  85. struct pt_regs *regs)
  86. {
  87. unsigned w;
  88. irqreturn_t rval = IRQ_NONE;
  89. unsigned gint = irq - IRQ_GINT (0);
  90. for (w = 0; w < GBUS_INT_NUM_WORDS; w++) {
  91. unsigned status = GBUS_INT_STATUS (w);
  92. unsigned enable = GBUS_INT_ENABLE (w, gint);
  93. /* Only pay attention to enabled interrupts. */
  94. status &= enable;
  95. if (status) {
  96. irq = IRQ_GBUS_INT (w * GBUS_INT_BITS_PER_WORD);
  97. do {
  98. /* There's an active interrupt in word
  99. W, find out which one, and call its
  100. handler. */
  101. while (! (status & 0x1)) {
  102. irq++;
  103. status >>= 1;
  104. }
  105. status &= ~0x1;
  106. /* Recursively call handle_irq to handle it. */
  107. handle_irq (irq, regs);
  108. rval = IRQ_HANDLED;
  109. } while (status);
  110. }
  111. }
  112. /* Toggle the `all enable' bit back and forth, which should cause
  113. another edge transition if there are any other interrupts
  114. still pending, and so result in another CPU interrupt. */
  115. GBUS_INT_ENABLE (0, gint) &= ~0x1;
  116. GBUS_INT_ENABLE (0, gint) |= 0x1;
  117. return rval;
  118. }
  119. /* Initialize GBUS interrupt sources. */
  120. static void irq_nop (unsigned irq) { }
  121. static unsigned gbus_int_startup_irq (unsigned irq)
  122. {
  123. unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
  124. if (gint_num_active_irqs[gint] == 0) {
  125. /* First enable the CPU interrupt. */
  126. int rval =
  127. request_irq (IRQ_GINT(gint), gbus_int_handle_irq,
  128. SA_INTERRUPT,
  129. "gbus_int_handler",
  130. &gint_num_active_irqs[gint]);
  131. if (rval != 0)
  132. return rval;
  133. }
  134. gint_num_active_irqs[gint]++;
  135. gbus_int_clear_pending_irq (irq);
  136. gbus_int_enable_irq (irq);
  137. return 0;
  138. }
  139. static void gbus_int_shutdown_irq (unsigned irq)
  140. {
  141. unsigned gint = gbus_int_gint[irq - GBUS_INT_BASE_IRQ];
  142. gbus_int_disable_irq (irq);
  143. if (--gint_num_active_irqs[gint] == 0)
  144. /* Disable the CPU interrupt. */
  145. free_irq (IRQ_GINT(gint), &gint_num_active_irqs[gint]);
  146. }
  147. /* Initialize HW_IRQ_TYPES for INTC-controlled irqs described in array
  148. INITS (which is terminated by an entry with the name field == 0). */
  149. void __init gbus_int_init_irq_types (struct gbus_int_irq_init *inits,
  150. struct hw_interrupt_type *hw_irq_types)
  151. {
  152. struct gbus_int_irq_init *init;
  153. for (init = inits; init->name; init++) {
  154. unsigned i;
  155. struct hw_interrupt_type *hwit = hw_irq_types++;
  156. hwit->typename = init->name;
  157. hwit->startup = gbus_int_startup_irq;
  158. hwit->shutdown = gbus_int_shutdown_irq;
  159. hwit->enable = gbus_int_enable_irq;
  160. hwit->disable = gbus_int_disable_irq;
  161. hwit->ack = irq_nop;
  162. hwit->end = irq_nop;
  163. /* Initialize kernel IRQ infrastructure for this interrupt. */
  164. init_irq_handlers(init->base, init->num, init->interval, hwit);
  165. /* Set the interrupt priorities. */
  166. for (i = 0; i < init->num; i++) {
  167. unsigned j;
  168. for (j = 0; j < NUM_USED_GINTS; j++)
  169. if (used_gint[j].priority > init->priority)
  170. break;
  171. /* Wherever we stopped looking is one past the
  172. GINT we want. */
  173. gbus_int_gint[init->base + i * init->interval
  174. - GBUS_INT_BASE_IRQ]
  175. = used_gint[j > 0 ? j - 1 : 0].gint;
  176. }
  177. }
  178. }
  179. /* Initialize IRQS. */
  180. /* Chip interrupts (GINTn) shared among GBUS interrupts. */
  181. static struct hw_interrupt_type gint_hw_itypes[NUM_USED_GINTS];
  182. /* GBUS interrupts themselves. */
  183. struct gbus_int_irq_init gbus_irq_inits[] __initdata = {
  184. /* First set defaults. */
  185. { "GBUS_INT", IRQ_GBUS_INT(0), IRQ_GBUS_INT_NUM, 1, 6},
  186. { 0 }
  187. };
  188. #define NUM_GBUS_IRQ_INITS \
  189. ((sizeof gbus_irq_inits / sizeof gbus_irq_inits[0]) - 1)
  190. static struct hw_interrupt_type gbus_hw_itypes[NUM_GBUS_IRQ_INITS];
  191. /* Initialize GBUS interrupts. */
  192. void __init gbus_int_init_irqs (void)
  193. {
  194. unsigned i;
  195. /* First initialize the shared gint interrupts. */
  196. for (i = 0; i < NUM_USED_GINTS; i++) {
  197. unsigned gint = used_gint[i].gint;
  198. struct v850e_intc_irq_init gint_irq_init[2];
  199. /* We initialize one GINT interrupt at a time. */
  200. gint_irq_init[0].name = "GINT";
  201. gint_irq_init[0].base = IRQ_GINT (gint);
  202. gint_irq_init[0].num = 1;
  203. gint_irq_init[0].interval = 1;
  204. gint_irq_init[0].priority = used_gint[i].priority;
  205. gint_irq_init[1].name = 0; /* Terminate the vector. */
  206. v850e_intc_init_irq_types (gint_irq_init, gint_hw_itypes);
  207. }
  208. /* Then the GBUS interrupts. */
  209. gbus_int_disable_irqs ();
  210. gbus_int_init_irq_types (gbus_irq_inits, gbus_hw_itypes);
  211. /* Turn on the `all enable' bits, which are ANDed with
  212. individual interrupt enable bits; we only want to bother with
  213. the latter. They are the first bit in the first word of each
  214. interrupt-enable area. */
  215. for (i = 0; i < NUM_USED_GINTS; i++)
  216. GBUS_INT_ENABLE (0, used_gint[i].gint) = 0x1;
  217. }