sun4d_irq.c 14 KB

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  1. /* $Id: sun4d_irq.c,v 1.29 2001/12/11 04:55:51 davem Exp $
  2. * arch/sparc/kernel/sun4d_irq.c:
  3. * SS1000/SC2000 interrupt handling.
  4. *
  5. * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  6. * Heavily based on arch/sparc/kernel/irq.c.
  7. */
  8. #include <linux/config.h>
  9. #include <linux/errno.h>
  10. #include <linux/linkage.h>
  11. #include <linux/kernel_stat.h>
  12. #include <linux/signal.h>
  13. #include <linux/sched.h>
  14. #include <linux/ptrace.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/slab.h>
  17. #include <linux/random.h>
  18. #include <linux/init.h>
  19. #include <linux/smp.h>
  20. #include <linux/smp_lock.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/seq_file.h>
  23. #include <asm/ptrace.h>
  24. #include <asm/processor.h>
  25. #include <asm/system.h>
  26. #include <asm/psr.h>
  27. #include <asm/smp.h>
  28. #include <asm/vaddrs.h>
  29. #include <asm/timer.h>
  30. #include <asm/openprom.h>
  31. #include <asm/oplib.h>
  32. #include <asm/traps.h>
  33. #include <asm/irq.h>
  34. #include <asm/io.h>
  35. #include <asm/pgalloc.h>
  36. #include <asm/pgtable.h>
  37. #include <asm/sbus.h>
  38. #include <asm/sbi.h>
  39. #include <asm/cacheflush.h>
  40. /* If you trust current SCSI layer to handle different SCSI IRQs, enable this. I don't trust it... -jj */
  41. /* #define DISTRIBUTE_IRQS */
  42. struct sun4d_timer_regs *sun4d_timers;
  43. #define TIMER_IRQ 10
  44. #define MAX_STATIC_ALLOC 4
  45. extern struct irqaction static_irqaction[MAX_STATIC_ALLOC];
  46. extern int static_irq_count;
  47. unsigned char cpu_leds[32];
  48. #ifdef CONFIG_SMP
  49. unsigned char sbus_tid[32];
  50. #endif
  51. extern struct irqaction *irq_action[];
  52. extern spinlock_t irq_action_lock;
  53. struct sbus_action {
  54. struct irqaction *action;
  55. /* For SMP this needs to be extended */
  56. } *sbus_actions;
  57. static int pil_to_sbus[] = {
  58. 0, 0, 1, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0, 0,
  59. };
  60. static int sbus_to_pil[] = {
  61. 0, 2, 3, 5, 7, 9, 11, 13,
  62. };
  63. static int nsbi;
  64. #ifdef CONFIG_SMP
  65. DEFINE_SPINLOCK(sun4d_imsk_lock);
  66. #endif
  67. int show_sun4d_interrupts(struct seq_file *p, void *v)
  68. {
  69. int i = *(loff_t *) v, j = 0, k = 0, sbusl;
  70. struct irqaction * action;
  71. unsigned long flags;
  72. #ifdef CONFIG_SMP
  73. int x;
  74. #endif
  75. spin_lock_irqsave(&irq_action_lock, flags);
  76. if (i < NR_IRQS) {
  77. sbusl = pil_to_sbus[i];
  78. if (!sbusl) {
  79. action = *(i + irq_action);
  80. if (!action)
  81. goto out_unlock;
  82. } else {
  83. for (j = 0; j < nsbi; j++) {
  84. for (k = 0; k < 4; k++)
  85. if ((action = sbus_actions [(j << 5) + (sbusl << 2) + k].action))
  86. goto found_it;
  87. }
  88. goto out_unlock;
  89. }
  90. found_it: seq_printf(p, "%3d: ", i);
  91. #ifndef CONFIG_SMP
  92. seq_printf(p, "%10u ", kstat_irqs(i));
  93. #else
  94. for (x = 0; x < NR_CPUS; x++) {
  95. if (cpu_online(x))
  96. seq_printf(p, "%10u ",
  97. kstat_cpu(cpu_logical_map(x)).irqs[i]);
  98. }
  99. #endif
  100. seq_printf(p, "%c %s",
  101. (action->flags & SA_INTERRUPT) ? '+' : ' ',
  102. action->name);
  103. action = action->next;
  104. for (;;) {
  105. for (; action; action = action->next) {
  106. seq_printf(p, ",%s %s",
  107. (action->flags & SA_INTERRUPT) ? " +" : "",
  108. action->name);
  109. }
  110. if (!sbusl) break;
  111. k++;
  112. if (k < 4)
  113. action = sbus_actions [(j << 5) + (sbusl << 2) + k].action;
  114. else {
  115. j++;
  116. if (j == nsbi) break;
  117. k = 0;
  118. action = sbus_actions [(j << 5) + (sbusl << 2)].action;
  119. }
  120. }
  121. seq_putc(p, '\n');
  122. }
  123. out_unlock:
  124. spin_unlock_irqrestore(&irq_action_lock, flags);
  125. return 0;
  126. }
  127. void sun4d_free_irq(unsigned int irq, void *dev_id)
  128. {
  129. struct irqaction *action, **actionp;
  130. struct irqaction *tmp = NULL;
  131. unsigned long flags;
  132. spin_lock_irqsave(&irq_action_lock, flags);
  133. if (irq < 15)
  134. actionp = irq + irq_action;
  135. else
  136. actionp = &(sbus_actions[irq - (1 << 5)].action);
  137. action = *actionp;
  138. if (!action) {
  139. printk("Trying to free free IRQ%d\n",irq);
  140. goto out_unlock;
  141. }
  142. if (dev_id) {
  143. for (; action; action = action->next) {
  144. if (action->dev_id == dev_id)
  145. break;
  146. tmp = action;
  147. }
  148. if (!action) {
  149. printk("Trying to free free shared IRQ%d\n",irq);
  150. goto out_unlock;
  151. }
  152. } else if (action->flags & SA_SHIRQ) {
  153. printk("Trying to free shared IRQ%d with NULL device ID\n", irq);
  154. goto out_unlock;
  155. }
  156. if (action->flags & SA_STATIC_ALLOC)
  157. {
  158. /* This interrupt is marked as specially allocated
  159. * so it is a bad idea to free it.
  160. */
  161. printk("Attempt to free statically allocated IRQ%d (%s)\n",
  162. irq, action->name);
  163. goto out_unlock;
  164. }
  165. if (action && tmp)
  166. tmp->next = action->next;
  167. else
  168. *actionp = action->next;
  169. spin_unlock_irqrestore(&irq_action_lock, flags);
  170. synchronize_irq(irq);
  171. spin_lock_irqsave(&irq_action_lock, flags);
  172. kfree(action);
  173. if (!(*actionp))
  174. disable_irq(irq);
  175. out_unlock:
  176. spin_unlock_irqrestore(&irq_action_lock, flags);
  177. }
  178. extern void unexpected_irq(int, void *, struct pt_regs *);
  179. void sun4d_handler_irq(int irq, struct pt_regs * regs)
  180. {
  181. struct irqaction * action;
  182. int cpu = smp_processor_id();
  183. /* SBUS IRQ level (1 - 7) */
  184. int sbusl = pil_to_sbus[irq];
  185. /* FIXME: Is this necessary?? */
  186. cc_get_ipen();
  187. cc_set_iclr(1 << irq);
  188. irq_enter();
  189. kstat_cpu(cpu).irqs[irq]++;
  190. if (!sbusl) {
  191. action = *(irq + irq_action);
  192. if (!action)
  193. unexpected_irq(irq, NULL, regs);
  194. do {
  195. action->handler(irq, action->dev_id, regs);
  196. action = action->next;
  197. } while (action);
  198. } else {
  199. int bus_mask = bw_get_intr_mask(sbusl) & 0x3ffff;
  200. int sbino;
  201. struct sbus_action *actionp;
  202. unsigned mask, slot;
  203. int sbil = (sbusl << 2);
  204. bw_clear_intr_mask(sbusl, bus_mask);
  205. /* Loop for each pending SBI */
  206. for (sbino = 0; bus_mask; sbino++, bus_mask >>= 1)
  207. if (bus_mask & 1) {
  208. mask = acquire_sbi(SBI2DEVID(sbino), 0xf << sbil);
  209. mask &= (0xf << sbil);
  210. actionp = sbus_actions + (sbino << 5) + (sbil);
  211. /* Loop for each pending SBI slot */
  212. for (slot = (1 << sbil); mask; slot <<= 1, actionp++)
  213. if (mask & slot) {
  214. mask &= ~slot;
  215. action = actionp->action;
  216. if (!action)
  217. unexpected_irq(irq, NULL, regs);
  218. do {
  219. action->handler(irq, action->dev_id, regs);
  220. action = action->next;
  221. } while (action);
  222. release_sbi(SBI2DEVID(sbino), slot);
  223. }
  224. }
  225. }
  226. irq_exit();
  227. }
  228. unsigned int sun4d_build_irq(struct sbus_dev *sdev, int irq)
  229. {
  230. int sbusl = pil_to_sbus[irq];
  231. if (sbusl)
  232. return ((sdev->bus->board + 1) << 5) + (sbusl << 2) + sdev->slot;
  233. else
  234. return irq;
  235. }
  236. unsigned int sun4d_sbint_to_irq(struct sbus_dev *sdev, unsigned int sbint)
  237. {
  238. if (sbint >= sizeof(sbus_to_pil)) {
  239. printk(KERN_ERR "%s: bogus SBINT %d\n", sdev->prom_name, sbint);
  240. BUG();
  241. }
  242. return sun4d_build_irq(sdev, sbus_to_pil[sbint]);
  243. }
  244. int sun4d_request_irq(unsigned int irq,
  245. irqreturn_t (*handler)(int, void *, struct pt_regs *),
  246. unsigned long irqflags, const char * devname, void *dev_id)
  247. {
  248. struct irqaction *action, *tmp = NULL, **actionp;
  249. unsigned long flags;
  250. int ret;
  251. if(irq > 14 && irq < (1 << 5)) {
  252. ret = -EINVAL;
  253. goto out;
  254. }
  255. if (!handler) {
  256. ret = -EINVAL;
  257. goto out;
  258. }
  259. spin_lock_irqsave(&irq_action_lock, flags);
  260. if (irq >= (1 << 5))
  261. actionp = &(sbus_actions[irq - (1 << 5)].action);
  262. else
  263. actionp = irq + irq_action;
  264. action = *actionp;
  265. if (action) {
  266. if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
  267. for (tmp = action; tmp->next; tmp = tmp->next);
  268. } else {
  269. ret = -EBUSY;
  270. goto out_unlock;
  271. }
  272. if ((action->flags & SA_INTERRUPT) ^ (irqflags & SA_INTERRUPT)) {
  273. printk("Attempt to mix fast and slow interrupts on IRQ%d denied\n", irq);
  274. ret = -EBUSY;
  275. goto out_unlock;
  276. }
  277. action = NULL; /* Or else! */
  278. }
  279. /* If this is flagged as statically allocated then we use our
  280. * private struct which is never freed.
  281. */
  282. if (irqflags & SA_STATIC_ALLOC) {
  283. if (static_irq_count < MAX_STATIC_ALLOC)
  284. action = &static_irqaction[static_irq_count++];
  285. else
  286. printk("Request for IRQ%d (%s) SA_STATIC_ALLOC failed using kmalloc\n", irq, devname);
  287. }
  288. if (action == NULL)
  289. action = (struct irqaction *)kmalloc(sizeof(struct irqaction),
  290. GFP_ATOMIC);
  291. if (!action) {
  292. ret = -ENOMEM;
  293. goto out_unlock;
  294. }
  295. action->handler = handler;
  296. action->flags = irqflags;
  297. cpus_clear(action->mask);
  298. action->name = devname;
  299. action->next = NULL;
  300. action->dev_id = dev_id;
  301. if (tmp)
  302. tmp->next = action;
  303. else
  304. *actionp = action;
  305. enable_irq(irq);
  306. ret = 0;
  307. out_unlock:
  308. spin_unlock_irqrestore(&irq_action_lock, flags);
  309. out:
  310. return ret;
  311. }
  312. static void sun4d_disable_irq(unsigned int irq)
  313. {
  314. #ifdef CONFIG_SMP
  315. int tid = sbus_tid[(irq >> 5) - 1];
  316. unsigned long flags;
  317. #endif
  318. if (irq < NR_IRQS) return;
  319. #ifdef CONFIG_SMP
  320. spin_lock_irqsave(&sun4d_imsk_lock, flags);
  321. cc_set_imsk_other(tid, cc_get_imsk_other(tid) | (1 << sbus_to_pil[(irq >> 2) & 7]));
  322. spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
  323. #else
  324. cc_set_imsk(cc_get_imsk() | (1 << sbus_to_pil[(irq >> 2) & 7]));
  325. #endif
  326. }
  327. static void sun4d_enable_irq(unsigned int irq)
  328. {
  329. #ifdef CONFIG_SMP
  330. int tid = sbus_tid[(irq >> 5) - 1];
  331. unsigned long flags;
  332. #endif
  333. if (irq < NR_IRQS) return;
  334. #ifdef CONFIG_SMP
  335. spin_lock_irqsave(&sun4d_imsk_lock, flags);
  336. cc_set_imsk_other(tid, cc_get_imsk_other(tid) & ~(1 << sbus_to_pil[(irq >> 2) & 7]));
  337. spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
  338. #else
  339. cc_set_imsk(cc_get_imsk() & ~(1 << sbus_to_pil[(irq >> 2) & 7]));
  340. #endif
  341. }
  342. #ifdef CONFIG_SMP
  343. static void sun4d_set_cpu_int(int cpu, int level)
  344. {
  345. sun4d_send_ipi(cpu, level);
  346. }
  347. static void sun4d_clear_ipi(int cpu, int level)
  348. {
  349. }
  350. static void sun4d_set_udt(int cpu)
  351. {
  352. }
  353. /* Setup IRQ distribution scheme. */
  354. void __init sun4d_distribute_irqs(void)
  355. {
  356. #ifdef DISTRIBUTE_IRQS
  357. struct sbus_bus *sbus;
  358. unsigned long sbus_serving_map;
  359. sbus_serving_map = cpu_present_map;
  360. for_each_sbus(sbus) {
  361. if ((sbus->board * 2) == boot_cpu_id && (cpu_present_map & (1 << (sbus->board * 2 + 1))))
  362. sbus_tid[sbus->board] = (sbus->board * 2 + 1);
  363. else if (cpu_present_map & (1 << (sbus->board * 2)))
  364. sbus_tid[sbus->board] = (sbus->board * 2);
  365. else if (cpu_present_map & (1 << (sbus->board * 2 + 1)))
  366. sbus_tid[sbus->board] = (sbus->board * 2 + 1);
  367. else
  368. sbus_tid[sbus->board] = 0xff;
  369. if (sbus_tid[sbus->board] != 0xff)
  370. sbus_serving_map &= ~(1 << sbus_tid[sbus->board]);
  371. }
  372. for_each_sbus(sbus)
  373. if (sbus_tid[sbus->board] == 0xff) {
  374. int i = 31;
  375. if (!sbus_serving_map)
  376. sbus_serving_map = cpu_present_map;
  377. while (!(sbus_serving_map & (1 << i)))
  378. i--;
  379. sbus_tid[sbus->board] = i;
  380. sbus_serving_map &= ~(1 << i);
  381. }
  382. for_each_sbus(sbus) {
  383. printk("sbus%d IRQs directed to CPU%d\n", sbus->board, sbus_tid[sbus->board]);
  384. set_sbi_tid(sbus->devid, sbus_tid[sbus->board] << 3);
  385. }
  386. #else
  387. struct sbus_bus *sbus;
  388. int cpuid = cpu_logical_map(1);
  389. if (cpuid == -1)
  390. cpuid = cpu_logical_map(0);
  391. for_each_sbus(sbus) {
  392. sbus_tid[sbus->board] = cpuid;
  393. set_sbi_tid(sbus->devid, cpuid << 3);
  394. }
  395. printk("All sbus IRQs directed to CPU%d\n", cpuid);
  396. #endif
  397. }
  398. #endif
  399. static void sun4d_clear_clock_irq(void)
  400. {
  401. volatile unsigned int clear_intr;
  402. clear_intr = sun4d_timers->l10_timer_limit;
  403. }
  404. static void sun4d_clear_profile_irq(int cpu)
  405. {
  406. bw_get_prof_limit(cpu);
  407. }
  408. static void sun4d_load_profile_irq(int cpu, unsigned int limit)
  409. {
  410. bw_set_prof_limit(cpu, limit);
  411. }
  412. static void __init sun4d_init_timers(irqreturn_t (*counter_fn)(int, void *, struct pt_regs *))
  413. {
  414. int irq;
  415. int cpu;
  416. struct resource r;
  417. int mid;
  418. /* Map the User Timer registers. */
  419. memset(&r, 0, sizeof(r));
  420. #ifdef CONFIG_SMP
  421. r.start = CSR_BASE(boot_cpu_id)+BW_TIMER_LIMIT;
  422. #else
  423. r.start = CSR_BASE(0)+BW_TIMER_LIMIT;
  424. #endif
  425. r.flags = 0xf;
  426. sun4d_timers = (struct sun4d_timer_regs *) sbus_ioremap(&r, 0,
  427. PAGE_SIZE, "user timer");
  428. sun4d_timers->l10_timer_limit = (((1000000/HZ) + 1) << 10);
  429. master_l10_counter = &sun4d_timers->l10_cur_count;
  430. master_l10_limit = &sun4d_timers->l10_timer_limit;
  431. irq = request_irq(TIMER_IRQ,
  432. counter_fn,
  433. (SA_INTERRUPT | SA_STATIC_ALLOC),
  434. "timer", NULL);
  435. if (irq) {
  436. prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
  437. prom_halt();
  438. }
  439. /* Enable user timer free run for CPU 0 in BW */
  440. /* bw_set_ctrl(0, bw_get_ctrl(0) | BW_CTRL_USER_TIMER); */
  441. cpu = 0;
  442. while (!cpu_find_by_instance(cpu, NULL, &mid)) {
  443. sun4d_load_profile_irq(mid >> 3, 0);
  444. cpu++;
  445. }
  446. #ifdef CONFIG_SMP
  447. {
  448. unsigned long flags;
  449. extern unsigned long lvl14_save[4];
  450. struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
  451. extern unsigned int real_irq_entry[], smp4d_ticker[];
  452. extern unsigned int patchme_maybe_smp_msg[];
  453. /* Adjust so that we jump directly to smp4d_ticker */
  454. lvl14_save[2] += smp4d_ticker - real_irq_entry;
  455. /* For SMP we use the level 14 ticker, however the bootup code
  456. * has copied the firmwares level 14 vector into boot cpu's
  457. * trap table, we must fix this now or we get squashed.
  458. */
  459. local_irq_save(flags);
  460. patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */
  461. trap_table->inst_one = lvl14_save[0];
  462. trap_table->inst_two = lvl14_save[1];
  463. trap_table->inst_three = lvl14_save[2];
  464. trap_table->inst_four = lvl14_save[3];
  465. local_flush_cache_all();
  466. local_irq_restore(flags);
  467. }
  468. #endif
  469. }
  470. void __init sun4d_init_sbi_irq(void)
  471. {
  472. struct sbus_bus *sbus;
  473. unsigned mask;
  474. nsbi = 0;
  475. for_each_sbus(sbus)
  476. nsbi++;
  477. sbus_actions = (struct sbus_action *)kmalloc (nsbi * 8 * 4 * sizeof(struct sbus_action), GFP_ATOMIC);
  478. memset (sbus_actions, 0, (nsbi * 8 * 4 * sizeof(struct sbus_action)));
  479. for_each_sbus(sbus) {
  480. #ifdef CONFIG_SMP
  481. extern unsigned char boot_cpu_id;
  482. set_sbi_tid(sbus->devid, boot_cpu_id << 3);
  483. sbus_tid[sbus->board] = boot_cpu_id;
  484. #endif
  485. /* Get rid of pending irqs from PROM */
  486. mask = acquire_sbi(sbus->devid, 0xffffffff);
  487. if (mask) {
  488. printk ("Clearing pending IRQs %08x on SBI %d\n", mask, sbus->board);
  489. release_sbi(sbus->devid, mask);
  490. }
  491. }
  492. }
  493. static char *sun4d_irq_itoa(unsigned int irq)
  494. {
  495. static char buff[16];
  496. if (irq < (1 << 5))
  497. sprintf(buff, "%d", irq);
  498. else
  499. sprintf(buff, "%d,%x", sbus_to_pil[(irq >> 2) & 7], irq);
  500. return buff;
  501. }
  502. void __init sun4d_init_IRQ(void)
  503. {
  504. local_irq_disable();
  505. BTFIXUPSET_CALL(sbint_to_irq, sun4d_sbint_to_irq, BTFIXUPCALL_NORM);
  506. BTFIXUPSET_CALL(enable_irq, sun4d_enable_irq, BTFIXUPCALL_NORM);
  507. BTFIXUPSET_CALL(disable_irq, sun4d_disable_irq, BTFIXUPCALL_NORM);
  508. BTFIXUPSET_CALL(clear_clock_irq, sun4d_clear_clock_irq, BTFIXUPCALL_NORM);
  509. BTFIXUPSET_CALL(clear_profile_irq, sun4d_clear_profile_irq, BTFIXUPCALL_NORM);
  510. BTFIXUPSET_CALL(load_profile_irq, sun4d_load_profile_irq, BTFIXUPCALL_NORM);
  511. BTFIXUPSET_CALL(__irq_itoa, sun4d_irq_itoa, BTFIXUPCALL_NORM);
  512. sparc_init_timers = sun4d_init_timers;
  513. #ifdef CONFIG_SMP
  514. BTFIXUPSET_CALL(set_cpu_int, sun4d_set_cpu_int, BTFIXUPCALL_NORM);
  515. BTFIXUPSET_CALL(clear_cpu_int, sun4d_clear_ipi, BTFIXUPCALL_NOP);
  516. BTFIXUPSET_CALL(set_irq_udt, sun4d_set_udt, BTFIXUPCALL_NOP);
  517. #endif
  518. /* Cannot enable interrupts until OBP ticker is disabled. */
  519. }