ppc405_pci.c 5.0 KB

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  1. /*
  2. * Authors: Frank Rowand <frank_rowand@mvista.com>,
  3. * Debbie Chu <debbie_chu@mvista.com>, or source@mvista.com
  4. * Further modifications by Armin Kuster <akuster@mvista.com>
  5. *
  6. * 2000 (c) MontaVista, Software, Inc. This file is licensed under
  7. * the terms of the GNU General Public License version 2. This program
  8. * is licensed "as is" without any warranty of any kind, whether express
  9. * or implied.
  10. *
  11. * Based on arch/ppc/kernel/indirect.c, Copyright (C) 1998 Gabriel Paubert.
  12. */
  13. #include <linux/pci.h>
  14. #include <asm/io.h>
  15. #include <asm/system.h>
  16. #include <asm/machdep.h>
  17. #include <linux/init.h>
  18. #include <linux/errno.h>
  19. #include <asm/ocp.h>
  20. #include <asm/ibm4xx.h>
  21. #include <asm/pci-bridge.h>
  22. #include <asm/ibm_ocp_pci.h>
  23. extern void bios_fixup(struct pci_controller *, struct pcil0_regs *);
  24. extern int ppc405_map_irq(struct pci_dev *dev, unsigned char idsel,
  25. unsigned char pin);
  26. void
  27. ppc405_pcibios_fixup_resources(struct pci_dev *dev)
  28. {
  29. int i;
  30. unsigned long max_host_addr;
  31. unsigned long min_host_addr;
  32. struct resource *res;
  33. /*
  34. * openbios puts some graphics cards in the same range as the host
  35. * controller uses to map to SDRAM. Fix it.
  36. */
  37. min_host_addr = 0;
  38. max_host_addr = PPC405_PCI_MEM_BASE - 1;
  39. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  40. res = dev->resource + i;
  41. if (!res->start)
  42. continue;
  43. if ((res->flags & IORESOURCE_MEM) &&
  44. (((res->start >= min_host_addr)
  45. && (res->start <= max_host_addr))
  46. || ((res->end >= min_host_addr)
  47. && (res->end <= max_host_addr))
  48. || ((res->start < min_host_addr)
  49. && (res->end > max_host_addr))
  50. )
  51. ) {
  52. /* force pcibios_assign_resources() to assign a new address */
  53. res->end -= res->start;
  54. res->start = 0;
  55. }
  56. }
  57. }
  58. static int
  59. ppc4xx_exclude_device(unsigned char bus, unsigned char devfn)
  60. {
  61. /* We prevent us from seeing ourselves to avoid having
  62. * the kernel try to remap our BAR #1 and fuck up bus
  63. * master from external PCI devices
  64. */
  65. return (bus == 0 && devfn == 0);
  66. }
  67. void
  68. ppc4xx_find_bridges(void)
  69. {
  70. struct pci_controller *hose_a;
  71. struct pcil0_regs *pcip;
  72. unsigned int tmp_addr;
  73. unsigned int tmp_size;
  74. unsigned int reg_index;
  75. unsigned int new_pmm_max = 0;
  76. unsigned int new_pmm_min = 0;
  77. isa_io_base = 0;
  78. isa_mem_base = 0;
  79. pci_dram_offset = 0;
  80. #if (PSR_PCI_ARBIT_EN > 1)
  81. /* Check if running in slave mode */
  82. if ((mfdcr(DCRN_CHPSR) & PSR_PCI_ARBIT_EN) == 0) {
  83. printk("Running as PCI slave, kernel PCI disabled !\n");
  84. return;
  85. }
  86. #endif
  87. /* Setup PCI32 hose */
  88. hose_a = pcibios_alloc_controller();
  89. if (!hose_a)
  90. return;
  91. setup_indirect_pci(hose_a, PPC405_PCI_CONFIG_ADDR,
  92. PPC405_PCI_CONFIG_DATA);
  93. pcip = ioremap(PPC4xx_PCI_LCFG_PADDR, PAGE_SIZE);
  94. if (pcip != NULL) {
  95. #if defined(CONFIG_BIOS_FIXUP)
  96. bios_fixup(hose_a, pcip);
  97. #endif
  98. new_pmm_min = 0xffffffff;
  99. for (reg_index = 0; reg_index < 3; reg_index++) {
  100. tmp_size = in_le32(&pcip->pmm[reg_index].ma); // mask & attrs
  101. /* test the enable bit */
  102. if ((tmp_size & 0x1) == 0)
  103. continue;
  104. tmp_addr = in_le32(&pcip->pmm[reg_index].pcila); // PCI addr
  105. if (tmp_addr < PPC405_PCI_PHY_MEM_BASE) {
  106. printk(KERN_DEBUG
  107. "Disabling mapping to PCI mem addr 0x%8.8x\n",
  108. tmp_addr);
  109. out_le32(&pcip->pmm[reg_index].ma, tmp_size & ~1); // *_PMMOMA
  110. continue;
  111. }
  112. tmp_addr = in_le32(&pcip->pmm[reg_index].la); // *_PMMOLA
  113. if (tmp_addr < new_pmm_min)
  114. new_pmm_min = tmp_addr;
  115. tmp_addr = tmp_addr +
  116. (0xffffffff - (tmp_size & 0xffffc000));
  117. if (tmp_addr > PPC405_PCI_UPPER_MEM) {
  118. new_pmm_max = tmp_addr; // PPC405_PCI_UPPER_MEM
  119. } else {
  120. new_pmm_max = PPC405_PCI_UPPER_MEM;
  121. }
  122. } // for
  123. iounmap(pcip);
  124. }
  125. hose_a->first_busno = 0;
  126. hose_a->last_busno = 0xff;
  127. hose_a->pci_mem_offset = 0;
  128. /* Setup bridge memory/IO ranges & resources
  129. * TODO: Handle firmwares setting up a legacy ISA mem base
  130. */
  131. hose_a->io_space.start = PPC405_PCI_LOWER_IO;
  132. hose_a->io_space.end = PPC405_PCI_UPPER_IO;
  133. hose_a->mem_space.start = new_pmm_min;
  134. hose_a->mem_space.end = new_pmm_max;
  135. hose_a->io_base_phys = PPC405_PCI_PHY_IO_BASE;
  136. hose_a->io_base_virt = ioremap(hose_a->io_base_phys, 0x10000);
  137. hose_a->io_resource.start = 0;
  138. hose_a->io_resource.end = PPC405_PCI_UPPER_IO - PPC405_PCI_LOWER_IO;
  139. hose_a->io_resource.flags = IORESOURCE_IO;
  140. hose_a->io_resource.name = "PCI I/O";
  141. hose_a->mem_resources[0].start = new_pmm_min;
  142. hose_a->mem_resources[0].end = new_pmm_max;
  143. hose_a->mem_resources[0].flags = IORESOURCE_MEM;
  144. hose_a->mem_resources[0].name = "PCI Memory";
  145. isa_io_base = (int) hose_a->io_base_virt;
  146. isa_mem_base = 0; /* ISA not implemented */
  147. ISA_DMA_THRESHOLD = 0x00ffffff; /* ??? ISA not implemented */
  148. /* Scan busses & initial setup by pci_auto */
  149. hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
  150. hose_a->last_busno = 0;
  151. /* Setup ppc_md */
  152. ppc_md.pcibios_fixup = NULL;
  153. ppc_md.pci_exclude_device = ppc4xx_exclude_device;
  154. ppc_md.pcibios_fixup_resources = ppc405_pcibios_fixup_resources;
  155. ppc_md.pci_swizzle = common_swizzle;
  156. ppc_md.pci_map_irq = ppc405_map_irq;
  157. }