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ppc
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syslib
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cpc710.h

cpc710.h 2.2 KB
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  1. /*
    2. 

  2.  * arch/ppc/syslib/cpc710.h
    3. 

  3.  *
    4. 

  4.  * Definitions for the IBM CPC710 PCI Host Bridge
    5. 

  5.  *
    6. 

  6.  * Author: Matt Porter <mporter@mvista.com>
    7. 

  7.  *
    8. 

  8.  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
    9. 

  9.  * the terms of the GNU General Public License version 2.  This program
    10. 

  10.  * is licensed "as is" without any warranty of any kind, whether express
    11. 

  11.  * or implied.
    12. 

  12.  */
    13. 

  13. 

  14. #ifndef __PPC_PLATFORMS_CPC710_H
    15. 

  15. #define __PPC_PLATFORMS_CPC710_H
    16. 

  16. 

  17. /* General bridge and memory controller registers */
    18. 

  18. #define PIDR	0xff000008
    19. 

  19. #define	CNFR	0xff00000c
    20. 

  20. #define	RSTR	0xff000010
    21. 

  21. #define UCTL	0xff001000
    22. 

  22. #define	MPSR	0xff001010
    23. 

  23. #define	SIOC	0xff001020
    24. 

  24. #define	ABCNTL	0xff001030
    25. 

  25. #define SRST	0xff001040
    26. 

  26. #define	ERRC	0xff001050
    27. 

  27. #define	SESR	0xff001060
    28. 

  28. #define	SEAR	0xff001070
    29. 

  29. #define	SIOC1	0xff001090
    30. 

  30. #define	PGCHP	0xff001100
    31. 

  31. #define	GPDIR	0xff001130
    32. 

  32. #define	GPOUT	0xff001150
    33. 

  33. #define	ATAS	0xff001160
    34. 

  34. #define	AVDG	0xff001170
    35. 

  35. #define	MCCR	0xff001200
    36. 

  36. #define	MESR	0xff001220
    37. 

  37. #define	MEAR	0xff001230
    38. 

  38. #define	MCER0	0xff001300
    39. 

  39. #define	MCER1	0xff001310
    40. 

  40. #define	MCER2	0xff001320
    41. 

  41. #define	MCER3	0xff001330
    42. 

  42. #define	MCER4	0xff001340
    43. 

  43. #define	MCER5	0xff001350
    44. 

  44. #define	MCER6	0xff001360
    45. 

  45. #define	MCER7	0xff001370
    46. 

  46. 

  47. /*
    48. 

  48.  * PCI32/64 configuration registers
    49. 

  49.  * Given as offsets from their
    50. 

  50.  * respective physical segment BAR
    51. 

  51.  */
    52. 

  52. #define PIBAR	0x000f7800
    53. 

  53. #define PMBAR	0x000f7810
    54. 

  54. #define MSIZE	0x000f7f40
    55. 

  55. #define IOSIZE	0x000f7f60
    56. 

  56. #define SMBAR	0x000f7f80
    57. 

  57. #define SIBAR	0x000f7fc0
    58. 

  58. #define PSSIZE	0x000f8100
    59. 

  59. #define PPSIZE	0x000f8110
    60. 

  60. #define BARPS	0x000f8120
    61. 

  61. #define BARPP	0x000f8130
    62. 

  62. #define PSBAR	0x000f8140
    63. 

  63. #define PPBAR	0x000f8150
    64. 

  64. #define BPMDLK	0x000f8200      /* Bottom of Peripheral Memory Space */
    65. 

  65. #define TPMDLK	0x000f8210      /* Top of Peripheral Memory Space */
    66. 

  66. #define BIODLK	0x000f8220      /* Bottom of Peripheral I/O Space */
    67. 

  67. #define TIODLK	0x000f8230      /* Top of Perioheral I/O Space */
    68. 

  68. #define DLKCTRL	0x000f8240      /* Deadlock control */
    69. 

  69. #define DLKDEV	0x000f8250      /* Deadlock device */
    70. 

  70. 

  71. /* System standard configuration registers space */
    72. 

  72. #define	DCR	0xff200000
    73. 

  73. #define	DID	0xff200004
    74. 

  74. #define	BAR	0xff200018
    75. 

  75. 

  76. /* Device specific configuration space */
    77. 

  77. #define	PCIENB	0xff201000
    78. 

  78. 

  79. /* Configuration space registers */
    80. 

  80. #define CPC710_BUS_NUMBER	0x40
    81. 

  81. #define CPC710_SUB_BUS_NUMBER	0x41
    82. 

  82. 

  83. #endif /* __PPC_PLATFORMS_CPC710_H */
    84.