cpci690.h 2.4 KB

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  1. /*
  2. * arch/ppc/platforms/cpci690.h
  3. *
  4. * Definitions for Force CPCI690
  5. *
  6. * Author: Mark A. Greer <mgreer@mvista.com>
  7. *
  8. * 2003 (c) MontaVista, Software, Inc. This file is licensed under
  9. * the terms of the GNU General Public License version 2. This program
  10. * is licensed "as is" without any warranty of any kind, whether express
  11. * or implied.
  12. */
  13. /*
  14. * The GT64260 has 2 PCI buses each with 1 window from the CPU bus to
  15. * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
  16. */
  17. #ifndef __PPC_PLATFORMS_CPCI690_H
  18. #define __PPC_PLATFORMS_CPCI690_H
  19. /*
  20. * Define bd_t to pass in the MAC addresses used by the GT64260's enet ctlrs.
  21. */
  22. #define CPCI690_BI_MAGIC 0xFE8765DC
  23. typedef struct board_info {
  24. u32 bi_magic;
  25. u8 bi_enetaddr[3][6];
  26. } bd_t;
  27. /* PCI bus Resource setup */
  28. #define CPCI690_PCI0_MEM_START_PROC_ADDR 0x80000000
  29. #define CPCI690_PCI0_MEM_START_PCI_HI_ADDR 0x00000000
  30. #define CPCI690_PCI0_MEM_START_PCI_LO_ADDR 0x80000000
  31. #define CPCI690_PCI0_MEM_SIZE 0x10000000
  32. #define CPCI690_PCI0_IO_START_PROC_ADDR 0xa0000000
  33. #define CPCI690_PCI0_IO_START_PCI_ADDR 0x00000000
  34. #define CPCI690_PCI0_IO_SIZE 0x01000000
  35. #define CPCI690_PCI1_MEM_START_PROC_ADDR 0x90000000
  36. #define CPCI690_PCI1_MEM_START_PCI_HI_ADDR 0x00000000
  37. #define CPCI690_PCI1_MEM_START_PCI_LO_ADDR 0x90000000
  38. #define CPCI690_PCI1_MEM_SIZE 0x10000000
  39. #define CPCI690_PCI1_IO_START_PROC_ADDR 0xa1000000
  40. #define CPCI690_PCI1_IO_START_PCI_ADDR 0x01000000
  41. #define CPCI690_PCI1_IO_SIZE 0x01000000
  42. /* Board Registers */
  43. #define CPCI690_BR_BASE 0xf0000000
  44. #define CPCI690_BR_SIZE_ACTUAL 0x8
  45. #define CPCI690_BR_SIZE max(GT64260_WINDOW_SIZE_MIN, \
  46. CPCI690_BR_SIZE_ACTUAL)
  47. #define CPCI690_BR_LED_CNTL 0x00
  48. #define CPCI690_BR_SW_RESET 0x01
  49. #define CPCI690_BR_MISC_STATUS 0x02
  50. #define CPCI690_BR_SWITCH_STATUS 0x03
  51. #define CPCI690_BR_MEM_CTLR 0x04
  52. #define CPCI690_BR_LAST_RESET_1 0x05
  53. #define CPCI690_BR_LAST_RESET_2 0x06
  54. #define CPCI690_TODC_BASE 0xf0100000
  55. #define CPCI690_TODC_SIZE_ACTUAL 0x8000 /* Size or NVRAM + RTC */
  56. #define CPCI690_TODC_SIZE max(GT64260_WINDOW_SIZE_MIN, \
  57. CPCI690_TODC_SIZE_ACTUAL)
  58. #define CPCI690_MAC_OFFSET 0x7c10 /* MAC in RTC NVRAM */
  59. #define CPCI690_IPMI_BASE 0xf0200000
  60. #define CPCI690_IPMI_SIZE_ACTUAL 0x10 /* 16 bytes of IPMI */
  61. #define CPCI690_IPMI_SIZE max(GT64260_WINDOW_SIZE_MIN, \
  62. CPCI690_IPMI_SIZE_ACTUAL)
  63. #define CPCI690_MPSC_BAUD 9600
  64. #define CPCI690_MPSC_CLK_SRC 8 /* TCLK */
  65. #endif /* __PPC_PLATFORMS_CPCI690_H */