mpc834x_sys.c 8.0 KB

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  1. /*
  2. * arch/ppc/platforms/83xx/mpc834x_sys.c
  3. *
  4. * MPC834x SYS board specific routines
  5. *
  6. * Maintainer: Kumar Gala <kumar.gala@freescale.com>
  7. *
  8. * Copyright 2005 Freescale Semiconductor Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. #include <linux/config.h>
  16. #include <linux/stddef.h>
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/errno.h>
  20. #include <linux/reboot.h>
  21. #include <linux/pci.h>
  22. #include <linux/kdev_t.h>
  23. #include <linux/major.h>
  24. #include <linux/console.h>
  25. #include <linux/delay.h>
  26. #include <linux/irq.h>
  27. #include <linux/seq_file.h>
  28. #include <linux/root_dev.h>
  29. #include <linux/serial.h>
  30. #include <linux/tty.h> /* for linux/serial_core.h */
  31. #include <linux/serial_core.h>
  32. #include <linux/initrd.h>
  33. #include <linux/module.h>
  34. #include <linux/fsl_devices.h>
  35. #include <asm/system.h>
  36. #include <asm/pgtable.h>
  37. #include <asm/page.h>
  38. #include <asm/atomic.h>
  39. #include <asm/time.h>
  40. #include <asm/io.h>
  41. #include <asm/machdep.h>
  42. #include <asm/ipic.h>
  43. #include <asm/bootinfo.h>
  44. #include <asm/pci-bridge.h>
  45. #include <asm/mpc83xx.h>
  46. #include <asm/irq.h>
  47. #include <asm/kgdb.h>
  48. #include <asm/ppc_sys.h>
  49. #include <mm/mmu_decl.h>
  50. #include <syslib/ppc83xx_setup.h>
  51. #ifndef CONFIG_PCI
  52. unsigned long isa_io_base = 0;
  53. unsigned long isa_mem_base = 0;
  54. #endif
  55. extern unsigned long total_memory; /* in mm/init */
  56. unsigned char __res[sizeof (bd_t)];
  57. #ifdef CONFIG_PCI
  58. int
  59. mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  60. {
  61. static char pci_irq_table[][4] =
  62. /*
  63. * PCI IDSEL/INTPIN->INTLINE
  64. * A B C D
  65. */
  66. {
  67. {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */
  68. {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */
  69. {PIRQD, PIRQA, PIRQB, PIRQC} /* idsel 0x13 */
  70. };
  71. const long min_idsel = 0x11, max_idsel = 0x13, irqs_per_slot = 4;
  72. return PCI_IRQ_TABLE_LOOKUP;
  73. }
  74. int
  75. mpc83xx_exclude_device(u_char bus, u_char devfn)
  76. {
  77. return PCIBIOS_SUCCESSFUL;
  78. }
  79. #endif /* CONFIG_PCI */
  80. /* ************************************************************************
  81. *
  82. * Setup the architecture
  83. *
  84. */
  85. static void __init
  86. mpc834x_sys_setup_arch(void)
  87. {
  88. bd_t *binfo = (bd_t *) __res;
  89. unsigned int freq;
  90. struct gianfar_platform_data *pdata;
  91. /* get the core frequency */
  92. freq = binfo->bi_intfreq;
  93. /* Set loops_per_jiffy to a half-way reasonable value,
  94. for use until calibrate_delay gets called. */
  95. loops_per_jiffy = freq / HZ;
  96. #ifdef CONFIG_PCI
  97. /* setup PCI host bridges */
  98. mpc83xx_setup_hose();
  99. #endif
  100. mpc83xx_early_serial_map();
  101. /* setup the board related information for the enet controllers */
  102. pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1);
  103. if (pdata) {
  104. pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
  105. pdata->interruptPHY = MPC83xx_IRQ_EXT1;
  106. pdata->phyid = 0;
  107. /* fixup phy address */
  108. pdata->phy_reg_addr += binfo->bi_immr_base;
  109. memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
  110. }
  111. pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2);
  112. if (pdata) {
  113. pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
  114. pdata->interruptPHY = MPC83xx_IRQ_EXT2;
  115. pdata->phyid = 1;
  116. /* fixup phy address */
  117. pdata->phy_reg_addr += binfo->bi_immr_base;
  118. memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
  119. }
  120. #ifdef CONFIG_BLK_DEV_INITRD
  121. if (initrd_start)
  122. ROOT_DEV = Root_RAM0;
  123. else
  124. #endif
  125. #ifdef CONFIG_ROOT_NFS
  126. ROOT_DEV = Root_NFS;
  127. #else
  128. ROOT_DEV = Root_HDA1;
  129. #endif
  130. }
  131. static void __init
  132. mpc834x_sys_map_io(void)
  133. {
  134. /* we steal the lowest ioremap addr for virt space */
  135. io_block_mapping(VIRT_IMMRBAR, immrbar, 1024*1024, _PAGE_IO);
  136. }
  137. int
  138. mpc834x_sys_show_cpuinfo(struct seq_file *m)
  139. {
  140. uint pvid, svid, phid1;
  141. bd_t *binfo = (bd_t *) __res;
  142. unsigned int freq;
  143. /* get the core frequency */
  144. freq = binfo->bi_intfreq;
  145. pvid = mfspr(SPRN_PVR);
  146. svid = mfspr(SPRN_SVR);
  147. seq_printf(m, "Vendor\t\t: Freescale Inc.\n");
  148. seq_printf(m, "Machine\t\t: mpc%s sys\n", cur_ppc_sys_spec->ppc_sys_name);
  149. seq_printf(m, "core clock\t: %d MHz\n"
  150. "bus clock\t: %d MHz\n",
  151. (int)(binfo->bi_intfreq / 1000000),
  152. (int)(binfo->bi_busfreq / 1000000));
  153. seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
  154. seq_printf(m, "SVR\t\t: 0x%x\n", svid);
  155. /* Display cpu Pll setting */
  156. phid1 = mfspr(SPRN_HID1);
  157. seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
  158. /* Display the amount of memory */
  159. seq_printf(m, "Memory\t\t: %d MB\n", (int)(binfo->bi_memsize / (1024 * 1024)));
  160. return 0;
  161. }
  162. void __init
  163. mpc834x_sys_init_IRQ(void)
  164. {
  165. bd_t *binfo = (bd_t *) __res;
  166. u8 senses[8] = {
  167. 0, /* EXT 0 */
  168. IRQ_SENSE_LEVEL, /* EXT 1 */
  169. IRQ_SENSE_LEVEL, /* EXT 2 */
  170. 0, /* EXT 3 */
  171. #ifdef CONFIG_PCI
  172. IRQ_SENSE_LEVEL, /* EXT 4 */
  173. IRQ_SENSE_LEVEL, /* EXT 5 */
  174. IRQ_SENSE_LEVEL, /* EXT 6 */
  175. IRQ_SENSE_LEVEL, /* EXT 7 */
  176. #else
  177. 0, /* EXT 4 */
  178. 0, /* EXT 5 */
  179. 0, /* EXT 6 */
  180. 0, /* EXT 7 */
  181. #endif
  182. };
  183. ipic_init(binfo->bi_immr_base + 0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8);
  184. /* Initialize the default interrupt mapping priorities,
  185. * in case the boot rom changed something on us.
  186. */
  187. ipic_set_default_priority();
  188. }
  189. #if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
  190. extern ulong ds1374_get_rtc_time(void);
  191. extern int ds1374_set_rtc_time(ulong);
  192. static int __init
  193. mpc834x_rtc_hookup(void)
  194. {
  195. struct timespec tv;
  196. ppc_md.get_rtc_time = ds1374_get_rtc_time;
  197. ppc_md.set_rtc_time = ds1374_set_rtc_time;
  198. tv.tv_nsec = 0;
  199. tv.tv_sec = (ppc_md.get_rtc_time)();
  200. do_settimeofday(&tv);
  201. return 0;
  202. }
  203. late_initcall(mpc834x_rtc_hookup);
  204. #endif
  205. static __inline__ void
  206. mpc834x_sys_set_bat(void)
  207. {
  208. /* we steal the lowest ioremap addr for virt space */
  209. mb();
  210. mtspr(SPRN_DBAT1U, VIRT_IMMRBAR | 0x1e);
  211. mtspr(SPRN_DBAT1L, immrbar | 0x2a);
  212. mb();
  213. }
  214. void __init
  215. platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
  216. unsigned long r6, unsigned long r7)
  217. {
  218. bd_t *binfo = (bd_t *) __res;
  219. /* parse_bootinfo must always be called first */
  220. parse_bootinfo(find_bootinfo());
  221. /*
  222. * If we were passed in a board information, copy it into the
  223. * residual data area.
  224. */
  225. if (r3) {
  226. memcpy((void *) __res, (void *) (r3 + KERNELBASE),
  227. sizeof (bd_t));
  228. }
  229. #if defined(CONFIG_BLK_DEV_INITRD)
  230. /*
  231. * If the init RAM disk has been configured in, and there's a valid
  232. * starting address for it, set it up.
  233. */
  234. if (r4) {
  235. initrd_start = r4 + KERNELBASE;
  236. initrd_end = r5 + KERNELBASE;
  237. }
  238. #endif /* CONFIG_BLK_DEV_INITRD */
  239. /* Copy the kernel command line arguments to a safe place. */
  240. if (r6) {
  241. *(char *) (r7 + KERNELBASE) = 0;
  242. strcpy(cmd_line, (char *) (r6 + KERNELBASE));
  243. }
  244. immrbar = binfo->bi_immr_base;
  245. mpc834x_sys_set_bat();
  246. #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
  247. {
  248. struct uart_port p;
  249. memset(&p, 0, sizeof (p));
  250. p.iotype = SERIAL_IO_MEM;
  251. p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4500);
  252. p.uartclk = binfo->bi_busfreq;
  253. gen550_init(0, &p);
  254. memset(&p, 0, sizeof (p));
  255. p.iotype = SERIAL_IO_MEM;
  256. p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4600);
  257. p.uartclk = binfo->bi_busfreq;
  258. gen550_init(1, &p);
  259. }
  260. #endif
  261. identify_ppc_sys_by_id(mfspr(SPRN_SVR));
  262. /* setup the PowerPC module struct */
  263. ppc_md.setup_arch = mpc834x_sys_setup_arch;
  264. ppc_md.show_cpuinfo = mpc834x_sys_show_cpuinfo;
  265. ppc_md.init_IRQ = mpc834x_sys_init_IRQ;
  266. ppc_md.get_irq = ipic_get_irq;
  267. ppc_md.restart = mpc83xx_restart;
  268. ppc_md.power_off = mpc83xx_power_off;
  269. ppc_md.halt = mpc83xx_halt;
  270. ppc_md.find_end_of_memory = mpc83xx_find_end_of_memory;
  271. ppc_md.setup_io_mappings = mpc834x_sys_map_io;
  272. ppc_md.time_init = mpc83xx_time_init;
  273. ppc_md.set_rtc_time = NULL;
  274. ppc_md.get_rtc_time = NULL;
  275. ppc_md.calibrate_decr = mpc83xx_calibrate_decr;
  276. ppc_md.early_serial_map = mpc83xx_early_serial_map;
  277. #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
  278. ppc_md.progress = gen550_progress;
  279. #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
  280. if (ppc_md.progress)
  281. ppc_md.progress("mpc834x_sys_init(): exit", 0);
  282. return;
  283. }