ibm440sp.h 2.5 KB

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  1. /*
  2. * arch/ppc/platforms/4xx/ibm440sp.h
  3. *
  4. * PPC440SP definitions
  5. *
  6. * Matt Porter <mporter@kernel.crashing.org>
  7. *
  8. * Copyright 2004-2005 MontaVista Software, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. */
  15. #ifdef __KERNEL__
  16. #ifndef __PPC_PLATFORMS_IBM440SP_H
  17. #define __PPC_PLATFORMS_IBM440SP_H
  18. #include <linux/config.h>
  19. #include <asm/ibm44x.h>
  20. /* UART */
  21. #define PPC440SP_UART0_ADDR 0x00000001f0000200ULL
  22. #define PPC440SP_UART1_ADDR 0x00000001f0000300ULL
  23. #define PPC440SP_UART2_ADDR 0x00000001f0000600ULL
  24. #define UART0_INT 0
  25. #define UART1_INT 1
  26. #define UART2_INT 2
  27. /* Clock and Power Management */
  28. #define IBM_CPM_IIC0 0x80000000 /* IIC interface */
  29. #define IBM_CPM_IIC1 0x40000000 /* IIC interface */
  30. #define IBM_CPM_PCI 0x20000000 /* PCI bridge */
  31. #define IBM_CPM_CPU 0x02000000 /* processor core */
  32. #define IBM_CPM_DMA 0x01000000 /* DMA controller */
  33. #define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
  34. #define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
  35. #define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
  36. #define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
  37. #define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
  38. #define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
  39. #define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
  40. #define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
  41. #define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
  42. #define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
  43. #define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
  44. #define IBM_CPM_UART0 0x00000200 /* serial port 0 */
  45. #define IBM_CPM_UART1 0x00000100 /* serial port 1 */
  46. #define IBM_CPM_UART2 0x00000100 /* serial port 1 */
  47. #define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
  48. #define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
  49. #define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
  50. #define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
  51. | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
  52. | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
  53. | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
  54. | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
  55. | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
  56. | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
  57. #endif /* __PPC_PLATFORMS_IBM440SP_H */
  58. #endif /* __KERNEL__ */