ibm440sp.c 3.6 KB

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  1. /*
  2. * arch/ppc/platforms/4xx/ibm440sp.c
  3. *
  4. * PPC440SP I/O descriptions
  5. *
  6. * Matt Porter <mporter@kernel.crashing.org>
  7. * Copyright 2002-2005 MontaVista Software Inc.
  8. *
  9. * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
  10. * Copyright (c) 2003, 2004 Zultys Technologies
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. *
  17. */
  18. #include <linux/init.h>
  19. #include <linux/module.h>
  20. #include <platforms/4xx/ibm440sp.h>
  21. #include <asm/ocp.h>
  22. static struct ocp_func_emac_data ibm440sp_emac0_def = {
  23. .rgmii_idx = -1, /* No RGMII */
  24. .rgmii_mux = -1, /* No RGMII */
  25. .zmii_idx = -1, /* No ZMII */
  26. .zmii_mux = -1, /* No ZMII */
  27. .mal_idx = 0, /* MAL device index */
  28. .mal_rx_chan = 0, /* MAL rx channel number */
  29. .mal_tx_chan = 0, /* MAL tx channel number */
  30. .wol_irq = 61, /* WOL interrupt number */
  31. .mdio_idx = -1, /* No shared MDIO */
  32. .tah_idx = -1, /* No TAH */
  33. .jumbo = 1, /* Jumbo frames supported */
  34. };
  35. OCP_SYSFS_EMAC_DATA()
  36. static struct ocp_func_mal_data ibm440sp_mal0_def = {
  37. .num_tx_chans = 1, /* Number of TX channels */
  38. .num_rx_chans = 1, /* Number of RX channels */
  39. .txeob_irq = 38, /* TX End Of Buffer IRQ */
  40. .rxeob_irq = 39, /* RX End Of Buffer IRQ */
  41. .txde_irq = 34, /* TX Descriptor Error IRQ */
  42. .rxde_irq = 35, /* RX Descriptor Error IRQ */
  43. .serr_irq = 33, /* MAL System Error IRQ */
  44. .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
  45. };
  46. OCP_SYSFS_MAL_DATA()
  47. static struct ocp_func_iic_data ibm440sp_iic0_def = {
  48. .fast_mode = 0, /* Use standad mode (100Khz) */
  49. };
  50. static struct ocp_func_iic_data ibm440sp_iic1_def = {
  51. .fast_mode = 0, /* Use standad mode (100Khz) */
  52. };
  53. OCP_SYSFS_IIC_DATA()
  54. struct ocp_def core_ocp[] = {
  55. { .vendor = OCP_VENDOR_IBM,
  56. .function = OCP_FUNC_OPB,
  57. .index = 0,
  58. .paddr = 0x0000000140000000ULL,
  59. .irq = OCP_IRQ_NA,
  60. .pm = OCP_CPM_NA,
  61. },
  62. { .vendor = OCP_VENDOR_IBM,
  63. .function = OCP_FUNC_16550,
  64. .index = 0,
  65. .paddr = PPC440SP_UART0_ADDR,
  66. .irq = UART0_INT,
  67. .pm = IBM_CPM_UART0,
  68. },
  69. { .vendor = OCP_VENDOR_IBM,
  70. .function = OCP_FUNC_16550,
  71. .index = 1,
  72. .paddr = PPC440SP_UART1_ADDR,
  73. .irq = UART1_INT,
  74. .pm = IBM_CPM_UART1,
  75. },
  76. { .vendor = OCP_VENDOR_IBM,
  77. .function = OCP_FUNC_16550,
  78. .index = 2,
  79. .paddr = PPC440SP_UART2_ADDR,
  80. .irq = UART2_INT,
  81. .pm = IBM_CPM_UART2,
  82. },
  83. { .vendor = OCP_VENDOR_IBM,
  84. .function = OCP_FUNC_IIC,
  85. .index = 0,
  86. .paddr = 0x00000001f0000400ULL,
  87. .irq = 2,
  88. .pm = IBM_CPM_IIC0,
  89. .additions = &ibm440sp_iic0_def,
  90. .show = &ocp_show_iic_data
  91. },
  92. { .vendor = OCP_VENDOR_IBM,
  93. .function = OCP_FUNC_IIC,
  94. .index = 1,
  95. .paddr = 0x00000001f0000500ULL,
  96. .irq = 3,
  97. .pm = IBM_CPM_IIC1,
  98. .additions = &ibm440sp_iic1_def,
  99. .show = &ocp_show_iic_data
  100. },
  101. { .vendor = OCP_VENDOR_IBM,
  102. .function = OCP_FUNC_GPIO,
  103. .index = 0,
  104. .paddr = 0x00000001f0000700ULL,
  105. .irq = OCP_IRQ_NA,
  106. .pm = IBM_CPM_GPIO0,
  107. },
  108. { .vendor = OCP_VENDOR_IBM,
  109. .function = OCP_FUNC_MAL,
  110. .paddr = OCP_PADDR_NA,
  111. .irq = OCP_IRQ_NA,
  112. .pm = OCP_CPM_NA,
  113. .additions = &ibm440sp_mal0_def,
  114. .show = &ocp_show_mal_data,
  115. },
  116. { .vendor = OCP_VENDOR_IBM,
  117. .function = OCP_FUNC_EMAC,
  118. .index = 0,
  119. .paddr = 0x00000001f0000800ULL,
  120. .irq = 60,
  121. .pm = OCP_CPM_NA,
  122. .additions = &ibm440sp_emac0_def,
  123. .show = &ocp_show_emac_data,
  124. },
  125. { .vendor = OCP_VENDOR_INVALID
  126. }
  127. };