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phyus
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linux-vybrid_public
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linux-vybrid_pu...
/
arch
/
ppc
/
kernel
/
idle_power4.S

idle_power4.S 2.1 KB
تاريخچه خام

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  1. /*
    2. 

  2.  *  This file contains the power_save function for 6xx & 7xxx CPUs
    3. 

  3.  *  rewritten in assembler
    4. 

  4.  *
    5. 

  5.  *  Warning ! This code assumes that if your machine has a 750fx
    6. 

  6.  *  it will have PLL 1 set to low speed mode (used during NAP/DOZE).
    7. 

  7.  *  if this is not the case some additional changes will have to
    8. 

  8.  *  be done to check a runtime var (a bit like powersave-nap)
    9. 

  9.  *
    10. 

  10.  *  This program is free software; you can redistribute it and/or
    11. 

  11.  *  modify it under the terms of the GNU General Public License
    12. 

  12.  *  as published by the Free Software Foundation; either version
    13. 

  13.  *  2 of the License, or (at your option) any later version.
    14. 

  14.  */
    15. 

  15. 

  16. #include <linux/config.h>
    17. 

  17. #include <linux/threads.h>
    18. 

  18. #include <asm/processor.h>
    19. 

  19. #include <asm/page.h>
    20. 

  20. #include <asm/cputable.h>
    21. 

  21. #include <asm/thread_info.h>
    22. 

  22. #include <asm/ppc_asm.h>
    23. 

  23. #include <asm/offsets.h>
    24. 

  24. 

  25. #undef DEBUG
    26. 

  26. 

  27. 	.text
    28. 

  28. 

  29. /*
    30. 

  30.  * Init idle, called at early CPU setup time from head.S for each CPU
    31. 

  31.  * So nothing for now. Called with r24 containing CPU number and r3
    32. 

  32.  * reloc offset
    33. 

  33.  */
    34. 

  34.  	.globl	init_idle_power4
    35. 

  35. init_idle_power4:
    36. 

  36. 	blr
    37. 

  37. 

  38. /*
    39. 

  39.  * Here is the power_save_6xx function. This could eventually be
    40. 

  40.  * split into several functions & changing the function pointer
    41. 

  41.  * depending on the various features.
    42. 

  42.  */
    43. 

  43. 	.globl	power4_idle
    44. 

  44. power4_idle:
    45. 

  45. BEGIN_FTR_SECTION
    46. 

  46. 	blr
    47. 

  47. END_FTR_SECTION_IFCLR(CPU_FTR_CAN_NAP)
    48. 

  48. 	/* We must dynamically check for the NAP feature as it
    49. 

  49. 	 * can be cleared by CPU init after the fixups are done
    50. 

  50. 	 */
    51. 

  51. 	lis	r4,cur_cpu_spec@ha
    52. 

  52. 	lwz	r4,cur_cpu_spec@l(r4)
    53. 

  53. 	lwz	r4,CPU_SPEC_FEATURES(r4)
    54. 

  54. 	andi.	r0,r4,CPU_FTR_CAN_NAP
    55. 

  55. 	beqlr
    56. 

  56. 	/* Now check if user or arch enabled NAP mode */
    57. 

  57. 	lis	r4,powersave_nap@ha
    58. 

  58. 	lwz	r4,powersave_nap@l(r4)
    59. 

  59. 	cmpwi	0,r4,0
    60. 

  60. 	beqlr
    61. 

  61. 

  62. 	/* Clear MSR:EE */
    63. 

  63. 	mfmsr	r7
    64. 

  64. 	rlwinm	r0,r7,0,17,15
    65. 

  65. 	mtmsr	r0
    66. 

  66. 

  67. 	/* Check current_thread_info()->flags */
    68. 

  68. 	rlwinm	r4,r1,0,0,18
    69. 

  69. 	lwz	r4,TI_FLAGS(r4)
    70. 

  70. 	andi.	r0,r4,_TIF_NEED_RESCHED
    71. 

  71. 	beq	1f
    72. 

  72. 	mtmsr	r7	/* out of line this ? */
    73. 

  73. 	blr
    74. 

  74. 1:	
    75. 

  75. 	/* Go to NAP now */	
    76. 

  76. BEGIN_FTR_SECTION
    77. 

  77. 	DSSALL
    78. 

  78. 	sync
    79. 

  79. END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
    80. 

  80. 	ori	r7,r7,MSR_EE /* Could be ommited (already set) */
    81. 

  81. 	oris	r7,r7,MSR_POW@h
    82. 

  82. 	sync
    83. 

  83. 	isync
    84. 

  84. 	mtmsr	r7
    85. 

  85. 	isync
    86. 

  86. 	sync
    87. 

  87. 	blr
    88. 

  88. 	
    89. 

  89. 	.globl powersave_nap
    90. 

  90. powersave_nap:
    91. 

  91. 	.long	0
    92.