head_fsl_booke.S 26 KB

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  1. /*
  2. * arch/ppc/kernel/head_fsl_booke.S
  3. *
  4. * Kernel execution entry point code.
  5. *
  6. * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
  7. * Initial PowerPC version.
  8. * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
  9. * Rewritten for PReP
  10. * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
  11. * Low-level exception handers, MMU support, and rewrite.
  12. * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
  13. * PowerPC 8xx modifications.
  14. * Copyright (c) 1998-1999 TiVo, Inc.
  15. * PowerPC 403GCX modifications.
  16. * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  17. * PowerPC 403GCX/405GP modifications.
  18. * Copyright 2000 MontaVista Software Inc.
  19. * PPC405 modifications
  20. * PowerPC 403GCX/405GP modifications.
  21. * Author: MontaVista Software, Inc.
  22. * frank_rowand@mvista.com or source@mvista.com
  23. * debbie_chu@mvista.com
  24. * Copyright 2002-2004 MontaVista Software, Inc.
  25. * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
  26. * Copyright 2004 Freescale Semiconductor, Inc
  27. * PowerPC e500 modifications, Kumar Gala <kumar.gala@freescale.com>
  28. *
  29. * This program is free software; you can redistribute it and/or modify it
  30. * under the terms of the GNU General Public License as published by the
  31. * Free Software Foundation; either version 2 of the License, or (at your
  32. * option) any later version.
  33. */
  34. #include <linux/config.h>
  35. #include <linux/threads.h>
  36. #include <asm/processor.h>
  37. #include <asm/page.h>
  38. #include <asm/mmu.h>
  39. #include <asm/pgtable.h>
  40. #include <asm/cputable.h>
  41. #include <asm/thread_info.h>
  42. #include <asm/ppc_asm.h>
  43. #include <asm/offsets.h>
  44. #include "head_booke.h"
  45. /* As with the other PowerPC ports, it is expected that when code
  46. * execution begins here, the following registers contain valid, yet
  47. * optional, information:
  48. *
  49. * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  50. * r4 - Starting address of the init RAM disk
  51. * r5 - Ending address of the init RAM disk
  52. * r6 - Start of kernel command line string (e.g. "mem=128")
  53. * r7 - End of kernel command line string
  54. *
  55. */
  56. .text
  57. _GLOBAL(_stext)
  58. _GLOBAL(_start)
  59. /*
  60. * Reserve a word at a fixed location to store the address
  61. * of abatron_pteptrs
  62. */
  63. nop
  64. /*
  65. * Save parameters we are passed
  66. */
  67. mr r31,r3
  68. mr r30,r4
  69. mr r29,r5
  70. mr r28,r6
  71. mr r27,r7
  72. li r24,0 /* CPU number */
  73. /* We try to not make any assumptions about how the boot loader
  74. * setup or used the TLBs. We invalidate all mappings from the
  75. * boot loader and load a single entry in TLB1[0] to map the
  76. * first 16M of kernel memory. Any boot info passed from the
  77. * bootloader needs to live in this first 16M.
  78. *
  79. * Requirement on bootloader:
  80. * - The page we're executing in needs to reside in TLB1 and
  81. * have IPROT=1. If not an invalidate broadcast could
  82. * evict the entry we're currently executing in.
  83. *
  84. * r3 = Index of TLB1 were executing in
  85. * r4 = Current MSR[IS]
  86. * r5 = Index of TLB1 temp mapping
  87. *
  88. * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
  89. * if needed
  90. */
  91. /* 1. Find the index of the entry we're executing in */
  92. bl invstr /* Find our address */
  93. invstr: mflr r6 /* Make it accessible */
  94. mfmsr r7
  95. rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
  96. mfspr r7, SPRN_PID0
  97. slwi r7,r7,16
  98. or r7,r7,r4
  99. mtspr SPRN_MAS6,r7
  100. tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
  101. #ifndef CONFIG_E200
  102. mfspr r7,SPRN_MAS1
  103. andis. r7,r7,MAS1_VALID@h
  104. bne match_TLB
  105. mfspr r7,SPRN_PID1
  106. slwi r7,r7,16
  107. or r7,r7,r4
  108. mtspr SPRN_MAS6,r7
  109. tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
  110. mfspr r7,SPRN_MAS1
  111. andis. r7,r7,MAS1_VALID@h
  112. bne match_TLB
  113. mfspr r7, SPRN_PID2
  114. slwi r7,r7,16
  115. or r7,r7,r4
  116. mtspr SPRN_MAS6,r7
  117. tlbsx 0,r6 /* Fall through, we had to match */
  118. #endif
  119. match_TLB:
  120. mfspr r7,SPRN_MAS0
  121. rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
  122. mfspr r7,SPRN_MAS1 /* Insure IPROT set */
  123. oris r7,r7,MAS1_IPROT@h
  124. mtspr SPRN_MAS1,r7
  125. tlbwe
  126. /* 2. Invalidate all entries except the entry we're executing in */
  127. mfspr r9,SPRN_TLB1CFG
  128. andi. r9,r9,0xfff
  129. li r6,0 /* Set Entry counter to 0 */
  130. 1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
  131. rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
  132. mtspr SPRN_MAS0,r7
  133. tlbre
  134. mfspr r7,SPRN_MAS1
  135. rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
  136. cmpw r3,r6
  137. beq skpinv /* Dont update the current execution TLB */
  138. mtspr SPRN_MAS1,r7
  139. tlbwe
  140. isync
  141. skpinv: addi r6,r6,1 /* Increment */
  142. cmpw r6,r9 /* Are we done? */
  143. bne 1b /* If not, repeat */
  144. /* Invalidate TLB0 */
  145. li r6,0x04
  146. tlbivax 0,r6
  147. #ifdef CONFIG_SMP
  148. tlbsync
  149. #endif
  150. /* Invalidate TLB1 */
  151. li r6,0x0c
  152. tlbivax 0,r6
  153. #ifdef CONFIG_SMP
  154. tlbsync
  155. #endif
  156. msync
  157. /* 3. Setup a temp mapping and jump to it */
  158. andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
  159. addi r5, r5, 0x1
  160. lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
  161. rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
  162. mtspr SPRN_MAS0,r7
  163. tlbre
  164. /* Just modify the entry ID and EPN for the temp mapping */
  165. lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
  166. rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
  167. mtspr SPRN_MAS0,r7
  168. xori r6,r4,1 /* Setup TMP mapping in the other Address space */
  169. slwi r6,r6,12
  170. oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
  171. ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
  172. mtspr SPRN_MAS1,r6
  173. mfspr r6,SPRN_MAS2
  174. li r7,0 /* temp EPN = 0 */
  175. rlwimi r7,r6,0,20,31
  176. mtspr SPRN_MAS2,r7
  177. tlbwe
  178. xori r6,r4,1
  179. slwi r6,r6,5 /* setup new context with other address space */
  180. bl 1f /* Find our address */
  181. 1: mflr r9
  182. rlwimi r7,r9,0,20,31
  183. addi r7,r7,24
  184. mtspr SPRN_SRR0,r7
  185. mtspr SPRN_SRR1,r6
  186. rfi
  187. /* 4. Clear out PIDs & Search info */
  188. li r6,0
  189. mtspr SPRN_PID0,r6
  190. #ifndef CONFIG_E200
  191. mtspr SPRN_PID1,r6
  192. mtspr SPRN_PID2,r6
  193. #endif
  194. mtspr SPRN_MAS6,r6
  195. /* 5. Invalidate mapping we started in */
  196. lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
  197. rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
  198. mtspr SPRN_MAS0,r7
  199. tlbre
  200. li r6,0
  201. mtspr SPRN_MAS1,r6
  202. tlbwe
  203. /* Invalidate TLB1 */
  204. li r9,0x0c
  205. tlbivax 0,r9
  206. #ifdef CONFIG_SMP
  207. tlbsync
  208. #endif
  209. msync
  210. /* 6. Setup KERNELBASE mapping in TLB1[0] */
  211. lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
  212. mtspr SPRN_MAS0,r6
  213. lis r6,(MAS1_VALID|MAS1_IPROT)@h
  214. ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_16M))@l
  215. mtspr SPRN_MAS1,r6
  216. li r7,0
  217. lis r6,KERNELBASE@h
  218. ori r6,r6,KERNELBASE@l
  219. rlwimi r6,r7,0,20,31
  220. mtspr SPRN_MAS2,r6
  221. li r7,(MAS3_SX|MAS3_SW|MAS3_SR)
  222. mtspr SPRN_MAS3,r7
  223. tlbwe
  224. /* 7. Jump to KERNELBASE mapping */
  225. lis r7,MSR_KERNEL@h
  226. ori r7,r7,MSR_KERNEL@l
  227. bl 1f /* Find our address */
  228. 1: mflr r9
  229. rlwimi r6,r9,0,20,31
  230. addi r6,r6,24
  231. mtspr SPRN_SRR0,r6
  232. mtspr SPRN_SRR1,r7
  233. rfi /* start execution out of TLB1[0] entry */
  234. /* 8. Clear out the temp mapping */
  235. lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
  236. rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
  237. mtspr SPRN_MAS0,r7
  238. tlbre
  239. mtspr SPRN_MAS1,r8
  240. tlbwe
  241. /* Invalidate TLB1 */
  242. li r9,0x0c
  243. tlbivax 0,r9
  244. #ifdef CONFIG_SMP
  245. tlbsync
  246. #endif
  247. msync
  248. /* Establish the interrupt vector offsets */
  249. SET_IVOR(0, CriticalInput);
  250. SET_IVOR(1, MachineCheck);
  251. SET_IVOR(2, DataStorage);
  252. SET_IVOR(3, InstructionStorage);
  253. SET_IVOR(4, ExternalInput);
  254. SET_IVOR(5, Alignment);
  255. SET_IVOR(6, Program);
  256. SET_IVOR(7, FloatingPointUnavailable);
  257. SET_IVOR(8, SystemCall);
  258. SET_IVOR(9, AuxillaryProcessorUnavailable);
  259. SET_IVOR(10, Decrementer);
  260. SET_IVOR(11, FixedIntervalTimer);
  261. SET_IVOR(12, WatchdogTimer);
  262. SET_IVOR(13, DataTLBError);
  263. SET_IVOR(14, InstructionTLBError);
  264. SET_IVOR(15, Debug);
  265. SET_IVOR(32, SPEUnavailable);
  266. SET_IVOR(33, SPEFloatingPointData);
  267. SET_IVOR(34, SPEFloatingPointRound);
  268. #ifndef CONFIG_E200
  269. SET_IVOR(35, PerformanceMonitor);
  270. #endif
  271. /* Establish the interrupt vector base */
  272. lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
  273. mtspr SPRN_IVPR,r4
  274. /* Setup the defaults for TLB entries */
  275. li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l
  276. #ifdef CONFIG_E200
  277. oris r2,r2,MAS4_TLBSELD(1)@h
  278. #endif
  279. mtspr SPRN_MAS4, r2
  280. #if 0
  281. /* Enable DOZE */
  282. mfspr r2,SPRN_HID0
  283. oris r2,r2,HID0_DOZE@h
  284. mtspr SPRN_HID0, r2
  285. #endif
  286. #ifdef CONFIG_E200
  287. /* enable dedicated debug exception handling resources (Debug APU) */
  288. mfspr r2,SPRN_HID0
  289. ori r2,r2,HID0_DAPUEN@l
  290. mtspr SPRN_HID0,r2
  291. #endif
  292. #if !defined(CONFIG_BDI_SWITCH)
  293. /*
  294. * The Abatron BDI JTAG debugger does not tolerate others
  295. * mucking with the debug registers.
  296. */
  297. lis r2,DBCR0_IDM@h
  298. mtspr SPRN_DBCR0,r2
  299. /* clear any residual debug events */
  300. li r2,-1
  301. mtspr SPRN_DBSR,r2
  302. #endif
  303. /*
  304. * This is where the main kernel code starts.
  305. */
  306. /* ptr to current */
  307. lis r2,init_task@h
  308. ori r2,r2,init_task@l
  309. /* ptr to current thread */
  310. addi r4,r2,THREAD /* init task's THREAD */
  311. mtspr SPRN_SPRG3,r4
  312. /* stack */
  313. lis r1,init_thread_union@h
  314. ori r1,r1,init_thread_union@l
  315. li r0,0
  316. stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
  317. bl early_init
  318. mfspr r3,SPRN_TLB1CFG
  319. andi. r3,r3,0xfff
  320. lis r4,num_tlbcam_entries@ha
  321. stw r3,num_tlbcam_entries@l(r4)
  322. /*
  323. * Decide what sort of machine this is and initialize the MMU.
  324. */
  325. mr r3,r31
  326. mr r4,r30
  327. mr r5,r29
  328. mr r6,r28
  329. mr r7,r27
  330. bl machine_init
  331. bl MMU_init
  332. /* Setup PTE pointers for the Abatron bdiGDB */
  333. lis r6, swapper_pg_dir@h
  334. ori r6, r6, swapper_pg_dir@l
  335. lis r5, abatron_pteptrs@h
  336. ori r5, r5, abatron_pteptrs@l
  337. lis r4, KERNELBASE@h
  338. ori r4, r4, KERNELBASE@l
  339. stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
  340. stw r6, 0(r5)
  341. /* Let's move on */
  342. lis r4,start_kernel@h
  343. ori r4,r4,start_kernel@l
  344. lis r3,MSR_KERNEL@h
  345. ori r3,r3,MSR_KERNEL@l
  346. mtspr SPRN_SRR0,r4
  347. mtspr SPRN_SRR1,r3
  348. rfi /* change context and jump to start_kernel */
  349. /* Macros to hide the PTE size differences
  350. *
  351. * FIND_PTE -- walks the page tables given EA & pgdir pointer
  352. * r10 -- EA of fault
  353. * r11 -- PGDIR pointer
  354. * r12 -- free
  355. * label 2: is the bailout case
  356. *
  357. * if we find the pte (fall through):
  358. * r11 is low pte word
  359. * r12 is pointer to the pte
  360. */
  361. #ifdef CONFIG_PTE_64BIT
  362. #define PTE_FLAGS_OFFSET 4
  363. #define FIND_PTE \
  364. rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
  365. lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
  366. rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
  367. beq 2f; /* Bail if no table */ \
  368. rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
  369. lwz r11, 4(r12); /* Get pte entry */
  370. #else
  371. #define PTE_FLAGS_OFFSET 0
  372. #define FIND_PTE \
  373. rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
  374. lwz r11, 0(r11); /* Get L1 entry */ \
  375. rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
  376. beq 2f; /* Bail if no table */ \
  377. rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
  378. lwz r11, 0(r12); /* Get Linux PTE */
  379. #endif
  380. /*
  381. * Interrupt vector entry code
  382. *
  383. * The Book E MMUs are always on so we don't need to handle
  384. * interrupts in real mode as with previous PPC processors. In
  385. * this case we handle interrupts in the kernel virtual address
  386. * space.
  387. *
  388. * Interrupt vectors are dynamically placed relative to the
  389. * interrupt prefix as determined by the address of interrupt_base.
  390. * The interrupt vectors offsets are programmed using the labels
  391. * for each interrupt vector entry.
  392. *
  393. * Interrupt vectors must be aligned on a 16 byte boundary.
  394. * We align on a 32 byte cache line boundary for good measure.
  395. */
  396. interrupt_base:
  397. /* Critical Input Interrupt */
  398. CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException)
  399. /* Machine Check Interrupt */
  400. #ifdef CONFIG_E200
  401. /* no RFMCI, MCSRRs on E200 */
  402. CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
  403. #else
  404. MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
  405. #endif
  406. /* Data Storage Interrupt */
  407. START_EXCEPTION(DataStorage)
  408. mtspr SPRN_SPRG0, r10 /* Save some working registers */
  409. mtspr SPRN_SPRG1, r11
  410. mtspr SPRN_SPRG4W, r12
  411. mtspr SPRN_SPRG5W, r13
  412. mfcr r11
  413. mtspr SPRN_SPRG7W, r11
  414. /*
  415. * Check if it was a store fault, if not then bail
  416. * because a user tried to access a kernel or
  417. * read-protected page. Otherwise, get the
  418. * offending address and handle it.
  419. */
  420. mfspr r10, SPRN_ESR
  421. andis. r10, r10, ESR_ST@h
  422. beq 2f
  423. mfspr r10, SPRN_DEAR /* Get faulting address */
  424. /* If we are faulting a kernel address, we have to use the
  425. * kernel page tables.
  426. */
  427. lis r11, TASK_SIZE@h
  428. ori r11, r11, TASK_SIZE@l
  429. cmplw 0, r10, r11
  430. bge 2f
  431. /* Get the PGD for the current thread */
  432. 3:
  433. mfspr r11,SPRN_SPRG3
  434. lwz r11,PGDIR(r11)
  435. 4:
  436. FIND_PTE
  437. /* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
  438. andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
  439. cmpwi 0, r13, _PAGE_RW|_PAGE_USER
  440. bne 2f /* Bail if not */
  441. /* Update 'changed'. */
  442. ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
  443. stw r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */
  444. /* MAS2 not updated as the entry does exist in the tlb, this
  445. fault taken to detect state transition (eg: COW -> DIRTY)
  446. */
  447. andi. r11, r11, _PAGE_HWEXEC
  448. rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */
  449. ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
  450. /* update search PID in MAS6, AS = 0 */
  451. mfspr r12, SPRN_PID0
  452. slwi r12, r12, 16
  453. mtspr SPRN_MAS6, r12
  454. /* find the TLB index that caused the fault. It has to be here. */
  455. tlbsx 0, r10
  456. /* only update the perm bits, assume the RPN is fine */
  457. mfspr r12, SPRN_MAS3
  458. rlwimi r12, r11, 0, 20, 31
  459. mtspr SPRN_MAS3,r12
  460. tlbwe
  461. /* Done...restore registers and get out of here. */
  462. mfspr r11, SPRN_SPRG7R
  463. mtcr r11
  464. mfspr r13, SPRN_SPRG5R
  465. mfspr r12, SPRN_SPRG4R
  466. mfspr r11, SPRN_SPRG1
  467. mfspr r10, SPRN_SPRG0
  468. rfi /* Force context change */
  469. 2:
  470. /*
  471. * The bailout. Restore registers to pre-exception conditions
  472. * and call the heavyweights to help us out.
  473. */
  474. mfspr r11, SPRN_SPRG7R
  475. mtcr r11
  476. mfspr r13, SPRN_SPRG5R
  477. mfspr r12, SPRN_SPRG4R
  478. mfspr r11, SPRN_SPRG1
  479. mfspr r10, SPRN_SPRG0
  480. b data_access
  481. /* Instruction Storage Interrupt */
  482. INSTRUCTION_STORAGE_EXCEPTION
  483. /* External Input Interrupt */
  484. EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
  485. /* Alignment Interrupt */
  486. ALIGNMENT_EXCEPTION
  487. /* Program Interrupt */
  488. PROGRAM_EXCEPTION
  489. /* Floating Point Unavailable Interrupt */
  490. #ifdef CONFIG_PPC_FPU
  491. FP_UNAVAILABLE_EXCEPTION
  492. #else
  493. #ifdef CONFIG_E200
  494. /* E200 treats 'normal' floating point instructions as FP Unavail exception */
  495. EXCEPTION(0x0800, FloatingPointUnavailable, ProgramCheckException, EXC_XFER_EE)
  496. #else
  497. EXCEPTION(0x0800, FloatingPointUnavailable, UnknownException, EXC_XFER_EE)
  498. #endif
  499. #endif
  500. /* System Call Interrupt */
  501. START_EXCEPTION(SystemCall)
  502. NORMAL_EXCEPTION_PROLOG
  503. EXC_XFER_EE_LITE(0x0c00, DoSyscall)
  504. /* Auxillary Processor Unavailable Interrupt */
  505. EXCEPTION(0x2900, AuxillaryProcessorUnavailable, UnknownException, EXC_XFER_EE)
  506. /* Decrementer Interrupt */
  507. DECREMENTER_EXCEPTION
  508. /* Fixed Internal Timer Interrupt */
  509. /* TODO: Add FIT support */
  510. EXCEPTION(0x3100, FixedIntervalTimer, UnknownException, EXC_XFER_EE)
  511. /* Watchdog Timer Interrupt */
  512. #ifdef CONFIG_BOOKE_WDT
  513. CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
  514. #else
  515. CRITICAL_EXCEPTION(0x3200, WatchdogTimer, UnknownException)
  516. #endif
  517. /* Data TLB Error Interrupt */
  518. START_EXCEPTION(DataTLBError)
  519. mtspr SPRN_SPRG0, r10 /* Save some working registers */
  520. mtspr SPRN_SPRG1, r11
  521. mtspr SPRN_SPRG4W, r12
  522. mtspr SPRN_SPRG5W, r13
  523. mfcr r11
  524. mtspr SPRN_SPRG7W, r11
  525. mfspr r10, SPRN_DEAR /* Get faulting address */
  526. /* If we are faulting a kernel address, we have to use the
  527. * kernel page tables.
  528. */
  529. lis r11, TASK_SIZE@h
  530. ori r11, r11, TASK_SIZE@l
  531. cmplw 5, r10, r11
  532. blt 5, 3f
  533. lis r11, swapper_pg_dir@h
  534. ori r11, r11, swapper_pg_dir@l
  535. mfspr r12,SPRN_MAS1 /* Set TID to 0 */
  536. rlwinm r12,r12,0,16,1
  537. mtspr SPRN_MAS1,r12
  538. b 4f
  539. /* Get the PGD for the current thread */
  540. 3:
  541. mfspr r11,SPRN_SPRG3
  542. lwz r11,PGDIR(r11)
  543. 4:
  544. FIND_PTE
  545. andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
  546. beq 2f /* Bail if not present */
  547. #ifdef CONFIG_PTE_64BIT
  548. lwz r13, 0(r12)
  549. #endif
  550. ori r11, r11, _PAGE_ACCESSED
  551. stw r11, PTE_FLAGS_OFFSET(r12)
  552. /* Jump to common tlb load */
  553. b finish_tlb_load
  554. 2:
  555. /* The bailout. Restore registers to pre-exception conditions
  556. * and call the heavyweights to help us out.
  557. */
  558. mfspr r11, SPRN_SPRG7R
  559. mtcr r11
  560. mfspr r13, SPRN_SPRG5R
  561. mfspr r12, SPRN_SPRG4R
  562. mfspr r11, SPRN_SPRG1
  563. mfspr r10, SPRN_SPRG0
  564. b data_access
  565. /* Instruction TLB Error Interrupt */
  566. /*
  567. * Nearly the same as above, except we get our
  568. * information from different registers and bailout
  569. * to a different point.
  570. */
  571. START_EXCEPTION(InstructionTLBError)
  572. mtspr SPRN_SPRG0, r10 /* Save some working registers */
  573. mtspr SPRN_SPRG1, r11
  574. mtspr SPRN_SPRG4W, r12
  575. mtspr SPRN_SPRG5W, r13
  576. mfcr r11
  577. mtspr SPRN_SPRG7W, r11
  578. mfspr r10, SPRN_SRR0 /* Get faulting address */
  579. /* If we are faulting a kernel address, we have to use the
  580. * kernel page tables.
  581. */
  582. lis r11, TASK_SIZE@h
  583. ori r11, r11, TASK_SIZE@l
  584. cmplw 5, r10, r11
  585. blt 5, 3f
  586. lis r11, swapper_pg_dir@h
  587. ori r11, r11, swapper_pg_dir@l
  588. mfspr r12,SPRN_MAS1 /* Set TID to 0 */
  589. rlwinm r12,r12,0,16,1
  590. mtspr SPRN_MAS1,r12
  591. b 4f
  592. /* Get the PGD for the current thread */
  593. 3:
  594. mfspr r11,SPRN_SPRG3
  595. lwz r11,PGDIR(r11)
  596. 4:
  597. FIND_PTE
  598. andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
  599. beq 2f /* Bail if not present */
  600. #ifdef CONFIG_PTE_64BIT
  601. lwz r13, 0(r12)
  602. #endif
  603. ori r11, r11, _PAGE_ACCESSED
  604. stw r11, PTE_FLAGS_OFFSET(r12)
  605. /* Jump to common TLB load point */
  606. b finish_tlb_load
  607. 2:
  608. /* The bailout. Restore registers to pre-exception conditions
  609. * and call the heavyweights to help us out.
  610. */
  611. mfspr r11, SPRN_SPRG7R
  612. mtcr r11
  613. mfspr r13, SPRN_SPRG5R
  614. mfspr r12, SPRN_SPRG4R
  615. mfspr r11, SPRN_SPRG1
  616. mfspr r10, SPRN_SPRG0
  617. b InstructionStorage
  618. #ifdef CONFIG_SPE
  619. /* SPE Unavailable */
  620. START_EXCEPTION(SPEUnavailable)
  621. NORMAL_EXCEPTION_PROLOG
  622. bne load_up_spe
  623. addi r3,r1,STACK_FRAME_OVERHEAD
  624. EXC_XFER_EE_LITE(0x2010, KernelSPE)
  625. #else
  626. EXCEPTION(0x2020, SPEUnavailable, UnknownException, EXC_XFER_EE)
  627. #endif /* CONFIG_SPE */
  628. /* SPE Floating Point Data */
  629. #ifdef CONFIG_SPE
  630. EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
  631. #else
  632. EXCEPTION(0x2040, SPEFloatingPointData, UnknownException, EXC_XFER_EE)
  633. #endif /* CONFIG_SPE */
  634. /* SPE Floating Point Round */
  635. EXCEPTION(0x2050, SPEFloatingPointRound, UnknownException, EXC_XFER_EE)
  636. /* Performance Monitor */
  637. EXCEPTION(0x2060, PerformanceMonitor, PerformanceMonitorException, EXC_XFER_STD)
  638. /* Debug Interrupt */
  639. DEBUG_EXCEPTION
  640. /*
  641. * Local functions
  642. */
  643. /*
  644. * Data TLB exceptions will bail out to this point
  645. * if they can't resolve the lightweight TLB fault.
  646. */
  647. data_access:
  648. NORMAL_EXCEPTION_PROLOG
  649. mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
  650. stw r5,_ESR(r11)
  651. mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
  652. andis. r10,r5,(ESR_ILK|ESR_DLK)@h
  653. bne 1f
  654. EXC_XFER_EE_LITE(0x0300, handle_page_fault)
  655. 1:
  656. addi r3,r1,STACK_FRAME_OVERHEAD
  657. EXC_XFER_EE_LITE(0x0300, CacheLockingException)
  658. /*
  659. * Both the instruction and data TLB miss get to this
  660. * point to load the TLB.
  661. * r10 - EA of fault
  662. * r11 - TLB (info from Linux PTE)
  663. * r12, r13 - available to use
  664. * CR5 - results of addr < TASK_SIZE
  665. * MAS0, MAS1 - loaded with proper value when we get here
  666. * MAS2, MAS3 - will need additional info from Linux PTE
  667. * Upon exit, we reload everything and RFI.
  668. */
  669. finish_tlb_load:
  670. /*
  671. * We set execute, because we don't have the granularity to
  672. * properly set this at the page level (Linux problem).
  673. * Many of these bits are software only. Bits we don't set
  674. * here we (properly should) assume have the appropriate value.
  675. */
  676. mfspr r12, SPRN_MAS2
  677. #ifdef CONFIG_PTE_64BIT
  678. rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */
  679. #else
  680. rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
  681. #endif
  682. mtspr SPRN_MAS2, r12
  683. bge 5, 1f
  684. /* is user addr */
  685. andi. r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
  686. andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
  687. srwi r10, r12, 1
  688. or r12, r12, r10 /* Copy user perms into supervisor */
  689. iseleq r12, 0, r12
  690. b 2f
  691. /* is kernel addr */
  692. 1: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */
  693. ori r12, r12, (MAS3_SX | MAS3_SR)
  694. #ifdef CONFIG_PTE_64BIT
  695. 2: rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */
  696. rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */
  697. mtspr SPRN_MAS3, r12
  698. BEGIN_FTR_SECTION
  699. srwi r10, r13, 8 /* grab RPN[8:31] */
  700. mtspr SPRN_MAS7, r10
  701. END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS)
  702. #else
  703. 2: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
  704. mtspr SPRN_MAS3, r11
  705. #endif
  706. #ifdef CONFIG_E200
  707. /* Round robin TLB1 entries assignment */
  708. mfspr r12, SPRN_MAS0
  709. /* Extract TLB1CFG(NENTRY) */
  710. mfspr r11, SPRN_TLB1CFG
  711. andi. r11, r11, 0xfff
  712. /* Extract MAS0(NV) */
  713. andi. r13, r12, 0xfff
  714. addi r13, r13, 1
  715. cmpw 0, r13, r11
  716. addi r12, r12, 1
  717. /* check if we need to wrap */
  718. blt 7f
  719. /* wrap back to first free tlbcam entry */
  720. lis r13, tlbcam_index@ha
  721. lwz r13, tlbcam_index@l(r13)
  722. rlwimi r12, r13, 0, 20, 31
  723. 7:
  724. mtspr SPRN_MAS0,r12
  725. #endif /* CONFIG_E200 */
  726. tlbwe
  727. /* Done...restore registers and get out of here. */
  728. mfspr r11, SPRN_SPRG7R
  729. mtcr r11
  730. mfspr r13, SPRN_SPRG5R
  731. mfspr r12, SPRN_SPRG4R
  732. mfspr r11, SPRN_SPRG1
  733. mfspr r10, SPRN_SPRG0
  734. rfi /* Force context change */
  735. #ifdef CONFIG_SPE
  736. /* Note that the SPE support is closely modeled after the AltiVec
  737. * support. Changes to one are likely to be applicable to the
  738. * other! */
  739. load_up_spe:
  740. /*
  741. * Disable SPE for the task which had SPE previously,
  742. * and save its SPE registers in its thread_struct.
  743. * Enables SPE for use in the kernel on return.
  744. * On SMP we know the SPE units are free, since we give it up every
  745. * switch. -- Kumar
  746. */
  747. mfmsr r5
  748. oris r5,r5,MSR_SPE@h
  749. mtmsr r5 /* enable use of SPE now */
  750. isync
  751. /*
  752. * For SMP, we don't do lazy SPE switching because it just gets too
  753. * horrendously complex, especially when a task switches from one CPU
  754. * to another. Instead we call giveup_spe in switch_to.
  755. */
  756. #ifndef CONFIG_SMP
  757. lis r3,last_task_used_spe@ha
  758. lwz r4,last_task_used_spe@l(r3)
  759. cmpi 0,r4,0
  760. beq 1f
  761. addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
  762. SAVE_32EVR(0,r10,r4)
  763. evxor evr10, evr10, evr10 /* clear out evr10 */
  764. evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
  765. li r5,THREAD_ACC
  766. evstddx evr10, r4, r5 /* save off accumulator */
  767. lwz r5,PT_REGS(r4)
  768. lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
  769. lis r10,MSR_SPE@h
  770. andc r4,r4,r10 /* disable SPE for previous task */
  771. stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
  772. 1:
  773. #endif /* CONFIG_SMP */
  774. /* enable use of SPE after return */
  775. oris r9,r9,MSR_SPE@h
  776. mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
  777. li r4,1
  778. li r10,THREAD_ACC
  779. stw r4,THREAD_USED_SPE(r5)
  780. evlddx evr4,r10,r5
  781. evmra evr4,evr4
  782. REST_32EVR(0,r10,r5)
  783. #ifndef CONFIG_SMP
  784. subi r4,r5,THREAD
  785. stw r4,last_task_used_spe@l(r3)
  786. #endif /* CONFIG_SMP */
  787. /* restore registers and return */
  788. 2: REST_4GPRS(3, r11)
  789. lwz r10,_CCR(r11)
  790. REST_GPR(1, r11)
  791. mtcr r10
  792. lwz r10,_LINK(r11)
  793. mtlr r10
  794. REST_GPR(10, r11)
  795. mtspr SPRN_SRR1,r9
  796. mtspr SPRN_SRR0,r12
  797. REST_GPR(9, r11)
  798. REST_GPR(12, r11)
  799. lwz r11,GPR11(r11)
  800. SYNC
  801. rfi
  802. /*
  803. * SPE unavailable trap from kernel - print a message, but let
  804. * the task use SPE in the kernel until it returns to user mode.
  805. */
  806. KernelSPE:
  807. lwz r3,_MSR(r1)
  808. oris r3,r3,MSR_SPE@h
  809. stw r3,_MSR(r1) /* enable use of SPE after return */
  810. lis r3,87f@h
  811. ori r3,r3,87f@l
  812. mr r4,r2 /* current */
  813. lwz r5,_NIP(r1)
  814. bl printk
  815. b ret_from_except
  816. 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
  817. .align 4,0
  818. #endif /* CONFIG_SPE */
  819. /*
  820. * Global functions
  821. */
  822. /*
  823. * extern void loadcam_entry(unsigned int index)
  824. *
  825. * Load TLBCAM[index] entry in to the L2 CAM MMU
  826. */
  827. _GLOBAL(loadcam_entry)
  828. lis r4,TLBCAM@ha
  829. addi r4,r4,TLBCAM@l
  830. mulli r5,r3,20
  831. add r3,r5,r4
  832. lwz r4,0(r3)
  833. mtspr SPRN_MAS0,r4
  834. lwz r4,4(r3)
  835. mtspr SPRN_MAS1,r4
  836. lwz r4,8(r3)
  837. mtspr SPRN_MAS2,r4
  838. lwz r4,12(r3)
  839. mtspr SPRN_MAS3,r4
  840. tlbwe
  841. isync
  842. blr
  843. /*
  844. * extern void giveup_altivec(struct task_struct *prev)
  845. *
  846. * The e500 core does not have an AltiVec unit.
  847. */
  848. _GLOBAL(giveup_altivec)
  849. blr
  850. #ifdef CONFIG_SPE
  851. /*
  852. * extern void giveup_spe(struct task_struct *prev)
  853. *
  854. */
  855. _GLOBAL(giveup_spe)
  856. mfmsr r5
  857. oris r5,r5,MSR_SPE@h
  858. SYNC
  859. mtmsr r5 /* enable use of SPE now */
  860. isync
  861. cmpi 0,r3,0
  862. beqlr- /* if no previous owner, done */
  863. addi r3,r3,THREAD /* want THREAD of task */
  864. lwz r5,PT_REGS(r3)
  865. cmpi 0,r5,0
  866. SAVE_32EVR(0, r4, r3)
  867. evxor evr6, evr6, evr6 /* clear out evr6 */
  868. evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
  869. li r4,THREAD_ACC
  870. evstddx evr6, r4, r3 /* save off accumulator */
  871. mfspr r6,SPRN_SPEFSCR
  872. stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
  873. beq 1f
  874. lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
  875. lis r3,MSR_SPE@h
  876. andc r4,r4,r3 /* disable SPE for previous task */
  877. stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
  878. 1:
  879. #ifndef CONFIG_SMP
  880. li r5,0
  881. lis r4,last_task_used_spe@ha
  882. stw r5,last_task_used_spe@l(r4)
  883. #endif /* CONFIG_SMP */
  884. blr
  885. #endif /* CONFIG_SPE */
  886. /*
  887. * extern void giveup_fpu(struct task_struct *prev)
  888. *
  889. * Not all FSL Book-E cores have an FPU
  890. */
  891. #ifndef CONFIG_PPC_FPU
  892. _GLOBAL(giveup_fpu)
  893. blr
  894. #endif
  895. /*
  896. * extern void abort(void)
  897. *
  898. * At present, this routine just applies a system reset.
  899. */
  900. _GLOBAL(abort)
  901. li r13,0
  902. mtspr SPRN_DBCR0,r13 /* disable all debug events */
  903. mfmsr r13
  904. ori r13,r13,MSR_DE@l /* Enable Debug Events */
  905. mtmsr r13
  906. mfspr r13,SPRN_DBCR0
  907. lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
  908. mtspr SPRN_DBCR0,r13
  909. _GLOBAL(set_context)
  910. #ifdef CONFIG_BDI_SWITCH
  911. /* Context switch the PTE pointer for the Abatron BDI2000.
  912. * The PGDIR is the second parameter.
  913. */
  914. lis r5, abatron_pteptrs@h
  915. ori r5, r5, abatron_pteptrs@l
  916. stw r4, 0x4(r5)
  917. #endif
  918. mtspr SPRN_PID,r3
  919. isync /* Force context change */
  920. blr
  921. /*
  922. * We put a few things here that have to be page-aligned. This stuff
  923. * goes at the beginning of the data segment, which is page-aligned.
  924. */
  925. .data
  926. _GLOBAL(sdata)
  927. _GLOBAL(empty_zero_page)
  928. .space 4096
  929. _GLOBAL(swapper_pg_dir)
  930. .space 4096
  931. /* Reserved 4k for the critical exception stack & 4k for the machine
  932. * check stack per CPU for kernel mode exceptions */
  933. .section .bss
  934. .align 12
  935. exception_stack_bottom:
  936. .space BOOKE_EXCEPTION_STACK_SIZE * NR_CPUS
  937. _GLOBAL(exception_stack_top)
  938. /*
  939. * This space gets a copy of optional info passed to us by the bootstrap
  940. * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
  941. */
  942. _GLOBAL(cmd_line)
  943. .space 512
  944. /*
  945. * Room for two PTE pointers, usually the kernel and current user pointers
  946. * to their respective root page table.
  947. */
  948. abatron_pteptrs:
  949. .space 8