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mpc10x.h

mpc10x.h 2.2 KB
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  1. /*
    2. 

  2.  * arch/ppc/boot/include/mpc10.h
    3. 

  3.  *
    4. 

  4.  * Common defines for the Motorola SPS MPC106/8240/107 Host bridge/Mem
    5. 

  5.  * ctrl/EPIC/etc.
    6. 

  6.  *
    7. 

  7.  * Author: Tom Rini <trini@mvista.com>
    8. 

  8.  *
    9. 

  9.  * This is a heavily stripped down version of:
    10. 

  10.  * include/asm-ppc/mpc10x.h
    11. 

  11.  *
    12. 

  12.  * Author: Mark A. Greer
    13. 

  13.  *         mgreer@mvista.com
    14. 

  14.  *
    15. 

  15.  * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
    16. 

  16.  * the terms of the GNU General Public License version 2.  This program
    17. 

  17.  * is licensed "as is" without any warranty of any kind, whether express
    18. 

  18.  * or implied.
    19. 

  19.  */
    20. 

  20. #ifndef __BOOT_MPC10X_H__
    21. 

  21. #define __BOOT_MPC10X_H__
    22. 

  22. 

  23. /*
    24. 

  24.  * The values here don't completely map everything but should work in most
    25. 

  25.  * cases.
    26. 

  26.  *
    27. 

  27.  * MAP A (PReP Map)
    28. 

  28.  *   Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
    29. 

  29.  *   Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
    30. 

  30.  *   PCI MEM:   0x80000000 -> Processor System Memory: 0x00000000
    31. 

  31.  *   EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
    32. 

  32.  *
    33. 

  33.  * MAP B (CHRP Map)
    34. 

  34.  *   Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
    35. 

  35.  *   Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
    36. 

  36.  *   PCI MEM:   0x00000000 -> Processor System Memory: 0x00000000
    37. 

  37.  *   EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
    38. 

  38.  */
    39. 

  39. 

  40. /* Define the type of map to use */
    41. 

  41. #define	MPC10X_MEM_MAP_A		1
    42. 

  42. #define	MPC10X_MEM_MAP_B		2
    43. 

  43. 

  44. /* Map A (PReP Map) Defines */
    45. 

  45. #define	MPC10X_MAPA_CNFG_ADDR		0x80000cf8
    46. 

  46. #define	MPC10X_MAPA_CNFG_DATA		0x80000cfc
    47. 

  47. 

  48. /* Map B (CHRP Map) Defines */
    49. 

  49. #define	MPC10X_MAPB_CNFG_ADDR		0xfec00000
    50. 

  50. #define	MPC10X_MAPB_CNFG_DATA		0xfee00000
    51. 

  51. 

  52. /* Define offsets for the memory controller registers in the config space */
    53. 

  53. #define MPC10X_MCTLR_MEM_START_1	0x80	/* Banks 0-3 */
    54. 

  54. #define MPC10X_MCTLR_MEM_START_2	0x84	/* Banks 4-7 */
    55. 

  55. #define MPC10X_MCTLR_EXT_MEM_START_1	0x88	/* Banks 0-3 */
    56. 

  56. #define MPC10X_MCTLR_EXT_MEM_START_2	0x8c	/* Banks 4-7 */
    57. 

  57. 

  58. #define MPC10X_MCTLR_MEM_END_1		0x90	/* Banks 0-3 */
    59. 

  59. #define MPC10X_MCTLR_MEM_END_2		0x94	/* Banks 4-7 */
    60. 

  60. #define MPC10X_MCTLR_EXT_MEM_END_1	0x98	/* Banks 0-3 */
    61. 

  61. #define MPC10X_MCTLR_EXT_MEM_END_2	0x9c	/* Banks 4-7 */
    62. 

  62. 

  63. #define MPC10X_MCTLR_MEM_BANK_ENABLES	0xa0
    64. 

  64. 

  65. #endif	/* __BOOT_MPC10X_H__ */
    66.