ops-mace.c 1.9 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091
  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2000, 2001 Keith M Wesolowski
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/init.h>
  10. #include <linux/pci.h>
  11. #include <linux/types.h>
  12. #include <asm/pci.h>
  13. #include <asm/ip32/mace.h>
  14. #if 0
  15. # define DPRINTK(args...) printk(args);
  16. #else
  17. # define DPRINTK(args...)
  18. #endif
  19. /*
  20. * O2 has up to 5 PCI devices connected into the MACE bridge. The device
  21. * map looks like this:
  22. *
  23. * 0 aic7xxx 0
  24. * 1 aic7xxx 1
  25. * 2 expansion slot
  26. * 3 N/C
  27. * 4 N/C
  28. */
  29. #define chkslot(_bus,_devfn) \
  30. do { \
  31. if ((_bus)->number > 0 || PCI_SLOT (_devfn) < 1 \
  32. || PCI_SLOT (_devfn) > 3) \
  33. return PCIBIOS_DEVICE_NOT_FOUND; \
  34. } while (0)
  35. #define mkaddr(_devfn, _reg) \
  36. ((((_devfn) & 0xffUL) << 8) | ((_reg) & 0xfcUL))
  37. static int
  38. mace_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  39. int reg, int size, u32 *val)
  40. {
  41. chkslot(bus, devfn);
  42. mace->pci.config_addr = mkaddr(devfn, reg);
  43. switch (size) {
  44. case 1:
  45. *val = mace->pci.config_data.b[(reg & 3) ^ 3];
  46. break;
  47. case 2:
  48. *val = mace->pci.config_data.w[((reg >> 1) & 1) ^ 1];
  49. break;
  50. case 4:
  51. *val = mace->pci.config_data.l;
  52. break;
  53. }
  54. DPRINTK("read%d: reg=%08x,val=%02x\n", size * 8, reg, *val);
  55. return PCIBIOS_SUCCESSFUL;
  56. }
  57. static int
  58. mace_pci_write_config(struct pci_bus *bus, unsigned int devfn,
  59. int reg, int size, u32 val)
  60. {
  61. chkslot(bus, devfn);
  62. mace->pci.config_addr = mkaddr(devfn, reg);
  63. switch (size) {
  64. case 1:
  65. mace->pci.config_data.b[(reg & 3) ^ 3] = val;
  66. break;
  67. case 2:
  68. mace->pci.config_data.w[((reg >> 1) & 1) ^ 1] = val;
  69. break;
  70. case 4:
  71. mace->pci.config_data.l = val;
  72. break;
  73. }
  74. DPRINTK("write%d: reg=%08x,val=%02x\n", size * 8, reg, val);
  75. return PCIBIOS_SUCCESSFUL;
  76. }
  77. struct pci_ops mace_pci_ops = {
  78. .read = mace_pci_read_config,
  79. .write = mace_pci_write_config,
  80. };