gdb-low.S 8.2 KB

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  1. /*
  2. * gdb-low.S contains the low-level trap handler for the GDB stub.
  3. *
  4. * Copyright (C) 1995 Andreas Busse
  5. */
  6. #include <linux/config.h>
  7. #include <linux/sys.h>
  8. #include <asm/asm.h>
  9. #include <asm/errno.h>
  10. #include <asm/mipsregs.h>
  11. #include <asm/regdef.h>
  12. #include <asm/stackframe.h>
  13. #include <asm/gdb-stub.h>
  14. #ifdef CONFIG_32BIT
  15. #define DMFC0 mfc0
  16. #define DMTC0 mtc0
  17. #define LDC1 lwc1
  18. #define SDC1 lwc1
  19. #endif
  20. #ifdef CONFIG_64BIT
  21. #define DMFC0 dmfc0
  22. #define DMTC0 dmtc0
  23. #define LDC1 ldc1
  24. #define SDC1 ldc1
  25. #endif
  26. /*
  27. * [jsun] We reserves about 2x GDB_FR_SIZE in stack. The lower (addressed)
  28. * part is used to store registers and passed to exception handler.
  29. * The upper part is reserved for "call func" feature where gdb client
  30. * saves some of the regs, setups call frame and passes args.
  31. *
  32. * A trace shows about 200 bytes are used to store about half of all regs.
  33. * The rest should be big enough for frame setup and passing args.
  34. */
  35. /*
  36. * The low level trap handler
  37. */
  38. .align 5
  39. NESTED(trap_low, GDB_FR_SIZE, sp)
  40. .set noat
  41. .set noreorder
  42. mfc0 k0, CP0_STATUS
  43. sll k0, 3 /* extract cu0 bit */
  44. bltz k0, 1f
  45. move k1, sp
  46. /*
  47. * Called from user mode, go somewhere else.
  48. */
  49. lui k1, %hi(saved_vectors)
  50. mfc0 k0, CP0_CAUSE
  51. andi k0, k0, 0x7c
  52. add k1, k1, k0
  53. lw k0, %lo(saved_vectors)(k1)
  54. jr k0
  55. nop
  56. 1:
  57. move k0, sp
  58. subu sp, k1, GDB_FR_SIZE*2 # see comment above
  59. LONG_S k0, GDB_FR_REG29(sp)
  60. LONG_S $2, GDB_FR_REG2(sp)
  61. /*
  62. * First save the CP0 and special registers
  63. */
  64. mfc0 v0, CP0_STATUS
  65. LONG_S v0, GDB_FR_STATUS(sp)
  66. mfc0 v0, CP0_CAUSE
  67. LONG_S v0, GDB_FR_CAUSE(sp)
  68. DMFC0 v0, CP0_EPC
  69. LONG_S v0, GDB_FR_EPC(sp)
  70. DMFC0 v0, CP0_BADVADDR
  71. LONG_S v0, GDB_FR_BADVADDR(sp)
  72. mfhi v0
  73. LONG_S v0, GDB_FR_HI(sp)
  74. mflo v0
  75. LONG_S v0, GDB_FR_LO(sp)
  76. /*
  77. * Now the integer registers
  78. */
  79. LONG_S zero, GDB_FR_REG0(sp) /* I know... */
  80. LONG_S $1, GDB_FR_REG1(sp)
  81. /* v0 already saved */
  82. LONG_S $3, GDB_FR_REG3(sp)
  83. LONG_S $4, GDB_FR_REG4(sp)
  84. LONG_S $5, GDB_FR_REG5(sp)
  85. LONG_S $6, GDB_FR_REG6(sp)
  86. LONG_S $7, GDB_FR_REG7(sp)
  87. LONG_S $8, GDB_FR_REG8(sp)
  88. LONG_S $9, GDB_FR_REG9(sp)
  89. LONG_S $10, GDB_FR_REG10(sp)
  90. LONG_S $11, GDB_FR_REG11(sp)
  91. LONG_S $12, GDB_FR_REG12(sp)
  92. LONG_S $13, GDB_FR_REG13(sp)
  93. LONG_S $14, GDB_FR_REG14(sp)
  94. LONG_S $15, GDB_FR_REG15(sp)
  95. LONG_S $16, GDB_FR_REG16(sp)
  96. LONG_S $17, GDB_FR_REG17(sp)
  97. LONG_S $18, GDB_FR_REG18(sp)
  98. LONG_S $19, GDB_FR_REG19(sp)
  99. LONG_S $20, GDB_FR_REG20(sp)
  100. LONG_S $21, GDB_FR_REG21(sp)
  101. LONG_S $22, GDB_FR_REG22(sp)
  102. LONG_S $23, GDB_FR_REG23(sp)
  103. LONG_S $24, GDB_FR_REG24(sp)
  104. LONG_S $25, GDB_FR_REG25(sp)
  105. LONG_S $26, GDB_FR_REG26(sp)
  106. LONG_S $27, GDB_FR_REG27(sp)
  107. LONG_S $28, GDB_FR_REG28(sp)
  108. /* sp already saved */
  109. LONG_S $30, GDB_FR_REG30(sp)
  110. LONG_S $31, GDB_FR_REG31(sp)
  111. CLI /* disable interrupts */
  112. /*
  113. * Followed by the floating point registers
  114. */
  115. mfc0 v0, CP0_STATUS /* FPU enabled? */
  116. srl v0, v0, 16
  117. andi v0, v0, (ST0_CU1 >> 16)
  118. beqz v0,2f /* disabled, skip */
  119. nop
  120. SDC1 $0, GDB_FR_FPR0(sp)
  121. SDC1 $1, GDB_FR_FPR1(sp)
  122. SDC1 $2, GDB_FR_FPR2(sp)
  123. SDC1 $3, GDB_FR_FPR3(sp)
  124. SDC1 $4, GDB_FR_FPR4(sp)
  125. SDC1 $5, GDB_FR_FPR5(sp)
  126. SDC1 $6, GDB_FR_FPR6(sp)
  127. SDC1 $7, GDB_FR_FPR7(sp)
  128. SDC1 $8, GDB_FR_FPR8(sp)
  129. SDC1 $9, GDB_FR_FPR9(sp)
  130. SDC1 $10, GDB_FR_FPR10(sp)
  131. SDC1 $11, GDB_FR_FPR11(sp)
  132. SDC1 $12, GDB_FR_FPR12(sp)
  133. SDC1 $13, GDB_FR_FPR13(sp)
  134. SDC1 $14, GDB_FR_FPR14(sp)
  135. SDC1 $15, GDB_FR_FPR15(sp)
  136. SDC1 $16, GDB_FR_FPR16(sp)
  137. SDC1 $17, GDB_FR_FPR17(sp)
  138. SDC1 $18, GDB_FR_FPR18(sp)
  139. SDC1 $19, GDB_FR_FPR19(sp)
  140. SDC1 $20, GDB_FR_FPR20(sp)
  141. SDC1 $21, GDB_FR_FPR21(sp)
  142. SDC1 $22, GDB_FR_FPR22(sp)
  143. SDC1 $23, GDB_FR_FPR23(sp)
  144. SDC1 $24, GDB_FR_FPR24(sp)
  145. SDC1 $25, GDB_FR_FPR25(sp)
  146. SDC1 $26, GDB_FR_FPR26(sp)
  147. SDC1 $27, GDB_FR_FPR27(sp)
  148. SDC1 $28, GDB_FR_FPR28(sp)
  149. SDC1 $29, GDB_FR_FPR29(sp)
  150. SDC1 $30, GDB_FR_FPR30(sp)
  151. SDC1 $31, GDB_FR_FPR31(sp)
  152. /*
  153. * FPU control registers
  154. */
  155. cfc1 v0, CP1_STATUS
  156. LONG_S v0, GDB_FR_FSR(sp)
  157. cfc1 v0, CP1_REVISION
  158. LONG_S v0, GDB_FR_FIR(sp)
  159. /*
  160. * Current stack frame ptr
  161. */
  162. 2:
  163. LONG_S sp, GDB_FR_FRP(sp)
  164. /*
  165. * CP0 registers (R4000/R4400 unused registers skipped)
  166. */
  167. mfc0 v0, CP0_INDEX
  168. LONG_S v0, GDB_FR_CP0_INDEX(sp)
  169. mfc0 v0, CP0_RANDOM
  170. LONG_S v0, GDB_FR_CP0_RANDOM(sp)
  171. DMFC0 v0, CP0_ENTRYLO0
  172. LONG_S v0, GDB_FR_CP0_ENTRYLO0(sp)
  173. DMFC0 v0, CP0_ENTRYLO1
  174. LONG_S v0, GDB_FR_CP0_ENTRYLO1(sp)
  175. DMFC0 v0, CP0_CONTEXT
  176. LONG_S v0, GDB_FR_CP0_CONTEXT(sp)
  177. mfc0 v0, CP0_PAGEMASK
  178. LONG_S v0, GDB_FR_CP0_PAGEMASK(sp)
  179. mfc0 v0, CP0_WIRED
  180. LONG_S v0, GDB_FR_CP0_WIRED(sp)
  181. DMFC0 v0, CP0_ENTRYHI
  182. LONG_S v0, GDB_FR_CP0_ENTRYHI(sp)
  183. mfc0 v0, CP0_PRID
  184. LONG_S v0, GDB_FR_CP0_PRID(sp)
  185. .set at
  186. /*
  187. * Continue with the higher level handler
  188. */
  189. move a0,sp
  190. jal handle_exception
  191. nop
  192. /*
  193. * Restore all writable registers, in reverse order
  194. */
  195. .set noat
  196. LONG_L v0, GDB_FR_CP0_ENTRYHI(sp)
  197. LONG_L v1, GDB_FR_CP0_WIRED(sp)
  198. DMTC0 v0, CP0_ENTRYHI
  199. mtc0 v1, CP0_WIRED
  200. LONG_L v0, GDB_FR_CP0_PAGEMASK(sp)
  201. LONG_L v1, GDB_FR_CP0_ENTRYLO1(sp)
  202. mtc0 v0, CP0_PAGEMASK
  203. DMTC0 v1, CP0_ENTRYLO1
  204. LONG_L v0, GDB_FR_CP0_ENTRYLO0(sp)
  205. LONG_L v1, GDB_FR_CP0_INDEX(sp)
  206. DMTC0 v0, CP0_ENTRYLO0
  207. LONG_L v0, GDB_FR_CP0_CONTEXT(sp)
  208. mtc0 v1, CP0_INDEX
  209. DMTC0 v0, CP0_CONTEXT
  210. /*
  211. * Next, the floating point registers
  212. */
  213. mfc0 v0, CP0_STATUS /* check if the FPU is enabled */
  214. srl v0, v0, 16
  215. andi v0, v0, (ST0_CU1 >> 16)
  216. beqz v0, 3f /* disabled, skip */
  217. nop
  218. LDC1 $31, GDB_FR_FPR31(sp)
  219. LDC1 $30, GDB_FR_FPR30(sp)
  220. LDC1 $29, GDB_FR_FPR29(sp)
  221. LDC1 $28, GDB_FR_FPR28(sp)
  222. LDC1 $27, GDB_FR_FPR27(sp)
  223. LDC1 $26, GDB_FR_FPR26(sp)
  224. LDC1 $25, GDB_FR_FPR25(sp)
  225. LDC1 $24, GDB_FR_FPR24(sp)
  226. LDC1 $23, GDB_FR_FPR23(sp)
  227. LDC1 $22, GDB_FR_FPR22(sp)
  228. LDC1 $21, GDB_FR_FPR21(sp)
  229. LDC1 $20, GDB_FR_FPR20(sp)
  230. LDC1 $19, GDB_FR_FPR19(sp)
  231. LDC1 $18, GDB_FR_FPR18(sp)
  232. LDC1 $17, GDB_FR_FPR17(sp)
  233. LDC1 $16, GDB_FR_FPR16(sp)
  234. LDC1 $15, GDB_FR_FPR15(sp)
  235. LDC1 $14, GDB_FR_FPR14(sp)
  236. LDC1 $13, GDB_FR_FPR13(sp)
  237. LDC1 $12, GDB_FR_FPR12(sp)
  238. LDC1 $11, GDB_FR_FPR11(sp)
  239. LDC1 $10, GDB_FR_FPR10(sp)
  240. LDC1 $9, GDB_FR_FPR9(sp)
  241. LDC1 $8, GDB_FR_FPR8(sp)
  242. LDC1 $7, GDB_FR_FPR7(sp)
  243. LDC1 $6, GDB_FR_FPR6(sp)
  244. LDC1 $5, GDB_FR_FPR5(sp)
  245. LDC1 $4, GDB_FR_FPR4(sp)
  246. LDC1 $3, GDB_FR_FPR3(sp)
  247. LDC1 $2, GDB_FR_FPR2(sp)
  248. LDC1 $1, GDB_FR_FPR1(sp)
  249. LDC1 $0, GDB_FR_FPR0(sp)
  250. /*
  251. * Now the CP0 and integer registers
  252. */
  253. 3:
  254. mfc0 t0, CP0_STATUS
  255. ori t0, 0x1f
  256. xori t0, 0x1f
  257. mtc0 t0, CP0_STATUS
  258. LONG_L v0, GDB_FR_STATUS(sp)
  259. LONG_L v1, GDB_FR_EPC(sp)
  260. mtc0 v0, CP0_STATUS
  261. DMTC0 v1, CP0_EPC
  262. LONG_L v0, GDB_FR_HI(sp)
  263. LONG_L v1, GDB_FR_LO(sp)
  264. mthi v0
  265. mtlo v1
  266. LONG_L $31, GDB_FR_REG31(sp)
  267. LONG_L $30, GDB_FR_REG30(sp)
  268. LONG_L $28, GDB_FR_REG28(sp)
  269. LONG_L $27, GDB_FR_REG27(sp)
  270. LONG_L $26, GDB_FR_REG26(sp)
  271. LONG_L $25, GDB_FR_REG25(sp)
  272. LONG_L $24, GDB_FR_REG24(sp)
  273. LONG_L $23, GDB_FR_REG23(sp)
  274. LONG_L $22, GDB_FR_REG22(sp)
  275. LONG_L $21, GDB_FR_REG21(sp)
  276. LONG_L $20, GDB_FR_REG20(sp)
  277. LONG_L $19, GDB_FR_REG19(sp)
  278. LONG_L $18, GDB_FR_REG18(sp)
  279. LONG_L $17, GDB_FR_REG17(sp)
  280. LONG_L $16, GDB_FR_REG16(sp)
  281. LONG_L $15, GDB_FR_REG15(sp)
  282. LONG_L $14, GDB_FR_REG14(sp)
  283. LONG_L $13, GDB_FR_REG13(sp)
  284. LONG_L $12, GDB_FR_REG12(sp)
  285. LONG_L $11, GDB_FR_REG11(sp)
  286. LONG_L $10, GDB_FR_REG10(sp)
  287. LONG_L $9, GDB_FR_REG9(sp)
  288. LONG_L $8, GDB_FR_REG8(sp)
  289. LONG_L $7, GDB_FR_REG7(sp)
  290. LONG_L $6, GDB_FR_REG6(sp)
  291. LONG_L $5, GDB_FR_REG5(sp)
  292. LONG_L $4, GDB_FR_REG4(sp)
  293. LONG_L $3, GDB_FR_REG3(sp)
  294. LONG_L $2, GDB_FR_REG2(sp)
  295. LONG_L $1, GDB_FR_REG1(sp)
  296. #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
  297. LONG_L k0, GDB_FR_EPC(sp)
  298. LONG_L $29, GDB_FR_REG29(sp) /* Deallocate stack */
  299. jr k0
  300. rfe
  301. #else
  302. LONG_L sp, GDB_FR_REG29(sp) /* Deallocate stack */
  303. .set mips3
  304. eret
  305. .set mips0
  306. #endif
  307. .set at
  308. .set reorder
  309. END(trap_low)
  310. LEAF(kgdb_read_byte)
  311. 4: lb t0, (a0)
  312. sb t0, (a1)
  313. li v0, 0
  314. jr ra
  315. .section __ex_table,"a"
  316. PTR 4b, kgdbfault
  317. .previous
  318. END(kgdb_read_byte)
  319. LEAF(kgdb_write_byte)
  320. 5: sb a0, (a1)
  321. li v0, 0
  322. jr ra
  323. .section __ex_table,"a"
  324. PTR 5b, kgdbfault
  325. .previous
  326. END(kgdb_write_byte)
  327. .type kgdbfault@function
  328. .ent kgdbfault
  329. kgdbfault: li v0, -EFAULT
  330. jr ra
  331. .end kgdbfault